1/*-
2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: releng/10.3/sys/dev/sfxge/common/efx.h 295526 2016-02-11 16:39:30Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_phy_ids.h"
38
39#ifdef	__cplusplus
40extern "C" {
41#endif
42
43#define	EFX_STATIC_ASSERT(_cond)		\
44	((void)sizeof(char[(_cond) ? 1 : -1]))
45
46#define	EFX_ARRAY_SIZE(_array)			\
47	(sizeof(_array) / sizeof((_array)[0]))
48
49#define	EFX_FIELD_OFFSET(_type, _field)		\
50	((size_t) &(((_type *)0)->_field))
51
52/* Return codes */
53
54typedef __success(return == 0) int efx_rc_t;
55
56
57/* Chip families */
58
59typedef enum efx_family_e {
60	EFX_FAMILY_INVALID,
61	EFX_FAMILY_FALCON,
62	EFX_FAMILY_SIENA,
63	EFX_FAMILY_HUNTINGTON,
64	EFX_FAMILY_MEDFORD,
65	EFX_FAMILY_NTYPES
66} efx_family_t;
67
68extern	__checkReturn	efx_rc_t
69efx_family(
70	__in		uint16_t venid,
71	__in		uint16_t devid,
72	__out		efx_family_t *efp);
73
74extern	__checkReturn	efx_rc_t
75efx_infer_family(
76	__in		efsys_bar_t *esbp,
77	__out		efx_family_t *efp);
78
79#define	EFX_PCI_VENID_SFC			0x1924
80
81#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
82
83#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
84#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
85#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
86
87#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
88#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
89#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
90
91#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
92#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
93
94#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
95#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
96#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
97
98#define	EFX_MEM_BAR	2
99
100/* Error codes */
101
102enum {
103	EFX_ERR_INVALID,
104	EFX_ERR_SRAM_OOB,
105	EFX_ERR_BUFID_DC_OOB,
106	EFX_ERR_MEM_PERR,
107	EFX_ERR_RBUF_OWN,
108	EFX_ERR_TBUF_OWN,
109	EFX_ERR_RDESQ_OWN,
110	EFX_ERR_TDESQ_OWN,
111	EFX_ERR_EVQ_OWN,
112	EFX_ERR_EVFF_OFLO,
113	EFX_ERR_ILL_ADDR,
114	EFX_ERR_SRAM_PERR,
115	EFX_ERR_NCODES
116};
117
118/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119extern	__checkReturn		uint32_t
120efx_crc32_calculate(
121	__in			uint32_t crc_init,
122	__in_ecount(length)	uint8_t const *input,
123	__in			int length);
124
125
126/* Type prototypes */
127
128typedef struct efx_rxq_s	efx_rxq_t;
129
130/* NIC */
131
132typedef struct efx_nic_s	efx_nic_t;
133
134#define	EFX_NIC_FUNC_PRIMARY	0x00000001
135#define	EFX_NIC_FUNC_LINKCTRL	0x00000002
136#define	EFX_NIC_FUNC_TRUSTED	0x00000004
137
138
139extern	__checkReturn	efx_rc_t
140efx_nic_create(
141	__in		efx_family_t family,
142	__in		efsys_identifier_t *esip,
143	__in		efsys_bar_t *esbp,
144	__in		efsys_lock_t *eslp,
145	__deref_out	efx_nic_t **enpp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_probe(
149	__in		efx_nic_t *enp);
150
151#if EFSYS_OPT_PCIE_TUNE
152
153extern	__checkReturn	efx_rc_t
154efx_nic_pcie_tune(
155	__in		efx_nic_t *enp,
156	unsigned int	nlanes);
157
158extern	__checkReturn	efx_rc_t
159efx_nic_pcie_extended_sync(
160	__in		efx_nic_t *enp);
161
162#endif	/* EFSYS_OPT_PCIE_TUNE */
163
164extern	__checkReturn	efx_rc_t
165efx_nic_init(
166	__in		efx_nic_t *enp);
167
168extern	__checkReturn	efx_rc_t
169efx_nic_reset(
170	__in		efx_nic_t *enp);
171
172#if EFSYS_OPT_DIAG
173
174extern	__checkReturn	efx_rc_t
175efx_nic_register_test(
176	__in		efx_nic_t *enp);
177
178#endif	/* EFSYS_OPT_DIAG */
179
180extern		void
181efx_nic_fini(
182	__in		efx_nic_t *enp);
183
184extern		void
185efx_nic_unprobe(
186	__in		efx_nic_t *enp);
187
188extern 		void
189efx_nic_destroy(
190	__in	efx_nic_t *enp);
191
192#if EFSYS_OPT_MCDI
193
194#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195/* Huntington and Medford require MCDIv2 commands */
196#define	WITH_MCDI_V2 1
197#endif
198
199typedef struct efx_mcdi_req_s efx_mcdi_req_t;
200
201typedef enum efx_mcdi_exception_e {
202	EFX_MCDI_EXCEPTION_MC_REBOOT,
203	EFX_MCDI_EXCEPTION_MC_BADASSERT,
204} efx_mcdi_exception_t;
205
206#if EFSYS_OPT_MCDI_LOGGING
207typedef enum efx_log_msg_e
208{
209	EFX_LOG_INVALID,
210	EFX_LOG_MCDI_REQUEST,
211	EFX_LOG_MCDI_RESPONSE,
212} efx_log_msg_t;
213#endif /* EFSYS_OPT_MCDI_LOGGING */
214
215typedef struct efx_mcdi_transport_s {
216	void		*emt_context;
217	efsys_mem_t	*emt_dma_mem;
218	void		(*emt_execute)(void *, efx_mcdi_req_t *);
219	void		(*emt_ev_cpl)(void *);
220	void		(*emt_exception)(void *, efx_mcdi_exception_t);
221#if EFSYS_OPT_MCDI_LOGGING
222	void		(*emt_logger)(void *, efx_log_msg_t,
223					void *, size_t, void *, size_t);
224#endif /* EFSYS_OPT_MCDI_LOGGING */
225#if EFSYS_OPT_MCDI_PROXY_AUTH
226	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228} efx_mcdi_transport_t;
229
230extern	__checkReturn	efx_rc_t
231efx_mcdi_init(
232	__in		efx_nic_t *enp,
233	__in		const efx_mcdi_transport_t *mtp);
234
235extern	__checkReturn	efx_rc_t
236efx_mcdi_reboot(
237	__in		efx_nic_t *enp);
238
239			void
240efx_mcdi_new_epoch(
241	__in		efx_nic_t *enp);
242
243extern			void
244efx_mcdi_request_start(
245	__in		efx_nic_t *enp,
246	__in		efx_mcdi_req_t *emrp,
247	__in		boolean_t ev_cpl);
248
249extern	__checkReturn	boolean_t
250efx_mcdi_request_poll(
251	__in		efx_nic_t *enp);
252
253extern	__checkReturn	boolean_t
254efx_mcdi_request_abort(
255	__in		efx_nic_t *enp);
256
257extern			void
258efx_mcdi_fini(
259	__in		efx_nic_t *enp);
260
261#endif	/* EFSYS_OPT_MCDI */
262
263/* INTR */
264
265#define	EFX_NINTR_FALCON 64
266#define	EFX_NINTR_SIENA 1024
267
268typedef enum efx_intr_type_e {
269	EFX_INTR_INVALID = 0,
270	EFX_INTR_LINE,
271	EFX_INTR_MESSAGE,
272	EFX_INTR_NTYPES
273} efx_intr_type_t;
274
275#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
276
277extern	__checkReturn	efx_rc_t
278efx_intr_init(
279	__in		efx_nic_t *enp,
280	__in		efx_intr_type_t type,
281	__in		efsys_mem_t *esmp);
282
283extern 			void
284efx_intr_enable(
285	__in		efx_nic_t *enp);
286
287extern 			void
288efx_intr_disable(
289	__in		efx_nic_t *enp);
290
291extern 			void
292efx_intr_disable_unlocked(
293	__in		efx_nic_t *enp);
294
295#define	EFX_INTR_NEVQS	32
296
297extern __checkReturn	efx_rc_t
298efx_intr_trigger(
299	__in		efx_nic_t *enp,
300	__in		unsigned int level);
301
302extern			void
303efx_intr_status_line(
304	__in		efx_nic_t *enp,
305	__out		boolean_t *fatalp,
306	__out		uint32_t *maskp);
307
308extern			void
309efx_intr_status_message(
310	__in		efx_nic_t *enp,
311	__in		unsigned int message,
312	__out		boolean_t *fatalp);
313
314extern			void
315efx_intr_fatal(
316	__in		efx_nic_t *enp);
317
318extern			void
319efx_intr_fini(
320	__in		efx_nic_t *enp);
321
322/* MAC */
323
324#if EFSYS_OPT_MAC_STATS
325
326/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327typedef enum efx_mac_stat_e {
328	EFX_MAC_RX_OCTETS,
329	EFX_MAC_RX_PKTS,
330	EFX_MAC_RX_UNICST_PKTS,
331	EFX_MAC_RX_MULTICST_PKTS,
332	EFX_MAC_RX_BRDCST_PKTS,
333	EFX_MAC_RX_PAUSE_PKTS,
334	EFX_MAC_RX_LE_64_PKTS,
335	EFX_MAC_RX_65_TO_127_PKTS,
336	EFX_MAC_RX_128_TO_255_PKTS,
337	EFX_MAC_RX_256_TO_511_PKTS,
338	EFX_MAC_RX_512_TO_1023_PKTS,
339	EFX_MAC_RX_1024_TO_15XX_PKTS,
340	EFX_MAC_RX_GE_15XX_PKTS,
341	EFX_MAC_RX_ERRORS,
342	EFX_MAC_RX_FCS_ERRORS,
343	EFX_MAC_RX_DROP_EVENTS,
344	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345	EFX_MAC_RX_SYMBOL_ERRORS,
346	EFX_MAC_RX_ALIGN_ERRORS,
347	EFX_MAC_RX_INTERNAL_ERRORS,
348	EFX_MAC_RX_JABBER_PKTS,
349	EFX_MAC_RX_LANE0_CHAR_ERR,
350	EFX_MAC_RX_LANE1_CHAR_ERR,
351	EFX_MAC_RX_LANE2_CHAR_ERR,
352	EFX_MAC_RX_LANE3_CHAR_ERR,
353	EFX_MAC_RX_LANE0_DISP_ERR,
354	EFX_MAC_RX_LANE1_DISP_ERR,
355	EFX_MAC_RX_LANE2_DISP_ERR,
356	EFX_MAC_RX_LANE3_DISP_ERR,
357	EFX_MAC_RX_MATCH_FAULT,
358	EFX_MAC_RX_NODESC_DROP_CNT,
359	EFX_MAC_TX_OCTETS,
360	EFX_MAC_TX_PKTS,
361	EFX_MAC_TX_UNICST_PKTS,
362	EFX_MAC_TX_MULTICST_PKTS,
363	EFX_MAC_TX_BRDCST_PKTS,
364	EFX_MAC_TX_PAUSE_PKTS,
365	EFX_MAC_TX_LE_64_PKTS,
366	EFX_MAC_TX_65_TO_127_PKTS,
367	EFX_MAC_TX_128_TO_255_PKTS,
368	EFX_MAC_TX_256_TO_511_PKTS,
369	EFX_MAC_TX_512_TO_1023_PKTS,
370	EFX_MAC_TX_1024_TO_15XX_PKTS,
371	EFX_MAC_TX_GE_15XX_PKTS,
372	EFX_MAC_TX_ERRORS,
373	EFX_MAC_TX_SGL_COL_PKTS,
374	EFX_MAC_TX_MULT_COL_PKTS,
375	EFX_MAC_TX_EX_COL_PKTS,
376	EFX_MAC_TX_LATE_COL_PKTS,
377	EFX_MAC_TX_DEF_PKTS,
378	EFX_MAC_TX_EX_DEF_PKTS,
379	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381	EFX_MAC_PM_TRUNC_VFIFO_FULL,
382	EFX_MAC_PM_DISCARD_VFIFO_FULL,
383	EFX_MAC_PM_TRUNC_QBB,
384	EFX_MAC_PM_DISCARD_QBB,
385	EFX_MAC_PM_DISCARD_MAPPING,
386	EFX_MAC_RXDP_Q_DISABLED_PKTS,
387	EFX_MAC_RXDP_DI_DROPPED_PKTS,
388	EFX_MAC_RXDP_STREAMING_PKTS,
389	EFX_MAC_RXDP_HLB_FETCH,
390	EFX_MAC_RXDP_HLB_WAIT,
391	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398	EFX_MAC_VADAPTER_RX_BAD_BYTES,
399	EFX_MAC_VADAPTER_RX_OVERFLOW,
400	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407	EFX_MAC_VADAPTER_TX_BAD_BYTES,
408	EFX_MAC_VADAPTER_TX_OVERFLOW,
409	EFX_MAC_NSTATS
410} efx_mac_stat_t;
411
412/* END MKCONFIG GENERATED EfxHeaderMacBlock */
413
414#endif	/* EFSYS_OPT_MAC_STATS */
415
416typedef enum efx_link_mode_e {
417	EFX_LINK_UNKNOWN = 0,
418	EFX_LINK_DOWN,
419	EFX_LINK_10HDX,
420	EFX_LINK_10FDX,
421	EFX_LINK_100HDX,
422	EFX_LINK_100FDX,
423	EFX_LINK_1000HDX,
424	EFX_LINK_1000FDX,
425	EFX_LINK_10000FDX,
426	EFX_LINK_40000FDX,
427	EFX_LINK_NMODES
428} efx_link_mode_t;
429
430#define	EFX_MAC_ADDR_LEN 6
431
432#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
433
434#define	EFX_MAC_MULTICAST_LIST_MAX	256
435
436#define	EFX_MAC_SDU_MAX	9202
437
438#define	EFX_MAC_PDU(_sdu) 				\
439	P2ROUNDUP(((_sdu)				\
440		    + /* EtherII */ 14			\
441		    + /* VLAN */ 4			\
442		    + /* CRC */ 4			\
443		    + /* bug16011 */ 16),		\
444		    (1 << 3))
445
446#define	EFX_MAC_PDU_MIN	60
447#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
448
449extern	__checkReturn	efx_rc_t
450efx_mac_pdu_set(
451	__in		efx_nic_t *enp,
452	__in		size_t pdu);
453
454extern	__checkReturn	efx_rc_t
455efx_mac_addr_set(
456	__in		efx_nic_t *enp,
457	__in		uint8_t *addr);
458
459extern	__checkReturn			efx_rc_t
460efx_mac_filter_set(
461	__in				efx_nic_t *enp,
462	__in				boolean_t all_unicst,
463	__in				boolean_t mulcst,
464	__in				boolean_t all_mulcst,
465	__in				boolean_t brdcst);
466
467extern	__checkReturn	efx_rc_t
468efx_mac_multicast_list_set(
469	__in				efx_nic_t *enp,
470	__in_ecount(6*count)		uint8_t const *addrs,
471	__in				int count);
472
473extern	__checkReturn	efx_rc_t
474efx_mac_filter_default_rxq_set(
475	__in		efx_nic_t *enp,
476	__in		efx_rxq_t *erp,
477	__in		boolean_t using_rss);
478
479extern			void
480efx_mac_filter_default_rxq_clear(
481	__in		efx_nic_t *enp);
482
483extern	__checkReturn	efx_rc_t
484efx_mac_drain(
485	__in		efx_nic_t *enp,
486	__in		boolean_t enabled);
487
488extern	__checkReturn	efx_rc_t
489efx_mac_up(
490	__in		efx_nic_t *enp,
491	__out		boolean_t *mac_upp);
492
493#define	EFX_FCNTL_RESPOND	0x00000001
494#define	EFX_FCNTL_GENERATE	0x00000002
495
496extern	__checkReturn	efx_rc_t
497efx_mac_fcntl_set(
498	__in		efx_nic_t *enp,
499	__in		unsigned int fcntl,
500	__in		boolean_t autoneg);
501
502extern			void
503efx_mac_fcntl_get(
504	__in		efx_nic_t *enp,
505	__out		unsigned int *fcntl_wantedp,
506	__out		unsigned int *fcntl_linkp);
507
508
509#if EFSYS_OPT_MAC_STATS
510
511#if EFSYS_OPT_NAMES
512
513extern	__checkReturn			const char *
514efx_mac_stat_name(
515	__in				efx_nic_t *enp,
516	__in				unsigned int id);
517
518#endif	/* EFSYS_OPT_NAMES */
519
520#define	EFX_MAC_STATS_SIZE 0x400
521
522/*
523 * Upload mac statistics supported by the hardware into the given buffer.
524 *
525 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
526 * and page aligned.
527 *
528 * The hardware will only DMA statistics that it understands (of course).
529 * Drivers should not make any assumptions about which statistics are
530 * supported, especially when the statistics are generated by firmware.
531 *
532 * Thus, drivers should zero this buffer before use, so that not-understood
533 * statistics read back as zero.
534 */
535extern	__checkReturn			efx_rc_t
536efx_mac_stats_upload(
537	__in				efx_nic_t *enp,
538	__in				efsys_mem_t *esmp);
539
540extern	__checkReturn			efx_rc_t
541efx_mac_stats_periodic(
542	__in				efx_nic_t *enp,
543	__in				efsys_mem_t *esmp,
544	__in				uint16_t period_ms,
545	__in				boolean_t events);
546
547extern	__checkReturn			efx_rc_t
548efx_mac_stats_update(
549	__in				efx_nic_t *enp,
550	__in				efsys_mem_t *esmp,
551	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
552	__inout_opt			uint32_t *generationp);
553
554#endif	/* EFSYS_OPT_MAC_STATS */
555
556/* MON */
557
558typedef enum efx_mon_type_e {
559	EFX_MON_INVALID = 0,
560	EFX_MON_NULL,
561	EFX_MON_LM87,
562	EFX_MON_MAX6647,
563	EFX_MON_SFC90X0,
564	EFX_MON_SFC91X0,
565	EFX_MON_SFC92X0,
566	EFX_MON_NTYPES
567} efx_mon_type_t;
568
569#if EFSYS_OPT_NAMES
570
571extern		const char *
572efx_mon_name(
573	__in	efx_nic_t *enp);
574
575#endif	/* EFSYS_OPT_NAMES */
576
577extern	__checkReturn	efx_rc_t
578efx_mon_init(
579	__in		efx_nic_t *enp);
580
581#if EFSYS_OPT_MON_STATS
582
583#define	EFX_MON_STATS_PAGE_SIZE 0x100
584#define	EFX_MON_MASK_ELEMENT_SIZE 32
585
586/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
587typedef enum efx_mon_stat_e {
588	EFX_MON_STAT_2_5V,
589	EFX_MON_STAT_VCCP1,
590	EFX_MON_STAT_VCC,
591	EFX_MON_STAT_5V,
592	EFX_MON_STAT_12V,
593	EFX_MON_STAT_VCCP2,
594	EFX_MON_STAT_EXT_TEMP,
595	EFX_MON_STAT_INT_TEMP,
596	EFX_MON_STAT_AIN1,
597	EFX_MON_STAT_AIN2,
598	EFX_MON_STAT_INT_COOLING,
599	EFX_MON_STAT_EXT_COOLING,
600	EFX_MON_STAT_1V,
601	EFX_MON_STAT_1_2V,
602	EFX_MON_STAT_1_8V,
603	EFX_MON_STAT_3_3V,
604	EFX_MON_STAT_1_2VA,
605	EFX_MON_STAT_VREF,
606	EFX_MON_STAT_VAOE,
607	EFX_MON_STAT_AOE_TEMP,
608	EFX_MON_STAT_PSU_AOE_TEMP,
609	EFX_MON_STAT_PSU_TEMP,
610	EFX_MON_STAT_FAN0,
611	EFX_MON_STAT_FAN1,
612	EFX_MON_STAT_FAN2,
613	EFX_MON_STAT_FAN3,
614	EFX_MON_STAT_FAN4,
615	EFX_MON_STAT_VAOE_IN,
616	EFX_MON_STAT_IAOE,
617	EFX_MON_STAT_IAOE_IN,
618	EFX_MON_STAT_NIC_POWER,
619	EFX_MON_STAT_0_9V,
620	EFX_MON_STAT_I0_9V,
621	EFX_MON_STAT_I1_2V,
622	EFX_MON_STAT_0_9V_ADC,
623	EFX_MON_STAT_INT_TEMP2,
624	EFX_MON_STAT_VREG_TEMP,
625	EFX_MON_STAT_VREG_0_9V_TEMP,
626	EFX_MON_STAT_VREG_1_2V_TEMP,
627	EFX_MON_STAT_INT_VPTAT,
628	EFX_MON_STAT_INT_ADC_TEMP,
629	EFX_MON_STAT_EXT_VPTAT,
630	EFX_MON_STAT_EXT_ADC_TEMP,
631	EFX_MON_STAT_AMBIENT_TEMP,
632	EFX_MON_STAT_AIRFLOW,
633	EFX_MON_STAT_VDD08D_VSS08D_CSR,
634	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
635	EFX_MON_STAT_HOTPOINT_TEMP,
636	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
637	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
638	EFX_MON_STAT_MUM_VCC,
639	EFX_MON_STAT_0V9_A,
640	EFX_MON_STAT_I0V9_A,
641	EFX_MON_STAT_0V9_A_TEMP,
642	EFX_MON_STAT_0V9_B,
643	EFX_MON_STAT_I0V9_B,
644	EFX_MON_STAT_0V9_B_TEMP,
645	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
646	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
647	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
648	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
649	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
650	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
651	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
652	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
653	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
654	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
655	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
656	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
657	EFX_MON_STAT_SODIMM_VOUT,
658	EFX_MON_STAT_SODIMM_0_TEMP,
659	EFX_MON_STAT_SODIMM_1_TEMP,
660	EFX_MON_STAT_PHY0_VCC,
661	EFX_MON_STAT_PHY1_VCC,
662	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
663	EFX_MON_NSTATS
664} efx_mon_stat_t;
665
666/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
667
668typedef enum efx_mon_stat_state_e {
669	EFX_MON_STAT_STATE_OK = 0,
670	EFX_MON_STAT_STATE_WARNING = 1,
671	EFX_MON_STAT_STATE_FATAL = 2,
672	EFX_MON_STAT_STATE_BROKEN = 3,
673	EFX_MON_STAT_STATE_NO_READING = 4,
674} efx_mon_stat_state_t;
675
676typedef struct efx_mon_stat_value_s {
677	uint16_t	emsv_value;
678	uint16_t	emsv_state;
679} efx_mon_stat_value_t;
680
681#if EFSYS_OPT_NAMES
682
683extern					const char *
684efx_mon_stat_name(
685	__in				efx_nic_t *enp,
686	__in				efx_mon_stat_t id);
687
688#endif	/* EFSYS_OPT_NAMES */
689
690extern	__checkReturn			efx_rc_t
691efx_mon_stats_update(
692	__in				efx_nic_t *enp,
693	__in				efsys_mem_t *esmp,
694	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
695
696#endif	/* EFSYS_OPT_MON_STATS */
697
698extern		void
699efx_mon_fini(
700	__in	efx_nic_t *enp);
701
702/* PHY */
703
704#define	PMA_PMD_MMD	1
705#define	PCS_MMD		3
706#define	PHY_XS_MMD	4
707#define	DTE_XS_MMD	5
708#define	AN_MMD		7
709#define	CL22EXT_MMD	29
710
711#define	MAXMMD		((1 << 5) - 1)
712
713extern	__checkReturn	efx_rc_t
714efx_phy_verify(
715	__in		efx_nic_t *enp);
716
717#if EFSYS_OPT_PHY_LED_CONTROL
718
719typedef enum efx_phy_led_mode_e {
720	EFX_PHY_LED_DEFAULT = 0,
721	EFX_PHY_LED_OFF,
722	EFX_PHY_LED_ON,
723	EFX_PHY_LED_FLASH,
724	EFX_PHY_LED_NMODES
725} efx_phy_led_mode_t;
726
727extern	__checkReturn	efx_rc_t
728efx_phy_led_set(
729	__in	efx_nic_t *enp,
730	__in	efx_phy_led_mode_t mode);
731
732#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
733
734extern	__checkReturn	efx_rc_t
735efx_port_init(
736	__in		efx_nic_t *enp);
737
738#if EFSYS_OPT_LOOPBACK
739
740typedef enum efx_loopback_type_e {
741	EFX_LOOPBACK_OFF = 0,
742	EFX_LOOPBACK_DATA = 1,
743	EFX_LOOPBACK_GMAC = 2,
744	EFX_LOOPBACK_XGMII = 3,
745	EFX_LOOPBACK_XGXS = 4,
746	EFX_LOOPBACK_XAUI = 5,
747	EFX_LOOPBACK_GMII = 6,
748	EFX_LOOPBACK_SGMII = 7,
749	EFX_LOOPBACK_XGBR = 8,
750	EFX_LOOPBACK_XFI = 9,
751	EFX_LOOPBACK_XAUI_FAR = 10,
752	EFX_LOOPBACK_GMII_FAR = 11,
753	EFX_LOOPBACK_SGMII_FAR = 12,
754	EFX_LOOPBACK_XFI_FAR = 13,
755	EFX_LOOPBACK_GPHY = 14,
756	EFX_LOOPBACK_PHY_XS = 15,
757	EFX_LOOPBACK_PCS = 16,
758	EFX_LOOPBACK_PMA_PMD = 17,
759	EFX_LOOPBACK_XPORT = 18,
760	EFX_LOOPBACK_XGMII_WS = 19,
761	EFX_LOOPBACK_XAUI_WS = 20,
762	EFX_LOOPBACK_XAUI_WS_FAR = 21,
763	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
764	EFX_LOOPBACK_GMII_WS = 23,
765	EFX_LOOPBACK_XFI_WS = 24,
766	EFX_LOOPBACK_XFI_WS_FAR = 25,
767	EFX_LOOPBACK_PHYXS_WS = 26,
768	EFX_LOOPBACK_PMA_INT = 27,
769	EFX_LOOPBACK_SD_NEAR = 28,
770	EFX_LOOPBACK_SD_FAR = 29,
771	EFX_LOOPBACK_PMA_INT_WS = 30,
772	EFX_LOOPBACK_SD_FEP2_WS = 31,
773	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
774	EFX_LOOPBACK_SD_FEP_WS = 33,
775	EFX_LOOPBACK_SD_FES_WS = 34,
776	EFX_LOOPBACK_NTYPES
777} efx_loopback_type_t;
778
779typedef enum efx_loopback_kind_e {
780	EFX_LOOPBACK_KIND_OFF = 0,
781	EFX_LOOPBACK_KIND_ALL,
782	EFX_LOOPBACK_KIND_MAC,
783	EFX_LOOPBACK_KIND_PHY,
784	EFX_LOOPBACK_NKINDS
785} efx_loopback_kind_t;
786
787extern			void
788efx_loopback_mask(
789	__in	efx_loopback_kind_t loopback_kind,
790	__out	efx_qword_t *maskp);
791
792extern	__checkReturn	efx_rc_t
793efx_port_loopback_set(
794	__in	efx_nic_t *enp,
795	__in	efx_link_mode_t link_mode,
796	__in	efx_loopback_type_t type);
797
798#if EFSYS_OPT_NAMES
799
800extern	__checkReturn	const char *
801efx_loopback_type_name(
802	__in		efx_nic_t *enp,
803	__in		efx_loopback_type_t type);
804
805#endif	/* EFSYS_OPT_NAMES */
806
807#endif	/* EFSYS_OPT_LOOPBACK */
808
809extern	__checkReturn	efx_rc_t
810efx_port_poll(
811	__in		efx_nic_t *enp,
812	__out_opt	efx_link_mode_t	*link_modep);
813
814extern 		void
815efx_port_fini(
816	__in	efx_nic_t *enp);
817
818typedef enum efx_phy_cap_type_e {
819	EFX_PHY_CAP_INVALID = 0,
820	EFX_PHY_CAP_10HDX,
821	EFX_PHY_CAP_10FDX,
822	EFX_PHY_CAP_100HDX,
823	EFX_PHY_CAP_100FDX,
824	EFX_PHY_CAP_1000HDX,
825	EFX_PHY_CAP_1000FDX,
826	EFX_PHY_CAP_10000FDX,
827	EFX_PHY_CAP_PAUSE,
828	EFX_PHY_CAP_ASYM,
829	EFX_PHY_CAP_AN,
830	EFX_PHY_CAP_40000FDX,
831	EFX_PHY_CAP_NTYPES
832} efx_phy_cap_type_t;
833
834
835#define	EFX_PHY_CAP_CURRENT	0x00000000
836#define	EFX_PHY_CAP_DEFAULT	0x00000001
837#define	EFX_PHY_CAP_PERM	0x00000002
838
839extern		void
840efx_phy_adv_cap_get(
841	__in		efx_nic_t *enp,
842	__in            uint32_t flag,
843	__out		uint32_t *maskp);
844
845extern	__checkReturn	efx_rc_t
846efx_phy_adv_cap_set(
847	__in		efx_nic_t *enp,
848	__in		uint32_t mask);
849
850extern			void
851efx_phy_lp_cap_get(
852	__in		efx_nic_t *enp,
853	__out		uint32_t *maskp);
854
855extern	__checkReturn	efx_rc_t
856efx_phy_oui_get(
857	__in		efx_nic_t *enp,
858	__out		uint32_t *ouip);
859
860typedef enum efx_phy_media_type_e {
861	EFX_PHY_MEDIA_INVALID = 0,
862	EFX_PHY_MEDIA_XAUI,
863	EFX_PHY_MEDIA_CX4,
864	EFX_PHY_MEDIA_KX4,
865	EFX_PHY_MEDIA_XFP,
866	EFX_PHY_MEDIA_SFP_PLUS,
867	EFX_PHY_MEDIA_BASE_T,
868	EFX_PHY_MEDIA_QSFP_PLUS,
869	EFX_PHY_MEDIA_NTYPES
870} efx_phy_media_type_t;
871
872/* Get the type of medium currently used.  If the board has ports for
873 * modules, a module is present, and we recognise the media type of
874 * the module, then this will be the media type of the module.
875 * Otherwise it will be the media type of the port.
876 */
877extern			void
878efx_phy_media_type_get(
879	__in		efx_nic_t *enp,
880	__out		efx_phy_media_type_t *typep);
881
882extern					efx_rc_t
883efx_phy_module_get_info(
884	__in				efx_nic_t *enp,
885	__in				uint8_t dev_addr,
886	__in				uint8_t offset,
887	__in				uint8_t len,
888	__out_bcount(len)		uint8_t *data);
889
890#if EFSYS_OPT_PHY_STATS
891
892/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
893typedef enum efx_phy_stat_e {
894	EFX_PHY_STAT_OUI,
895	EFX_PHY_STAT_PMA_PMD_LINK_UP,
896	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
897	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
898	EFX_PHY_STAT_PMA_PMD_REV_A,
899	EFX_PHY_STAT_PMA_PMD_REV_B,
900	EFX_PHY_STAT_PMA_PMD_REV_C,
901	EFX_PHY_STAT_PMA_PMD_REV_D,
902	EFX_PHY_STAT_PCS_LINK_UP,
903	EFX_PHY_STAT_PCS_RX_FAULT,
904	EFX_PHY_STAT_PCS_TX_FAULT,
905	EFX_PHY_STAT_PCS_BER,
906	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
907	EFX_PHY_STAT_PHY_XS_LINK_UP,
908	EFX_PHY_STAT_PHY_XS_RX_FAULT,
909	EFX_PHY_STAT_PHY_XS_TX_FAULT,
910	EFX_PHY_STAT_PHY_XS_ALIGN,
911	EFX_PHY_STAT_PHY_XS_SYNC_A,
912	EFX_PHY_STAT_PHY_XS_SYNC_B,
913	EFX_PHY_STAT_PHY_XS_SYNC_C,
914	EFX_PHY_STAT_PHY_XS_SYNC_D,
915	EFX_PHY_STAT_AN_LINK_UP,
916	EFX_PHY_STAT_AN_MASTER,
917	EFX_PHY_STAT_AN_LOCAL_RX_OK,
918	EFX_PHY_STAT_AN_REMOTE_RX_OK,
919	EFX_PHY_STAT_CL22EXT_LINK_UP,
920	EFX_PHY_STAT_SNR_A,
921	EFX_PHY_STAT_SNR_B,
922	EFX_PHY_STAT_SNR_C,
923	EFX_PHY_STAT_SNR_D,
924	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
925	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
926	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
927	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
928	EFX_PHY_STAT_AN_COMPLETE,
929	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
930	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
931	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
932	EFX_PHY_STAT_PCS_FW_VERSION_0,
933	EFX_PHY_STAT_PCS_FW_VERSION_1,
934	EFX_PHY_STAT_PCS_FW_VERSION_2,
935	EFX_PHY_STAT_PCS_FW_VERSION_3,
936	EFX_PHY_STAT_PCS_FW_BUILD_YY,
937	EFX_PHY_STAT_PCS_FW_BUILD_MM,
938	EFX_PHY_STAT_PCS_FW_BUILD_DD,
939	EFX_PHY_STAT_PCS_OP_MODE,
940	EFX_PHY_NSTATS
941} efx_phy_stat_t;
942
943/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
944
945#if EFSYS_OPT_NAMES
946
947extern					const char *
948efx_phy_stat_name(
949	__in				efx_nic_t *enp,
950	__in				efx_phy_stat_t stat);
951
952#endif	/* EFSYS_OPT_NAMES */
953
954#define	EFX_PHY_STATS_SIZE 0x100
955
956extern	__checkReturn			efx_rc_t
957efx_phy_stats_update(
958	__in				efx_nic_t *enp,
959	__in				efsys_mem_t *esmp,
960	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
961
962#endif	/* EFSYS_OPT_PHY_STATS */
963
964#if EFSYS_OPT_PHY_PROPS
965
966#if EFSYS_OPT_NAMES
967
968extern		const char *
969efx_phy_prop_name(
970	__in	efx_nic_t *enp,
971	__in	unsigned int id);
972
973#endif	/* EFSYS_OPT_NAMES */
974
975#define	EFX_PHY_PROP_DEFAULT	0x00000001
976
977extern	__checkReturn	efx_rc_t
978efx_phy_prop_get(
979	__in		efx_nic_t *enp,
980	__in		unsigned int id,
981	__in		uint32_t flags,
982	__out		uint32_t *valp);
983
984extern	__checkReturn	efx_rc_t
985efx_phy_prop_set(
986	__in		efx_nic_t *enp,
987	__in		unsigned int id,
988	__in		uint32_t val);
989
990#endif	/* EFSYS_OPT_PHY_PROPS */
991
992#if EFSYS_OPT_BIST
993
994typedef enum efx_bist_type_e {
995	EFX_BIST_TYPE_UNKNOWN,
996	EFX_BIST_TYPE_PHY_NORMAL,
997	EFX_BIST_TYPE_PHY_CABLE_SHORT,
998	EFX_BIST_TYPE_PHY_CABLE_LONG,
999	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1000	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1001	EFX_BIST_TYPE_REG,	/* Test the register memories */
1002	EFX_BIST_TYPE_NTYPES,
1003} efx_bist_type_t;
1004
1005typedef enum efx_bist_result_e {
1006	EFX_BIST_RESULT_UNKNOWN,
1007	EFX_BIST_RESULT_RUNNING,
1008	EFX_BIST_RESULT_PASSED,
1009	EFX_BIST_RESULT_FAILED,
1010} efx_bist_result_t;
1011
1012typedef enum efx_phy_cable_status_e {
1013	EFX_PHY_CABLE_STATUS_OK,
1014	EFX_PHY_CABLE_STATUS_INVALID,
1015	EFX_PHY_CABLE_STATUS_OPEN,
1016	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1017	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1018	EFX_PHY_CABLE_STATUS_BUSY,
1019} efx_phy_cable_status_t;
1020
1021typedef enum efx_bist_value_e {
1022	EFX_BIST_PHY_CABLE_LENGTH_A,
1023	EFX_BIST_PHY_CABLE_LENGTH_B,
1024	EFX_BIST_PHY_CABLE_LENGTH_C,
1025	EFX_BIST_PHY_CABLE_LENGTH_D,
1026	EFX_BIST_PHY_CABLE_STATUS_A,
1027	EFX_BIST_PHY_CABLE_STATUS_B,
1028	EFX_BIST_PHY_CABLE_STATUS_C,
1029	EFX_BIST_PHY_CABLE_STATUS_D,
1030	EFX_BIST_FAULT_CODE,
1031	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1032	 * response. */
1033	EFX_BIST_MEM_TEST,
1034	EFX_BIST_MEM_ADDR,
1035	EFX_BIST_MEM_BUS,
1036	EFX_BIST_MEM_EXPECT,
1037	EFX_BIST_MEM_ACTUAL,
1038	EFX_BIST_MEM_ECC,
1039	EFX_BIST_MEM_ECC_PARITY,
1040	EFX_BIST_MEM_ECC_FATAL,
1041	EFX_BIST_NVALUES,
1042} efx_bist_value_t;
1043
1044extern	__checkReturn		efx_rc_t
1045efx_bist_enable_offline(
1046	__in			efx_nic_t *enp);
1047
1048extern	__checkReturn		efx_rc_t
1049efx_bist_start(
1050	__in			efx_nic_t *enp,
1051	__in			efx_bist_type_t type);
1052
1053extern	__checkReturn		efx_rc_t
1054efx_bist_poll(
1055	__in			efx_nic_t *enp,
1056	__in			efx_bist_type_t type,
1057	__out			efx_bist_result_t *resultp,
1058	__out_opt		uint32_t *value_maskp,
1059	__out_ecount_opt(count)	unsigned long *valuesp,
1060	__in			size_t count);
1061
1062extern				void
1063efx_bist_stop(
1064	__in			efx_nic_t *enp,
1065	__in			efx_bist_type_t type);
1066
1067#endif	/* EFSYS_OPT_BIST */
1068
1069#define	EFX_FEATURE_IPV6		0x00000001
1070#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1071#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1072#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1073#define	EFX_FEATURE_WOL			0x00000010
1074#define	EFX_FEATURE_MCDI		0x00000020
1075#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1076#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1077#define	EFX_FEATURE_TURBO		0x00000100
1078#define	EFX_FEATURE_MCDI_DMA		0x00000200
1079#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1080#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1081#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1082#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1083
1084typedef struct efx_nic_cfg_s {
1085	uint32_t		enc_board_type;
1086	uint32_t		enc_phy_type;
1087#if EFSYS_OPT_NAMES
1088	char			enc_phy_name[21];
1089#endif
1090	char			enc_phy_revision[21];
1091	efx_mon_type_t		enc_mon_type;
1092#if EFSYS_OPT_MON_STATS
1093	uint32_t		enc_mon_stat_dma_buf_size;
1094	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1095#endif
1096	unsigned int		enc_features;
1097	uint8_t			enc_mac_addr[6];
1098	uint8_t			enc_port;	/* PHY port number */
1099	uint32_t		enc_func_flags;
1100	uint32_t		enc_intr_vec_base;
1101	uint32_t		enc_intr_limit;
1102	uint32_t		enc_evq_limit;
1103	uint32_t		enc_txq_limit;
1104	uint32_t		enc_rxq_limit;
1105	uint32_t		enc_buftbl_limit;
1106	uint32_t		enc_piobuf_limit;
1107	uint32_t		enc_piobuf_size;
1108	uint32_t		enc_piobuf_min_alloc_size;
1109	uint32_t		enc_evq_timer_quantum_ns;
1110	uint32_t		enc_evq_timer_max_us;
1111	uint32_t		enc_clk_mult;
1112	uint32_t		enc_rx_prefix_size;
1113	uint32_t		enc_rx_buf_align_start;
1114	uint32_t		enc_rx_buf_align_end;
1115#if EFSYS_OPT_LOOPBACK
1116	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1117#endif	/* EFSYS_OPT_LOOPBACK */
1118#if EFSYS_OPT_PHY_FLAGS
1119	uint32_t		enc_phy_flags_mask;
1120#endif	/* EFSYS_OPT_PHY_FLAGS */
1121#if EFSYS_OPT_PHY_LED_CONTROL
1122	uint32_t		enc_led_mask;
1123#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1124#if EFSYS_OPT_PHY_STATS
1125	uint64_t		enc_phy_stat_mask;
1126#endif	/* EFSYS_OPT_PHY_STATS */
1127#if EFSYS_OPT_PHY_PROPS
1128	unsigned int		enc_phy_nprops;
1129#endif	/* EFSYS_OPT_PHY_PROPS */
1130#if EFSYS_OPT_SIENA
1131	uint8_t			enc_mcdi_mdio_channel;
1132#if EFSYS_OPT_PHY_STATS
1133	uint32_t		enc_mcdi_phy_stat_mask;
1134#endif	/* EFSYS_OPT_PHY_STATS */
1135#endif /* EFSYS_OPT_SIENA */
1136#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1137#if EFSYS_OPT_MON_STATS
1138	uint32_t		*enc_mcdi_sensor_maskp;
1139	uint32_t		enc_mcdi_sensor_mask_size;
1140#endif	/* EFSYS_OPT_MON_STATS */
1141#endif	/* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1142#if EFSYS_OPT_BIST
1143	uint32_t		enc_bist_mask;
1144#endif	/* EFSYS_OPT_BIST */
1145#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1146	uint32_t		enc_pf;
1147	uint32_t		enc_vf;
1148	uint32_t		enc_privilege_mask;
1149#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1150	boolean_t		enc_bug26807_workaround;
1151	boolean_t		enc_bug35388_workaround;
1152	boolean_t		enc_bug41750_workaround;
1153	boolean_t		enc_rx_batching_enabled;
1154	/* Maximum number of descriptors completed in an rx event. */
1155	uint32_t		enc_rx_batch_max;
1156        /* Number of rx descriptors the hardware requires for a push. */
1157        uint32_t		enc_rx_push_align;
1158	/*
1159	 * Maximum number of bytes into the packet the TCP header can start for
1160	 * the hardware to apply TSO packet edits.
1161	 */
1162	uint32_t                enc_tx_tso_tcp_header_offset_limit;
1163	boolean_t               enc_fw_assisted_tso_enabled;
1164	boolean_t               enc_fw_assisted_tso_v2_enabled;
1165	boolean_t               enc_hw_tx_insert_vlan_enabled;
1166	/* Datapath firmware vadapter/vport/vswitch support */
1167	boolean_t		enc_datapath_cap_evb;
1168	boolean_t               enc_rx_disable_scatter_supported;
1169	boolean_t               enc_allow_set_mac_with_installed_filters;
1170	boolean_t		enc_enhanced_set_mac_supported;
1171	/* External port identifier */
1172	uint8_t			enc_external_port;
1173	uint32_t		enc_mcdi_max_payload_length;
1174	/* VPD may be per-PF or global */
1175	boolean_t		enc_vpd_is_global;
1176} efx_nic_cfg_t;
1177
1178#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1179#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1180
1181#define	EFX_PCI_FUNCTION(_encp)	\
1182	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1183
1184#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1185
1186extern			const efx_nic_cfg_t *
1187efx_nic_cfg_get(
1188	__in		efx_nic_t *enp);
1189
1190/* Driver resource limits (minimum required/maximum usable). */
1191typedef struct efx_drv_limits_s
1192{
1193	uint32_t	edl_min_evq_count;
1194	uint32_t	edl_max_evq_count;
1195
1196	uint32_t	edl_min_rxq_count;
1197	uint32_t	edl_max_rxq_count;
1198
1199	uint32_t	edl_min_txq_count;
1200	uint32_t	edl_max_txq_count;
1201
1202	/* PIO blocks (sub-allocated from piobuf) */
1203	uint32_t	edl_min_pio_alloc_size;
1204	uint32_t	edl_max_pio_alloc_count;
1205} efx_drv_limits_t;
1206
1207extern	__checkReturn	efx_rc_t
1208efx_nic_set_drv_limits(
1209	__inout		efx_nic_t *enp,
1210	__in		efx_drv_limits_t *edlp);
1211
1212typedef enum efx_nic_region_e {
1213	EFX_REGION_VI,			/* Memory BAR UC mapping */
1214	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1215} efx_nic_region_t;
1216
1217extern	__checkReturn	efx_rc_t
1218efx_nic_get_bar_region(
1219	__in		efx_nic_t *enp,
1220	__in		efx_nic_region_t region,
1221	__out		uint32_t *offsetp,
1222	__out		size_t *sizep);
1223
1224extern	__checkReturn	efx_rc_t
1225efx_nic_get_vi_pool(
1226	__in		efx_nic_t *enp,
1227	__out		uint32_t *evq_countp,
1228	__out		uint32_t *rxq_countp,
1229	__out		uint32_t *txq_countp);
1230
1231
1232#if EFSYS_OPT_VPD
1233
1234typedef enum efx_vpd_tag_e {
1235	EFX_VPD_ID = 0x02,
1236	EFX_VPD_END = 0x0f,
1237	EFX_VPD_RO = 0x10,
1238	EFX_VPD_RW = 0x11,
1239} efx_vpd_tag_t;
1240
1241typedef uint16_t efx_vpd_keyword_t;
1242
1243typedef struct efx_vpd_value_s {
1244	efx_vpd_tag_t		evv_tag;
1245	efx_vpd_keyword_t	evv_keyword;
1246	uint8_t			evv_length;
1247	uint8_t			evv_value[0x100];
1248} efx_vpd_value_t;
1249
1250
1251#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1252
1253extern	__checkReturn		efx_rc_t
1254efx_vpd_init(
1255	__in			efx_nic_t *enp);
1256
1257extern	__checkReturn		efx_rc_t
1258efx_vpd_size(
1259	__in			efx_nic_t *enp,
1260	__out			size_t *sizep);
1261
1262extern	__checkReturn		efx_rc_t
1263efx_vpd_read(
1264	__in			efx_nic_t *enp,
1265	__out_bcount(size)	caddr_t data,
1266	__in			size_t size);
1267
1268extern	__checkReturn		efx_rc_t
1269efx_vpd_verify(
1270	__in			efx_nic_t *enp,
1271	__in_bcount(size)	caddr_t data,
1272	__in			size_t size);
1273
1274extern  __checkReturn		efx_rc_t
1275efx_vpd_reinit(
1276	__in			efx_nic_t *enp,
1277	__in_bcount(size)	caddr_t data,
1278	__in			size_t size);
1279
1280extern	__checkReturn		efx_rc_t
1281efx_vpd_get(
1282	__in			efx_nic_t *enp,
1283	__in_bcount(size)	caddr_t data,
1284	__in			size_t size,
1285	__inout			efx_vpd_value_t *evvp);
1286
1287extern	__checkReturn		efx_rc_t
1288efx_vpd_set(
1289	__in			efx_nic_t *enp,
1290	__inout_bcount(size)	caddr_t data,
1291	__in			size_t size,
1292	__in			efx_vpd_value_t *evvp);
1293
1294extern	__checkReturn		efx_rc_t
1295efx_vpd_next(
1296	__in			efx_nic_t *enp,
1297	__inout_bcount(size)	caddr_t data,
1298	__in			size_t size,
1299	__out			efx_vpd_value_t *evvp,
1300	__inout			unsigned int *contp);
1301
1302extern __checkReturn		efx_rc_t
1303efx_vpd_write(
1304	__in			efx_nic_t *enp,
1305	__in_bcount(size)	caddr_t data,
1306	__in			size_t size);
1307
1308extern				void
1309efx_vpd_fini(
1310	__in			efx_nic_t *enp);
1311
1312#endif	/* EFSYS_OPT_VPD */
1313
1314/* NVRAM */
1315
1316#if EFSYS_OPT_NVRAM
1317
1318typedef enum efx_nvram_type_e {
1319	EFX_NVRAM_INVALID = 0,
1320	EFX_NVRAM_BOOTROM,
1321	EFX_NVRAM_BOOTROM_CFG,
1322	EFX_NVRAM_MC_FIRMWARE,
1323	EFX_NVRAM_MC_GOLDEN,
1324	EFX_NVRAM_PHY,
1325	EFX_NVRAM_NULLPHY,
1326	EFX_NVRAM_FPGA,
1327	EFX_NVRAM_FCFW,
1328	EFX_NVRAM_CPLD,
1329	EFX_NVRAM_FPGA_BACKUP,
1330	EFX_NVRAM_DYNAMIC_CFG,
1331	EFX_NVRAM_LICENSE,
1332	EFX_NVRAM_NTYPES,
1333} efx_nvram_type_t;
1334
1335extern	__checkReturn		efx_rc_t
1336efx_nvram_init(
1337	__in			efx_nic_t *enp);
1338
1339#if EFSYS_OPT_DIAG
1340
1341extern	__checkReturn		efx_rc_t
1342efx_nvram_test(
1343	__in			efx_nic_t *enp);
1344
1345#endif	/* EFSYS_OPT_DIAG */
1346
1347extern	__checkReturn		efx_rc_t
1348efx_nvram_size(
1349	__in			efx_nic_t *enp,
1350	__in			efx_nvram_type_t type,
1351	__out			size_t *sizep);
1352
1353extern	__checkReturn		efx_rc_t
1354efx_nvram_rw_start(
1355	__in			efx_nic_t *enp,
1356	__in			efx_nvram_type_t type,
1357	__out_opt		size_t *pref_chunkp);
1358
1359extern				void
1360efx_nvram_rw_finish(
1361	__in			efx_nic_t *enp,
1362	__in			efx_nvram_type_t type);
1363
1364extern	__checkReturn		efx_rc_t
1365efx_nvram_get_version(
1366	__in			efx_nic_t *enp,
1367	__in			efx_nvram_type_t type,
1368	__out			uint32_t *subtypep,
1369	__out_ecount(4)		uint16_t version[4]);
1370
1371extern	__checkReturn		efx_rc_t
1372efx_nvram_read_chunk(
1373	__in			efx_nic_t *enp,
1374	__in			efx_nvram_type_t type,
1375	__in			unsigned int offset,
1376	__out_bcount(size)	caddr_t data,
1377	__in			size_t size);
1378
1379extern	__checkReturn		efx_rc_t
1380efx_nvram_set_version(
1381	__in			efx_nic_t *enp,
1382	__in			efx_nvram_type_t type,
1383	__in_ecount(4)		uint16_t version[4]);
1384
1385/* Validate contents of TLV formatted partition */
1386extern	__checkReturn		efx_rc_t
1387efx_nvram_tlv_validate(
1388	__in			efx_nic_t *enp,
1389	__in			uint32_t partn,
1390	__in_bcount(partn_size)	caddr_t partn_data,
1391	__in			size_t partn_size);
1392
1393extern	 __checkReturn		efx_rc_t
1394efx_nvram_erase(
1395	__in			efx_nic_t *enp,
1396	__in			efx_nvram_type_t type);
1397
1398extern	__checkReturn		efx_rc_t
1399efx_nvram_write_chunk(
1400	__in			efx_nic_t *enp,
1401	__in			efx_nvram_type_t type,
1402	__in			unsigned int offset,
1403	__in_bcount(size)	caddr_t data,
1404	__in			size_t size);
1405
1406extern				void
1407efx_nvram_fini(
1408	__in			efx_nic_t *enp);
1409
1410#endif	/* EFSYS_OPT_NVRAM */
1411
1412#if EFSYS_OPT_BOOTCFG
1413
1414extern				efx_rc_t
1415efx_bootcfg_read(
1416	__in			efx_nic_t *enp,
1417	__out_bcount(size)	caddr_t data,
1418	__in			size_t size);
1419
1420extern				efx_rc_t
1421efx_bootcfg_write(
1422	__in			efx_nic_t *enp,
1423	__in_bcount(size)	caddr_t data,
1424	__in			size_t size);
1425
1426#endif	/* EFSYS_OPT_BOOTCFG */
1427
1428#if EFSYS_OPT_WOL
1429
1430typedef enum efx_wol_type_e {
1431	EFX_WOL_TYPE_INVALID,
1432	EFX_WOL_TYPE_MAGIC,
1433	EFX_WOL_TYPE_BITMAP,
1434	EFX_WOL_TYPE_LINK,
1435	EFX_WOL_NTYPES,
1436} efx_wol_type_t;
1437
1438typedef enum efx_lightsout_offload_type_e {
1439	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1440	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1441	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1442} efx_lightsout_offload_type_t;
1443
1444#define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1445#define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1446
1447typedef union efx_wol_param_u {
1448	struct {
1449		uint8_t mac_addr[6];
1450	} ewp_magic;
1451	struct {
1452		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1453		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1454		uint8_t value_len;
1455	} ewp_bitmap;
1456} efx_wol_param_t;
1457
1458typedef union efx_lightsout_offload_param_u {
1459	struct {
1460		uint8_t mac_addr[6];
1461		uint32_t ip;
1462	} elop_arp;
1463	struct {
1464		uint8_t mac_addr[6];
1465		uint32_t solicited_node[4];
1466		uint32_t ip[4];
1467	} elop_ns;
1468} efx_lightsout_offload_param_t;
1469
1470extern	__checkReturn	efx_rc_t
1471efx_wol_init(
1472	__in		efx_nic_t *enp);
1473
1474extern	__checkReturn	efx_rc_t
1475efx_wol_filter_clear(
1476	__in		efx_nic_t *enp);
1477
1478extern	__checkReturn	efx_rc_t
1479efx_wol_filter_add(
1480	__in		efx_nic_t *enp,
1481	__in		efx_wol_type_t type,
1482	__in		efx_wol_param_t *paramp,
1483	__out		uint32_t *filter_idp);
1484
1485extern	__checkReturn	efx_rc_t
1486efx_wol_filter_remove(
1487	__in		efx_nic_t *enp,
1488	__in		uint32_t filter_id);
1489
1490extern	__checkReturn	efx_rc_t
1491efx_lightsout_offload_add(
1492	__in		efx_nic_t *enp,
1493	__in		efx_lightsout_offload_type_t type,
1494	__in		efx_lightsout_offload_param_t *paramp,
1495	__out		uint32_t *filter_idp);
1496
1497extern	__checkReturn	efx_rc_t
1498efx_lightsout_offload_remove(
1499	__in		efx_nic_t *enp,
1500	__in		efx_lightsout_offload_type_t type,
1501	__in		uint32_t filter_id);
1502
1503extern			void
1504efx_wol_fini(
1505	__in		efx_nic_t *enp);
1506
1507#endif	/* EFSYS_OPT_WOL */
1508
1509#if EFSYS_OPT_DIAG
1510
1511typedef enum efx_pattern_type_t {
1512	EFX_PATTERN_BYTE_INCREMENT = 0,
1513	EFX_PATTERN_ALL_THE_SAME,
1514	EFX_PATTERN_BIT_ALTERNATE,
1515	EFX_PATTERN_BYTE_ALTERNATE,
1516	EFX_PATTERN_BYTE_CHANGING,
1517	EFX_PATTERN_BIT_SWEEP,
1518	EFX_PATTERN_NTYPES
1519} efx_pattern_type_t;
1520
1521typedef 		void
1522(*efx_sram_pattern_fn_t)(
1523	__in		size_t row,
1524	__in		boolean_t negate,
1525	__out		efx_qword_t *eqp);
1526
1527extern	__checkReturn	efx_rc_t
1528efx_sram_test(
1529	__in		efx_nic_t *enp,
1530	__in		efx_pattern_type_t type);
1531
1532#endif	/* EFSYS_OPT_DIAG */
1533
1534extern	__checkReturn	efx_rc_t
1535efx_sram_buf_tbl_set(
1536	__in		efx_nic_t *enp,
1537	__in		uint32_t id,
1538	__in		efsys_mem_t *esmp,
1539	__in		size_t n);
1540
1541extern		void
1542efx_sram_buf_tbl_clear(
1543	__in	efx_nic_t *enp,
1544	__in	uint32_t id,
1545	__in	size_t n);
1546
1547#define	EFX_BUF_TBL_SIZE	0x20000
1548
1549#define	EFX_BUF_SIZE		4096
1550
1551/* EV */
1552
1553typedef struct efx_evq_s	efx_evq_t;
1554
1555#if EFSYS_OPT_QSTATS
1556
1557/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1558typedef enum efx_ev_qstat_e {
1559	EV_ALL,
1560	EV_RX,
1561	EV_RX_OK,
1562	EV_RX_FRM_TRUNC,
1563	EV_RX_TOBE_DISC,
1564	EV_RX_PAUSE_FRM_ERR,
1565	EV_RX_BUF_OWNER_ID_ERR,
1566	EV_RX_IPV4_HDR_CHKSUM_ERR,
1567	EV_RX_TCP_UDP_CHKSUM_ERR,
1568	EV_RX_ETH_CRC_ERR,
1569	EV_RX_IP_FRAG_ERR,
1570	EV_RX_MCAST_PKT,
1571	EV_RX_MCAST_HASH_MATCH,
1572	EV_RX_TCP_IPV4,
1573	EV_RX_TCP_IPV6,
1574	EV_RX_UDP_IPV4,
1575	EV_RX_UDP_IPV6,
1576	EV_RX_OTHER_IPV4,
1577	EV_RX_OTHER_IPV6,
1578	EV_RX_NON_IP,
1579	EV_RX_BATCH,
1580	EV_TX,
1581	EV_TX_WQ_FF_FULL,
1582	EV_TX_PKT_ERR,
1583	EV_TX_PKT_TOO_BIG,
1584	EV_TX_UNEXPECTED,
1585	EV_GLOBAL,
1586	EV_GLOBAL_MNT,
1587	EV_DRIVER,
1588	EV_DRIVER_SRM_UPD_DONE,
1589	EV_DRIVER_TX_DESCQ_FLS_DONE,
1590	EV_DRIVER_RX_DESCQ_FLS_DONE,
1591	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1592	EV_DRIVER_RX_DSC_ERROR,
1593	EV_DRIVER_TX_DSC_ERROR,
1594	EV_DRV_GEN,
1595	EV_MCDI_RESPONSE,
1596	EV_NQSTATS
1597} efx_ev_qstat_t;
1598
1599/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1600
1601#endif	/* EFSYS_OPT_QSTATS */
1602
1603extern	__checkReturn	efx_rc_t
1604efx_ev_init(
1605	__in		efx_nic_t *enp);
1606
1607extern		void
1608efx_ev_fini(
1609	__in		efx_nic_t *enp);
1610
1611#define	EFX_EVQ_MAXNEVS		32768
1612#define	EFX_EVQ_MINNEVS		512
1613
1614#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1615#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1616
1617extern	__checkReturn	efx_rc_t
1618efx_ev_qcreate(
1619	__in		efx_nic_t *enp,
1620	__in		unsigned int index,
1621	__in		efsys_mem_t *esmp,
1622	__in		size_t n,
1623	__in		uint32_t id,
1624	__deref_out	efx_evq_t **eepp);
1625
1626extern		void
1627efx_ev_qpost(
1628	__in		efx_evq_t *eep,
1629	__in		uint16_t data);
1630
1631typedef __checkReturn	boolean_t
1632(*efx_initialized_ev_t)(
1633	__in_opt	void *arg);
1634
1635#define	EFX_PKT_UNICAST		0x0004
1636#define	EFX_PKT_START		0x0008
1637
1638#define	EFX_PKT_VLAN_TAGGED	0x0010
1639#define	EFX_CKSUM_TCPUDP	0x0020
1640#define	EFX_CKSUM_IPV4		0x0040
1641#define	EFX_PKT_CONT		0x0080
1642
1643#define	EFX_CHECK_VLAN		0x0100
1644#define	EFX_PKT_TCP		0x0200
1645#define	EFX_PKT_UDP		0x0400
1646#define	EFX_PKT_IPV4		0x0800
1647
1648#define	EFX_PKT_IPV6		0x1000
1649#define	EFX_PKT_PREFIX_LEN	0x2000
1650#define	EFX_ADDR_MISMATCH	0x4000
1651#define	EFX_DISCARD		0x8000
1652
1653#define	EFX_EV_RX_NLABELS	32
1654#define	EFX_EV_TX_NLABELS	32
1655
1656typedef	__checkReturn	boolean_t
1657(*efx_rx_ev_t)(
1658	__in_opt	void *arg,
1659	__in		uint32_t label,
1660	__in		uint32_t id,
1661	__in		uint32_t size,
1662	__in		uint16_t flags);
1663
1664typedef	__checkReturn	boolean_t
1665(*efx_tx_ev_t)(
1666	__in_opt	void *arg,
1667	__in		uint32_t label,
1668	__in		uint32_t id);
1669
1670#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1671#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1672#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1673#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1674#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1675#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1676#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1677#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1678#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1679
1680typedef	__checkReturn	boolean_t
1681(*efx_exception_ev_t)(
1682	__in_opt	void *arg,
1683	__in		uint32_t label,
1684	__in		uint32_t data);
1685
1686typedef	__checkReturn	boolean_t
1687(*efx_rxq_flush_done_ev_t)(
1688	__in_opt	void *arg,
1689	__in		uint32_t rxq_index);
1690
1691typedef	__checkReturn	boolean_t
1692(*efx_rxq_flush_failed_ev_t)(
1693	__in_opt	void *arg,
1694	__in		uint32_t rxq_index);
1695
1696typedef	__checkReturn	boolean_t
1697(*efx_txq_flush_done_ev_t)(
1698	__in_opt	void *arg,
1699	__in		uint32_t txq_index);
1700
1701typedef	__checkReturn	boolean_t
1702(*efx_software_ev_t)(
1703	__in_opt	void *arg,
1704	__in		uint16_t magic);
1705
1706typedef	__checkReturn	boolean_t
1707(*efx_sram_ev_t)(
1708	__in_opt	void *arg,
1709	__in		uint32_t code);
1710
1711#define	EFX_SRAM_CLEAR		0
1712#define	EFX_SRAM_UPDATE		1
1713#define	EFX_SRAM_ILLEGAL_CLEAR	2
1714
1715typedef	__checkReturn	boolean_t
1716(*efx_wake_up_ev_t)(
1717	__in_opt	void *arg,
1718	__in		uint32_t label);
1719
1720typedef	__checkReturn	boolean_t
1721(*efx_timer_ev_t)(
1722	__in_opt	void *arg,
1723	__in		uint32_t label);
1724
1725typedef __checkReturn	boolean_t
1726(*efx_link_change_ev_t)(
1727	__in_opt	void *arg,
1728	__in		efx_link_mode_t	link_mode);
1729
1730#if EFSYS_OPT_MON_STATS
1731
1732typedef __checkReturn	boolean_t
1733(*efx_monitor_ev_t)(
1734	__in_opt	void *arg,
1735	__in		efx_mon_stat_t id,
1736	__in		efx_mon_stat_value_t value);
1737
1738#endif	/* EFSYS_OPT_MON_STATS */
1739
1740#if EFSYS_OPT_MAC_STATS
1741
1742typedef __checkReturn	boolean_t
1743(*efx_mac_stats_ev_t)(
1744	__in_opt	void *arg,
1745	__in		uint32_t generation
1746	);
1747
1748#endif	/* EFSYS_OPT_MAC_STATS */
1749
1750typedef struct efx_ev_callbacks_s {
1751	efx_initialized_ev_t		eec_initialized;
1752	efx_rx_ev_t			eec_rx;
1753	efx_tx_ev_t			eec_tx;
1754	efx_exception_ev_t		eec_exception;
1755	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1756	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1757	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1758	efx_software_ev_t		eec_software;
1759	efx_sram_ev_t			eec_sram;
1760	efx_wake_up_ev_t		eec_wake_up;
1761	efx_timer_ev_t			eec_timer;
1762	efx_link_change_ev_t		eec_link_change;
1763#if EFSYS_OPT_MON_STATS
1764	efx_monitor_ev_t		eec_monitor;
1765#endif	/* EFSYS_OPT_MON_STATS */
1766#if EFSYS_OPT_MAC_STATS
1767	efx_mac_stats_ev_t		eec_mac_stats;
1768#endif	/* EFSYS_OPT_MAC_STATS */
1769} efx_ev_callbacks_t;
1770
1771extern	__checkReturn	boolean_t
1772efx_ev_qpending(
1773	__in		efx_evq_t *eep,
1774	__in		unsigned int count);
1775
1776#if EFSYS_OPT_EV_PREFETCH
1777
1778extern			void
1779efx_ev_qprefetch(
1780	__in		efx_evq_t *eep,
1781	__in		unsigned int count);
1782
1783#endif	/* EFSYS_OPT_EV_PREFETCH */
1784
1785extern			void
1786efx_ev_qpoll(
1787	__in		efx_evq_t *eep,
1788	__inout		unsigned int *countp,
1789	__in		const efx_ev_callbacks_t *eecp,
1790	__in_opt	void *arg);
1791
1792extern	__checkReturn	efx_rc_t
1793efx_ev_qmoderate(
1794	__in		efx_evq_t *eep,
1795	__in		unsigned int us);
1796
1797extern	__checkReturn	efx_rc_t
1798efx_ev_qprime(
1799	__in		efx_evq_t *eep,
1800	__in		unsigned int count);
1801
1802#if EFSYS_OPT_QSTATS
1803
1804#if EFSYS_OPT_NAMES
1805
1806extern		const char *
1807efx_ev_qstat_name(
1808	__in	efx_nic_t *enp,
1809	__in	unsigned int id);
1810
1811#endif	/* EFSYS_OPT_NAMES */
1812
1813extern					void
1814efx_ev_qstats_update(
1815	__in				efx_evq_t *eep,
1816	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1817
1818#endif	/* EFSYS_OPT_QSTATS */
1819
1820extern		void
1821efx_ev_qdestroy(
1822	__in	efx_evq_t *eep);
1823
1824/* RX */
1825
1826extern	__checkReturn	efx_rc_t
1827efx_rx_init(
1828	__inout		efx_nic_t *enp);
1829
1830extern		void
1831efx_rx_fini(
1832	__in		efx_nic_t *enp);
1833
1834#if EFSYS_OPT_RX_SCATTER
1835	__checkReturn	efx_rc_t
1836efx_rx_scatter_enable(
1837	__in		efx_nic_t *enp,
1838	__in		unsigned int buf_size);
1839#endif	/* EFSYS_OPT_RX_SCATTER */
1840
1841#if EFSYS_OPT_RX_SCALE
1842
1843typedef enum efx_rx_hash_alg_e {
1844	EFX_RX_HASHALG_LFSR = 0,
1845	EFX_RX_HASHALG_TOEPLITZ
1846} efx_rx_hash_alg_t;
1847
1848typedef enum efx_rx_hash_type_e {
1849	EFX_RX_HASH_IPV4 = 0,
1850	EFX_RX_HASH_TCPIPV4,
1851	EFX_RX_HASH_IPV6,
1852	EFX_RX_HASH_TCPIPV6,
1853} efx_rx_hash_type_t;
1854
1855typedef enum efx_rx_hash_support_e {
1856	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1857	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1858} efx_rx_hash_support_t;
1859
1860#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1861#define	EFX_MAXRSS	    	64	/* RX indirection entry range */
1862#define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
1863
1864typedef enum efx_rx_scale_support_e {
1865	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1866	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1867	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1868} efx_rx_scale_support_t;
1869
1870extern	__checkReturn	efx_rc_t
1871efx_rx_hash_support_get(
1872	__in		efx_nic_t *enp,
1873	__out		efx_rx_hash_support_t *supportp);
1874
1875
1876extern	__checkReturn	efx_rc_t
1877efx_rx_scale_support_get(
1878	__in		efx_nic_t *enp,
1879	__out		efx_rx_scale_support_t *supportp);
1880
1881extern	__checkReturn	efx_rc_t
1882efx_rx_scale_mode_set(
1883	__in	efx_nic_t *enp,
1884	__in	efx_rx_hash_alg_t alg,
1885	__in	efx_rx_hash_type_t type,
1886	__in	boolean_t insert);
1887
1888extern	__checkReturn	efx_rc_t
1889efx_rx_scale_tbl_set(
1890	__in		efx_nic_t *enp,
1891	__in_ecount(n)	unsigned int *table,
1892	__in		size_t n);
1893
1894extern	__checkReturn	efx_rc_t
1895efx_rx_scale_key_set(
1896	__in		efx_nic_t *enp,
1897	__in_ecount(n)	uint8_t *key,
1898	__in		size_t n);
1899
1900extern	__checkReturn	uint32_t
1901efx_psuedo_hdr_hash_get(
1902	__in		efx_nic_t *enp,
1903	__in		efx_rx_hash_alg_t func,
1904	__in		uint8_t *buffer);
1905
1906#endif	/* EFSYS_OPT_RX_SCALE */
1907
1908extern	__checkReturn	efx_rc_t
1909efx_psuedo_hdr_pkt_length_get(
1910	__in		efx_nic_t *enp,
1911	__in		uint8_t *buffer,
1912	__out		uint16_t *pkt_lengthp);
1913
1914#define	EFX_RXQ_MAXNDESCS		4096
1915#define	EFX_RXQ_MINNDESCS		512
1916
1917#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1918#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1919#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1920#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1921
1922typedef enum efx_rxq_type_e {
1923	EFX_RXQ_TYPE_DEFAULT,
1924	EFX_RXQ_TYPE_SCATTER,
1925	EFX_RXQ_NTYPES
1926} efx_rxq_type_t;
1927
1928extern	__checkReturn	efx_rc_t
1929efx_rx_qcreate(
1930	__in		efx_nic_t *enp,
1931	__in		unsigned int index,
1932	__in		unsigned int label,
1933	__in		efx_rxq_type_t type,
1934	__in		efsys_mem_t *esmp,
1935	__in		size_t n,
1936	__in		uint32_t id,
1937	__in		efx_evq_t *eep,
1938	__deref_out	efx_rxq_t **erpp);
1939
1940typedef struct efx_buffer_s {
1941	efsys_dma_addr_t	eb_addr;
1942	size_t			eb_size;
1943	boolean_t		eb_eop;
1944} efx_buffer_t;
1945
1946typedef struct efx_desc_s {
1947	efx_qword_t ed_eq;
1948} efx_desc_t;
1949
1950extern			void
1951efx_rx_qpost(
1952	__in		efx_rxq_t *erp,
1953	__in_ecount(n)	efsys_dma_addr_t *addrp,
1954	__in		size_t size,
1955	__in		unsigned int n,
1956	__in		unsigned int completed,
1957	__in		unsigned int added);
1958
1959extern		void
1960efx_rx_qpush(
1961	__in	efx_rxq_t *erp,
1962	__in	unsigned int added,
1963	__inout	unsigned int *pushedp);
1964
1965extern	__checkReturn	efx_rc_t
1966efx_rx_qflush(
1967	__in	efx_rxq_t *erp);
1968
1969extern		void
1970efx_rx_qenable(
1971	__in	efx_rxq_t *erp);
1972
1973extern		void
1974efx_rx_qdestroy(
1975	__in	efx_rxq_t *erp);
1976
1977/* TX */
1978
1979typedef struct efx_txq_s	efx_txq_t;
1980
1981#if EFSYS_OPT_QSTATS
1982
1983/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1984typedef enum efx_tx_qstat_e {
1985	TX_POST,
1986	TX_POST_PIO,
1987	TX_NQSTATS
1988} efx_tx_qstat_t;
1989
1990/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1991
1992#endif	/* EFSYS_OPT_QSTATS */
1993
1994extern	__checkReturn	efx_rc_t
1995efx_tx_init(
1996	__in		efx_nic_t *enp);
1997
1998extern		void
1999efx_tx_fini(
2000	__in	efx_nic_t *enp);
2001
2002#define	EFX_BUG35388_WORKAROUND(_encp)					\
2003	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2004
2005#define	EFX_TXQ_MAXNDESCS(_encp)					\
2006	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2007
2008#define	EFX_TXQ_MINNDESCS		512
2009
2010#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2011#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2012#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2013#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2014
2015#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2016
2017#define	EFX_TXQ_CKSUM_IPV4	0x0001
2018#define	EFX_TXQ_CKSUM_TCPUDP	0x0002
2019#define	EFX_TXQ_FATSOV2		0x0004
2020
2021extern	__checkReturn	efx_rc_t
2022efx_tx_qcreate(
2023	__in		efx_nic_t *enp,
2024	__in		unsigned int index,
2025	__in		unsigned int label,
2026	__in		efsys_mem_t *esmp,
2027	__in		size_t n,
2028	__in		uint32_t id,
2029	__in		uint16_t flags,
2030	__in		efx_evq_t *eep,
2031	__deref_out	efx_txq_t **etpp,
2032	__out		unsigned int *addedp);
2033
2034extern	__checkReturn	efx_rc_t
2035efx_tx_qpost(
2036	__in		efx_txq_t *etp,
2037	__in_ecount(n)	efx_buffer_t *eb,
2038	__in		unsigned int n,
2039	__in		unsigned int completed,
2040	__inout		unsigned int *addedp);
2041
2042extern	__checkReturn	efx_rc_t
2043efx_tx_qpace(
2044	__in		efx_txq_t *etp,
2045	__in		unsigned int ns);
2046
2047extern			void
2048efx_tx_qpush(
2049	__in		efx_txq_t *etp,
2050	__in		unsigned int added,
2051	__in		unsigned int pushed);
2052
2053extern	__checkReturn	efx_rc_t
2054efx_tx_qflush(
2055	__in		efx_txq_t *etp);
2056
2057extern			void
2058efx_tx_qenable(
2059	__in		efx_txq_t *etp);
2060
2061extern	__checkReturn	efx_rc_t
2062efx_tx_qpio_enable(
2063	__in		efx_txq_t *etp);
2064
2065extern			void
2066efx_tx_qpio_disable(
2067	__in		efx_txq_t *etp);
2068
2069extern	__checkReturn	efx_rc_t
2070efx_tx_qpio_write(
2071	__in			efx_txq_t *etp,
2072	__in_ecount(buf_length)	uint8_t *buffer,
2073	__in			size_t buf_length,
2074	__in                    size_t pio_buf_offset);
2075
2076extern	__checkReturn	efx_rc_t
2077efx_tx_qpio_post(
2078	__in			efx_txq_t *etp,
2079	__in			size_t pkt_length,
2080	__in			unsigned int completed,
2081	__inout			unsigned int *addedp);
2082
2083extern	__checkReturn	efx_rc_t
2084efx_tx_qdesc_post(
2085	__in		efx_txq_t *etp,
2086	__in_ecount(n)	efx_desc_t *ed,
2087	__in		unsigned int n,
2088	__in		unsigned int completed,
2089	__inout		unsigned int *addedp);
2090
2091extern	void
2092efx_tx_qdesc_dma_create(
2093	__in	efx_txq_t *etp,
2094	__in	efsys_dma_addr_t addr,
2095	__in	size_t size,
2096	__in	boolean_t eop,
2097	__out	efx_desc_t *edp);
2098
2099extern	void
2100efx_tx_qdesc_tso_create(
2101	__in	efx_txq_t *etp,
2102	__in	uint16_t ipv4_id,
2103	__in	uint32_t tcp_seq,
2104	__in	uint8_t  tcp_flags,
2105	__out	efx_desc_t *edp);
2106
2107/* Number of FATSOv2 option descriptors */
2108#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2109
2110/* Maximum number of DMA segments per TSO packet (not superframe) */
2111#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2112
2113extern	void
2114efx_tx_qdesc_tso2_create(
2115	__in			efx_txq_t *etp,
2116	__in			uint16_t ipv4_id,
2117	__in			uint32_t tcp_seq,
2118	__in			uint16_t tcp_mss,
2119	__out_ecount(count)	efx_desc_t *edp,
2120	__in			int count);
2121
2122extern	void
2123efx_tx_qdesc_vlantci_create(
2124	__in	efx_txq_t *etp,
2125	__in	uint16_t tci,
2126	__out	efx_desc_t *edp);
2127
2128#if EFSYS_OPT_QSTATS
2129
2130#if EFSYS_OPT_NAMES
2131
2132extern		const char *
2133efx_tx_qstat_name(
2134	__in	efx_nic_t *etp,
2135	__in	unsigned int id);
2136
2137#endif	/* EFSYS_OPT_NAMES */
2138
2139extern					void
2140efx_tx_qstats_update(
2141	__in				efx_txq_t *etp,
2142	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2143
2144#endif	/* EFSYS_OPT_QSTATS */
2145
2146extern		void
2147efx_tx_qdestroy(
2148	__in	efx_txq_t *etp);
2149
2150
2151/* FILTER */
2152
2153#if EFSYS_OPT_FILTER
2154
2155#define	EFX_ETHER_TYPE_IPV4 0x0800
2156#define	EFX_ETHER_TYPE_IPV6 0x86DD
2157
2158#define	EFX_IPPROTO_TCP 6
2159#define	EFX_IPPROTO_UDP 17
2160
2161typedef enum efx_filter_flag_e {
2162	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2163						 * multiple queues */
2164	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2165	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2166						 * (priority EFX_FILTER_PRI_AUTO).
2167						 * May only be set by the filter
2168						 * implementation for each type.
2169						 * A removal request will
2170						 * restore the automatic filter
2171						 * in its place. */
2172	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2173	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2174} efx_filter_flag_t;
2175
2176typedef enum efx_filter_match_flags_e {
2177	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2178						 * address */
2179	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2180						 * address */
2181	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2182	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2183	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2184	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2185	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2186	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2187	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2188	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2189						 * protocol */
2190	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2191						 * I/G bit. Used for RX default
2192						 * unicast and multicast/
2193						 * broadcast filters. */
2194} efx_filter_match_flags_t;
2195
2196typedef enum efx_filter_priority_s {
2197	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2198	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2199					 * address list or hardware
2200					 * requirements. This may only be used
2201					 * by the filter implementation for
2202					 * each NIC type. */
2203	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2204	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2205					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2206					 */
2207} efx_filter_priority_t;
2208
2209/*
2210 * FIXME: All these fields are assumed to be in little-endian byte order.
2211 * It may be better for some to be big-endian. See bug42804.
2212 */
2213
2214typedef struct efx_filter_spec_s {
2215	uint32_t	efs_match_flags:12;
2216	uint32_t	efs_priority:2;
2217	uint32_t	efs_flags:6;
2218	uint32_t	efs_dmaq_id:12;
2219	uint32_t	efs_rss_context;
2220	uint16_t	efs_outer_vid;
2221	uint16_t	efs_inner_vid;
2222	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2223	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2224	uint16_t	efs_ether_type;
2225	uint8_t		efs_ip_proto;
2226	uint16_t	efs_loc_port;
2227	uint16_t	efs_rem_port;
2228	efx_oword_t	efs_rem_host;
2229	efx_oword_t	efs_loc_host;
2230} efx_filter_spec_t;
2231
2232
2233/* Default values for use in filter specifications */
2234#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2235#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2236#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2237
2238extern	__checkReturn	efx_rc_t
2239efx_filter_init(
2240	__in		efx_nic_t *enp);
2241
2242extern			void
2243efx_filter_fini(
2244	__in		efx_nic_t *enp);
2245
2246extern	__checkReturn	efx_rc_t
2247efx_filter_insert(
2248	__in		efx_nic_t *enp,
2249	__inout		efx_filter_spec_t *spec);
2250
2251extern	__checkReturn	efx_rc_t
2252efx_filter_remove(
2253	__in		efx_nic_t *enp,
2254	__inout		efx_filter_spec_t *spec);
2255
2256extern	__checkReturn	efx_rc_t
2257efx_filter_restore(
2258	__in		efx_nic_t *enp);
2259
2260extern	__checkReturn	efx_rc_t
2261efx_filter_supported_filters(
2262	__in		efx_nic_t *enp,
2263	__out		uint32_t *list,
2264	__out		size_t *length);
2265
2266extern			void
2267efx_filter_spec_init_rx(
2268	__out		efx_filter_spec_t *spec,
2269	__in		efx_filter_priority_t priority,
2270	__in		efx_filter_flag_t flags,
2271	__in		efx_rxq_t *erp);
2272
2273extern			void
2274efx_filter_spec_init_tx(
2275	__out		efx_filter_spec_t *spec,
2276	__in		efx_txq_t *etp);
2277
2278extern	__checkReturn	efx_rc_t
2279efx_filter_spec_set_ipv4_local(
2280	__inout		efx_filter_spec_t *spec,
2281	__in		uint8_t proto,
2282	__in		uint32_t host,
2283	__in		uint16_t port);
2284
2285extern	__checkReturn	efx_rc_t
2286efx_filter_spec_set_ipv4_full(
2287	__inout		efx_filter_spec_t *spec,
2288	__in		uint8_t proto,
2289	__in		uint32_t lhost,
2290	__in		uint16_t lport,
2291	__in		uint32_t rhost,
2292	__in		uint16_t rport);
2293
2294extern	__checkReturn	efx_rc_t
2295efx_filter_spec_set_eth_local(
2296	__inout		efx_filter_spec_t *spec,
2297	__in		uint16_t vid,
2298	__in		const uint8_t *addr);
2299
2300extern	__checkReturn	efx_rc_t
2301efx_filter_spec_set_uc_def(
2302	__inout		efx_filter_spec_t *spec);
2303
2304extern	__checkReturn	efx_rc_t
2305efx_filter_spec_set_mc_def(
2306	__inout		efx_filter_spec_t *spec);
2307
2308#endif	/* EFSYS_OPT_FILTER */
2309
2310/* HASH */
2311
2312extern	__checkReturn		uint32_t
2313efx_hash_dwords(
2314	__in_ecount(count)	uint32_t const *input,
2315	__in			size_t count,
2316	__in			uint32_t init);
2317
2318extern	__checkReturn		uint32_t
2319efx_hash_bytes(
2320	__in_ecount(length)	uint8_t const *input,
2321	__in			size_t length,
2322	__in			uint32_t init);
2323
2324#if EFSYS_OPT_LICENSING
2325
2326/* LICENSING */
2327
2328typedef struct efx_key_stats_s {
2329	uint32_t	eks_valid;
2330	uint32_t	eks_invalid;
2331	uint32_t	eks_blacklisted;
2332	uint32_t	eks_unverifiable;
2333	uint32_t	eks_wrong_node;
2334	uint32_t	eks_licensed_apps_lo;
2335	uint32_t	eks_licensed_apps_hi;
2336	uint32_t	eks_licensed_features_lo;
2337	uint32_t	eks_licensed_features_hi;
2338} efx_key_stats_t;
2339
2340extern	__checkReturn		efx_rc_t
2341efx_lic_init(
2342	__in			efx_nic_t *enp);
2343
2344extern				void
2345efx_lic_fini(
2346	__in			efx_nic_t *enp);
2347
2348extern	__checkReturn	efx_rc_t
2349efx_lic_update_licenses(
2350	__in		efx_nic_t *enp);
2351
2352extern	__checkReturn	efx_rc_t
2353efx_lic_get_key_stats(
2354	__in		efx_nic_t *enp,
2355	__out		efx_key_stats_t *ksp);
2356
2357extern	__checkReturn	efx_rc_t
2358efx_lic_app_state(
2359	__in		efx_nic_t *enp,
2360	__in		uint64_t app_id,
2361	__out		boolean_t *licensedp);
2362
2363extern	__checkReturn	efx_rc_t
2364efx_lic_get_id(
2365	__in		efx_nic_t *enp,
2366	__in		size_t buffer_size,
2367	__out		uint32_t *typep,
2368	__out		size_t *lengthp,
2369	__out_opt	uint8_t *bufferp);
2370
2371
2372#endif	/* EFSYS_OPT_LICENSING */
2373
2374
2375
2376#ifdef	__cplusplus
2377}
2378#endif
2379
2380#endif	/* _SYS_EFX_H */
2381