efx.h revision 293981
1218893Sdim/*- 2212793Sdim * Copyright (c) 2006-2015 Solarflare Communications Inc. 3212793Sdim * All rights reserved. 4212793Sdim * 5212793Sdim * Redistribution and use in source and binary forms, with or without 6212793Sdim * modification, are permitted provided that the following conditions are met: 7212793Sdim * 8212793Sdim * 1. Redistributions of source code must retain the above copyright notice, 9212793Sdim * this list of conditions and the following disclaimer. 10212793Sdim * 2. Redistributions in binary form must reproduce the above copyright notice, 11212793Sdim * this list of conditions and the following disclaimer in the documentation 12212793Sdim * and/or other materials provided with the distribution. 13212793Sdim * 14212793Sdim * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15221345Sdim * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16221345Sdim * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17221345Sdim * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18226633Sdim * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19221345Sdim * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20218893Sdim * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21218893Sdim * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22212793Sdim * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23212793Sdim * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24212793Sdim * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25212793Sdim * 26218893Sdim * The views and conclusions contained in the software and documentation are 27212793Sdim * those of the authors and should not be interpreted as representing official 28212793Sdim * policies, either expressed or implied, of the FreeBSD Project. 29218893Sdim * 30263508Sdim * $FreeBSD: stable/10/sys/dev/sfxge/common/efx.h 293981 2016-01-14 15:54:13Z arybchik $ 31212793Sdim */ 32212793Sdim 33212793Sdim#ifndef _SYS_EFX_H 34212793Sdim#define _SYS_EFX_H 35218893Sdim 36212793Sdim#include "efsys.h" 37212793Sdim#include "efx_phy_ids.h" 38218893Sdim 39212793Sdim#ifdef __cplusplus 40212793Sdimextern "C" { 41212793Sdim#endif 42212793Sdim 43212793Sdim#define EFX_STATIC_ASSERT(_cond) \ 44218893Sdim ((void)sizeof(char[(_cond) ? 1 : -1])) 45218893Sdim 46218893Sdim#define EFX_ARRAY_SIZE(_array) \ 47218893Sdim (sizeof(_array) / sizeof((_array)[0])) 48218893Sdim 49212793Sdim#define EFX_FIELD_OFFSET(_type, _field) \ 50218893Sdim ((size_t) &(((_type *)0)->_field)) 51218893Sdim 52218893Sdim/* Return codes */ 53218893Sdim 54218893Sdimtypedef __success(return == 0) int efx_rc_t; 55218893Sdim 56223017Sdim 57218893Sdim/* Chip families */ 58223017Sdim 59218893Sdimtypedef enum efx_family_e { 60223017Sdim EFX_FAMILY_INVALID, 61223017Sdim EFX_FAMILY_FALCON, 62223017Sdim EFX_FAMILY_SIENA, 63223017Sdim EFX_FAMILY_HUNTINGTON, 64223017Sdim EFX_FAMILY_MEDFORD, 65223017Sdim EFX_FAMILY_NTYPES 66223017Sdim} efx_family_t; 67218893Sdim 68218893Sdimextern __checkReturn efx_rc_t 69226633Sdimefx_family( 70226633Sdim __in uint16_t venid, 71226633Sdim __in uint16_t devid, 72218893Sdim __out efx_family_t *efp); 73218893Sdim 74224145Sdimextern __checkReturn efx_rc_t 75224145Sdimefx_infer_family( 76224145Sdim __in efsys_bar_t *esbp, 77224145Sdim __out efx_family_t *efp); 78226633Sdim 79224145Sdim#define EFX_PCI_VENID_SFC 0x1924 80218893Sdim 81218893Sdim#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 82212793Sdim 83212793Sdim#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 84218893Sdim#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 85212793Sdim#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 86234353Sdim 87234353Sdim#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 88234353Sdim#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 89221345Sdim#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 90221345Sdim 91221345Sdim#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 92221345Sdim#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 93221345Sdim 94221345Sdim#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 95221345Sdim#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 96221345Sdim#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 97221345Sdim 98223017Sdim#define EFX_MEM_BAR 2 99223017Sdim 100223017Sdim/* Error codes */ 101223017Sdim 102221345Sdimenum { 103221345Sdim EFX_ERR_INVALID, 104221345Sdim EFX_ERR_SRAM_OOB, 105221345Sdim EFX_ERR_BUFID_DC_OOB, 106221345Sdim EFX_ERR_MEM_PERR, 107221345Sdim EFX_ERR_RBUF_OWN, 108223017Sdim EFX_ERR_TBUF_OWN, 109223017Sdim EFX_ERR_RDESQ_OWN, 110223017Sdim EFX_ERR_TDESQ_OWN, 111221345Sdim EFX_ERR_EVQ_OWN, 112221345Sdim EFX_ERR_EVFF_OFLO, 113218893Sdim EFX_ERR_ILL_ADDR, 114212793Sdim EFX_ERR_SRAM_PERR, 115212793Sdim EFX_ERR_NCODES 116218893Sdim}; 117221345Sdim 118218893Sdim/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 119212793Sdimextern __checkReturn uint32_t 120218893Sdimefx_crc32_calculate( 121212793Sdim __in uint32_t crc_init, 122212793Sdim __in_ecount(length) uint8_t const *input, 123218893Sdim __in int length); 124212793Sdim 125212793Sdim 126212793Sdim/* Type prototypes */ 127223017Sdim 128223017Sdimtypedef struct efx_rxq_s efx_rxq_t; 129223017Sdim 130223017Sdim/* NIC */ 131223017Sdim 132212793Sdimtypedef struct efx_nic_s efx_nic_t; 133212793Sdim 134212793Sdim#define EFX_NIC_FUNC_PRIMARY 0x00000001 135212793Sdim#define EFX_NIC_FUNC_LINKCTRL 0x00000002 136218893Sdim#define EFX_NIC_FUNC_TRUSTED 0x00000004 137218893Sdim 138212793Sdim 139234353Sdimextern __checkReturn efx_rc_t 140221345Sdimefx_nic_create( 141221345Sdim __in efx_family_t family, 142221345Sdim __in efsys_identifier_t *esip, 143221345Sdim __in efsys_bar_t *esbp, 144221345Sdim __in efsys_lock_t *eslp, 145221345Sdim __deref_out efx_nic_t **enpp); 146221345Sdim 147218893Sdimextern __checkReturn efx_rc_t 148212793Sdimefx_nic_probe( 149234353Sdim __in efx_nic_t *enp); 150234353Sdim 151234353Sdim#if EFSYS_OPT_PCIE_TUNE 152219077Sdim 153219077Sdimextern __checkReturn efx_rc_t 154219077Sdimefx_nic_pcie_tune( 155219077Sdim __in efx_nic_t *enp, 156219077Sdim unsigned int nlanes); 157219077Sdim 158219077Sdimextern __checkReturn efx_rc_t 159234353Sdimefx_nic_pcie_extended_sync( 160234353Sdim __in efx_nic_t *enp); 161234353Sdim 162234353Sdim#endif /* EFSYS_OPT_PCIE_TUNE */ 163221345Sdim 164221345Sdimextern __checkReturn efx_rc_t 165223017Sdimefx_nic_init( 166221345Sdim __in efx_nic_t *enp); 167221345Sdim 168221345Sdimextern __checkReturn efx_rc_t 169221345Sdimefx_nic_reset( 170221345Sdim __in efx_nic_t *enp); 171221345Sdim 172221345Sdim#if EFSYS_OPT_DIAG 173221345Sdim 174221345Sdimextern __checkReturn efx_rc_t 175221345Sdimefx_nic_register_test( 176223017Sdim __in efx_nic_t *enp); 177223017Sdim 178223017Sdim#endif /* EFSYS_OPT_DIAG */ 179223017Sdim 180223017Sdimextern void 181223017Sdimefx_nic_fini( 182223017Sdim __in efx_nic_t *enp); 183223017Sdim 184221345Sdimextern void 185221345Sdimefx_nic_unprobe( 186218893Sdim __in efx_nic_t *enp); 187212793Sdim 188226633Sdimextern void 189226633Sdimefx_nic_destroy( 190226633Sdim __in efx_nic_t *enp); 191226633Sdim 192226633Sdim#if EFSYS_OPT_MCDI 193226633Sdim 194226633Sdim#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 195226633Sdim/* Huntington and Medford require MCDIv2 commands */ 196226633Sdim#define WITH_MCDI_V2 1 197212793Sdim#endif 198212793Sdim 199212793Sdimtypedef struct efx_mcdi_req_s efx_mcdi_req_t; 200212793Sdim 201212793Sdimtypedef enum efx_mcdi_exception_e { 202212793Sdim EFX_MCDI_EXCEPTION_MC_REBOOT, 203212793Sdim EFX_MCDI_EXCEPTION_MC_BADASSERT, 204212793Sdim} efx_mcdi_exception_t; 205212793Sdim 206212793Sdim#if EFSYS_OPT_MCDI_LOGGING 207212793Sdimtypedef enum efx_log_msg_e 208212793Sdim{ 209218893Sdim EFX_LOG_INVALID, 210212793Sdim EFX_LOG_MCDI_REQUEST, 211212793Sdim EFX_LOG_MCDI_RESPONSE, 212218893Sdim} efx_log_msg_t; 213218893Sdim#endif /* EFSYS_OPT_MCDI_LOGGING */ 214218893Sdim 215218893Sdimtypedef struct efx_mcdi_transport_s { 216218893Sdim void *emt_context; 217218893Sdim efsys_mem_t *emt_dma_mem; 218218893Sdim void (*emt_execute)(void *, efx_mcdi_req_t *); 219263508Sdim void (*emt_ev_cpl)(void *); 220212793Sdim void (*emt_exception)(void *, efx_mcdi_exception_t); 221226633Sdim#if EFSYS_OPT_MCDI_LOGGING 222226633Sdim void (*emt_logger)(void *, efx_log_msg_t, 223226633Sdim void *, size_t, void *, size_t); 224226633Sdim#endif /* EFSYS_OPT_MCDI_LOGGING */ 225226633Sdim#if EFSYS_OPT_MCDI_PROXY_AUTH 226226633Sdim void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 227226633Sdim#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 228226633Sdim} efx_mcdi_transport_t; 229226633Sdim 230226633Sdimextern __checkReturn efx_rc_t 231226633Sdimefx_mcdi_init( 232226633Sdim __in efx_nic_t *enp, 233226633Sdim __in const efx_mcdi_transport_t *mtp); 234226633Sdim 235226633Sdimextern __checkReturn efx_rc_t 236226633Sdimefx_mcdi_reboot( 237226633Sdim __in efx_nic_t *enp); 238226633Sdim 239226633Sdim void 240226633Sdimefx_mcdi_new_epoch( 241226633Sdim __in efx_nic_t *enp); 242226633Sdim 243226633Sdimextern void 244226633Sdimefx_mcdi_request_start( 245226633Sdim __in efx_nic_t *enp, 246226633Sdim __in efx_mcdi_req_t *emrp, 247226633Sdim __in boolean_t ev_cpl); 248226633Sdim 249226633Sdimextern __checkReturn boolean_t 250226633Sdimefx_mcdi_request_poll( 251218893Sdim __in efx_nic_t *enp); 252221345Sdim 253212793Sdimextern __checkReturn boolean_t 254218893Sdimefx_mcdi_request_abort( 255218893Sdim __in efx_nic_t *enp); 256218893Sdim 257218893Sdimextern void 258212793Sdimefx_mcdi_fini( 259226633Sdim __in efx_nic_t *enp); 260226633Sdim 261226633Sdim#endif /* EFSYS_OPT_MCDI */ 262218893Sdim 263212793Sdim/* INTR */ 264218893Sdim 265218893Sdim#define EFX_NINTR_FALCON 64 266218893Sdim#define EFX_NINTR_SIENA 1024 267212793Sdim 268218893Sdimtypedef enum efx_intr_type_e { 269218893Sdim EFX_INTR_INVALID = 0, 270218893Sdim EFX_INTR_LINE, 271218893Sdim EFX_INTR_MESSAGE, 272212793Sdim EFX_INTR_NTYPES 273226633Sdim} efx_intr_type_t; 274226633Sdim 275212793Sdim#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 276221345Sdim 277221345Sdimextern __checkReturn efx_rc_t 278221345Sdimefx_intr_init( 279221345Sdim __in efx_nic_t *enp, 280226633Sdim __in efx_intr_type_t type, 281226633Sdim __in efsys_mem_t *esmp); 282226633Sdim 283226633Sdimextern void 284226633Sdimefx_intr_enable( 285226633Sdim __in efx_nic_t *enp); 286226633Sdim 287221345Sdimextern void 288221345Sdimefx_intr_disable( 289221345Sdim __in efx_nic_t *enp); 290226633Sdim 291226633Sdimextern void 292226633Sdimefx_intr_disable_unlocked( 293226633Sdim __in efx_nic_t *enp); 294221345Sdim 295226633Sdim#define EFX_INTR_NEVQS 32 296226633Sdim 297226633Sdimextern __checkReturn efx_rc_t 298226633Sdimefx_intr_trigger( 299226633Sdim __in efx_nic_t *enp, 300226633Sdim __in unsigned int level); 301221345Sdim 302221345Sdimextern void 303221345Sdimefx_intr_status_line( 304221345Sdim __in efx_nic_t *enp, 305221345Sdim __out boolean_t *fatalp, 306221345Sdim __out uint32_t *maskp); 307221345Sdim 308221345Sdimextern void 309226633Sdimefx_intr_status_message( 310226633Sdim __in efx_nic_t *enp, 311226633Sdim __in unsigned int message, 312226633Sdim __out boolean_t *fatalp); 313226633Sdim 314221345Sdimextern void 315218893Sdimefx_intr_fatal( 316218893Sdim __in efx_nic_t *enp); 317218893Sdim 318218893Sdimextern void 319218893Sdimefx_intr_fini( 320218893Sdim __in efx_nic_t *enp); 321218893Sdim 322212793Sdim/* MAC */ 323226633Sdim 324226633Sdim#if EFSYS_OPT_MAC_STATS 325226633Sdim 326221345Sdim/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 327226633Sdimtypedef enum efx_mac_stat_e { 328226633Sdim EFX_MAC_RX_OCTETS, 329226633Sdim EFX_MAC_RX_PKTS, 330226633Sdim EFX_MAC_RX_UNICST_PKTS, 331221345Sdim EFX_MAC_RX_MULTICST_PKTS, 332226633Sdim EFX_MAC_RX_BRDCST_PKTS, 333226633Sdim EFX_MAC_RX_PAUSE_PKTS, 334226633Sdim EFX_MAC_RX_LE_64_PKTS, 335221345Sdim EFX_MAC_RX_65_TO_127_PKTS, 336221345Sdim EFX_MAC_RX_128_TO_255_PKTS, 337221345Sdim EFX_MAC_RX_256_TO_511_PKTS, 338221345Sdim EFX_MAC_RX_512_TO_1023_PKTS, 339221345Sdim EFX_MAC_RX_1024_TO_15XX_PKTS, 340221345Sdim EFX_MAC_RX_GE_15XX_PKTS, 341221345Sdim EFX_MAC_RX_ERRORS, 342221345Sdim EFX_MAC_RX_FCS_ERRORS, 343221345Sdim EFX_MAC_RX_DROP_EVENTS, 344218893Sdim EFX_MAC_RX_FALSE_CARRIER_ERRORS, 345221345Sdim EFX_MAC_RX_SYMBOL_ERRORS, 346212793Sdim EFX_MAC_RX_ALIGN_ERRORS, 347221345Sdim EFX_MAC_RX_INTERNAL_ERRORS, 348221345Sdim EFX_MAC_RX_JABBER_PKTS, 349212793Sdim EFX_MAC_RX_LANE0_CHAR_ERR, 350212793Sdim EFX_MAC_RX_LANE1_CHAR_ERR, 351212793Sdim EFX_MAC_RX_LANE2_CHAR_ERR, 352212793Sdim EFX_MAC_RX_LANE3_CHAR_ERR, 353212793Sdim EFX_MAC_RX_LANE0_DISP_ERR, 354263508Sdim EFX_MAC_RX_LANE1_DISP_ERR, 355212793Sdim EFX_MAC_RX_LANE2_DISP_ERR, 356221345Sdim EFX_MAC_RX_LANE3_DISP_ERR, 357226633Sdim EFX_MAC_RX_MATCH_FAULT, 358212793Sdim EFX_MAC_RX_NODESC_DROP_CNT, 359212793Sdim EFX_MAC_TX_OCTETS, 360221345Sdim EFX_MAC_TX_PKTS, 361221345Sdim EFX_MAC_TX_UNICST_PKTS, 362221345Sdim EFX_MAC_TX_MULTICST_PKTS, 363212793Sdim EFX_MAC_TX_BRDCST_PKTS, 364221345Sdim EFX_MAC_TX_PAUSE_PKTS, 365221345Sdim EFX_MAC_TX_LE_64_PKTS, 366221345Sdim EFX_MAC_TX_65_TO_127_PKTS, 367221345Sdim EFX_MAC_TX_128_TO_255_PKTS, 368221345Sdim EFX_MAC_TX_256_TO_511_PKTS, 369221345Sdim EFX_MAC_TX_512_TO_1023_PKTS, 370218893Sdim EFX_MAC_TX_1024_TO_15XX_PKTS, 371218893Sdim EFX_MAC_TX_GE_15XX_PKTS, 372218893Sdim EFX_MAC_TX_ERRORS, 373218893Sdim EFX_MAC_TX_SGL_COL_PKTS, 374212793Sdim EFX_MAC_TX_MULT_COL_PKTS, 375224145Sdim EFX_MAC_TX_EX_COL_PKTS, 376224145Sdim EFX_MAC_TX_LATE_COL_PKTS, 377224145Sdim EFX_MAC_TX_DEF_PKTS, 378224145Sdim EFX_MAC_TX_EX_DEF_PKTS, 379218893Sdim EFX_MAC_PM_TRUNC_BB_OVERFLOW, 380218893Sdim EFX_MAC_PM_DISCARD_BB_OVERFLOW, 381218893Sdim EFX_MAC_PM_TRUNC_VFIFO_FULL, 382218893Sdim EFX_MAC_PM_DISCARD_VFIFO_FULL, 383212793Sdim EFX_MAC_PM_TRUNC_QBB, 384218893Sdim EFX_MAC_PM_DISCARD_QBB, 385212793Sdim EFX_MAC_PM_DISCARD_MAPPING, 386212793Sdim EFX_MAC_RXDP_Q_DISABLED_PKTS, 387218893Sdim EFX_MAC_RXDP_DI_DROPPED_PKTS, 388212793Sdim EFX_MAC_RXDP_STREAMING_PKTS, 389212793Sdim EFX_MAC_RXDP_HLB_FETCH, 390218893Sdim EFX_MAC_RXDP_HLB_WAIT, 391218893Sdim EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 392218893Sdim EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 393212793Sdim EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 394218893Sdim EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 395218893Sdim EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 396218893Sdim EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 397218893Sdim EFX_MAC_VADAPTER_RX_BAD_PACKETS, 398212793Sdim EFX_MAC_VADAPTER_RX_BAD_BYTES, 399218893Sdim EFX_MAC_VADAPTER_RX_OVERFLOW, 400218893Sdim EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 401218893Sdim EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 402212793Sdim EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 403218893Sdim EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 404218893Sdim EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 405218893Sdim EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 406218893Sdim EFX_MAC_VADAPTER_TX_BAD_PACKETS, 407218893Sdim EFX_MAC_VADAPTER_TX_BAD_BYTES, 408218893Sdim EFX_MAC_VADAPTER_TX_OVERFLOW, 409218893Sdim EFX_MAC_NSTATS 410218893Sdim} efx_mac_stat_t; 411218893Sdim 412218893Sdim/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 413218893Sdim 414218893Sdim#endif /* EFSYS_OPT_MAC_STATS */ 415218893Sdim 416218893Sdimtypedef enum efx_link_mode_e { 417221345Sdim EFX_LINK_UNKNOWN = 0, 418221345Sdim EFX_LINK_DOWN, 419221345Sdim EFX_LINK_10HDX, 420221345Sdim EFX_LINK_10FDX, 421212793Sdim EFX_LINK_100HDX, 422218893Sdim EFX_LINK_100FDX, 423218893Sdim EFX_LINK_1000HDX, 424218893Sdim EFX_LINK_1000FDX, 425212793Sdim EFX_LINK_10000FDX, 426212793Sdim EFX_LINK_40000FDX, 427221345Sdim EFX_LINK_NMODES 428221345Sdim} efx_link_mode_t; 429221345Sdim 430221345Sdim#define EFX_MAC_ADDR_LEN 6 431221345Sdim 432224145Sdim#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) 433224145Sdim 434224145Sdim#define EFX_MAC_MULTICAST_LIST_MAX 256 435224145Sdim 436224145Sdim#define EFX_MAC_SDU_MAX 9202 437224145Sdim 438224145Sdim#define EFX_MAC_PDU(_sdu) \ 439224145Sdim P2ROUNDUP(((_sdu) \ 440224145Sdim + /* EtherII */ 14 \ 441224145Sdim + /* VLAN */ 4 \ 442224145Sdim + /* CRC */ 4 \ 443224145Sdim + /* bug16011 */ 16), \ 444224145Sdim (1 << 3)) 445224145Sdim 446224145Sdim#define EFX_MAC_PDU_MIN 60 447224145Sdim#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 448224145Sdim 449224145Sdimextern __checkReturn efx_rc_t 450224145Sdimefx_mac_pdu_set( 451224145Sdim __in efx_nic_t *enp, 452224145Sdim __in size_t pdu); 453224145Sdim 454224145Sdimextern __checkReturn efx_rc_t 455224145Sdimefx_mac_addr_set( 456224145Sdim __in efx_nic_t *enp, 457224145Sdim __in uint8_t *addr); 458224145Sdim 459224145Sdimextern __checkReturn efx_rc_t 460224145Sdimefx_mac_filter_set( 461224145Sdim __in efx_nic_t *enp, 462224145Sdim __in boolean_t all_unicst, 463224145Sdim __in boolean_t mulcst, 464224145Sdim __in boolean_t all_mulcst, 465224145Sdim __in boolean_t brdcst); 466224145Sdim 467212793Sdimextern __checkReturn efx_rc_t 468212793Sdimefx_mac_multicast_list_set( 469212793Sdim __in efx_nic_t *enp, 470221345Sdim __in_ecount(6*count) uint8_t const *addrs, 471221345Sdim __in int count); 472 473extern __checkReturn efx_rc_t 474efx_mac_filter_default_rxq_set( 475 __in efx_nic_t *enp, 476 __in efx_rxq_t *erp, 477 __in boolean_t using_rss); 478 479extern void 480efx_mac_filter_default_rxq_clear( 481 __in efx_nic_t *enp); 482 483extern __checkReturn efx_rc_t 484efx_mac_drain( 485 __in efx_nic_t *enp, 486 __in boolean_t enabled); 487 488extern __checkReturn efx_rc_t 489efx_mac_up( 490 __in efx_nic_t *enp, 491 __out boolean_t *mac_upp); 492 493#define EFX_FCNTL_RESPOND 0x00000001 494#define EFX_FCNTL_GENERATE 0x00000002 495 496extern __checkReturn efx_rc_t 497efx_mac_fcntl_set( 498 __in efx_nic_t *enp, 499 __in unsigned int fcntl, 500 __in boolean_t autoneg); 501 502extern void 503efx_mac_fcntl_get( 504 __in efx_nic_t *enp, 505 __out unsigned int *fcntl_wantedp, 506 __out unsigned int *fcntl_linkp); 507 508#define EFX_MAC_HASH_BITS (1 << 8) 509 510extern __checkReturn efx_rc_t 511efx_pktfilter_init( 512 __in efx_nic_t *enp); 513 514extern void 515efx_pktfilter_fini( 516 __in efx_nic_t *enp); 517 518extern __checkReturn efx_rc_t 519efx_pktfilter_set( 520 __in efx_nic_t *enp, 521 __in boolean_t unicst, 522 __in boolean_t brdcst); 523 524extern __checkReturn efx_rc_t 525efx_mac_hash_set( 526 __in efx_nic_t *enp, 527 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); 528 529#if EFSYS_OPT_MCAST_FILTER_LIST 530extern __checkReturn efx_rc_t 531efx_pktfilter_mcast_list_set( 532 __in efx_nic_t *enp, 533 __in uint8_t const *addrs, 534 __in int count); 535#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ 536 537extern __checkReturn efx_rc_t 538efx_pktfilter_mcast_all( 539 __in efx_nic_t *enp); 540 541#if EFSYS_OPT_MAC_STATS 542 543#if EFSYS_OPT_NAMES 544 545extern __checkReturn const char * 546efx_mac_stat_name( 547 __in efx_nic_t *enp, 548 __in unsigned int id); 549 550#endif /* EFSYS_OPT_NAMES */ 551 552#define EFX_MAC_STATS_SIZE 0x400 553 554/* 555 * Upload mac statistics supported by the hardware into the given buffer. 556 * 557 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 558 * and page aligned. 559 * 560 * The hardware will only DMA statistics that it understands (of course). 561 * Drivers should not make any assumptions about which statistics are 562 * supported, especially when the statistics are generated by firmware. 563 * 564 * Thus, drivers should zero this buffer before use, so that not-understood 565 * statistics read back as zero. 566 */ 567extern __checkReturn efx_rc_t 568efx_mac_stats_upload( 569 __in efx_nic_t *enp, 570 __in efsys_mem_t *esmp); 571 572extern __checkReturn efx_rc_t 573efx_mac_stats_periodic( 574 __in efx_nic_t *enp, 575 __in efsys_mem_t *esmp, 576 __in uint16_t period_ms, 577 __in boolean_t events); 578 579extern __checkReturn efx_rc_t 580efx_mac_stats_update( 581 __in efx_nic_t *enp, 582 __in efsys_mem_t *esmp, 583 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 584 __inout_opt uint32_t *generationp); 585 586#endif /* EFSYS_OPT_MAC_STATS */ 587 588/* MON */ 589 590typedef enum efx_mon_type_e { 591 EFX_MON_INVALID = 0, 592 EFX_MON_NULL, 593 EFX_MON_LM87, 594 EFX_MON_MAX6647, 595 EFX_MON_SFC90X0, 596 EFX_MON_SFC91X0, 597 EFX_MON_SFC92X0, 598 EFX_MON_NTYPES 599} efx_mon_type_t; 600 601#if EFSYS_OPT_NAMES 602 603extern const char * 604efx_mon_name( 605 __in efx_nic_t *enp); 606 607#endif /* EFSYS_OPT_NAMES */ 608 609extern __checkReturn efx_rc_t 610efx_mon_init( 611 __in efx_nic_t *enp); 612 613#if EFSYS_OPT_MON_STATS 614 615#define EFX_MON_STATS_PAGE_SIZE 0x100 616#define EFX_MON_MASK_ELEMENT_SIZE 32 617 618/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */ 619typedef enum efx_mon_stat_e { 620 EFX_MON_STAT_2_5V, 621 EFX_MON_STAT_VCCP1, 622 EFX_MON_STAT_VCC, 623 EFX_MON_STAT_5V, 624 EFX_MON_STAT_12V, 625 EFX_MON_STAT_VCCP2, 626 EFX_MON_STAT_EXT_TEMP, 627 EFX_MON_STAT_INT_TEMP, 628 EFX_MON_STAT_AIN1, 629 EFX_MON_STAT_AIN2, 630 EFX_MON_STAT_INT_COOLING, 631 EFX_MON_STAT_EXT_COOLING, 632 EFX_MON_STAT_1V, 633 EFX_MON_STAT_1_2V, 634 EFX_MON_STAT_1_8V, 635 EFX_MON_STAT_3_3V, 636 EFX_MON_STAT_1_2VA, 637 EFX_MON_STAT_VREF, 638 EFX_MON_STAT_VAOE, 639 EFX_MON_STAT_AOE_TEMP, 640 EFX_MON_STAT_PSU_AOE_TEMP, 641 EFX_MON_STAT_PSU_TEMP, 642 EFX_MON_STAT_FAN0, 643 EFX_MON_STAT_FAN1, 644 EFX_MON_STAT_FAN2, 645 EFX_MON_STAT_FAN3, 646 EFX_MON_STAT_FAN4, 647 EFX_MON_STAT_VAOE_IN, 648 EFX_MON_STAT_IAOE, 649 EFX_MON_STAT_IAOE_IN, 650 EFX_MON_STAT_NIC_POWER, 651 EFX_MON_STAT_0_9V, 652 EFX_MON_STAT_I0_9V, 653 EFX_MON_STAT_I1_2V, 654 EFX_MON_STAT_0_9V_ADC, 655 EFX_MON_STAT_INT_TEMP2, 656 EFX_MON_STAT_VREG_TEMP, 657 EFX_MON_STAT_VREG_0_9V_TEMP, 658 EFX_MON_STAT_VREG_1_2V_TEMP, 659 EFX_MON_STAT_INT_VPTAT, 660 EFX_MON_STAT_INT_ADC_TEMP, 661 EFX_MON_STAT_EXT_VPTAT, 662 EFX_MON_STAT_EXT_ADC_TEMP, 663 EFX_MON_STAT_AMBIENT_TEMP, 664 EFX_MON_STAT_AIRFLOW, 665 EFX_MON_STAT_VDD08D_VSS08D_CSR, 666 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 667 EFX_MON_STAT_HOTPOINT_TEMP, 668 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 669 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 670 EFX_MON_STAT_MUM_VCC, 671 EFX_MON_STAT_0V9_A, 672 EFX_MON_STAT_I0V9_A, 673 EFX_MON_STAT_0V9_A_TEMP, 674 EFX_MON_STAT_0V9_B, 675 EFX_MON_STAT_I0V9_B, 676 EFX_MON_STAT_0V9_B_TEMP, 677 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 678 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 679 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 680 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 681 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 682 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 683 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 684 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 685 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 686 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 687 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 688 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 689 EFX_MON_STAT_SODIMM_VOUT, 690 EFX_MON_STAT_SODIMM_0_TEMP, 691 EFX_MON_STAT_SODIMM_1_TEMP, 692 EFX_MON_STAT_PHY0_VCC, 693 EFX_MON_STAT_PHY1_VCC, 694 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 695 EFX_MON_NSTATS 696} efx_mon_stat_t; 697 698/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 699 700typedef enum efx_mon_stat_state_e { 701 EFX_MON_STAT_STATE_OK = 0, 702 EFX_MON_STAT_STATE_WARNING = 1, 703 EFX_MON_STAT_STATE_FATAL = 2, 704 EFX_MON_STAT_STATE_BROKEN = 3, 705 EFX_MON_STAT_STATE_NO_READING = 4, 706} efx_mon_stat_state_t; 707 708typedef struct efx_mon_stat_value_s { 709 uint16_t emsv_value; 710 uint16_t emsv_state; 711} efx_mon_stat_value_t; 712 713#if EFSYS_OPT_NAMES 714 715extern const char * 716efx_mon_stat_name( 717 __in efx_nic_t *enp, 718 __in efx_mon_stat_t id); 719 720#endif /* EFSYS_OPT_NAMES */ 721 722extern __checkReturn efx_rc_t 723efx_mon_stats_update( 724 __in efx_nic_t *enp, 725 __in efsys_mem_t *esmp, 726 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 727 728#endif /* EFSYS_OPT_MON_STATS */ 729 730extern void 731efx_mon_fini( 732 __in efx_nic_t *enp); 733 734/* PHY */ 735 736#define PMA_PMD_MMD 1 737#define PCS_MMD 3 738#define PHY_XS_MMD 4 739#define DTE_XS_MMD 5 740#define AN_MMD 7 741#define CL22EXT_MMD 29 742 743#define MAXMMD ((1 << 5) - 1) 744 745extern __checkReturn efx_rc_t 746efx_phy_verify( 747 __in efx_nic_t *enp); 748 749#if EFSYS_OPT_PHY_LED_CONTROL 750 751typedef enum efx_phy_led_mode_e { 752 EFX_PHY_LED_DEFAULT = 0, 753 EFX_PHY_LED_OFF, 754 EFX_PHY_LED_ON, 755 EFX_PHY_LED_FLASH, 756 EFX_PHY_LED_NMODES 757} efx_phy_led_mode_t; 758 759extern __checkReturn efx_rc_t 760efx_phy_led_set( 761 __in efx_nic_t *enp, 762 __in efx_phy_led_mode_t mode); 763 764#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 765 766extern __checkReturn efx_rc_t 767efx_port_init( 768 __in efx_nic_t *enp); 769 770#if EFSYS_OPT_LOOPBACK 771 772typedef enum efx_loopback_type_e { 773 EFX_LOOPBACK_OFF = 0, 774 EFX_LOOPBACK_DATA = 1, 775 EFX_LOOPBACK_GMAC = 2, 776 EFX_LOOPBACK_XGMII = 3, 777 EFX_LOOPBACK_XGXS = 4, 778 EFX_LOOPBACK_XAUI = 5, 779 EFX_LOOPBACK_GMII = 6, 780 EFX_LOOPBACK_SGMII = 7, 781 EFX_LOOPBACK_XGBR = 8, 782 EFX_LOOPBACK_XFI = 9, 783 EFX_LOOPBACK_XAUI_FAR = 10, 784 EFX_LOOPBACK_GMII_FAR = 11, 785 EFX_LOOPBACK_SGMII_FAR = 12, 786 EFX_LOOPBACK_XFI_FAR = 13, 787 EFX_LOOPBACK_GPHY = 14, 788 EFX_LOOPBACK_PHY_XS = 15, 789 EFX_LOOPBACK_PCS = 16, 790 EFX_LOOPBACK_PMA_PMD = 17, 791 EFX_LOOPBACK_XPORT = 18, 792 EFX_LOOPBACK_XGMII_WS = 19, 793 EFX_LOOPBACK_XAUI_WS = 20, 794 EFX_LOOPBACK_XAUI_WS_FAR = 21, 795 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 796 EFX_LOOPBACK_GMII_WS = 23, 797 EFX_LOOPBACK_XFI_WS = 24, 798 EFX_LOOPBACK_XFI_WS_FAR = 25, 799 EFX_LOOPBACK_PHYXS_WS = 26, 800 EFX_LOOPBACK_PMA_INT = 27, 801 EFX_LOOPBACK_SD_NEAR = 28, 802 EFX_LOOPBACK_SD_FAR = 29, 803 EFX_LOOPBACK_PMA_INT_WS = 30, 804 EFX_LOOPBACK_SD_FEP2_WS = 31, 805 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 806 EFX_LOOPBACK_SD_FEP_WS = 33, 807 EFX_LOOPBACK_SD_FES_WS = 34, 808 EFX_LOOPBACK_NTYPES 809} efx_loopback_type_t; 810 811typedef enum efx_loopback_kind_e { 812 EFX_LOOPBACK_KIND_OFF = 0, 813 EFX_LOOPBACK_KIND_ALL, 814 EFX_LOOPBACK_KIND_MAC, 815 EFX_LOOPBACK_KIND_PHY, 816 EFX_LOOPBACK_NKINDS 817} efx_loopback_kind_t; 818 819extern void 820efx_loopback_mask( 821 __in efx_loopback_kind_t loopback_kind, 822 __out efx_qword_t *maskp); 823 824extern __checkReturn efx_rc_t 825efx_port_loopback_set( 826 __in efx_nic_t *enp, 827 __in efx_link_mode_t link_mode, 828 __in efx_loopback_type_t type); 829 830#if EFSYS_OPT_NAMES 831 832extern __checkReturn const char * 833efx_loopback_type_name( 834 __in efx_nic_t *enp, 835 __in efx_loopback_type_t type); 836 837#endif /* EFSYS_OPT_NAMES */ 838 839#endif /* EFSYS_OPT_LOOPBACK */ 840 841extern __checkReturn efx_rc_t 842efx_port_poll( 843 __in efx_nic_t *enp, 844 __out_opt efx_link_mode_t *link_modep); 845 846extern void 847efx_port_fini( 848 __in efx_nic_t *enp); 849 850typedef enum efx_phy_cap_type_e { 851 EFX_PHY_CAP_INVALID = 0, 852 EFX_PHY_CAP_10HDX, 853 EFX_PHY_CAP_10FDX, 854 EFX_PHY_CAP_100HDX, 855 EFX_PHY_CAP_100FDX, 856 EFX_PHY_CAP_1000HDX, 857 EFX_PHY_CAP_1000FDX, 858 EFX_PHY_CAP_10000FDX, 859 EFX_PHY_CAP_PAUSE, 860 EFX_PHY_CAP_ASYM, 861 EFX_PHY_CAP_AN, 862 EFX_PHY_CAP_40000FDX, 863 EFX_PHY_CAP_NTYPES 864} efx_phy_cap_type_t; 865 866 867#define EFX_PHY_CAP_CURRENT 0x00000000 868#define EFX_PHY_CAP_DEFAULT 0x00000001 869#define EFX_PHY_CAP_PERM 0x00000002 870 871extern void 872efx_phy_adv_cap_get( 873 __in efx_nic_t *enp, 874 __in uint32_t flag, 875 __out uint32_t *maskp); 876 877extern __checkReturn efx_rc_t 878efx_phy_adv_cap_set( 879 __in efx_nic_t *enp, 880 __in uint32_t mask); 881 882extern void 883efx_phy_lp_cap_get( 884 __in efx_nic_t *enp, 885 __out uint32_t *maskp); 886 887extern __checkReturn efx_rc_t 888efx_phy_oui_get( 889 __in efx_nic_t *enp, 890 __out uint32_t *ouip); 891 892typedef enum efx_phy_media_type_e { 893 EFX_PHY_MEDIA_INVALID = 0, 894 EFX_PHY_MEDIA_XAUI, 895 EFX_PHY_MEDIA_CX4, 896 EFX_PHY_MEDIA_KX4, 897 EFX_PHY_MEDIA_XFP, 898 EFX_PHY_MEDIA_SFP_PLUS, 899 EFX_PHY_MEDIA_BASE_T, 900 EFX_PHY_MEDIA_QSFP_PLUS, 901 EFX_PHY_MEDIA_NTYPES 902} efx_phy_media_type_t; 903 904/* Get the type of medium currently used. If the board has ports for 905 * modules, a module is present, and we recognise the media type of 906 * the module, then this will be the media type of the module. 907 * Otherwise it will be the media type of the port. 908 */ 909extern void 910efx_phy_media_type_get( 911 __in efx_nic_t *enp, 912 __out efx_phy_media_type_t *typep); 913 914#if EFSYS_OPT_PHY_STATS 915 916/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 917typedef enum efx_phy_stat_e { 918 EFX_PHY_STAT_OUI, 919 EFX_PHY_STAT_PMA_PMD_LINK_UP, 920 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 921 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 922 EFX_PHY_STAT_PMA_PMD_REV_A, 923 EFX_PHY_STAT_PMA_PMD_REV_B, 924 EFX_PHY_STAT_PMA_PMD_REV_C, 925 EFX_PHY_STAT_PMA_PMD_REV_D, 926 EFX_PHY_STAT_PCS_LINK_UP, 927 EFX_PHY_STAT_PCS_RX_FAULT, 928 EFX_PHY_STAT_PCS_TX_FAULT, 929 EFX_PHY_STAT_PCS_BER, 930 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 931 EFX_PHY_STAT_PHY_XS_LINK_UP, 932 EFX_PHY_STAT_PHY_XS_RX_FAULT, 933 EFX_PHY_STAT_PHY_XS_TX_FAULT, 934 EFX_PHY_STAT_PHY_XS_ALIGN, 935 EFX_PHY_STAT_PHY_XS_SYNC_A, 936 EFX_PHY_STAT_PHY_XS_SYNC_B, 937 EFX_PHY_STAT_PHY_XS_SYNC_C, 938 EFX_PHY_STAT_PHY_XS_SYNC_D, 939 EFX_PHY_STAT_AN_LINK_UP, 940 EFX_PHY_STAT_AN_MASTER, 941 EFX_PHY_STAT_AN_LOCAL_RX_OK, 942 EFX_PHY_STAT_AN_REMOTE_RX_OK, 943 EFX_PHY_STAT_CL22EXT_LINK_UP, 944 EFX_PHY_STAT_SNR_A, 945 EFX_PHY_STAT_SNR_B, 946 EFX_PHY_STAT_SNR_C, 947 EFX_PHY_STAT_SNR_D, 948 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 949 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 950 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 951 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 952 EFX_PHY_STAT_AN_COMPLETE, 953 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 954 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 955 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 956 EFX_PHY_STAT_PCS_FW_VERSION_0, 957 EFX_PHY_STAT_PCS_FW_VERSION_1, 958 EFX_PHY_STAT_PCS_FW_VERSION_2, 959 EFX_PHY_STAT_PCS_FW_VERSION_3, 960 EFX_PHY_STAT_PCS_FW_BUILD_YY, 961 EFX_PHY_STAT_PCS_FW_BUILD_MM, 962 EFX_PHY_STAT_PCS_FW_BUILD_DD, 963 EFX_PHY_STAT_PCS_OP_MODE, 964 EFX_PHY_NSTATS 965} efx_phy_stat_t; 966 967/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 968 969#if EFSYS_OPT_NAMES 970 971extern const char * 972efx_phy_stat_name( 973 __in efx_nic_t *enp, 974 __in efx_phy_stat_t stat); 975 976#endif /* EFSYS_OPT_NAMES */ 977 978#define EFX_PHY_STATS_SIZE 0x100 979 980extern __checkReturn efx_rc_t 981efx_phy_stats_update( 982 __in efx_nic_t *enp, 983 __in efsys_mem_t *esmp, 984 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 985 986#endif /* EFSYS_OPT_PHY_STATS */ 987 988#if EFSYS_OPT_PHY_PROPS 989 990#if EFSYS_OPT_NAMES 991 992extern const char * 993efx_phy_prop_name( 994 __in efx_nic_t *enp, 995 __in unsigned int id); 996 997#endif /* EFSYS_OPT_NAMES */ 998 999#define EFX_PHY_PROP_DEFAULT 0x00000001 1000 1001extern __checkReturn efx_rc_t 1002efx_phy_prop_get( 1003 __in efx_nic_t *enp, 1004 __in unsigned int id, 1005 __in uint32_t flags, 1006 __out uint32_t *valp); 1007 1008extern __checkReturn efx_rc_t 1009efx_phy_prop_set( 1010 __in efx_nic_t *enp, 1011 __in unsigned int id, 1012 __in uint32_t val); 1013 1014#endif /* EFSYS_OPT_PHY_PROPS */ 1015 1016#if EFSYS_OPT_BIST 1017 1018typedef enum efx_bist_type_e { 1019 EFX_BIST_TYPE_UNKNOWN, 1020 EFX_BIST_TYPE_PHY_NORMAL, 1021 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1022 EFX_BIST_TYPE_PHY_CABLE_LONG, 1023 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1024 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1025 EFX_BIST_TYPE_REG, /* Test the register memories */ 1026 EFX_BIST_TYPE_NTYPES, 1027} efx_bist_type_t; 1028 1029typedef enum efx_bist_result_e { 1030 EFX_BIST_RESULT_UNKNOWN, 1031 EFX_BIST_RESULT_RUNNING, 1032 EFX_BIST_RESULT_PASSED, 1033 EFX_BIST_RESULT_FAILED, 1034} efx_bist_result_t; 1035 1036typedef enum efx_phy_cable_status_e { 1037 EFX_PHY_CABLE_STATUS_OK, 1038 EFX_PHY_CABLE_STATUS_INVALID, 1039 EFX_PHY_CABLE_STATUS_OPEN, 1040 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1041 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1042 EFX_PHY_CABLE_STATUS_BUSY, 1043} efx_phy_cable_status_t; 1044 1045typedef enum efx_bist_value_e { 1046 EFX_BIST_PHY_CABLE_LENGTH_A, 1047 EFX_BIST_PHY_CABLE_LENGTH_B, 1048 EFX_BIST_PHY_CABLE_LENGTH_C, 1049 EFX_BIST_PHY_CABLE_LENGTH_D, 1050 EFX_BIST_PHY_CABLE_STATUS_A, 1051 EFX_BIST_PHY_CABLE_STATUS_B, 1052 EFX_BIST_PHY_CABLE_STATUS_C, 1053 EFX_BIST_PHY_CABLE_STATUS_D, 1054 EFX_BIST_FAULT_CODE, 1055 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1056 * response. */ 1057 EFX_BIST_MEM_TEST, 1058 EFX_BIST_MEM_ADDR, 1059 EFX_BIST_MEM_BUS, 1060 EFX_BIST_MEM_EXPECT, 1061 EFX_BIST_MEM_ACTUAL, 1062 EFX_BIST_MEM_ECC, 1063 EFX_BIST_MEM_ECC_PARITY, 1064 EFX_BIST_MEM_ECC_FATAL, 1065 EFX_BIST_NVALUES, 1066} efx_bist_value_t; 1067 1068extern __checkReturn efx_rc_t 1069efx_bist_enable_offline( 1070 __in efx_nic_t *enp); 1071 1072extern __checkReturn efx_rc_t 1073efx_bist_start( 1074 __in efx_nic_t *enp, 1075 __in efx_bist_type_t type); 1076 1077extern __checkReturn efx_rc_t 1078efx_bist_poll( 1079 __in efx_nic_t *enp, 1080 __in efx_bist_type_t type, 1081 __out efx_bist_result_t *resultp, 1082 __out_opt uint32_t *value_maskp, 1083 __out_ecount_opt(count) unsigned long *valuesp, 1084 __in size_t count); 1085 1086extern void 1087efx_bist_stop( 1088 __in efx_nic_t *enp, 1089 __in efx_bist_type_t type); 1090 1091#endif /* EFSYS_OPT_BIST */ 1092 1093#define EFX_FEATURE_IPV6 0x00000001 1094#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1095#define EFX_FEATURE_LINK_EVENTS 0x00000004 1096#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1097#define EFX_FEATURE_WOL 0x00000010 1098#define EFX_FEATURE_MCDI 0x00000020 1099#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1100#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1101#define EFX_FEATURE_TURBO 0x00000100 1102#define EFX_FEATURE_MCDI_DMA 0x00000200 1103#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1104#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1105#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1106 1107typedef struct efx_nic_cfg_s { 1108 uint32_t enc_board_type; 1109 uint32_t enc_phy_type; 1110#if EFSYS_OPT_NAMES 1111 char enc_phy_name[21]; 1112#endif 1113 char enc_phy_revision[21]; 1114 efx_mon_type_t enc_mon_type; 1115#if EFSYS_OPT_MON_STATS 1116 uint32_t enc_mon_stat_dma_buf_size; 1117 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1118#endif 1119 unsigned int enc_features; 1120 uint8_t enc_mac_addr[6]; 1121 uint8_t enc_port; /* PHY port number */ 1122 uint32_t enc_func_flags; 1123 uint32_t enc_intr_vec_base; 1124 uint32_t enc_intr_limit; 1125 uint32_t enc_evq_limit; 1126 uint32_t enc_txq_limit; 1127 uint32_t enc_rxq_limit; 1128 uint32_t enc_buftbl_limit; 1129 uint32_t enc_piobuf_limit; 1130 uint32_t enc_piobuf_size; 1131 uint32_t enc_evq_timer_quantum_ns; 1132 uint32_t enc_evq_timer_max_us; 1133 uint32_t enc_clk_mult; 1134 uint32_t enc_rx_prefix_size; 1135 uint32_t enc_rx_buf_align_start; 1136 uint32_t enc_rx_buf_align_end; 1137#if EFSYS_OPT_LOOPBACK 1138 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1139#endif /* EFSYS_OPT_LOOPBACK */ 1140#if EFSYS_OPT_PHY_FLAGS 1141 uint32_t enc_phy_flags_mask; 1142#endif /* EFSYS_OPT_PHY_FLAGS */ 1143#if EFSYS_OPT_PHY_LED_CONTROL 1144 uint32_t enc_led_mask; 1145#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1146#if EFSYS_OPT_PHY_STATS 1147 uint64_t enc_phy_stat_mask; 1148#endif /* EFSYS_OPT_PHY_STATS */ 1149#if EFSYS_OPT_PHY_PROPS 1150 unsigned int enc_phy_nprops; 1151#endif /* EFSYS_OPT_PHY_PROPS */ 1152#if EFSYS_OPT_SIENA 1153 uint8_t enc_mcdi_mdio_channel; 1154#if EFSYS_OPT_PHY_STATS 1155 uint32_t enc_mcdi_phy_stat_mask; 1156#endif /* EFSYS_OPT_PHY_STATS */ 1157#endif /* EFSYS_OPT_SIENA */ 1158#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 1159#if EFSYS_OPT_MON_STATS 1160 uint32_t *enc_mcdi_sensor_maskp; 1161 uint32_t enc_mcdi_sensor_mask_size; 1162#endif /* EFSYS_OPT_MON_STATS */ 1163#endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 1164#if EFSYS_OPT_BIST 1165 uint32_t enc_bist_mask; 1166#endif /* EFSYS_OPT_BIST */ 1167#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1168 uint32_t enc_pf; 1169 uint32_t enc_vf; 1170 uint32_t enc_privilege_mask; 1171#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1172 boolean_t enc_bug26807_workaround; 1173 boolean_t enc_bug35388_workaround; 1174 boolean_t enc_bug41750_workaround; 1175 boolean_t enc_rx_batching_enabled; 1176 /* Maximum number of descriptors completed in an rx event. */ 1177 uint32_t enc_rx_batch_max; 1178 /* Number of rx descriptors the hardware requires for a push. */ 1179 uint32_t enc_rx_push_align; 1180 /* 1181 * Maximum number of bytes into the packet the TCP header can start for 1182 * the hardware to apply TSO packet edits. 1183 */ 1184 uint32_t enc_tx_tso_tcp_header_offset_limit; 1185 boolean_t enc_fw_assisted_tso_enabled; 1186 boolean_t enc_hw_tx_insert_vlan_enabled; 1187 /* Datapath firmware vadapter/vport/vswitch support */ 1188 boolean_t enc_datapath_cap_evb; 1189 boolean_t enc_rx_disable_scatter_supported; 1190 boolean_t enc_allow_set_mac_with_installed_filters; 1191 /* External port identifier */ 1192 uint8_t enc_external_port; 1193 uint32_t enc_mcdi_max_payload_length; 1194} efx_nic_cfg_t; 1195 1196#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1197#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1198 1199#define EFX_PCI_FUNCTION(_encp) \ 1200 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1201 1202#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1203 1204extern const efx_nic_cfg_t * 1205efx_nic_cfg_get( 1206 __in efx_nic_t *enp); 1207 1208/* Driver resource limits (minimum required/maximum usable). */ 1209typedef struct efx_drv_limits_s 1210{ 1211 uint32_t edl_min_evq_count; 1212 uint32_t edl_max_evq_count; 1213 1214 uint32_t edl_min_rxq_count; 1215 uint32_t edl_max_rxq_count; 1216 1217 uint32_t edl_min_txq_count; 1218 uint32_t edl_max_txq_count; 1219 1220 /* PIO blocks (sub-allocated from piobuf) */ 1221 uint32_t edl_min_pio_alloc_size; 1222 uint32_t edl_max_pio_alloc_count; 1223} efx_drv_limits_t; 1224 1225extern __checkReturn efx_rc_t 1226efx_nic_set_drv_limits( 1227 __inout efx_nic_t *enp, 1228 __in efx_drv_limits_t *edlp); 1229 1230typedef enum efx_nic_region_e { 1231 EFX_REGION_VI, /* Memory BAR UC mapping */ 1232 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1233} efx_nic_region_t; 1234 1235extern __checkReturn efx_rc_t 1236efx_nic_get_bar_region( 1237 __in efx_nic_t *enp, 1238 __in efx_nic_region_t region, 1239 __out uint32_t *offsetp, 1240 __out size_t *sizep); 1241 1242extern __checkReturn efx_rc_t 1243efx_nic_get_vi_pool( 1244 __in efx_nic_t *enp, 1245 __out uint32_t *evq_countp, 1246 __out uint32_t *rxq_countp, 1247 __out uint32_t *txq_countp); 1248 1249 1250#if EFSYS_OPT_VPD 1251 1252typedef enum efx_vpd_tag_e { 1253 EFX_VPD_ID = 0x02, 1254 EFX_VPD_END = 0x0f, 1255 EFX_VPD_RO = 0x10, 1256 EFX_VPD_RW = 0x11, 1257} efx_vpd_tag_t; 1258 1259typedef uint16_t efx_vpd_keyword_t; 1260 1261typedef struct efx_vpd_value_s { 1262 efx_vpd_tag_t evv_tag; 1263 efx_vpd_keyword_t evv_keyword; 1264 uint8_t evv_length; 1265 uint8_t evv_value[0x100]; 1266} efx_vpd_value_t; 1267 1268 1269#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1270 1271extern __checkReturn efx_rc_t 1272efx_vpd_init( 1273 __in efx_nic_t *enp); 1274 1275extern __checkReturn efx_rc_t 1276efx_vpd_size( 1277 __in efx_nic_t *enp, 1278 __out size_t *sizep); 1279 1280extern __checkReturn efx_rc_t 1281efx_vpd_read( 1282 __in efx_nic_t *enp, 1283 __out_bcount(size) caddr_t data, 1284 __in size_t size); 1285 1286extern __checkReturn efx_rc_t 1287efx_vpd_verify( 1288 __in efx_nic_t *enp, 1289 __in_bcount(size) caddr_t data, 1290 __in size_t size); 1291 1292extern __checkReturn efx_rc_t 1293efx_vpd_reinit( 1294 __in efx_nic_t *enp, 1295 __in_bcount(size) caddr_t data, 1296 __in size_t size); 1297 1298extern __checkReturn efx_rc_t 1299efx_vpd_get( 1300 __in efx_nic_t *enp, 1301 __in_bcount(size) caddr_t data, 1302 __in size_t size, 1303 __inout efx_vpd_value_t *evvp); 1304 1305extern __checkReturn efx_rc_t 1306efx_vpd_set( 1307 __in efx_nic_t *enp, 1308 __inout_bcount(size) caddr_t data, 1309 __in size_t size, 1310 __in efx_vpd_value_t *evvp); 1311 1312extern __checkReturn efx_rc_t 1313efx_vpd_next( 1314 __in efx_nic_t *enp, 1315 __inout_bcount(size) caddr_t data, 1316 __in size_t size, 1317 __out efx_vpd_value_t *evvp, 1318 __inout unsigned int *contp); 1319 1320extern __checkReturn efx_rc_t 1321efx_vpd_write( 1322 __in efx_nic_t *enp, 1323 __in_bcount(size) caddr_t data, 1324 __in size_t size); 1325 1326extern void 1327efx_vpd_fini( 1328 __in efx_nic_t *enp); 1329 1330#endif /* EFSYS_OPT_VPD */ 1331 1332/* NVRAM */ 1333 1334#if EFSYS_OPT_NVRAM 1335 1336typedef enum efx_nvram_type_e { 1337 EFX_NVRAM_INVALID = 0, 1338 EFX_NVRAM_BOOTROM, 1339 EFX_NVRAM_BOOTROM_CFG, 1340 EFX_NVRAM_MC_FIRMWARE, 1341 EFX_NVRAM_MC_GOLDEN, 1342 EFX_NVRAM_PHY, 1343 EFX_NVRAM_NULLPHY, 1344 EFX_NVRAM_FPGA, 1345 EFX_NVRAM_FCFW, 1346 EFX_NVRAM_CPLD, 1347 EFX_NVRAM_FPGA_BACKUP, 1348 EFX_NVRAM_DYNAMIC_CFG, 1349 EFX_NVRAM_NTYPES, 1350} efx_nvram_type_t; 1351 1352extern __checkReturn efx_rc_t 1353efx_nvram_init( 1354 __in efx_nic_t *enp); 1355 1356#if EFSYS_OPT_DIAG 1357 1358extern __checkReturn efx_rc_t 1359efx_nvram_test( 1360 __in efx_nic_t *enp); 1361 1362#endif /* EFSYS_OPT_DIAG */ 1363 1364extern __checkReturn efx_rc_t 1365efx_nvram_size( 1366 __in efx_nic_t *enp, 1367 __in efx_nvram_type_t type, 1368 __out size_t *sizep); 1369 1370extern __checkReturn efx_rc_t 1371efx_nvram_rw_start( 1372 __in efx_nic_t *enp, 1373 __in efx_nvram_type_t type, 1374 __out_opt size_t *pref_chunkp); 1375 1376extern void 1377efx_nvram_rw_finish( 1378 __in efx_nic_t *enp, 1379 __in efx_nvram_type_t type); 1380 1381extern __checkReturn efx_rc_t 1382efx_nvram_get_version( 1383 __in efx_nic_t *enp, 1384 __in efx_nvram_type_t type, 1385 __out uint32_t *subtypep, 1386 __out_ecount(4) uint16_t version[4]); 1387 1388extern __checkReturn efx_rc_t 1389efx_nvram_read_chunk( 1390 __in efx_nic_t *enp, 1391 __in efx_nvram_type_t type, 1392 __in unsigned int offset, 1393 __out_bcount(size) caddr_t data, 1394 __in size_t size); 1395 1396extern __checkReturn efx_rc_t 1397efx_nvram_set_version( 1398 __in efx_nic_t *enp, 1399 __in efx_nvram_type_t type, 1400 __in_ecount(4) uint16_t version[4]); 1401 1402/* Validate contents of TLV formatted partition */ 1403extern __checkReturn efx_rc_t 1404efx_nvram_tlv_validate( 1405 __in efx_nic_t *enp, 1406 __in uint32_t partn, 1407 __in_bcount(partn_size) caddr_t partn_data, 1408 __in size_t partn_size); 1409 1410extern __checkReturn efx_rc_t 1411efx_nvram_erase( 1412 __in efx_nic_t *enp, 1413 __in efx_nvram_type_t type); 1414 1415extern __checkReturn efx_rc_t 1416efx_nvram_write_chunk( 1417 __in efx_nic_t *enp, 1418 __in efx_nvram_type_t type, 1419 __in unsigned int offset, 1420 __in_bcount(size) caddr_t data, 1421 __in size_t size); 1422 1423extern void 1424efx_nvram_fini( 1425 __in efx_nic_t *enp); 1426 1427#endif /* EFSYS_OPT_NVRAM */ 1428 1429#if EFSYS_OPT_BOOTCFG 1430 1431extern efx_rc_t 1432efx_bootcfg_read( 1433 __in efx_nic_t *enp, 1434 __out_bcount(size) caddr_t data, 1435 __in size_t size); 1436 1437extern efx_rc_t 1438efx_bootcfg_write( 1439 __in efx_nic_t *enp, 1440 __in_bcount(size) caddr_t data, 1441 __in size_t size); 1442 1443#endif /* EFSYS_OPT_BOOTCFG */ 1444 1445#if EFSYS_OPT_WOL 1446 1447typedef enum efx_wol_type_e { 1448 EFX_WOL_TYPE_INVALID, 1449 EFX_WOL_TYPE_MAGIC, 1450 EFX_WOL_TYPE_BITMAP, 1451 EFX_WOL_TYPE_LINK, 1452 EFX_WOL_NTYPES, 1453} efx_wol_type_t; 1454 1455typedef enum efx_lightsout_offload_type_e { 1456 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1457 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1458 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1459} efx_lightsout_offload_type_t; 1460 1461#define EFX_WOL_BITMAP_MASK_SIZE (48) 1462#define EFX_WOL_BITMAP_VALUE_SIZE (128) 1463 1464typedef union efx_wol_param_u { 1465 struct { 1466 uint8_t mac_addr[6]; 1467 } ewp_magic; 1468 struct { 1469 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1470 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1471 uint8_t value_len; 1472 } ewp_bitmap; 1473} efx_wol_param_t; 1474 1475typedef union efx_lightsout_offload_param_u { 1476 struct { 1477 uint8_t mac_addr[6]; 1478 uint32_t ip; 1479 } elop_arp; 1480 struct { 1481 uint8_t mac_addr[6]; 1482 uint32_t solicited_node[4]; 1483 uint32_t ip[4]; 1484 } elop_ns; 1485} efx_lightsout_offload_param_t; 1486 1487extern __checkReturn efx_rc_t 1488efx_wol_init( 1489 __in efx_nic_t *enp); 1490 1491extern __checkReturn efx_rc_t 1492efx_wol_filter_clear( 1493 __in efx_nic_t *enp); 1494 1495extern __checkReturn efx_rc_t 1496efx_wol_filter_add( 1497 __in efx_nic_t *enp, 1498 __in efx_wol_type_t type, 1499 __in efx_wol_param_t *paramp, 1500 __out uint32_t *filter_idp); 1501 1502extern __checkReturn efx_rc_t 1503efx_wol_filter_remove( 1504 __in efx_nic_t *enp, 1505 __in uint32_t filter_id); 1506 1507extern __checkReturn efx_rc_t 1508efx_lightsout_offload_add( 1509 __in efx_nic_t *enp, 1510 __in efx_lightsout_offload_type_t type, 1511 __in efx_lightsout_offload_param_t *paramp, 1512 __out uint32_t *filter_idp); 1513 1514extern __checkReturn efx_rc_t 1515efx_lightsout_offload_remove( 1516 __in efx_nic_t *enp, 1517 __in efx_lightsout_offload_type_t type, 1518 __in uint32_t filter_id); 1519 1520extern void 1521efx_wol_fini( 1522 __in efx_nic_t *enp); 1523 1524#endif /* EFSYS_OPT_WOL */ 1525 1526#if EFSYS_OPT_DIAG 1527 1528typedef enum efx_pattern_type_t { 1529 EFX_PATTERN_BYTE_INCREMENT = 0, 1530 EFX_PATTERN_ALL_THE_SAME, 1531 EFX_PATTERN_BIT_ALTERNATE, 1532 EFX_PATTERN_BYTE_ALTERNATE, 1533 EFX_PATTERN_BYTE_CHANGING, 1534 EFX_PATTERN_BIT_SWEEP, 1535 EFX_PATTERN_NTYPES 1536} efx_pattern_type_t; 1537 1538typedef void 1539(*efx_sram_pattern_fn_t)( 1540 __in size_t row, 1541 __in boolean_t negate, 1542 __out efx_qword_t *eqp); 1543 1544extern __checkReturn efx_rc_t 1545efx_sram_test( 1546 __in efx_nic_t *enp, 1547 __in efx_pattern_type_t type); 1548 1549#endif /* EFSYS_OPT_DIAG */ 1550 1551extern __checkReturn efx_rc_t 1552efx_sram_buf_tbl_set( 1553 __in efx_nic_t *enp, 1554 __in uint32_t id, 1555 __in efsys_mem_t *esmp, 1556 __in size_t n); 1557 1558extern void 1559efx_sram_buf_tbl_clear( 1560 __in efx_nic_t *enp, 1561 __in uint32_t id, 1562 __in size_t n); 1563 1564#define EFX_BUF_TBL_SIZE 0x20000 1565 1566#define EFX_BUF_SIZE 4096 1567 1568/* EV */ 1569 1570typedef struct efx_evq_s efx_evq_t; 1571 1572#if EFSYS_OPT_QSTATS 1573 1574/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1575typedef enum efx_ev_qstat_e { 1576 EV_ALL, 1577 EV_RX, 1578 EV_RX_OK, 1579 EV_RX_FRM_TRUNC, 1580 EV_RX_TOBE_DISC, 1581 EV_RX_PAUSE_FRM_ERR, 1582 EV_RX_BUF_OWNER_ID_ERR, 1583 EV_RX_IPV4_HDR_CHKSUM_ERR, 1584 EV_RX_TCP_UDP_CHKSUM_ERR, 1585 EV_RX_ETH_CRC_ERR, 1586 EV_RX_IP_FRAG_ERR, 1587 EV_RX_MCAST_PKT, 1588 EV_RX_MCAST_HASH_MATCH, 1589 EV_RX_TCP_IPV4, 1590 EV_RX_TCP_IPV6, 1591 EV_RX_UDP_IPV4, 1592 EV_RX_UDP_IPV6, 1593 EV_RX_OTHER_IPV4, 1594 EV_RX_OTHER_IPV6, 1595 EV_RX_NON_IP, 1596 EV_RX_BATCH, 1597 EV_TX, 1598 EV_TX_WQ_FF_FULL, 1599 EV_TX_PKT_ERR, 1600 EV_TX_PKT_TOO_BIG, 1601 EV_TX_UNEXPECTED, 1602 EV_GLOBAL, 1603 EV_GLOBAL_MNT, 1604 EV_DRIVER, 1605 EV_DRIVER_SRM_UPD_DONE, 1606 EV_DRIVER_TX_DESCQ_FLS_DONE, 1607 EV_DRIVER_RX_DESCQ_FLS_DONE, 1608 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1609 EV_DRIVER_RX_DSC_ERROR, 1610 EV_DRIVER_TX_DSC_ERROR, 1611 EV_DRV_GEN, 1612 EV_MCDI_RESPONSE, 1613 EV_NQSTATS 1614} efx_ev_qstat_t; 1615 1616/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1617 1618#endif /* EFSYS_OPT_QSTATS */ 1619 1620extern __checkReturn efx_rc_t 1621efx_ev_init( 1622 __in efx_nic_t *enp); 1623 1624extern void 1625efx_ev_fini( 1626 __in efx_nic_t *enp); 1627 1628#define EFX_EVQ_MAXNEVS 32768 1629#define EFX_EVQ_MINNEVS 512 1630 1631#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1632#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1633 1634extern __checkReturn efx_rc_t 1635efx_ev_qcreate( 1636 __in efx_nic_t *enp, 1637 __in unsigned int index, 1638 __in efsys_mem_t *esmp, 1639 __in size_t n, 1640 __in uint32_t id, 1641 __deref_out efx_evq_t **eepp); 1642 1643extern void 1644efx_ev_qpost( 1645 __in efx_evq_t *eep, 1646 __in uint16_t data); 1647 1648typedef __checkReturn boolean_t 1649(*efx_initialized_ev_t)( 1650 __in_opt void *arg); 1651 1652#define EFX_PKT_UNICAST 0x0004 1653#define EFX_PKT_START 0x0008 1654 1655#define EFX_PKT_VLAN_TAGGED 0x0010 1656#define EFX_CKSUM_TCPUDP 0x0020 1657#define EFX_CKSUM_IPV4 0x0040 1658#define EFX_PKT_CONT 0x0080 1659 1660#define EFX_CHECK_VLAN 0x0100 1661#define EFX_PKT_TCP 0x0200 1662#define EFX_PKT_UDP 0x0400 1663#define EFX_PKT_IPV4 0x0800 1664 1665#define EFX_PKT_IPV6 0x1000 1666#define EFX_PKT_PREFIX_LEN 0x2000 1667#define EFX_ADDR_MISMATCH 0x4000 1668#define EFX_DISCARD 0x8000 1669 1670#define EFX_EV_RX_NLABELS 32 1671#define EFX_EV_TX_NLABELS 32 1672 1673typedef __checkReturn boolean_t 1674(*efx_rx_ev_t)( 1675 __in_opt void *arg, 1676 __in uint32_t label, 1677 __in uint32_t id, 1678 __in uint32_t size, 1679 __in uint16_t flags); 1680 1681typedef __checkReturn boolean_t 1682(*efx_tx_ev_t)( 1683 __in_opt void *arg, 1684 __in uint32_t label, 1685 __in uint32_t id); 1686 1687#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1688#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1689#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1690#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1691#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1692#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1693#define EFX_EXCEPTION_RX_ERROR 0x00000007 1694#define EFX_EXCEPTION_TX_ERROR 0x00000008 1695#define EFX_EXCEPTION_EV_ERROR 0x00000009 1696 1697typedef __checkReturn boolean_t 1698(*efx_exception_ev_t)( 1699 __in_opt void *arg, 1700 __in uint32_t label, 1701 __in uint32_t data); 1702 1703typedef __checkReturn boolean_t 1704(*efx_rxq_flush_done_ev_t)( 1705 __in_opt void *arg, 1706 __in uint32_t rxq_index); 1707 1708typedef __checkReturn boolean_t 1709(*efx_rxq_flush_failed_ev_t)( 1710 __in_opt void *arg, 1711 __in uint32_t rxq_index); 1712 1713typedef __checkReturn boolean_t 1714(*efx_txq_flush_done_ev_t)( 1715 __in_opt void *arg, 1716 __in uint32_t txq_index); 1717 1718typedef __checkReturn boolean_t 1719(*efx_software_ev_t)( 1720 __in_opt void *arg, 1721 __in uint16_t magic); 1722 1723typedef __checkReturn boolean_t 1724(*efx_sram_ev_t)( 1725 __in_opt void *arg, 1726 __in uint32_t code); 1727 1728#define EFX_SRAM_CLEAR 0 1729#define EFX_SRAM_UPDATE 1 1730#define EFX_SRAM_ILLEGAL_CLEAR 2 1731 1732typedef __checkReturn boolean_t 1733(*efx_wake_up_ev_t)( 1734 __in_opt void *arg, 1735 __in uint32_t label); 1736 1737typedef __checkReturn boolean_t 1738(*efx_timer_ev_t)( 1739 __in_opt void *arg, 1740 __in uint32_t label); 1741 1742typedef __checkReturn boolean_t 1743(*efx_link_change_ev_t)( 1744 __in_opt void *arg, 1745 __in efx_link_mode_t link_mode); 1746 1747#if EFSYS_OPT_MON_STATS 1748 1749typedef __checkReturn boolean_t 1750(*efx_monitor_ev_t)( 1751 __in_opt void *arg, 1752 __in efx_mon_stat_t id, 1753 __in efx_mon_stat_value_t value); 1754 1755#endif /* EFSYS_OPT_MON_STATS */ 1756 1757#if EFSYS_OPT_MAC_STATS 1758 1759typedef __checkReturn boolean_t 1760(*efx_mac_stats_ev_t)( 1761 __in_opt void *arg, 1762 __in uint32_t generation 1763 ); 1764 1765#endif /* EFSYS_OPT_MAC_STATS */ 1766 1767typedef struct efx_ev_callbacks_s { 1768 efx_initialized_ev_t eec_initialized; 1769 efx_rx_ev_t eec_rx; 1770 efx_tx_ev_t eec_tx; 1771 efx_exception_ev_t eec_exception; 1772 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1773 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1774 efx_txq_flush_done_ev_t eec_txq_flush_done; 1775 efx_software_ev_t eec_software; 1776 efx_sram_ev_t eec_sram; 1777 efx_wake_up_ev_t eec_wake_up; 1778 efx_timer_ev_t eec_timer; 1779 efx_link_change_ev_t eec_link_change; 1780#if EFSYS_OPT_MON_STATS 1781 efx_monitor_ev_t eec_monitor; 1782#endif /* EFSYS_OPT_MON_STATS */ 1783#if EFSYS_OPT_MAC_STATS 1784 efx_mac_stats_ev_t eec_mac_stats; 1785#endif /* EFSYS_OPT_MAC_STATS */ 1786} efx_ev_callbacks_t; 1787 1788extern __checkReturn boolean_t 1789efx_ev_qpending( 1790 __in efx_evq_t *eep, 1791 __in unsigned int count); 1792 1793#if EFSYS_OPT_EV_PREFETCH 1794 1795extern void 1796efx_ev_qprefetch( 1797 __in efx_evq_t *eep, 1798 __in unsigned int count); 1799 1800#endif /* EFSYS_OPT_EV_PREFETCH */ 1801 1802extern void 1803efx_ev_qpoll( 1804 __in efx_evq_t *eep, 1805 __inout unsigned int *countp, 1806 __in const efx_ev_callbacks_t *eecp, 1807 __in_opt void *arg); 1808 1809extern __checkReturn efx_rc_t 1810efx_ev_qmoderate( 1811 __in efx_evq_t *eep, 1812 __in unsigned int us); 1813 1814extern __checkReturn efx_rc_t 1815efx_ev_qprime( 1816 __in efx_evq_t *eep, 1817 __in unsigned int count); 1818 1819#if EFSYS_OPT_QSTATS 1820 1821#if EFSYS_OPT_NAMES 1822 1823extern const char * 1824efx_ev_qstat_name( 1825 __in efx_nic_t *enp, 1826 __in unsigned int id); 1827 1828#endif /* EFSYS_OPT_NAMES */ 1829 1830extern void 1831efx_ev_qstats_update( 1832 __in efx_evq_t *eep, 1833 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1834 1835#endif /* EFSYS_OPT_QSTATS */ 1836 1837extern void 1838efx_ev_qdestroy( 1839 __in efx_evq_t *eep); 1840 1841/* RX */ 1842 1843extern __checkReturn efx_rc_t 1844efx_rx_init( 1845 __inout efx_nic_t *enp); 1846 1847extern void 1848efx_rx_fini( 1849 __in efx_nic_t *enp); 1850 1851#if EFSYS_OPT_RX_HDR_SPLIT 1852 __checkReturn efx_rc_t 1853efx_rx_hdr_split_enable( 1854 __in efx_nic_t *enp, 1855 __in unsigned int hdr_buf_size, 1856 __in unsigned int pld_buf_size); 1857 1858#endif /* EFSYS_OPT_RX_HDR_SPLIT */ 1859 1860#if EFSYS_OPT_RX_SCATTER 1861 __checkReturn efx_rc_t 1862efx_rx_scatter_enable( 1863 __in efx_nic_t *enp, 1864 __in unsigned int buf_size); 1865#endif /* EFSYS_OPT_RX_SCATTER */ 1866 1867#if EFSYS_OPT_RX_SCALE 1868 1869typedef enum efx_rx_hash_alg_e { 1870 EFX_RX_HASHALG_LFSR = 0, 1871 EFX_RX_HASHALG_TOEPLITZ 1872} efx_rx_hash_alg_t; 1873 1874typedef enum efx_rx_hash_type_e { 1875 EFX_RX_HASH_IPV4 = 0, 1876 EFX_RX_HASH_TCPIPV4, 1877 EFX_RX_HASH_IPV6, 1878 EFX_RX_HASH_TCPIPV6, 1879} efx_rx_hash_type_t; 1880 1881typedef enum efx_rx_hash_support_e { 1882 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1883 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1884} efx_rx_hash_support_t; 1885 1886#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1887#define EFX_MAXRSS 64 /* RX indirection entry range */ 1888#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1889 1890typedef enum efx_rx_scale_support_e { 1891 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1892 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1893 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1894} efx_rx_scale_support_t; 1895 1896extern __checkReturn efx_rc_t 1897efx_rx_hash_support_get( 1898 __in efx_nic_t *enp, 1899 __out efx_rx_hash_support_t *supportp); 1900 1901 1902extern __checkReturn efx_rc_t 1903efx_rx_scale_support_get( 1904 __in efx_nic_t *enp, 1905 __out efx_rx_scale_support_t *supportp); 1906 1907extern __checkReturn efx_rc_t 1908efx_rx_scale_mode_set( 1909 __in efx_nic_t *enp, 1910 __in efx_rx_hash_alg_t alg, 1911 __in efx_rx_hash_type_t type, 1912 __in boolean_t insert); 1913 1914extern __checkReturn efx_rc_t 1915efx_rx_scale_tbl_set( 1916 __in efx_nic_t *enp, 1917 __in_ecount(n) unsigned int *table, 1918 __in size_t n); 1919 1920extern __checkReturn efx_rc_t 1921efx_rx_scale_key_set( 1922 __in efx_nic_t *enp, 1923 __in_ecount(n) uint8_t *key, 1924 __in size_t n); 1925 1926extern uint32_t 1927efx_psuedo_hdr_hash_get( 1928 __in efx_nic_t *enp, 1929 __in efx_rx_hash_alg_t func, 1930 __in uint8_t *buffer); 1931 1932#endif /* EFSYS_OPT_RX_SCALE */ 1933 1934extern __checkReturn efx_rc_t 1935efx_psuedo_hdr_pkt_length_get( 1936 __in efx_nic_t *enp, 1937 __in uint8_t *buffer, 1938 __out uint16_t *pkt_lengthp); 1939 1940#define EFX_RXQ_MAXNDESCS 4096 1941#define EFX_RXQ_MINNDESCS 512 1942 1943#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1944#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1945#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1946#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1947 1948typedef enum efx_rxq_type_e { 1949 EFX_RXQ_TYPE_DEFAULT, 1950 EFX_RXQ_TYPE_SPLIT_HEADER, 1951 EFX_RXQ_TYPE_SPLIT_PAYLOAD, 1952 EFX_RXQ_TYPE_SCATTER, 1953 EFX_RXQ_NTYPES 1954} efx_rxq_type_t; 1955 1956extern __checkReturn efx_rc_t 1957efx_rx_qcreate( 1958 __in efx_nic_t *enp, 1959 __in unsigned int index, 1960 __in unsigned int label, 1961 __in efx_rxq_type_t type, 1962 __in efsys_mem_t *esmp, 1963 __in size_t n, 1964 __in uint32_t id, 1965 __in efx_evq_t *eep, 1966 __deref_out efx_rxq_t **erpp); 1967 1968typedef struct efx_buffer_s { 1969 efsys_dma_addr_t eb_addr; 1970 size_t eb_size; 1971 boolean_t eb_eop; 1972} efx_buffer_t; 1973 1974typedef struct efx_desc_s { 1975 efx_qword_t ed_eq; 1976} efx_desc_t; 1977 1978extern void 1979efx_rx_qpost( 1980 __in efx_rxq_t *erp, 1981 __in_ecount(n) efsys_dma_addr_t *addrp, 1982 __in size_t size, 1983 __in unsigned int n, 1984 __in unsigned int completed, 1985 __in unsigned int added); 1986 1987extern void 1988efx_rx_qpush( 1989 __in efx_rxq_t *erp, 1990 __in unsigned int added, 1991 __inout unsigned int *pushedp); 1992 1993extern __checkReturn efx_rc_t 1994efx_rx_qflush( 1995 __in efx_rxq_t *erp); 1996 1997extern void 1998efx_rx_qenable( 1999 __in efx_rxq_t *erp); 2000 2001extern void 2002efx_rx_qdestroy( 2003 __in efx_rxq_t *erp); 2004 2005/* TX */ 2006 2007typedef struct efx_txq_s efx_txq_t; 2008 2009#if EFSYS_OPT_QSTATS 2010 2011/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2012typedef enum efx_tx_qstat_e { 2013 TX_POST, 2014 TX_POST_PIO, 2015 TX_NQSTATS 2016} efx_tx_qstat_t; 2017 2018/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2019 2020#endif /* EFSYS_OPT_QSTATS */ 2021 2022extern __checkReturn efx_rc_t 2023efx_tx_init( 2024 __in efx_nic_t *enp); 2025 2026extern void 2027efx_tx_fini( 2028 __in efx_nic_t *enp); 2029 2030#define EFX_BUG35388_WORKAROUND(_encp) \ 2031 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 2032 2033#define EFX_TXQ_MAXNDESCS(_encp) \ 2034 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 2035 2036#define EFX_TXQ_MINNDESCS 512 2037 2038#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2039#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2040#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2041#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2042 2043#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2044 2045#define EFX_TXQ_CKSUM_IPV4 0x0001 2046#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2047 2048extern __checkReturn efx_rc_t 2049efx_tx_qcreate( 2050 __in efx_nic_t *enp, 2051 __in unsigned int index, 2052 __in unsigned int label, 2053 __in efsys_mem_t *esmp, 2054 __in size_t n, 2055 __in uint32_t id, 2056 __in uint16_t flags, 2057 __in efx_evq_t *eep, 2058 __deref_out efx_txq_t **etpp, 2059 __out unsigned int *addedp); 2060 2061extern __checkReturn efx_rc_t 2062efx_tx_qpost( 2063 __in efx_txq_t *etp, 2064 __in_ecount(n) efx_buffer_t *eb, 2065 __in unsigned int n, 2066 __in unsigned int completed, 2067 __inout unsigned int *addedp); 2068 2069extern __checkReturn efx_rc_t 2070efx_tx_qpace( 2071 __in efx_txq_t *etp, 2072 __in unsigned int ns); 2073 2074extern void 2075efx_tx_qpush( 2076 __in efx_txq_t *etp, 2077 __in unsigned int added, 2078 __in unsigned int pushed); 2079 2080extern __checkReturn efx_rc_t 2081efx_tx_qflush( 2082 __in efx_txq_t *etp); 2083 2084extern void 2085efx_tx_qenable( 2086 __in efx_txq_t *etp); 2087 2088extern __checkReturn efx_rc_t 2089efx_tx_qpio_enable( 2090 __in efx_txq_t *etp); 2091 2092extern void 2093efx_tx_qpio_disable( 2094 __in efx_txq_t *etp); 2095 2096extern __checkReturn efx_rc_t 2097efx_tx_qpio_write( 2098 __in efx_txq_t *etp, 2099 __in_ecount(buf_length) uint8_t *buffer, 2100 __in size_t buf_length, 2101 __in size_t pio_buf_offset); 2102 2103extern __checkReturn efx_rc_t 2104efx_tx_qpio_post( 2105 __in efx_txq_t *etp, 2106 __in size_t pkt_length, 2107 __in unsigned int completed, 2108 __inout unsigned int *addedp); 2109 2110extern __checkReturn efx_rc_t 2111efx_tx_qdesc_post( 2112 __in efx_txq_t *etp, 2113 __in_ecount(n) efx_desc_t *ed, 2114 __in unsigned int n, 2115 __in unsigned int completed, 2116 __inout unsigned int *addedp); 2117 2118extern void 2119efx_tx_qdesc_dma_create( 2120 __in efx_txq_t *etp, 2121 __in efsys_dma_addr_t addr, 2122 __in size_t size, 2123 __in boolean_t eop, 2124 __out efx_desc_t *edp); 2125 2126extern void 2127efx_tx_qdesc_tso_create( 2128 __in efx_txq_t *etp, 2129 __in uint16_t ipv4_id, 2130 __in uint32_t tcp_seq, 2131 __in uint8_t tcp_flags, 2132 __out efx_desc_t *edp); 2133 2134extern void 2135efx_tx_qdesc_vlantci_create( 2136 __in efx_txq_t *etp, 2137 __in uint16_t tci, 2138 __out efx_desc_t *edp); 2139 2140#if EFSYS_OPT_QSTATS 2141 2142#if EFSYS_OPT_NAMES 2143 2144extern const char * 2145efx_tx_qstat_name( 2146 __in efx_nic_t *etp, 2147 __in unsigned int id); 2148 2149#endif /* EFSYS_OPT_NAMES */ 2150 2151extern void 2152efx_tx_qstats_update( 2153 __in efx_txq_t *etp, 2154 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2155 2156#endif /* EFSYS_OPT_QSTATS */ 2157 2158extern void 2159efx_tx_qdestroy( 2160 __in efx_txq_t *etp); 2161 2162 2163/* FILTER */ 2164 2165#if EFSYS_OPT_FILTER 2166 2167#define EFX_ETHER_TYPE_IPV4 0x0800 2168#define EFX_ETHER_TYPE_IPV6 0x86DD 2169 2170#define EFX_IPPROTO_TCP 6 2171#define EFX_IPPROTO_UDP 17 2172 2173typedef enum efx_filter_flag_e { 2174 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 2175 * multiple queues */ 2176 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 2177 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter 2178 * (priority EFX_FILTER_PRI_AUTO). 2179 * May only be set by the filter 2180 * implementation for each type. 2181 * A removal request will 2182 * restore the automatic filter 2183 * in its place. */ 2184 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ 2185 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ 2186} efx_filter_flag_t; 2187 2188typedef enum efx_filter_match_flags_e { 2189 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2190 * address */ 2191 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2192 * address */ 2193 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2194 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2195 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2196 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2197 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2198 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2199 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2200 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2201 * protocol */ 2202 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address 2203 * I/G bit. Used for RX default 2204 * unicast and multicast/ 2205 * broadcast filters. */ 2206} efx_filter_match_flags_t; 2207 2208typedef enum efx_filter_priority_s { 2209 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2210 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2211 * address list or hardware 2212 * requirements. This may only be used 2213 * by the filter implementation for 2214 * each NIC type. */ 2215 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2216 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2217 * client (e.g. SR-IOV, HyperV VMQ etc.) 2218 */ 2219} efx_filter_priority_t; 2220 2221/* 2222 * FIXME: All these fields are assumed to be in little-endian byte order. 2223 * It may be better for some to be big-endian. See bug42804. 2224 */ 2225 2226typedef struct efx_filter_spec_s { 2227 uint32_t efs_match_flags:12; 2228 uint32_t efs_priority:2; 2229 uint32_t efs_flags:6; 2230 uint32_t efs_dmaq_id:12; 2231 uint32_t efs_rss_context; 2232 uint16_t efs_outer_vid; 2233 uint16_t efs_inner_vid; 2234 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2235 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2236 uint16_t efs_ether_type; 2237 uint8_t efs_ip_proto; 2238 uint16_t efs_loc_port; 2239 uint16_t efs_rem_port; 2240 efx_oword_t efs_rem_host; 2241 efx_oword_t efs_loc_host; 2242} efx_filter_spec_t; 2243 2244 2245/* Default values for use in filter specifications */ 2246#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2247#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2248#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2249 2250extern __checkReturn efx_rc_t 2251efx_filter_init( 2252 __in efx_nic_t *enp); 2253 2254extern void 2255efx_filter_fini( 2256 __in efx_nic_t *enp); 2257 2258extern __checkReturn efx_rc_t 2259efx_filter_insert( 2260 __in efx_nic_t *enp, 2261 __inout efx_filter_spec_t *spec); 2262 2263extern __checkReturn efx_rc_t 2264efx_filter_remove( 2265 __in efx_nic_t *enp, 2266 __inout efx_filter_spec_t *spec); 2267 2268extern __checkReturn efx_rc_t 2269efx_filter_restore( 2270 __in efx_nic_t *enp); 2271 2272extern __checkReturn efx_rc_t 2273efx_filter_supported_filters( 2274 __in efx_nic_t *enp, 2275 __out uint32_t *list, 2276 __out size_t *length); 2277 2278extern void 2279efx_filter_spec_init_rx( 2280 __inout efx_filter_spec_t *spec, 2281 __in efx_filter_priority_t priority, 2282 __in efx_filter_flag_t flags, 2283 __in efx_rxq_t *erp); 2284 2285extern void 2286efx_filter_spec_init_tx( 2287 __inout efx_filter_spec_t *spec, 2288 __in efx_txq_t *etp); 2289 2290extern __checkReturn efx_rc_t 2291efx_filter_spec_set_ipv4_local( 2292 __inout efx_filter_spec_t *spec, 2293 __in uint8_t proto, 2294 __in uint32_t host, 2295 __in uint16_t port); 2296 2297extern __checkReturn efx_rc_t 2298efx_filter_spec_set_ipv4_full( 2299 __inout efx_filter_spec_t *spec, 2300 __in uint8_t proto, 2301 __in uint32_t lhost, 2302 __in uint16_t lport, 2303 __in uint32_t rhost, 2304 __in uint16_t rport); 2305 2306extern __checkReturn efx_rc_t 2307efx_filter_spec_set_eth_local( 2308 __inout efx_filter_spec_t *spec, 2309 __in uint16_t vid, 2310 __in const uint8_t *addr); 2311 2312extern __checkReturn efx_rc_t 2313efx_filter_spec_set_uc_def( 2314 __inout efx_filter_spec_t *spec); 2315 2316extern __checkReturn efx_rc_t 2317efx_filter_spec_set_mc_def( 2318 __inout efx_filter_spec_t *spec); 2319 2320#endif /* EFSYS_OPT_FILTER */ 2321 2322/* HASH */ 2323 2324extern __checkReturn uint32_t 2325efx_hash_dwords( 2326 __in_ecount(count) uint32_t const *input, 2327 __in size_t count, 2328 __in uint32_t init); 2329 2330extern __checkReturn uint32_t 2331efx_hash_bytes( 2332 __in_ecount(length) uint8_t const *input, 2333 __in size_t length, 2334 __in uint32_t init); 2335 2336 2337#ifdef __cplusplus 2338} 2339#endif 2340 2341#endif /* _SYS_EFX_H */ 2342