efx.h revision 293976
1169689Skan/*- 2169689Skan * Copyright (c) 2006-2015 Solarflare Communications Inc. 3169689Skan * All rights reserved. 4169689Skan * 5169689Skan * Redistribution and use in source and binary forms, with or without 6169689Skan * modification, are permitted provided that the following conditions are met: 7169689Skan * 8169689Skan * 1. Redistributions of source code must retain the above copyright notice, 9169689Skan * this list of conditions and the following disclaimer. 10169689Skan * 2. Redistributions in binary form must reproduce the above copyright notice, 11169689Skan * this list of conditions and the following disclaimer in the documentation 12169689Skan * and/or other materials provided with the distribution. 13169689Skan * 14169689Skan * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15169689Skan * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16169689Skan * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17169689Skan * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18169689Skan * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19169689Skan * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20169689Skan * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21169689Skan * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22169689Skan * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23169689Skan * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24169689Skan * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25169689Skan * 26169689Skan * The views and conclusions contained in the software and documentation are 27169689Skan * those of the authors and should not be interpreted as representing official 28169689Skan * policies, either expressed or implied, of the FreeBSD Project. 29169689Skan * 30169689Skan * $FreeBSD: stable/10/sys/dev/sfxge/common/efx.h 293976 2016-01-14 15:49:15Z arybchik $ 31169689Skan */ 32169689Skan 33169689Skan#ifndef _SYS_EFX_H 34169689Skan#define _SYS_EFX_H 35169689Skan 36169689Skan#include "efsys.h" 37169689Skan#include "efx_phy_ids.h" 38169689Skan 39169689Skan#ifdef __cplusplus 40169689Skanextern "C" { 41169689Skan#endif 42169689Skan 43169689Skan#define EFX_STATIC_ASSERT(_cond) \ 44169689Skan ((void)sizeof(char[(_cond) ? 1 : -1])) 45169689Skan 46169689Skan#define EFX_ARRAY_SIZE(_array) \ 47169689Skan (sizeof(_array) / sizeof((_array)[0])) 48169689Skan 49169689Skan#define EFX_FIELD_OFFSET(_type, _field) \ 50169689Skan ((size_t) &(((_type *)0)->_field)) 51169689Skan 52169689Skan/* Return codes */ 53169689Skan 54169689Skantypedef __success(return == 0) int efx_rc_t; 55169689Skan 56169689Skan 57169689Skan/* Chip families */ 58169689Skan 59169689Skantypedef enum efx_family_e { 60169689Skan EFX_FAMILY_INVALID, 61169689Skan EFX_FAMILY_FALCON, 62169689Skan EFX_FAMILY_SIENA, 63169689Skan EFX_FAMILY_HUNTINGTON, 64169689Skan EFX_FAMILY_MEDFORD, 65169689Skan EFX_FAMILY_NTYPES 66169689Skan} efx_family_t; 67169689Skan 68169689Skanextern __checkReturn efx_rc_t 69169689Skanefx_family( 70169689Skan __in uint16_t venid, 71169689Skan __in uint16_t devid, 72169689Skan __out efx_family_t *efp); 73169689Skan 74169689Skanextern __checkReturn efx_rc_t 75169689Skanefx_infer_family( 76169689Skan __in efsys_bar_t *esbp, 77169689Skan __out efx_family_t *efp); 78169689Skan 79169689Skan#define EFX_PCI_VENID_SFC 0x1924 80169689Skan 81169689Skan#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 82169689Skan 83169689Skan#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 84169689Skan#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 85169689Skan#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 86169689Skan 87169689Skan#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 88169689Skan#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 89169689Skan#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 90169689Skan 91169689Skan#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 92169689Skan#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 93169689Skan 94169689Skan#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 95169689Skan#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 96169689Skan#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 97169689Skan 98169689Skan#define EFX_MEM_BAR 2 99169689Skan 100169689Skan/* Error codes */ 101169689Skan 102169689Skanenum { 103169689Skan EFX_ERR_INVALID, 104169689Skan EFX_ERR_SRAM_OOB, 105169689Skan EFX_ERR_BUFID_DC_OOB, 106169689Skan EFX_ERR_MEM_PERR, 107169689Skan EFX_ERR_RBUF_OWN, 108169689Skan EFX_ERR_TBUF_OWN, 109169689Skan EFX_ERR_RDESQ_OWN, 110169689Skan EFX_ERR_TDESQ_OWN, 111169689Skan EFX_ERR_EVQ_OWN, 112169689Skan EFX_ERR_EVFF_OFLO, 113169689Skan EFX_ERR_ILL_ADDR, 114169689Skan EFX_ERR_SRAM_PERR, 115169689Skan EFX_ERR_NCODES 116169689Skan}; 117169689Skan 118169689Skan/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 119169689Skanextern __checkReturn uint32_t 120169689Skanefx_crc32_calculate( 121169689Skan __in uint32_t crc_init, 122169689Skan __in_ecount(length) uint8_t const *input, 123169689Skan __in int length); 124169689Skan 125169689Skan 126169689Skan/* Type prototypes */ 127169689Skan 128169689Skantypedef struct efx_rxq_s efx_rxq_t; 129169689Skan 130169689Skan/* NIC */ 131169689Skan 132169689Skantypedef struct efx_nic_s efx_nic_t; 133169689Skan 134169689Skan#define EFX_NIC_FUNC_PRIMARY 0x00000001 135169689Skan#define EFX_NIC_FUNC_LINKCTRL 0x00000002 136169689Skan#define EFX_NIC_FUNC_TRUSTED 0x00000004 137169689Skan 138169689Skan 139169689Skanextern __checkReturn efx_rc_t 140169689Skanefx_nic_create( 141169689Skan __in efx_family_t family, 142169689Skan __in efsys_identifier_t *esip, 143169689Skan __in efsys_bar_t *esbp, 144169689Skan __in efsys_lock_t *eslp, 145169689Skan __deref_out efx_nic_t **enpp); 146169689Skan 147169689Skanextern __checkReturn efx_rc_t 148169689Skanefx_nic_probe( 149169689Skan __in efx_nic_t *enp); 150169689Skan 151169689Skan#if EFSYS_OPT_PCIE_TUNE 152169689Skan 153169689Skanextern __checkReturn efx_rc_t 154169689Skanefx_nic_pcie_tune( 155169689Skan __in efx_nic_t *enp, 156169689Skan unsigned int nlanes); 157169689Skan 158169689Skanextern __checkReturn efx_rc_t 159169689Skanefx_nic_pcie_extended_sync( 160169689Skan __in efx_nic_t *enp); 161169689Skan 162169689Skan#endif /* EFSYS_OPT_PCIE_TUNE */ 163169689Skan 164169689Skanextern __checkReturn efx_rc_t 165169689Skanefx_nic_init( 166169689Skan __in efx_nic_t *enp); 167169689Skan 168169689Skanextern __checkReturn efx_rc_t 169169689Skanefx_nic_reset( 170169689Skan __in efx_nic_t *enp); 171169689Skan 172169689Skan#if EFSYS_OPT_DIAG 173169689Skan 174169689Skanextern __checkReturn efx_rc_t 175169689Skanefx_nic_register_test( 176169689Skan __in efx_nic_t *enp); 177169689Skan 178169689Skan#endif /* EFSYS_OPT_DIAG */ 179169689Skan 180169689Skanextern void 181169689Skanefx_nic_fini( 182169689Skan __in efx_nic_t *enp); 183169689Skan 184169689Skanextern void 185169689Skanefx_nic_unprobe( 186169689Skan __in efx_nic_t *enp); 187169689Skan 188169689Skanextern void 189169689Skanefx_nic_destroy( 190169689Skan __in efx_nic_t *enp); 191169689Skan 192169689Skan#if EFSYS_OPT_MCDI 193169689Skan 194169689Skan#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 195169689Skan/* Huntington and Medford require MCDIv2 commands */ 196169689Skan#define WITH_MCDI_V2 1 197169689Skan#endif 198169689Skan 199169689Skantypedef struct efx_mcdi_req_s efx_mcdi_req_t; 200169689Skan 201169689Skantypedef enum efx_mcdi_exception_e { 202169689Skan EFX_MCDI_EXCEPTION_MC_REBOOT, 203169689Skan EFX_MCDI_EXCEPTION_MC_BADASSERT, 204169689Skan} efx_mcdi_exception_t; 205169689Skan 206169689Skan#if EFSYS_OPT_MCDI_LOGGING 207169689Skantypedef enum efx_log_msg_e 208169689Skan{ 209169689Skan EFX_LOG_INVALID, 210169689Skan EFX_LOG_MCDI_REQUEST, 211169689Skan EFX_LOG_MCDI_RESPONSE, 212169689Skan} efx_log_msg_t; 213169689Skan#endif /* EFSYS_OPT_MCDI_LOGGING */ 214169689Skan 215169689Skantypedef struct efx_mcdi_transport_s { 216169689Skan void *emt_context; 217169689Skan efsys_mem_t *emt_dma_mem; 218169689Skan void (*emt_execute)(void *, efx_mcdi_req_t *); 219169689Skan void (*emt_ev_cpl)(void *); 220169689Skan void (*emt_exception)(void *, efx_mcdi_exception_t); 221169689Skan#if EFSYS_OPT_MCDI_LOGGING 222169689Skan void (*emt_logger)(void *, efx_log_msg_t, 223169689Skan void *, size_t, void *, size_t); 224169689Skan#endif /* EFSYS_OPT_MCDI_LOGGING */ 225169689Skan#if EFSYS_OPT_MCDI_PROXY_AUTH 226169689Skan void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 227169689Skan#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 228169689Skan} efx_mcdi_transport_t; 229169689Skan 230169689Skanextern __checkReturn efx_rc_t 231169689Skanefx_mcdi_init( 232169689Skan __in efx_nic_t *enp, 233169689Skan __in const efx_mcdi_transport_t *mtp); 234169689Skan 235169689Skanextern __checkReturn efx_rc_t 236169689Skanefx_mcdi_reboot( 237169689Skan __in efx_nic_t *enp); 238169689Skan 239169689Skan void 240169689Skanefx_mcdi_new_epoch( 241169689Skan __in efx_nic_t *enp); 242169689Skan 243169689Skanextern void 244169689Skanefx_mcdi_request_start( 245169689Skan __in efx_nic_t *enp, 246169689Skan __in efx_mcdi_req_t *emrp, 247169689Skan __in boolean_t ev_cpl); 248169689Skan 249169689Skanextern __checkReturn boolean_t 250169689Skanefx_mcdi_request_poll( 251169689Skan __in efx_nic_t *enp); 252169689Skan 253169689Skanextern __checkReturn boolean_t 254169689Skanefx_mcdi_request_abort( 255169689Skan __in efx_nic_t *enp); 256169689Skan 257169689Skanextern void 258169689Skanefx_mcdi_fini( 259169689Skan __in efx_nic_t *enp); 260169689Skan 261169689Skan#endif /* EFSYS_OPT_MCDI */ 262169689Skan 263169689Skan/* INTR */ 264169689Skan 265169689Skan#define EFX_NINTR_FALCON 64 266169689Skan#define EFX_NINTR_SIENA 1024 267169689Skan 268169689Skantypedef enum efx_intr_type_e { 269169689Skan EFX_INTR_INVALID = 0, 270169689Skan EFX_INTR_LINE, 271169689Skan EFX_INTR_MESSAGE, 272169689Skan EFX_INTR_NTYPES 273169689Skan} efx_intr_type_t; 274169689Skan 275169689Skan#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 276169689Skan 277169689Skanextern __checkReturn efx_rc_t 278169689Skanefx_intr_init( 279169689Skan __in efx_nic_t *enp, 280169689Skan __in efx_intr_type_t type, 281169689Skan __in efsys_mem_t *esmp); 282169689Skan 283169689Skanextern void 284169689Skanefx_intr_enable( 285169689Skan __in efx_nic_t *enp); 286169689Skan 287169689Skanextern void 288169689Skanefx_intr_disable( 289169689Skan __in efx_nic_t *enp); 290169689Skan 291169689Skanextern void 292169689Skanefx_intr_disable_unlocked( 293169689Skan __in efx_nic_t *enp); 294169689Skan 295169689Skan#define EFX_INTR_NEVQS 32 296169689Skan 297169689Skanextern __checkReturn efx_rc_t 298169689Skanefx_intr_trigger( 299169689Skan __in efx_nic_t *enp, 300169689Skan __in unsigned int level); 301169689Skan 302169689Skanextern void 303169689Skanefx_intr_status_line( 304169689Skan __in efx_nic_t *enp, 305169689Skan __out boolean_t *fatalp, 306169689Skan __out uint32_t *maskp); 307169689Skan 308169689Skanextern void 309169689Skanefx_intr_status_message( 310169689Skan __in efx_nic_t *enp, 311169689Skan __in unsigned int message, 312169689Skan __out boolean_t *fatalp); 313169689Skan 314169689Skanextern void 315169689Skanefx_intr_fatal( 316169689Skan __in efx_nic_t *enp); 317169689Skan 318169689Skanextern void 319169689Skanefx_intr_fini( 320169689Skan __in efx_nic_t *enp); 321169689Skan 322169689Skan/* MAC */ 323169689Skan 324169689Skan#if EFSYS_OPT_MAC_STATS 325169689Skan 326169689Skan/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 327169689Skantypedef enum efx_mac_stat_e { 328169689Skan EFX_MAC_RX_OCTETS, 329169689Skan EFX_MAC_RX_PKTS, 330169689Skan EFX_MAC_RX_UNICST_PKTS, 331169689Skan EFX_MAC_RX_MULTICST_PKTS, 332169689Skan EFX_MAC_RX_BRDCST_PKTS, 333169689Skan EFX_MAC_RX_PAUSE_PKTS, 334169689Skan EFX_MAC_RX_LE_64_PKTS, 335169689Skan EFX_MAC_RX_65_TO_127_PKTS, 336169689Skan EFX_MAC_RX_128_TO_255_PKTS, 337169689Skan EFX_MAC_RX_256_TO_511_PKTS, 338169689Skan EFX_MAC_RX_512_TO_1023_PKTS, 339169689Skan EFX_MAC_RX_1024_TO_15XX_PKTS, 340169689Skan EFX_MAC_RX_GE_15XX_PKTS, 341169689Skan EFX_MAC_RX_ERRORS, 342169689Skan EFX_MAC_RX_FCS_ERRORS, 343169689Skan EFX_MAC_RX_DROP_EVENTS, 344169689Skan EFX_MAC_RX_FALSE_CARRIER_ERRORS, 345169689Skan EFX_MAC_RX_SYMBOL_ERRORS, 346169689Skan EFX_MAC_RX_ALIGN_ERRORS, 347169689Skan EFX_MAC_RX_INTERNAL_ERRORS, 348169689Skan EFX_MAC_RX_JABBER_PKTS, 349169689Skan EFX_MAC_RX_LANE0_CHAR_ERR, 350169689Skan EFX_MAC_RX_LANE1_CHAR_ERR, 351169689Skan EFX_MAC_RX_LANE2_CHAR_ERR, 352169689Skan EFX_MAC_RX_LANE3_CHAR_ERR, 353169689Skan EFX_MAC_RX_LANE0_DISP_ERR, 354169689Skan EFX_MAC_RX_LANE1_DISP_ERR, 355169689Skan EFX_MAC_RX_LANE2_DISP_ERR, 356169689Skan EFX_MAC_RX_LANE3_DISP_ERR, 357169689Skan EFX_MAC_RX_MATCH_FAULT, 358169689Skan EFX_MAC_RX_NODESC_DROP_CNT, 359169689Skan EFX_MAC_TX_OCTETS, 360169689Skan EFX_MAC_TX_PKTS, 361169689Skan EFX_MAC_TX_UNICST_PKTS, 362169689Skan EFX_MAC_TX_MULTICST_PKTS, 363169689Skan EFX_MAC_TX_BRDCST_PKTS, 364169689Skan EFX_MAC_TX_PAUSE_PKTS, 365169689Skan EFX_MAC_TX_LE_64_PKTS, 366169689Skan EFX_MAC_TX_65_TO_127_PKTS, 367169689Skan EFX_MAC_TX_128_TO_255_PKTS, 368169689Skan EFX_MAC_TX_256_TO_511_PKTS, 369169689Skan EFX_MAC_TX_512_TO_1023_PKTS, 370169689Skan EFX_MAC_TX_1024_TO_15XX_PKTS, 371169689Skan EFX_MAC_TX_GE_15XX_PKTS, 372169689Skan EFX_MAC_TX_ERRORS, 373169689Skan EFX_MAC_TX_SGL_COL_PKTS, 374169689Skan EFX_MAC_TX_MULT_COL_PKTS, 375169689Skan EFX_MAC_TX_EX_COL_PKTS, 376169689Skan EFX_MAC_TX_LATE_COL_PKTS, 377169689Skan EFX_MAC_TX_DEF_PKTS, 378169689Skan EFX_MAC_TX_EX_DEF_PKTS, 379169689Skan EFX_MAC_PM_TRUNC_BB_OVERFLOW, 380169689Skan EFX_MAC_PM_DISCARD_BB_OVERFLOW, 381169689Skan EFX_MAC_PM_TRUNC_VFIFO_FULL, 382169689Skan EFX_MAC_PM_DISCARD_VFIFO_FULL, 383169689Skan EFX_MAC_PM_TRUNC_QBB, 384169689Skan EFX_MAC_PM_DISCARD_QBB, 385169689Skan EFX_MAC_PM_DISCARD_MAPPING, 386169689Skan EFX_MAC_RXDP_Q_DISABLED_PKTS, 387169689Skan EFX_MAC_RXDP_DI_DROPPED_PKTS, 388169689Skan EFX_MAC_RXDP_STREAMING_PKTS, 389169689Skan EFX_MAC_RXDP_HLB_FETCH, 390169689Skan EFX_MAC_RXDP_HLB_WAIT, 391169689Skan EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 392169689Skan EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 393169689Skan EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 394169689Skan EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 395169689Skan EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 396169689Skan EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 397169689Skan EFX_MAC_VADAPTER_RX_BAD_PACKETS, 398169689Skan EFX_MAC_VADAPTER_RX_BAD_BYTES, 399169689Skan EFX_MAC_VADAPTER_RX_OVERFLOW, 400169689Skan EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 401169689Skan EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 402169689Skan EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 403169689Skan EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 404169689Skan EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 405169689Skan EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 406169689Skan EFX_MAC_VADAPTER_TX_BAD_PACKETS, 407169689Skan EFX_MAC_VADAPTER_TX_BAD_BYTES, 408169689Skan EFX_MAC_VADAPTER_TX_OVERFLOW, 409169689Skan EFX_MAC_NSTATS 410169689Skan} efx_mac_stat_t; 411169689Skan 412169689Skan/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 413169689Skan 414169689Skan#endif /* EFSYS_OPT_MAC_STATS */ 415169689Skan 416169689Skantypedef enum efx_link_mode_e { 417169689Skan EFX_LINK_UNKNOWN = 0, 418169689Skan EFX_LINK_DOWN, 419169689Skan EFX_LINK_10HDX, 420169689Skan EFX_LINK_10FDX, 421169689Skan EFX_LINK_100HDX, 422169689Skan EFX_LINK_100FDX, 423169689Skan EFX_LINK_1000HDX, 424169689Skan EFX_LINK_1000FDX, 425169689Skan EFX_LINK_10000FDX, 426169689Skan EFX_LINK_40000FDX, 427169689Skan EFX_LINK_NMODES 428169689Skan} efx_link_mode_t; 429169689Skan 430169689Skan#define EFX_MAC_ADDR_LEN 6 431169689Skan 432169689Skan#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) 433169689Skan 434169689Skan#define EFX_MAC_MULTICAST_LIST_MAX 256 435169689Skan 436169689Skan#define EFX_MAC_SDU_MAX 9202 437169689Skan 438169689Skan#define EFX_MAC_PDU(_sdu) \ 439169689Skan P2ROUNDUP(((_sdu) \ 440169689Skan + /* EtherII */ 14 \ 441169689Skan + /* VLAN */ 4 \ 442169689Skan + /* CRC */ 4 \ 443169689Skan + /* bug16011 */ 16), \ 444169689Skan (1 << 3)) 445169689Skan 446169689Skan#define EFX_MAC_PDU_MIN 60 447169689Skan#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 448169689Skan 449169689Skanextern __checkReturn efx_rc_t 450169689Skanefx_mac_pdu_set( 451169689Skan __in efx_nic_t *enp, 452169689Skan __in size_t pdu); 453169689Skan 454169689Skanextern __checkReturn efx_rc_t 455169689Skanefx_mac_addr_set( 456169689Skan __in efx_nic_t *enp, 457169689Skan __in uint8_t *addr); 458169689Skan 459169689Skanextern __checkReturn efx_rc_t 460169689Skanefx_mac_filter_set( 461169689Skan __in efx_nic_t *enp, 462169689Skan __in boolean_t all_unicst, 463169689Skan __in boolean_t mulcst, 464169689Skan __in boolean_t all_mulcst, 465169689Skan __in boolean_t brdcst); 466169689Skan 467169689Skanextern __checkReturn efx_rc_t 468169689Skanefx_mac_multicast_list_set( 469169689Skan __in efx_nic_t *enp, 470169689Skan __in_ecount(6*count) uint8_t const *addrs, 471169689Skan __in int count); 472169689Skan 473169689Skanextern __checkReturn efx_rc_t 474169689Skanefx_mac_filter_default_rxq_set( 475169689Skan __in efx_nic_t *enp, 476169689Skan __in efx_rxq_t *erp, 477169689Skan __in boolean_t using_rss); 478169689Skan 479169689Skanextern void 480169689Skanefx_mac_filter_default_rxq_clear( 481169689Skan __in efx_nic_t *enp); 482169689Skan 483169689Skanextern __checkReturn efx_rc_t 484169689Skanefx_mac_drain( 485169689Skan __in efx_nic_t *enp, 486169689Skan __in boolean_t enabled); 487169689Skan 488169689Skanextern __checkReturn efx_rc_t 489169689Skanefx_mac_up( 490169689Skan __in efx_nic_t *enp, 491169689Skan __out boolean_t *mac_upp); 492169689Skan 493169689Skan#define EFX_FCNTL_RESPOND 0x00000001 494169689Skan#define EFX_FCNTL_GENERATE 0x00000002 495169689Skan 496169689Skanextern __checkReturn efx_rc_t 497169689Skanefx_mac_fcntl_set( 498169689Skan __in efx_nic_t *enp, 499169689Skan __in unsigned int fcntl, 500169689Skan __in boolean_t autoneg); 501169689Skan 502169689Skanextern void 503169689Skanefx_mac_fcntl_get( 504169689Skan __in efx_nic_t *enp, 505169689Skan __out unsigned int *fcntl_wantedp, 506169689Skan __out unsigned int *fcntl_linkp); 507169689Skan 508169689Skan#define EFX_MAC_HASH_BITS (1 << 8) 509169689Skan 510169689Skanextern __checkReturn efx_rc_t 511169689Skanefx_pktfilter_init( 512169689Skan __in efx_nic_t *enp); 513169689Skan 514169689Skanextern void 515169689Skanefx_pktfilter_fini( 516169689Skan __in efx_nic_t *enp); 517169689Skan 518169689Skanextern __checkReturn efx_rc_t 519169689Skanefx_pktfilter_set( 520169689Skan __in efx_nic_t *enp, 521169689Skan __in boolean_t unicst, 522169689Skan __in boolean_t brdcst); 523169689Skan 524169689Skanextern __checkReturn efx_rc_t 525169689Skanefx_mac_hash_set( 526169689Skan __in efx_nic_t *enp, 527169689Skan __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); 528169689Skan 529169689Skan#if EFSYS_OPT_MCAST_FILTER_LIST 530169689Skanextern __checkReturn efx_rc_t 531169689Skanefx_pktfilter_mcast_list_set( 532169689Skan __in efx_nic_t *enp, 533169689Skan __in uint8_t const *addrs, 534169689Skan __in int count); 535169689Skan#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ 536169689Skan 537169689Skanextern __checkReturn efx_rc_t 538169689Skanefx_pktfilter_mcast_all( 539169689Skan __in efx_nic_t *enp); 540169689Skan 541169689Skan#if EFSYS_OPT_MAC_STATS 542169689Skan 543169689Skan#if EFSYS_OPT_NAMES 544169689Skan 545169689Skanextern __checkReturn const char * 546169689Skanefx_mac_stat_name( 547169689Skan __in efx_nic_t *enp, 548169689Skan __in unsigned int id); 549169689Skan 550169689Skan#endif /* EFSYS_OPT_NAMES */ 551169689Skan 552169689Skan#define EFX_MAC_STATS_SIZE 0x400 553169689Skan 554169689Skan/* 555169689Skan * Upload mac statistics supported by the hardware into the given buffer. 556169689Skan * 557169689Skan * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 558169689Skan * and page aligned. 559169689Skan * 560169689Skan * The hardware will only DMA statistics that it understands (of course). 561169689Skan * Drivers should not make any assumptions about which statistics are 562169689Skan * supported, especially when the statistics are generated by firmware. 563169689Skan * 564169689Skan * Thus, drivers should zero this buffer before use, so that not-understood 565169689Skan * statistics read back as zero. 566169689Skan */ 567169689Skanextern __checkReturn efx_rc_t 568169689Skanefx_mac_stats_upload( 569169689Skan __in efx_nic_t *enp, 570169689Skan __in efsys_mem_t *esmp); 571169689Skan 572169689Skanextern __checkReturn efx_rc_t 573169689Skanefx_mac_stats_periodic( 574169689Skan __in efx_nic_t *enp, 575169689Skan __in efsys_mem_t *esmp, 576169689Skan __in uint16_t period_ms, 577169689Skan __in boolean_t events); 578169689Skan 579169689Skanextern __checkReturn efx_rc_t 580169689Skanefx_mac_stats_update( 581169689Skan __in efx_nic_t *enp, 582169689Skan __in efsys_mem_t *esmp, 583169689Skan __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 584169689Skan __inout_opt uint32_t *generationp); 585169689Skan 586169689Skan#endif /* EFSYS_OPT_MAC_STATS */ 587169689Skan 588169689Skan/* MON */ 589169689Skan 590169689Skantypedef enum efx_mon_type_e { 591169689Skan EFX_MON_INVALID = 0, 592169689Skan EFX_MON_NULL, 593169689Skan EFX_MON_LM87, 594169689Skan EFX_MON_MAX6647, 595169689Skan EFX_MON_SFC90X0, 596169689Skan EFX_MON_SFC91X0, 597169689Skan EFX_MON_NTYPES 598169689Skan} efx_mon_type_t; 599169689Skan 600169689Skan#if EFSYS_OPT_NAMES 601169689Skan 602169689Skanextern const char * 603169689Skanefx_mon_name( 604169689Skan __in efx_nic_t *enp); 605169689Skan 606169689Skan#endif /* EFSYS_OPT_NAMES */ 607169689Skan 608169689Skanextern __checkReturn efx_rc_t 609169689Skanefx_mon_init( 610169689Skan __in efx_nic_t *enp); 611169689Skan 612169689Skan#if EFSYS_OPT_MON_STATS 613169689Skan 614169689Skan#define EFX_MON_STATS_PAGE_SIZE 0x100 615169689Skan#define EFX_MON_MASK_ELEMENT_SIZE 32 616169689Skan 617169689Skan/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */ 618169689Skantypedef enum efx_mon_stat_e { 619169689Skan EFX_MON_STAT_2_5V, 620169689Skan EFX_MON_STAT_VCCP1, 621169689Skan EFX_MON_STAT_VCC, 622169689Skan EFX_MON_STAT_5V, 623169689Skan EFX_MON_STAT_12V, 624169689Skan EFX_MON_STAT_VCCP2, 625169689Skan EFX_MON_STAT_EXT_TEMP, 626169689Skan EFX_MON_STAT_INT_TEMP, 627169689Skan EFX_MON_STAT_AIN1, 628169689Skan EFX_MON_STAT_AIN2, 629169689Skan EFX_MON_STAT_INT_COOLING, 630169689Skan EFX_MON_STAT_EXT_COOLING, 631169689Skan EFX_MON_STAT_1V, 632169689Skan EFX_MON_STAT_1_2V, 633169689Skan EFX_MON_STAT_1_8V, 634169689Skan EFX_MON_STAT_3_3V, 635169689Skan EFX_MON_STAT_1_2VA, 636169689Skan EFX_MON_STAT_VREF, 637169689Skan EFX_MON_STAT_VAOE, 638169689Skan EFX_MON_STAT_AOE_TEMP, 639169689Skan EFX_MON_STAT_PSU_AOE_TEMP, 640169689Skan EFX_MON_STAT_PSU_TEMP, 641169689Skan EFX_MON_STAT_FAN0, 642169689Skan EFX_MON_STAT_FAN1, 643169689Skan EFX_MON_STAT_FAN2, 644169689Skan EFX_MON_STAT_FAN3, 645169689Skan EFX_MON_STAT_FAN4, 646169689Skan EFX_MON_STAT_VAOE_IN, 647169689Skan EFX_MON_STAT_IAOE, 648169689Skan EFX_MON_STAT_IAOE_IN, 649169689Skan EFX_MON_STAT_NIC_POWER, 650169689Skan EFX_MON_STAT_0_9V, 651169689Skan EFX_MON_STAT_I0_9V, 652169689Skan EFX_MON_STAT_I1_2V, 653169689Skan EFX_MON_STAT_0_9V_ADC, 654169689Skan EFX_MON_STAT_INT_TEMP2, 655169689Skan EFX_MON_STAT_VREG_TEMP, 656169689Skan EFX_MON_STAT_VREG_0_9V_TEMP, 657169689Skan EFX_MON_STAT_VREG_1_2V_TEMP, 658169689Skan EFX_MON_STAT_INT_VPTAT, 659169689Skan EFX_MON_STAT_INT_ADC_TEMP, 660169689Skan EFX_MON_STAT_EXT_VPTAT, 661169689Skan EFX_MON_STAT_EXT_ADC_TEMP, 662169689Skan EFX_MON_STAT_AMBIENT_TEMP, 663169689Skan EFX_MON_STAT_AIRFLOW, 664169689Skan EFX_MON_STAT_VDD08D_VSS08D_CSR, 665169689Skan EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 666169689Skan EFX_MON_STAT_HOTPOINT_TEMP, 667169689Skan EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 668169689Skan EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 669169689Skan EFX_MON_STAT_MUM_VCC, 670169689Skan EFX_MON_STAT_0V9_A, 671169689Skan EFX_MON_STAT_I0V9_A, 672169689Skan EFX_MON_STAT_0V9_A_TEMP, 673169689Skan EFX_MON_STAT_0V9_B, 674169689Skan EFX_MON_STAT_I0V9_B, 675169689Skan EFX_MON_STAT_0V9_B_TEMP, 676169689Skan EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 677169689Skan EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 678169689Skan EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 679169689Skan EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 680169689Skan EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 681169689Skan EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 682169689Skan EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 683169689Skan EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 684169689Skan EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 685169689Skan EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 686169689Skan EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 687169689Skan EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 688169689Skan EFX_MON_NSTATS 689169689Skan} efx_mon_stat_t; 690169689Skan 691169689Skan/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 692169689Skan 693169689Skantypedef enum efx_mon_stat_state_e { 694169689Skan EFX_MON_STAT_STATE_OK = 0, 695169689Skan EFX_MON_STAT_STATE_WARNING = 1, 696169689Skan EFX_MON_STAT_STATE_FATAL = 2, 697169689Skan EFX_MON_STAT_STATE_BROKEN = 3, 698169689Skan EFX_MON_STAT_STATE_NO_READING = 4, 699169689Skan} efx_mon_stat_state_t; 700169689Skan 701169689Skantypedef struct efx_mon_stat_value_s { 702169689Skan uint16_t emsv_value; 703169689Skan uint16_t emsv_state; 704169689Skan} efx_mon_stat_value_t; 705169689Skan 706169689Skan#if EFSYS_OPT_NAMES 707169689Skan 708169689Skanextern const char * 709169689Skanefx_mon_stat_name( 710169689Skan __in efx_nic_t *enp, 711169689Skan __in efx_mon_stat_t id); 712169689Skan 713169689Skan#endif /* EFSYS_OPT_NAMES */ 714169689Skan 715169689Skanextern __checkReturn efx_rc_t 716169689Skanefx_mon_stats_update( 717169689Skan __in efx_nic_t *enp, 718169689Skan __in efsys_mem_t *esmp, 719169689Skan __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 720169689Skan 721169689Skan#endif /* EFSYS_OPT_MON_STATS */ 722169689Skan 723169689Skanextern void 724169689Skanefx_mon_fini( 725169689Skan __in efx_nic_t *enp); 726169689Skan 727169689Skan/* PHY */ 728169689Skan 729169689Skan#define PMA_PMD_MMD 1 730169689Skan#define PCS_MMD 3 731169689Skan#define PHY_XS_MMD 4 732169689Skan#define DTE_XS_MMD 5 733169689Skan#define AN_MMD 7 734169689Skan#define CL22EXT_MMD 29 735169689Skan 736169689Skan#define MAXMMD ((1 << 5) - 1) 737169689Skan 738169689Skanextern __checkReturn efx_rc_t 739169689Skanefx_phy_verify( 740169689Skan __in efx_nic_t *enp); 741169689Skan 742169689Skan#if EFSYS_OPT_PHY_LED_CONTROL 743169689Skan 744169689Skantypedef enum efx_phy_led_mode_e { 745169689Skan EFX_PHY_LED_DEFAULT = 0, 746169689Skan EFX_PHY_LED_OFF, 747169689Skan EFX_PHY_LED_ON, 748169689Skan EFX_PHY_LED_FLASH, 749169689Skan EFX_PHY_LED_NMODES 750169689Skan} efx_phy_led_mode_t; 751169689Skan 752169689Skanextern __checkReturn efx_rc_t 753169689Skanefx_phy_led_set( 754169689Skan __in efx_nic_t *enp, 755169689Skan __in efx_phy_led_mode_t mode); 756169689Skan 757169689Skan#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 758169689Skan 759169689Skanextern __checkReturn efx_rc_t 760169689Skanefx_port_init( 761169689Skan __in efx_nic_t *enp); 762169689Skan 763169689Skan#if EFSYS_OPT_LOOPBACK 764169689Skan 765169689Skantypedef enum efx_loopback_type_e { 766169689Skan EFX_LOOPBACK_OFF = 0, 767169689Skan EFX_LOOPBACK_DATA = 1, 768169689Skan EFX_LOOPBACK_GMAC = 2, 769169689Skan EFX_LOOPBACK_XGMII = 3, 770169689Skan EFX_LOOPBACK_XGXS = 4, 771169689Skan EFX_LOOPBACK_XAUI = 5, 772169689Skan EFX_LOOPBACK_GMII = 6, 773169689Skan EFX_LOOPBACK_SGMII = 7, 774169689Skan EFX_LOOPBACK_XGBR = 8, 775169689Skan EFX_LOOPBACK_XFI = 9, 776169689Skan EFX_LOOPBACK_XAUI_FAR = 10, 777169689Skan EFX_LOOPBACK_GMII_FAR = 11, 778169689Skan EFX_LOOPBACK_SGMII_FAR = 12, 779169689Skan EFX_LOOPBACK_XFI_FAR = 13, 780169689Skan EFX_LOOPBACK_GPHY = 14, 781169689Skan EFX_LOOPBACK_PHY_XS = 15, 782169689Skan EFX_LOOPBACK_PCS = 16, 783169689Skan EFX_LOOPBACK_PMA_PMD = 17, 784169689Skan EFX_LOOPBACK_XPORT = 18, 785169689Skan EFX_LOOPBACK_XGMII_WS = 19, 786169689Skan EFX_LOOPBACK_XAUI_WS = 20, 787169689Skan EFX_LOOPBACK_XAUI_WS_FAR = 21, 788169689Skan EFX_LOOPBACK_XAUI_WS_NEAR = 22, 789169689Skan EFX_LOOPBACK_GMII_WS = 23, 790169689Skan EFX_LOOPBACK_XFI_WS = 24, 791169689Skan EFX_LOOPBACK_XFI_WS_FAR = 25, 792169689Skan EFX_LOOPBACK_PHYXS_WS = 26, 793169689Skan EFX_LOOPBACK_PMA_INT = 27, 794169689Skan EFX_LOOPBACK_SD_NEAR = 28, 795169689Skan EFX_LOOPBACK_SD_FAR = 29, 796169689Skan EFX_LOOPBACK_PMA_INT_WS = 30, 797169689Skan EFX_LOOPBACK_SD_FEP2_WS = 31, 798169689Skan EFX_LOOPBACK_SD_FEP1_5_WS = 32, 799169689Skan EFX_LOOPBACK_SD_FEP_WS = 33, 800169689Skan EFX_LOOPBACK_SD_FES_WS = 34, 801169689Skan EFX_LOOPBACK_NTYPES 802169689Skan} efx_loopback_type_t; 803169689Skan 804169689Skantypedef enum efx_loopback_kind_e { 805169689Skan EFX_LOOPBACK_KIND_OFF = 0, 806169689Skan EFX_LOOPBACK_KIND_ALL, 807169689Skan EFX_LOOPBACK_KIND_MAC, 808169689Skan EFX_LOOPBACK_KIND_PHY, 809169689Skan EFX_LOOPBACK_NKINDS 810169689Skan} efx_loopback_kind_t; 811169689Skan 812169689Skanextern void 813169689Skanefx_loopback_mask( 814169689Skan __in efx_loopback_kind_t loopback_kind, 815169689Skan __out efx_qword_t *maskp); 816169689Skan 817169689Skanextern __checkReturn efx_rc_t 818169689Skanefx_port_loopback_set( 819169689Skan __in efx_nic_t *enp, 820169689Skan __in efx_link_mode_t link_mode, 821169689Skan __in efx_loopback_type_t type); 822169689Skan 823169689Skan#if EFSYS_OPT_NAMES 824169689Skan 825169689Skanextern __checkReturn const char * 826169689Skanefx_loopback_type_name( 827169689Skan __in efx_nic_t *enp, 828169689Skan __in efx_loopback_type_t type); 829169689Skan 830169689Skan#endif /* EFSYS_OPT_NAMES */ 831169689Skan 832169689Skan#endif /* EFSYS_OPT_LOOPBACK */ 833169689Skan 834169689Skanextern __checkReturn efx_rc_t 835169689Skanefx_port_poll( 836169689Skan __in efx_nic_t *enp, 837169689Skan __out_opt efx_link_mode_t *link_modep); 838169689Skan 839169689Skanextern void 840169689Skanefx_port_fini( 841169689Skan __in efx_nic_t *enp); 842169689Skan 843169689Skantypedef enum efx_phy_cap_type_e { 844169689Skan EFX_PHY_CAP_INVALID = 0, 845169689Skan EFX_PHY_CAP_10HDX, 846169689Skan EFX_PHY_CAP_10FDX, 847169689Skan EFX_PHY_CAP_100HDX, 848169689Skan EFX_PHY_CAP_100FDX, 849169689Skan EFX_PHY_CAP_1000HDX, 850169689Skan EFX_PHY_CAP_1000FDX, 851169689Skan EFX_PHY_CAP_10000FDX, 852169689Skan EFX_PHY_CAP_PAUSE, 853169689Skan EFX_PHY_CAP_ASYM, 854169689Skan EFX_PHY_CAP_AN, 855169689Skan EFX_PHY_CAP_40000FDX, 856169689Skan EFX_PHY_CAP_NTYPES 857169689Skan} efx_phy_cap_type_t; 858169689Skan 859169689Skan 860169689Skan#define EFX_PHY_CAP_CURRENT 0x00000000 861169689Skan#define EFX_PHY_CAP_DEFAULT 0x00000001 862169689Skan#define EFX_PHY_CAP_PERM 0x00000002 863169689Skan 864169689Skanextern void 865169689Skanefx_phy_adv_cap_get( 866169689Skan __in efx_nic_t *enp, 867169689Skan __in uint32_t flag, 868169689Skan __out uint32_t *maskp); 869169689Skan 870169689Skanextern __checkReturn efx_rc_t 871169689Skanefx_phy_adv_cap_set( 872169689Skan __in efx_nic_t *enp, 873169689Skan __in uint32_t mask); 874169689Skan 875169689Skanextern void 876169689Skanefx_phy_lp_cap_get( 877169689Skan __in efx_nic_t *enp, 878169689Skan __out uint32_t *maskp); 879169689Skan 880169689Skanextern __checkReturn efx_rc_t 881169689Skanefx_phy_oui_get( 882169689Skan __in efx_nic_t *enp, 883169689Skan __out uint32_t *ouip); 884169689Skan 885169689Skantypedef enum efx_phy_media_type_e { 886169689Skan EFX_PHY_MEDIA_INVALID = 0, 887169689Skan EFX_PHY_MEDIA_XAUI, 888169689Skan EFX_PHY_MEDIA_CX4, 889169689Skan EFX_PHY_MEDIA_KX4, 890169689Skan EFX_PHY_MEDIA_XFP, 891169689Skan EFX_PHY_MEDIA_SFP_PLUS, 892169689Skan EFX_PHY_MEDIA_BASE_T, 893169689Skan EFX_PHY_MEDIA_QSFP_PLUS, 894169689Skan EFX_PHY_MEDIA_NTYPES 895169689Skan} efx_phy_media_type_t; 896169689Skan 897169689Skan/* Get the type of medium currently used. If the board has ports for 898169689Skan * modules, a module is present, and we recognise the media type of 899169689Skan * the module, then this will be the media type of the module. 900169689Skan * Otherwise it will be the media type of the port. 901169689Skan */ 902169689Skanextern void 903169689Skanefx_phy_media_type_get( 904169689Skan __in efx_nic_t *enp, 905169689Skan __out efx_phy_media_type_t *typep); 906169689Skan 907169689Skan#if EFSYS_OPT_PHY_STATS 908169689Skan 909169689Skan/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 910169689Skantypedef enum efx_phy_stat_e { 911169689Skan EFX_PHY_STAT_OUI, 912169689Skan EFX_PHY_STAT_PMA_PMD_LINK_UP, 913169689Skan EFX_PHY_STAT_PMA_PMD_RX_FAULT, 914169689Skan EFX_PHY_STAT_PMA_PMD_TX_FAULT, 915169689Skan EFX_PHY_STAT_PMA_PMD_REV_A, 916169689Skan EFX_PHY_STAT_PMA_PMD_REV_B, 917169689Skan EFX_PHY_STAT_PMA_PMD_REV_C, 918169689Skan EFX_PHY_STAT_PMA_PMD_REV_D, 919169689Skan EFX_PHY_STAT_PCS_LINK_UP, 920169689Skan EFX_PHY_STAT_PCS_RX_FAULT, 921169689Skan EFX_PHY_STAT_PCS_TX_FAULT, 922169689Skan EFX_PHY_STAT_PCS_BER, 923169689Skan EFX_PHY_STAT_PCS_BLOCK_ERRORS, 924169689Skan EFX_PHY_STAT_PHY_XS_LINK_UP, 925169689Skan EFX_PHY_STAT_PHY_XS_RX_FAULT, 926169689Skan EFX_PHY_STAT_PHY_XS_TX_FAULT, 927169689Skan EFX_PHY_STAT_PHY_XS_ALIGN, 928169689Skan EFX_PHY_STAT_PHY_XS_SYNC_A, 929169689Skan EFX_PHY_STAT_PHY_XS_SYNC_B, 930169689Skan EFX_PHY_STAT_PHY_XS_SYNC_C, 931169689Skan EFX_PHY_STAT_PHY_XS_SYNC_D, 932169689Skan EFX_PHY_STAT_AN_LINK_UP, 933169689Skan EFX_PHY_STAT_AN_MASTER, 934169689Skan EFX_PHY_STAT_AN_LOCAL_RX_OK, 935169689Skan EFX_PHY_STAT_AN_REMOTE_RX_OK, 936169689Skan EFX_PHY_STAT_CL22EXT_LINK_UP, 937169689Skan EFX_PHY_STAT_SNR_A, 938169689Skan EFX_PHY_STAT_SNR_B, 939169689Skan EFX_PHY_STAT_SNR_C, 940169689Skan EFX_PHY_STAT_SNR_D, 941169689Skan EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 942169689Skan EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 943169689Skan EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 944169689Skan EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 945169689Skan EFX_PHY_STAT_AN_COMPLETE, 946169689Skan EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 947169689Skan EFX_PHY_STAT_PMA_PMD_REV_MINOR, 948169689Skan EFX_PHY_STAT_PMA_PMD_REV_MICRO, 949169689Skan EFX_PHY_STAT_PCS_FW_VERSION_0, 950169689Skan EFX_PHY_STAT_PCS_FW_VERSION_1, 951169689Skan EFX_PHY_STAT_PCS_FW_VERSION_2, 952169689Skan EFX_PHY_STAT_PCS_FW_VERSION_3, 953169689Skan EFX_PHY_STAT_PCS_FW_BUILD_YY, 954169689Skan EFX_PHY_STAT_PCS_FW_BUILD_MM, 955169689Skan EFX_PHY_STAT_PCS_FW_BUILD_DD, 956169689Skan EFX_PHY_STAT_PCS_OP_MODE, 957169689Skan EFX_PHY_NSTATS 958169689Skan} efx_phy_stat_t; 959169689Skan 960169689Skan/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 961169689Skan 962169689Skan#if EFSYS_OPT_NAMES 963169689Skan 964169689Skanextern const char * 965169689Skanefx_phy_stat_name( 966169689Skan __in efx_nic_t *enp, 967169689Skan __in efx_phy_stat_t stat); 968169689Skan 969169689Skan#endif /* EFSYS_OPT_NAMES */ 970169689Skan 971169689Skan#define EFX_PHY_STATS_SIZE 0x100 972169689Skan 973169689Skanextern __checkReturn efx_rc_t 974169689Skanefx_phy_stats_update( 975169689Skan __in efx_nic_t *enp, 976169689Skan __in efsys_mem_t *esmp, 977169689Skan __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 978169689Skan 979169689Skan#endif /* EFSYS_OPT_PHY_STATS */ 980169689Skan 981169689Skan#if EFSYS_OPT_PHY_PROPS 982169689Skan 983169689Skan#if EFSYS_OPT_NAMES 984169689Skan 985169689Skanextern const char * 986169689Skanefx_phy_prop_name( 987169689Skan __in efx_nic_t *enp, 988169689Skan __in unsigned int id); 989169689Skan 990169689Skan#endif /* EFSYS_OPT_NAMES */ 991169689Skan 992169689Skan#define EFX_PHY_PROP_DEFAULT 0x00000001 993169689Skan 994169689Skanextern __checkReturn efx_rc_t 995169689Skanefx_phy_prop_get( 996169689Skan __in efx_nic_t *enp, 997169689Skan __in unsigned int id, 998169689Skan __in uint32_t flags, 999169689Skan __out uint32_t *valp); 1000169689Skan 1001169689Skanextern __checkReturn efx_rc_t 1002169689Skanefx_phy_prop_set( 1003169689Skan __in efx_nic_t *enp, 1004169689Skan __in unsigned int id, 1005169689Skan __in uint32_t val); 1006169689Skan 1007169689Skan#endif /* EFSYS_OPT_PHY_PROPS */ 1008169689Skan 1009169689Skan#if EFSYS_OPT_BIST 1010169689Skan 1011169689Skantypedef enum efx_bist_type_e { 1012169689Skan EFX_BIST_TYPE_UNKNOWN, 1013169689Skan EFX_BIST_TYPE_PHY_NORMAL, 1014169689Skan EFX_BIST_TYPE_PHY_CABLE_SHORT, 1015169689Skan EFX_BIST_TYPE_PHY_CABLE_LONG, 1016169689Skan EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1017169689Skan EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1018169689Skan EFX_BIST_TYPE_REG, /* Test the register memories */ 1019169689Skan EFX_BIST_TYPE_NTYPES, 1020169689Skan} efx_bist_type_t; 1021169689Skan 1022169689Skantypedef enum efx_bist_result_e { 1023169689Skan EFX_BIST_RESULT_UNKNOWN, 1024169689Skan EFX_BIST_RESULT_RUNNING, 1025169689Skan EFX_BIST_RESULT_PASSED, 1026169689Skan EFX_BIST_RESULT_FAILED, 1027169689Skan} efx_bist_result_t; 1028169689Skan 1029169689Skantypedef enum efx_phy_cable_status_e { 1030169689Skan EFX_PHY_CABLE_STATUS_OK, 1031169689Skan EFX_PHY_CABLE_STATUS_INVALID, 1032169689Skan EFX_PHY_CABLE_STATUS_OPEN, 1033169689Skan EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1034169689Skan EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1035169689Skan EFX_PHY_CABLE_STATUS_BUSY, 1036169689Skan} efx_phy_cable_status_t; 1037169689Skan 1038169689Skantypedef enum efx_bist_value_e { 1039169689Skan EFX_BIST_PHY_CABLE_LENGTH_A, 1040169689Skan EFX_BIST_PHY_CABLE_LENGTH_B, 1041169689Skan EFX_BIST_PHY_CABLE_LENGTH_C, 1042169689Skan EFX_BIST_PHY_CABLE_LENGTH_D, 1043169689Skan EFX_BIST_PHY_CABLE_STATUS_A, 1044169689Skan EFX_BIST_PHY_CABLE_STATUS_B, 1045169689Skan EFX_BIST_PHY_CABLE_STATUS_C, 1046169689Skan EFX_BIST_PHY_CABLE_STATUS_D, 1047169689Skan EFX_BIST_FAULT_CODE, 1048169689Skan /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1049169689Skan * response. */ 1050169689Skan EFX_BIST_MEM_TEST, 1051169689Skan EFX_BIST_MEM_ADDR, 1052169689Skan EFX_BIST_MEM_BUS, 1053169689Skan EFX_BIST_MEM_EXPECT, 1054169689Skan EFX_BIST_MEM_ACTUAL, 1055169689Skan EFX_BIST_MEM_ECC, 1056169689Skan EFX_BIST_MEM_ECC_PARITY, 1057169689Skan EFX_BIST_MEM_ECC_FATAL, 1058169689Skan EFX_BIST_NVALUES, 1059169689Skan} efx_bist_value_t; 1060169689Skan 1061169689Skanextern __checkReturn efx_rc_t 1062169689Skanefx_bist_enable_offline( 1063169689Skan __in efx_nic_t *enp); 1064169689Skan 1065169689Skanextern __checkReturn efx_rc_t 1066169689Skanefx_bist_start( 1067169689Skan __in efx_nic_t *enp, 1068169689Skan __in efx_bist_type_t type); 1069169689Skan 1070169689Skanextern __checkReturn efx_rc_t 1071169689Skanefx_bist_poll( 1072169689Skan __in efx_nic_t *enp, 1073169689Skan __in efx_bist_type_t type, 1074169689Skan __out efx_bist_result_t *resultp, 1075169689Skan __out_opt uint32_t *value_maskp, 1076169689Skan __out_ecount_opt(count) unsigned long *valuesp, 1077169689Skan __in size_t count); 1078169689Skan 1079169689Skanextern void 1080169689Skanefx_bist_stop( 1081169689Skan __in efx_nic_t *enp, 1082169689Skan __in efx_bist_type_t type); 1083169689Skan 1084169689Skan#endif /* EFSYS_OPT_BIST */ 1085169689Skan 1086169689Skan#define EFX_FEATURE_IPV6 0x00000001 1087169689Skan#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1088169689Skan#define EFX_FEATURE_LINK_EVENTS 0x00000004 1089169689Skan#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1090169689Skan#define EFX_FEATURE_WOL 0x00000010 1091169689Skan#define EFX_FEATURE_MCDI 0x00000020 1092169689Skan#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1093169689Skan#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1094169689Skan#define EFX_FEATURE_TURBO 0x00000100 1095169689Skan#define EFX_FEATURE_MCDI_DMA 0x00000200 1096169689Skan#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1097169689Skan#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1098169689Skan#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1099169689Skan 1100169689Skantypedef struct efx_nic_cfg_s { 1101169689Skan uint32_t enc_board_type; 1102169689Skan uint32_t enc_phy_type; 1103169689Skan#if EFSYS_OPT_NAMES 1104169689Skan char enc_phy_name[21]; 1105169689Skan#endif 1106169689Skan char enc_phy_revision[21]; 1107169689Skan efx_mon_type_t enc_mon_type; 1108169689Skan#if EFSYS_OPT_MON_STATS 1109169689Skan uint32_t enc_mon_stat_dma_buf_size; 1110169689Skan uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1111169689Skan#endif 1112169689Skan unsigned int enc_features; 1113169689Skan uint8_t enc_mac_addr[6]; 1114169689Skan uint8_t enc_port; /* PHY port number */ 1115169689Skan uint32_t enc_func_flags; 1116169689Skan uint32_t enc_intr_vec_base; 1117169689Skan uint32_t enc_intr_limit; 1118169689Skan uint32_t enc_evq_limit; 1119169689Skan uint32_t enc_txq_limit; 1120169689Skan uint32_t enc_rxq_limit; 1121169689Skan uint32_t enc_buftbl_limit; 1122169689Skan uint32_t enc_piobuf_limit; 1123169689Skan uint32_t enc_piobuf_size; 1124169689Skan uint32_t enc_evq_timer_quantum_ns; 1125169689Skan uint32_t enc_evq_timer_max_us; 1126169689Skan uint32_t enc_clk_mult; 1127169689Skan uint32_t enc_rx_prefix_size; 1128169689Skan uint32_t enc_rx_buf_align_start; 1129169689Skan uint32_t enc_rx_buf_align_end; 1130169689Skan#if EFSYS_OPT_LOOPBACK 1131169689Skan efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1132169689Skan#endif /* EFSYS_OPT_LOOPBACK */ 1133169689Skan#if EFSYS_OPT_PHY_FLAGS 1134169689Skan uint32_t enc_phy_flags_mask; 1135169689Skan#endif /* EFSYS_OPT_PHY_FLAGS */ 1136169689Skan#if EFSYS_OPT_PHY_LED_CONTROL 1137169689Skan uint32_t enc_led_mask; 1138169689Skan#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1139169689Skan#if EFSYS_OPT_PHY_STATS 1140169689Skan uint64_t enc_phy_stat_mask; 1141169689Skan#endif /* EFSYS_OPT_PHY_STATS */ 1142169689Skan#if EFSYS_OPT_PHY_PROPS 1143169689Skan unsigned int enc_phy_nprops; 1144169689Skan#endif /* EFSYS_OPT_PHY_PROPS */ 1145169689Skan#if EFSYS_OPT_SIENA 1146169689Skan uint8_t enc_mcdi_mdio_channel; 1147169689Skan#if EFSYS_OPT_PHY_STATS 1148169689Skan uint32_t enc_mcdi_phy_stat_mask; 1149169689Skan#endif /* EFSYS_OPT_PHY_STATS */ 1150169689Skan#endif /* EFSYS_OPT_SIENA */ 1151169689Skan#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) 1152169689Skan#if EFSYS_OPT_MON_STATS 1153169689Skan uint32_t *enc_mcdi_sensor_maskp; 1154169689Skan uint32_t enc_mcdi_sensor_mask_size; 1155169689Skan#endif /* EFSYS_OPT_MON_STATS */ 1156169689Skan#endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */ 1157169689Skan#if EFSYS_OPT_BIST 1158169689Skan uint32_t enc_bist_mask; 1159169689Skan#endif /* EFSYS_OPT_BIST */ 1160169689Skan#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1161169689Skan uint32_t enc_pf; 1162169689Skan uint32_t enc_vf; 1163169689Skan uint32_t enc_privilege_mask; 1164169689Skan#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1165169689Skan boolean_t enc_bug26807_workaround; 1166169689Skan boolean_t enc_bug35388_workaround; 1167169689Skan boolean_t enc_bug41750_workaround; 1168169689Skan boolean_t enc_rx_batching_enabled; 1169169689Skan /* Maximum number of descriptors completed in an rx event. */ 1170169689Skan uint32_t enc_rx_batch_max; 1171169689Skan /* Number of rx descriptors the hardware requires for a push. */ 1172169689Skan uint32_t enc_rx_push_align; 1173169689Skan /* 1174169689Skan * Maximum number of bytes into the packet the TCP header can start for 1175169689Skan * the hardware to apply TSO packet edits. 1176169689Skan */ 1177169689Skan uint32_t enc_tx_tso_tcp_header_offset_limit; 1178169689Skan boolean_t enc_fw_assisted_tso_enabled; 1179169689Skan boolean_t enc_hw_tx_insert_vlan_enabled; 1180169689Skan /* Datapath firmware vadapter/vport/vswitch support */ 1181169689Skan boolean_t enc_datapath_cap_evb; 1182169689Skan boolean_t enc_rx_disable_scatter_supported; 1183169689Skan boolean_t enc_allow_set_mac_with_installed_filters; 1184169689Skan /* External port identifier */ 1185169689Skan uint8_t enc_external_port; 1186169689Skan uint32_t enc_mcdi_max_payload_length; 1187169689Skan} efx_nic_cfg_t; 1188169689Skan 1189169689Skan#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1190169689Skan#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1191169689Skan 1192169689Skan#define EFX_PCI_FUNCTION(_encp) \ 1193169689Skan (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1194169689Skan 1195169689Skan#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1196169689Skan 1197169689Skanextern const efx_nic_cfg_t * 1198169689Skanefx_nic_cfg_get( 1199169689Skan __in efx_nic_t *enp); 1200169689Skan 1201169689Skan/* Driver resource limits (minimum required/maximum usable). */ 1202169689Skantypedef struct efx_drv_limits_s 1203169689Skan{ 1204169689Skan uint32_t edl_min_evq_count; 1205169689Skan uint32_t edl_max_evq_count; 1206169689Skan 1207169689Skan uint32_t edl_min_rxq_count; 1208169689Skan uint32_t edl_max_rxq_count; 1209169689Skan 1210169689Skan uint32_t edl_min_txq_count; 1211169689Skan uint32_t edl_max_txq_count; 1212169689Skan 1213169689Skan /* PIO blocks (sub-allocated from piobuf) */ 1214169689Skan uint32_t edl_min_pio_alloc_size; 1215169689Skan uint32_t edl_max_pio_alloc_count; 1216169689Skan} efx_drv_limits_t; 1217169689Skan 1218169689Skanextern __checkReturn efx_rc_t 1219169689Skanefx_nic_set_drv_limits( 1220169689Skan __inout efx_nic_t *enp, 1221169689Skan __in efx_drv_limits_t *edlp); 1222169689Skan 1223169689Skantypedef enum efx_nic_region_e { 1224169689Skan EFX_REGION_VI, /* Memory BAR UC mapping */ 1225169689Skan EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1226169689Skan} efx_nic_region_t; 1227169689Skan 1228169689Skanextern __checkReturn efx_rc_t 1229169689Skanefx_nic_get_bar_region( 1230169689Skan __in efx_nic_t *enp, 1231169689Skan __in efx_nic_region_t region, 1232169689Skan __out uint32_t *offsetp, 1233169689Skan __out size_t *sizep); 1234169689Skan 1235169689Skanextern __checkReturn efx_rc_t 1236169689Skanefx_nic_get_vi_pool( 1237169689Skan __in efx_nic_t *enp, 1238169689Skan __out uint32_t *evq_countp, 1239169689Skan __out uint32_t *rxq_countp, 1240169689Skan __out uint32_t *txq_countp); 1241169689Skan 1242169689Skan 1243169689Skan#if EFSYS_OPT_VPD 1244169689Skan 1245169689Skantypedef enum efx_vpd_tag_e { 1246169689Skan EFX_VPD_ID = 0x02, 1247169689Skan EFX_VPD_END = 0x0f, 1248169689Skan EFX_VPD_RO = 0x10, 1249169689Skan EFX_VPD_RW = 0x11, 1250169689Skan} efx_vpd_tag_t; 1251169689Skan 1252169689Skantypedef uint16_t efx_vpd_keyword_t; 1253169689Skan 1254169689Skantypedef struct efx_vpd_value_s { 1255169689Skan efx_vpd_tag_t evv_tag; 1256169689Skan efx_vpd_keyword_t evv_keyword; 1257169689Skan uint8_t evv_length; 1258169689Skan uint8_t evv_value[0x100]; 1259169689Skan} efx_vpd_value_t; 1260169689Skan 1261169689Skan 1262169689Skan#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1263169689Skan 1264169689Skanextern __checkReturn efx_rc_t 1265169689Skanefx_vpd_init( 1266169689Skan __in efx_nic_t *enp); 1267169689Skan 1268169689Skanextern __checkReturn efx_rc_t 1269169689Skanefx_vpd_size( 1270169689Skan __in efx_nic_t *enp, 1271169689Skan __out size_t *sizep); 1272169689Skan 1273169689Skanextern __checkReturn efx_rc_t 1274169689Skanefx_vpd_read( 1275169689Skan __in efx_nic_t *enp, 1276169689Skan __out_bcount(size) caddr_t data, 1277169689Skan __in size_t size); 1278169689Skan 1279169689Skanextern __checkReturn efx_rc_t 1280169689Skanefx_vpd_verify( 1281169689Skan __in efx_nic_t *enp, 1282169689Skan __in_bcount(size) caddr_t data, 1283169689Skan __in size_t size); 1284169689Skan 1285169689Skanextern __checkReturn efx_rc_t 1286169689Skanefx_vpd_reinit( 1287169689Skan __in efx_nic_t *enp, 1288169689Skan __in_bcount(size) caddr_t data, 1289169689Skan __in size_t size); 1290169689Skan 1291169689Skanextern __checkReturn efx_rc_t 1292169689Skanefx_vpd_get( 1293169689Skan __in efx_nic_t *enp, 1294169689Skan __in_bcount(size) caddr_t data, 1295169689Skan __in size_t size, 1296169689Skan __inout efx_vpd_value_t *evvp); 1297169689Skan 1298169689Skanextern __checkReturn efx_rc_t 1299169689Skanefx_vpd_set( 1300169689Skan __in efx_nic_t *enp, 1301169689Skan __inout_bcount(size) caddr_t data, 1302169689Skan __in size_t size, 1303169689Skan __in efx_vpd_value_t *evvp); 1304169689Skan 1305169689Skanextern __checkReturn efx_rc_t 1306169689Skanefx_vpd_next( 1307169689Skan __in efx_nic_t *enp, 1308169689Skan __inout_bcount(size) caddr_t data, 1309169689Skan __in size_t size, 1310169689Skan __out efx_vpd_value_t *evvp, 1311169689Skan __inout unsigned int *contp); 1312169689Skan 1313169689Skanextern __checkReturn efx_rc_t 1314169689Skanefx_vpd_write( 1315169689Skan __in efx_nic_t *enp, 1316169689Skan __in_bcount(size) caddr_t data, 1317169689Skan __in size_t size); 1318169689Skan 1319169689Skanextern void 1320169689Skanefx_vpd_fini( 1321169689Skan __in efx_nic_t *enp); 1322169689Skan 1323169689Skan#endif /* EFSYS_OPT_VPD */ 1324169689Skan 1325169689Skan/* NVRAM */ 1326169689Skan 1327169689Skan#if EFSYS_OPT_NVRAM 1328169689Skan 1329169689Skantypedef enum efx_nvram_type_e { 1330169689Skan EFX_NVRAM_INVALID = 0, 1331169689Skan EFX_NVRAM_BOOTROM, 1332169689Skan EFX_NVRAM_BOOTROM_CFG, 1333169689Skan EFX_NVRAM_MC_FIRMWARE, 1334169689Skan EFX_NVRAM_MC_GOLDEN, 1335169689Skan EFX_NVRAM_PHY, 1336169689Skan EFX_NVRAM_NULLPHY, 1337169689Skan EFX_NVRAM_FPGA, 1338169689Skan EFX_NVRAM_FCFW, 1339169689Skan EFX_NVRAM_CPLD, 1340169689Skan EFX_NVRAM_FPGA_BACKUP, 1341169689Skan EFX_NVRAM_DYNAMIC_CFG, 1342169689Skan EFX_NVRAM_NTYPES, 1343169689Skan} efx_nvram_type_t; 1344169689Skan 1345169689Skanextern __checkReturn efx_rc_t 1346169689Skanefx_nvram_init( 1347169689Skan __in efx_nic_t *enp); 1348169689Skan 1349169689Skan#if EFSYS_OPT_DIAG 1350169689Skan 1351169689Skanextern __checkReturn efx_rc_t 1352169689Skanefx_nvram_test( 1353169689Skan __in efx_nic_t *enp); 1354169689Skan 1355169689Skan#endif /* EFSYS_OPT_DIAG */ 1356169689Skan 1357169689Skanextern __checkReturn efx_rc_t 1358169689Skanefx_nvram_size( 1359169689Skan __in efx_nic_t *enp, 1360169689Skan __in efx_nvram_type_t type, 1361169689Skan __out size_t *sizep); 1362169689Skan 1363169689Skanextern __checkReturn efx_rc_t 1364169689Skanefx_nvram_rw_start( 1365169689Skan __in efx_nic_t *enp, 1366169689Skan __in efx_nvram_type_t type, 1367169689Skan __out_opt size_t *pref_chunkp); 1368169689Skan 1369169689Skanextern void 1370169689Skanefx_nvram_rw_finish( 1371169689Skan __in efx_nic_t *enp, 1372169689Skan __in efx_nvram_type_t type); 1373169689Skan 1374169689Skanextern __checkReturn efx_rc_t 1375169689Skanefx_nvram_get_version( 1376169689Skan __in efx_nic_t *enp, 1377169689Skan __in efx_nvram_type_t type, 1378169689Skan __out uint32_t *subtypep, 1379169689Skan __out_ecount(4) uint16_t version[4]); 1380169689Skan 1381169689Skanextern __checkReturn efx_rc_t 1382169689Skanefx_nvram_read_chunk( 1383169689Skan __in efx_nic_t *enp, 1384169689Skan __in efx_nvram_type_t type, 1385169689Skan __in unsigned int offset, 1386169689Skan __out_bcount(size) caddr_t data, 1387169689Skan __in size_t size); 1388169689Skan 1389169689Skanextern __checkReturn efx_rc_t 1390169689Skanefx_nvram_set_version( 1391169689Skan __in efx_nic_t *enp, 1392169689Skan __in efx_nvram_type_t type, 1393169689Skan __in_ecount(4) uint16_t version[4]); 1394169689Skan 1395169689Skan/* Validate contents of TLV formatted partition */ 1396169689Skanextern __checkReturn efx_rc_t 1397169689Skanefx_nvram_tlv_validate( 1398169689Skan __in efx_nic_t *enp, 1399169689Skan __in uint32_t partn, 1400169689Skan __in_bcount(partn_size) caddr_t partn_data, 1401169689Skan __in size_t partn_size); 1402169689Skan 1403169689Skanextern __checkReturn efx_rc_t 1404169689Skanefx_nvram_erase( 1405169689Skan __in efx_nic_t *enp, 1406169689Skan __in efx_nvram_type_t type); 1407169689Skan 1408169689Skanextern __checkReturn efx_rc_t 1409169689Skanefx_nvram_write_chunk( 1410169689Skan __in efx_nic_t *enp, 1411169689Skan __in efx_nvram_type_t type, 1412169689Skan __in unsigned int offset, 1413169689Skan __in_bcount(size) caddr_t data, 1414169689Skan __in size_t size); 1415169689Skan 1416169689Skanextern void 1417169689Skanefx_nvram_fini( 1418169689Skan __in efx_nic_t *enp); 1419169689Skan 1420169689Skan#endif /* EFSYS_OPT_NVRAM */ 1421169689Skan 1422169689Skan#if EFSYS_OPT_BOOTCFG 1423169689Skan 1424169689Skanextern efx_rc_t 1425169689Skanefx_bootcfg_read( 1426169689Skan __in efx_nic_t *enp, 1427169689Skan __out_bcount(size) caddr_t data, 1428169689Skan __in size_t size); 1429169689Skan 1430169689Skanextern efx_rc_t 1431169689Skanefx_bootcfg_write( 1432169689Skan __in efx_nic_t *enp, 1433169689Skan __in_bcount(size) caddr_t data, 1434169689Skan __in size_t size); 1435169689Skan 1436169689Skan#endif /* EFSYS_OPT_BOOTCFG */ 1437169689Skan 1438169689Skan#if EFSYS_OPT_WOL 1439169689Skan 1440169689Skantypedef enum efx_wol_type_e { 1441169689Skan EFX_WOL_TYPE_INVALID, 1442169689Skan EFX_WOL_TYPE_MAGIC, 1443169689Skan EFX_WOL_TYPE_BITMAP, 1444169689Skan EFX_WOL_TYPE_LINK, 1445169689Skan EFX_WOL_NTYPES, 1446169689Skan} efx_wol_type_t; 1447169689Skan 1448169689Skantypedef enum efx_lightsout_offload_type_e { 1449169689Skan EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1450169689Skan EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1451169689Skan EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1452169689Skan} efx_lightsout_offload_type_t; 1453169689Skan 1454169689Skan#define EFX_WOL_BITMAP_MASK_SIZE (48) 1455169689Skan#define EFX_WOL_BITMAP_VALUE_SIZE (128) 1456169689Skan 1457169689Skantypedef union efx_wol_param_u { 1458169689Skan struct { 1459169689Skan uint8_t mac_addr[6]; 1460169689Skan } ewp_magic; 1461169689Skan struct { 1462169689Skan uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1463169689Skan uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1464169689Skan uint8_t value_len; 1465169689Skan } ewp_bitmap; 1466169689Skan} efx_wol_param_t; 1467169689Skan 1468169689Skantypedef union efx_lightsout_offload_param_u { 1469169689Skan struct { 1470169689Skan uint8_t mac_addr[6]; 1471169689Skan uint32_t ip; 1472169689Skan } elop_arp; 1473169689Skan struct { 1474169689Skan uint8_t mac_addr[6]; 1475169689Skan uint32_t solicited_node[4]; 1476169689Skan uint32_t ip[4]; 1477169689Skan } elop_ns; 1478169689Skan} efx_lightsout_offload_param_t; 1479169689Skan 1480169689Skanextern __checkReturn efx_rc_t 1481169689Skanefx_wol_init( 1482169689Skan __in efx_nic_t *enp); 1483169689Skan 1484169689Skanextern __checkReturn efx_rc_t 1485169689Skanefx_wol_filter_clear( 1486169689Skan __in efx_nic_t *enp); 1487169689Skan 1488169689Skanextern __checkReturn efx_rc_t 1489169689Skanefx_wol_filter_add( 1490169689Skan __in efx_nic_t *enp, 1491169689Skan __in efx_wol_type_t type, 1492169689Skan __in efx_wol_param_t *paramp, 1493169689Skan __out uint32_t *filter_idp); 1494169689Skan 1495169689Skanextern __checkReturn efx_rc_t 1496169689Skanefx_wol_filter_remove( 1497169689Skan __in efx_nic_t *enp, 1498169689Skan __in uint32_t filter_id); 1499169689Skan 1500169689Skanextern __checkReturn efx_rc_t 1501169689Skanefx_lightsout_offload_add( 1502169689Skan __in efx_nic_t *enp, 1503169689Skan __in efx_lightsout_offload_type_t type, 1504169689Skan __in efx_lightsout_offload_param_t *paramp, 1505169689Skan __out uint32_t *filter_idp); 1506169689Skan 1507169689Skanextern __checkReturn efx_rc_t 1508169689Skanefx_lightsout_offload_remove( 1509169689Skan __in efx_nic_t *enp, 1510169689Skan __in efx_lightsout_offload_type_t type, 1511169689Skan __in uint32_t filter_id); 1512169689Skan 1513169689Skanextern void 1514169689Skanefx_wol_fini( 1515169689Skan __in efx_nic_t *enp); 1516169689Skan 1517169689Skan#endif /* EFSYS_OPT_WOL */ 1518169689Skan 1519169689Skan#if EFSYS_OPT_DIAG 1520169689Skan 1521169689Skantypedef enum efx_pattern_type_t { 1522169689Skan EFX_PATTERN_BYTE_INCREMENT = 0, 1523169689Skan EFX_PATTERN_ALL_THE_SAME, 1524169689Skan EFX_PATTERN_BIT_ALTERNATE, 1525169689Skan EFX_PATTERN_BYTE_ALTERNATE, 1526169689Skan EFX_PATTERN_BYTE_CHANGING, 1527169689Skan EFX_PATTERN_BIT_SWEEP, 1528169689Skan EFX_PATTERN_NTYPES 1529169689Skan} efx_pattern_type_t; 1530169689Skan 1531169689Skantypedef void 1532169689Skan(*efx_sram_pattern_fn_t)( 1533169689Skan __in size_t row, 1534169689Skan __in boolean_t negate, 1535169689Skan __out efx_qword_t *eqp); 1536169689Skan 1537169689Skanextern __checkReturn efx_rc_t 1538169689Skanefx_sram_test( 1539169689Skan __in efx_nic_t *enp, 1540169689Skan __in efx_pattern_type_t type); 1541169689Skan 1542169689Skan#endif /* EFSYS_OPT_DIAG */ 1543169689Skan 1544169689Skanextern __checkReturn efx_rc_t 1545169689Skanefx_sram_buf_tbl_set( 1546169689Skan __in efx_nic_t *enp, 1547169689Skan __in uint32_t id, 1548169689Skan __in efsys_mem_t *esmp, 1549169689Skan __in size_t n); 1550169689Skan 1551169689Skanextern void 1552169689Skanefx_sram_buf_tbl_clear( 1553169689Skan __in efx_nic_t *enp, 1554169689Skan __in uint32_t id, 1555169689Skan __in size_t n); 1556169689Skan 1557169689Skan#define EFX_BUF_TBL_SIZE 0x20000 1558169689Skan 1559169689Skan#define EFX_BUF_SIZE 4096 1560169689Skan 1561169689Skan/* EV */ 1562169689Skan 1563169689Skantypedef struct efx_evq_s efx_evq_t; 1564169689Skan 1565169689Skan#if EFSYS_OPT_QSTATS 1566169689Skan 1567169689Skan/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1568169689Skantypedef enum efx_ev_qstat_e { 1569169689Skan EV_ALL, 1570169689Skan EV_RX, 1571169689Skan EV_RX_OK, 1572169689Skan EV_RX_FRM_TRUNC, 1573169689Skan EV_RX_TOBE_DISC, 1574169689Skan EV_RX_PAUSE_FRM_ERR, 1575169689Skan EV_RX_BUF_OWNER_ID_ERR, 1576169689Skan EV_RX_IPV4_HDR_CHKSUM_ERR, 1577169689Skan EV_RX_TCP_UDP_CHKSUM_ERR, 1578169689Skan EV_RX_ETH_CRC_ERR, 1579169689Skan EV_RX_IP_FRAG_ERR, 1580169689Skan EV_RX_MCAST_PKT, 1581169689Skan EV_RX_MCAST_HASH_MATCH, 1582169689Skan EV_RX_TCP_IPV4, 1583169689Skan EV_RX_TCP_IPV6, 1584169689Skan EV_RX_UDP_IPV4, 1585169689Skan EV_RX_UDP_IPV6, 1586169689Skan EV_RX_OTHER_IPV4, 1587169689Skan EV_RX_OTHER_IPV6, 1588169689Skan EV_RX_NON_IP, 1589169689Skan EV_RX_BATCH, 1590169689Skan EV_TX, 1591169689Skan EV_TX_WQ_FF_FULL, 1592169689Skan EV_TX_PKT_ERR, 1593169689Skan EV_TX_PKT_TOO_BIG, 1594169689Skan EV_TX_UNEXPECTED, 1595169689Skan EV_GLOBAL, 1596169689Skan EV_GLOBAL_MNT, 1597169689Skan EV_DRIVER, 1598169689Skan EV_DRIVER_SRM_UPD_DONE, 1599169689Skan EV_DRIVER_TX_DESCQ_FLS_DONE, 1600169689Skan EV_DRIVER_RX_DESCQ_FLS_DONE, 1601169689Skan EV_DRIVER_RX_DESCQ_FLS_FAILED, 1602169689Skan EV_DRIVER_RX_DSC_ERROR, 1603169689Skan EV_DRIVER_TX_DSC_ERROR, 1604169689Skan EV_DRV_GEN, 1605169689Skan EV_MCDI_RESPONSE, 1606169689Skan EV_NQSTATS 1607169689Skan} efx_ev_qstat_t; 1608169689Skan 1609169689Skan/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1610169689Skan 1611169689Skan#endif /* EFSYS_OPT_QSTATS */ 1612169689Skan 1613169689Skanextern __checkReturn efx_rc_t 1614169689Skanefx_ev_init( 1615169689Skan __in efx_nic_t *enp); 1616169689Skan 1617169689Skanextern void 1618169689Skanefx_ev_fini( 1619169689Skan __in efx_nic_t *enp); 1620169689Skan 1621169689Skan#define EFX_EVQ_MAXNEVS 32768 1622169689Skan#define EFX_EVQ_MINNEVS 512 1623169689Skan 1624169689Skan#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1625169689Skan#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1626169689Skan 1627169689Skanextern __checkReturn efx_rc_t 1628169689Skanefx_ev_qcreate( 1629169689Skan __in efx_nic_t *enp, 1630169689Skan __in unsigned int index, 1631169689Skan __in efsys_mem_t *esmp, 1632169689Skan __in size_t n, 1633169689Skan __in uint32_t id, 1634169689Skan __deref_out efx_evq_t **eepp); 1635169689Skan 1636169689Skanextern void 1637169689Skanefx_ev_qpost( 1638169689Skan __in efx_evq_t *eep, 1639169689Skan __in uint16_t data); 1640169689Skan 1641169689Skantypedef __checkReturn boolean_t 1642169689Skan(*efx_initialized_ev_t)( 1643169689Skan __in_opt void *arg); 1644169689Skan 1645169689Skan#define EFX_PKT_UNICAST 0x0004 1646169689Skan#define EFX_PKT_START 0x0008 1647169689Skan 1648169689Skan#define EFX_PKT_VLAN_TAGGED 0x0010 1649169689Skan#define EFX_CKSUM_TCPUDP 0x0020 1650169689Skan#define EFX_CKSUM_IPV4 0x0040 1651169689Skan#define EFX_PKT_CONT 0x0080 1652169689Skan 1653169689Skan#define EFX_CHECK_VLAN 0x0100 1654169689Skan#define EFX_PKT_TCP 0x0200 1655169689Skan#define EFX_PKT_UDP 0x0400 1656169689Skan#define EFX_PKT_IPV4 0x0800 1657169689Skan 1658169689Skan#define EFX_PKT_IPV6 0x1000 1659169689Skan#define EFX_PKT_PREFIX_LEN 0x2000 1660169689Skan#define EFX_ADDR_MISMATCH 0x4000 1661169689Skan#define EFX_DISCARD 0x8000 1662169689Skan 1663169689Skan#define EFX_EV_RX_NLABELS 32 1664169689Skan#define EFX_EV_TX_NLABELS 32 1665169689Skan 1666169689Skantypedef __checkReturn boolean_t 1667169689Skan(*efx_rx_ev_t)( 1668169689Skan __in_opt void *arg, 1669169689Skan __in uint32_t label, 1670169689Skan __in uint32_t id, 1671169689Skan __in uint32_t size, 1672169689Skan __in uint16_t flags); 1673169689Skan 1674169689Skantypedef __checkReturn boolean_t 1675169689Skan(*efx_tx_ev_t)( 1676169689Skan __in_opt void *arg, 1677169689Skan __in uint32_t label, 1678169689Skan __in uint32_t id); 1679169689Skan 1680169689Skan#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1681169689Skan#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1682169689Skan#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1683169689Skan#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1684169689Skan#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1685169689Skan#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1686169689Skan#define EFX_EXCEPTION_RX_ERROR 0x00000007 1687169689Skan#define EFX_EXCEPTION_TX_ERROR 0x00000008 1688169689Skan#define EFX_EXCEPTION_EV_ERROR 0x00000009 1689169689Skan 1690169689Skantypedef __checkReturn boolean_t 1691169689Skan(*efx_exception_ev_t)( 1692169689Skan __in_opt void *arg, 1693169689Skan __in uint32_t label, 1694169689Skan __in uint32_t data); 1695169689Skan 1696169689Skantypedef __checkReturn boolean_t 1697169689Skan(*efx_rxq_flush_done_ev_t)( 1698169689Skan __in_opt void *arg, 1699169689Skan __in uint32_t rxq_index); 1700169689Skan 1701169689Skantypedef __checkReturn boolean_t 1702169689Skan(*efx_rxq_flush_failed_ev_t)( 1703169689Skan __in_opt void *arg, 1704169689Skan __in uint32_t rxq_index); 1705169689Skan 1706169689Skantypedef __checkReturn boolean_t 1707169689Skan(*efx_txq_flush_done_ev_t)( 1708169689Skan __in_opt void *arg, 1709169689Skan __in uint32_t txq_index); 1710169689Skan 1711169689Skantypedef __checkReturn boolean_t 1712169689Skan(*efx_software_ev_t)( 1713169689Skan __in_opt void *arg, 1714169689Skan __in uint16_t magic); 1715169689Skan 1716169689Skantypedef __checkReturn boolean_t 1717169689Skan(*efx_sram_ev_t)( 1718169689Skan __in_opt void *arg, 1719169689Skan __in uint32_t code); 1720169689Skan 1721169689Skan#define EFX_SRAM_CLEAR 0 1722169689Skan#define EFX_SRAM_UPDATE 1 1723169689Skan#define EFX_SRAM_ILLEGAL_CLEAR 2 1724169689Skan 1725169689Skantypedef __checkReturn boolean_t 1726169689Skan(*efx_wake_up_ev_t)( 1727169689Skan __in_opt void *arg, 1728169689Skan __in uint32_t label); 1729169689Skan 1730169689Skantypedef __checkReturn boolean_t 1731169689Skan(*efx_timer_ev_t)( 1732169689Skan __in_opt void *arg, 1733169689Skan __in uint32_t label); 1734169689Skan 1735169689Skantypedef __checkReturn boolean_t 1736169689Skan(*efx_link_change_ev_t)( 1737169689Skan __in_opt void *arg, 1738169689Skan __in efx_link_mode_t link_mode); 1739169689Skan 1740169689Skan#if EFSYS_OPT_MON_STATS 1741169689Skan 1742169689Skantypedef __checkReturn boolean_t 1743169689Skan(*efx_monitor_ev_t)( 1744169689Skan __in_opt void *arg, 1745169689Skan __in efx_mon_stat_t id, 1746169689Skan __in efx_mon_stat_value_t value); 1747169689Skan 1748169689Skan#endif /* EFSYS_OPT_MON_STATS */ 1749169689Skan 1750169689Skan#if EFSYS_OPT_MAC_STATS 1751169689Skan 1752169689Skantypedef __checkReturn boolean_t 1753169689Skan(*efx_mac_stats_ev_t)( 1754169689Skan __in_opt void *arg, 1755169689Skan __in uint32_t generation 1756169689Skan ); 1757169689Skan 1758169689Skan#endif /* EFSYS_OPT_MAC_STATS */ 1759169689Skan 1760169689Skantypedef struct efx_ev_callbacks_s { 1761169689Skan efx_initialized_ev_t eec_initialized; 1762169689Skan efx_rx_ev_t eec_rx; 1763169689Skan efx_tx_ev_t eec_tx; 1764169689Skan efx_exception_ev_t eec_exception; 1765169689Skan efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1766169689Skan efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1767169689Skan efx_txq_flush_done_ev_t eec_txq_flush_done; 1768169689Skan efx_software_ev_t eec_software; 1769169689Skan efx_sram_ev_t eec_sram; 1770169689Skan efx_wake_up_ev_t eec_wake_up; 1771169689Skan efx_timer_ev_t eec_timer; 1772169689Skan efx_link_change_ev_t eec_link_change; 1773169689Skan#if EFSYS_OPT_MON_STATS 1774169689Skan efx_monitor_ev_t eec_monitor; 1775169689Skan#endif /* EFSYS_OPT_MON_STATS */ 1776169689Skan#if EFSYS_OPT_MAC_STATS 1777169689Skan efx_mac_stats_ev_t eec_mac_stats; 1778169689Skan#endif /* EFSYS_OPT_MAC_STATS */ 1779169689Skan} efx_ev_callbacks_t; 1780169689Skan 1781169689Skanextern __checkReturn boolean_t 1782169689Skanefx_ev_qpending( 1783169689Skan __in efx_evq_t *eep, 1784169689Skan __in unsigned int count); 1785169689Skan 1786169689Skan#if EFSYS_OPT_EV_PREFETCH 1787169689Skan 1788169689Skanextern void 1789169689Skanefx_ev_qprefetch( 1790169689Skan __in efx_evq_t *eep, 1791169689Skan __in unsigned int count); 1792169689Skan 1793169689Skan#endif /* EFSYS_OPT_EV_PREFETCH */ 1794169689Skan 1795169689Skanextern void 1796169689Skanefx_ev_qpoll( 1797169689Skan __in efx_evq_t *eep, 1798169689Skan __inout unsigned int *countp, 1799169689Skan __in const efx_ev_callbacks_t *eecp, 1800169689Skan __in_opt void *arg); 1801169689Skan 1802169689Skanextern __checkReturn efx_rc_t 1803169689Skanefx_ev_qmoderate( 1804169689Skan __in efx_evq_t *eep, 1805169689Skan __in unsigned int us); 1806169689Skan 1807169689Skanextern __checkReturn efx_rc_t 1808169689Skanefx_ev_qprime( 1809169689Skan __in efx_evq_t *eep, 1810169689Skan __in unsigned int count); 1811169689Skan 1812169689Skan#if EFSYS_OPT_QSTATS 1813169689Skan 1814169689Skan#if EFSYS_OPT_NAMES 1815169689Skan 1816169689Skanextern const char * 1817169689Skanefx_ev_qstat_name( 1818169689Skan __in efx_nic_t *enp, 1819169689Skan __in unsigned int id); 1820169689Skan 1821169689Skan#endif /* EFSYS_OPT_NAMES */ 1822169689Skan 1823169689Skanextern void 1824169689Skanefx_ev_qstats_update( 1825169689Skan __in efx_evq_t *eep, 1826169689Skan __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1827169689Skan 1828169689Skan#endif /* EFSYS_OPT_QSTATS */ 1829169689Skan 1830169689Skanextern void 1831169689Skanefx_ev_qdestroy( 1832169689Skan __in efx_evq_t *eep); 1833169689Skan 1834169689Skan/* RX */ 1835169689Skan 1836169689Skanextern __checkReturn efx_rc_t 1837169689Skanefx_rx_init( 1838169689Skan __inout efx_nic_t *enp); 1839169689Skan 1840169689Skanextern void 1841169689Skanefx_rx_fini( 1842169689Skan __in efx_nic_t *enp); 1843169689Skan 1844169689Skan#if EFSYS_OPT_RX_HDR_SPLIT 1845169689Skan __checkReturn efx_rc_t 1846169689Skanefx_rx_hdr_split_enable( 1847169689Skan __in efx_nic_t *enp, 1848169689Skan __in unsigned int hdr_buf_size, 1849169689Skan __in unsigned int pld_buf_size); 1850169689Skan 1851169689Skan#endif /* EFSYS_OPT_RX_HDR_SPLIT */ 1852169689Skan 1853169689Skan#if EFSYS_OPT_RX_SCATTER 1854169689Skan __checkReturn efx_rc_t 1855169689Skanefx_rx_scatter_enable( 1856169689Skan __in efx_nic_t *enp, 1857169689Skan __in unsigned int buf_size); 1858169689Skan#endif /* EFSYS_OPT_RX_SCATTER */ 1859169689Skan 1860169689Skan#if EFSYS_OPT_RX_SCALE 1861169689Skan 1862169689Skantypedef enum efx_rx_hash_alg_e { 1863169689Skan EFX_RX_HASHALG_LFSR = 0, 1864169689Skan EFX_RX_HASHALG_TOEPLITZ 1865169689Skan} efx_rx_hash_alg_t; 1866169689Skan 1867169689Skantypedef enum efx_rx_hash_type_e { 1868169689Skan EFX_RX_HASH_IPV4 = 0, 1869169689Skan EFX_RX_HASH_TCPIPV4, 1870169689Skan EFX_RX_HASH_IPV6, 1871169689Skan EFX_RX_HASH_TCPIPV6, 1872169689Skan} efx_rx_hash_type_t; 1873169689Skan 1874169689Skantypedef enum efx_rx_hash_support_e { 1875169689Skan EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1876169689Skan EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1877169689Skan} efx_rx_hash_support_t; 1878169689Skan 1879169689Skan#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1880169689Skan#define EFX_MAXRSS 64 /* RX indirection entry range */ 1881169689Skan#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1882169689Skan 1883169689Skantypedef enum efx_rx_scale_support_e { 1884169689Skan EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1885169689Skan EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1886169689Skan EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1887169689Skan} efx_rx_scale_support_t; 1888169689Skan 1889169689Skanextern __checkReturn efx_rc_t 1890169689Skanefx_rx_hash_support_get( 1891169689Skan __in efx_nic_t *enp, 1892169689Skan __out efx_rx_hash_support_t *supportp); 1893169689Skan 1894169689Skan 1895169689Skanextern __checkReturn efx_rc_t 1896169689Skanefx_rx_scale_support_get( 1897169689Skan __in efx_nic_t *enp, 1898169689Skan __out efx_rx_scale_support_t *supportp); 1899169689Skan 1900169689Skanextern __checkReturn efx_rc_t 1901169689Skanefx_rx_scale_mode_set( 1902169689Skan __in efx_nic_t *enp, 1903169689Skan __in efx_rx_hash_alg_t alg, 1904169689Skan __in efx_rx_hash_type_t type, 1905169689Skan __in boolean_t insert); 1906169689Skan 1907169689Skanextern __checkReturn efx_rc_t 1908169689Skanefx_rx_scale_tbl_set( 1909 __in efx_nic_t *enp, 1910 __in_ecount(n) unsigned int *table, 1911 __in size_t n); 1912 1913extern __checkReturn efx_rc_t 1914efx_rx_scale_key_set( 1915 __in efx_nic_t *enp, 1916 __in_ecount(n) uint8_t *key, 1917 __in size_t n); 1918 1919extern uint32_t 1920efx_psuedo_hdr_hash_get( 1921 __in efx_nic_t *enp, 1922 __in efx_rx_hash_alg_t func, 1923 __in uint8_t *buffer); 1924 1925#endif /* EFSYS_OPT_RX_SCALE */ 1926 1927extern __checkReturn efx_rc_t 1928efx_psuedo_hdr_pkt_length_get( 1929 __in efx_nic_t *enp, 1930 __in uint8_t *buffer, 1931 __out uint16_t *pkt_lengthp); 1932 1933#define EFX_RXQ_MAXNDESCS 4096 1934#define EFX_RXQ_MINNDESCS 512 1935 1936#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1937#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1938#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1939#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1940 1941typedef enum efx_rxq_type_e { 1942 EFX_RXQ_TYPE_DEFAULT, 1943 EFX_RXQ_TYPE_SPLIT_HEADER, 1944 EFX_RXQ_TYPE_SPLIT_PAYLOAD, 1945 EFX_RXQ_TYPE_SCATTER, 1946 EFX_RXQ_NTYPES 1947} efx_rxq_type_t; 1948 1949extern __checkReturn efx_rc_t 1950efx_rx_qcreate( 1951 __in efx_nic_t *enp, 1952 __in unsigned int index, 1953 __in unsigned int label, 1954 __in efx_rxq_type_t type, 1955 __in efsys_mem_t *esmp, 1956 __in size_t n, 1957 __in uint32_t id, 1958 __in efx_evq_t *eep, 1959 __deref_out efx_rxq_t **erpp); 1960 1961typedef struct efx_buffer_s { 1962 efsys_dma_addr_t eb_addr; 1963 size_t eb_size; 1964 boolean_t eb_eop; 1965} efx_buffer_t; 1966 1967typedef struct efx_desc_s { 1968 efx_qword_t ed_eq; 1969} efx_desc_t; 1970 1971extern void 1972efx_rx_qpost( 1973 __in efx_rxq_t *erp, 1974 __in_ecount(n) efsys_dma_addr_t *addrp, 1975 __in size_t size, 1976 __in unsigned int n, 1977 __in unsigned int completed, 1978 __in unsigned int added); 1979 1980extern void 1981efx_rx_qpush( 1982 __in efx_rxq_t *erp, 1983 __in unsigned int added, 1984 __inout unsigned int *pushedp); 1985 1986extern __checkReturn efx_rc_t 1987efx_rx_qflush( 1988 __in efx_rxq_t *erp); 1989 1990extern void 1991efx_rx_qenable( 1992 __in efx_rxq_t *erp); 1993 1994extern void 1995efx_rx_qdestroy( 1996 __in efx_rxq_t *erp); 1997 1998/* TX */ 1999 2000typedef struct efx_txq_s efx_txq_t; 2001 2002#if EFSYS_OPT_QSTATS 2003 2004/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2005typedef enum efx_tx_qstat_e { 2006 TX_POST, 2007 TX_POST_PIO, 2008 TX_NQSTATS 2009} efx_tx_qstat_t; 2010 2011/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2012 2013#endif /* EFSYS_OPT_QSTATS */ 2014 2015extern __checkReturn efx_rc_t 2016efx_tx_init( 2017 __in efx_nic_t *enp); 2018 2019extern void 2020efx_tx_fini( 2021 __in efx_nic_t *enp); 2022 2023#define EFX_BUG35388_WORKAROUND(_encp) \ 2024 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 2025 2026#define EFX_TXQ_MAXNDESCS(_encp) \ 2027 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 2028 2029#define EFX_TXQ_MINNDESCS 512 2030 2031#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2032#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2033#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2034#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2035 2036#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2037 2038#define EFX_TXQ_CKSUM_IPV4 0x0001 2039#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2040 2041extern __checkReturn efx_rc_t 2042efx_tx_qcreate( 2043 __in efx_nic_t *enp, 2044 __in unsigned int index, 2045 __in unsigned int label, 2046 __in efsys_mem_t *esmp, 2047 __in size_t n, 2048 __in uint32_t id, 2049 __in uint16_t flags, 2050 __in efx_evq_t *eep, 2051 __deref_out efx_txq_t **etpp, 2052 __out unsigned int *addedp); 2053 2054extern __checkReturn efx_rc_t 2055efx_tx_qpost( 2056 __in efx_txq_t *etp, 2057 __in_ecount(n) efx_buffer_t *eb, 2058 __in unsigned int n, 2059 __in unsigned int completed, 2060 __inout unsigned int *addedp); 2061 2062extern __checkReturn efx_rc_t 2063efx_tx_qpace( 2064 __in efx_txq_t *etp, 2065 __in unsigned int ns); 2066 2067extern void 2068efx_tx_qpush( 2069 __in efx_txq_t *etp, 2070 __in unsigned int added, 2071 __in unsigned int pushed); 2072 2073extern __checkReturn efx_rc_t 2074efx_tx_qflush( 2075 __in efx_txq_t *etp); 2076 2077extern void 2078efx_tx_qenable( 2079 __in efx_txq_t *etp); 2080 2081extern __checkReturn efx_rc_t 2082efx_tx_qpio_enable( 2083 __in efx_txq_t *etp); 2084 2085extern void 2086efx_tx_qpio_disable( 2087 __in efx_txq_t *etp); 2088 2089extern __checkReturn efx_rc_t 2090efx_tx_qpio_write( 2091 __in efx_txq_t *etp, 2092 __in_ecount(buf_length) uint8_t *buffer, 2093 __in size_t buf_length, 2094 __in size_t pio_buf_offset); 2095 2096extern __checkReturn efx_rc_t 2097efx_tx_qpio_post( 2098 __in efx_txq_t *etp, 2099 __in size_t pkt_length, 2100 __in unsigned int completed, 2101 __inout unsigned int *addedp); 2102 2103extern __checkReturn efx_rc_t 2104efx_tx_qdesc_post( 2105 __in efx_txq_t *etp, 2106 __in_ecount(n) efx_desc_t *ed, 2107 __in unsigned int n, 2108 __in unsigned int completed, 2109 __inout unsigned int *addedp); 2110 2111extern void 2112efx_tx_qdesc_dma_create( 2113 __in efx_txq_t *etp, 2114 __in efsys_dma_addr_t addr, 2115 __in size_t size, 2116 __in boolean_t eop, 2117 __out efx_desc_t *edp); 2118 2119extern void 2120efx_tx_qdesc_tso_create( 2121 __in efx_txq_t *etp, 2122 __in uint16_t ipv4_id, 2123 __in uint32_t tcp_seq, 2124 __in uint8_t tcp_flags, 2125 __out efx_desc_t *edp); 2126 2127extern void 2128efx_tx_qdesc_vlantci_create( 2129 __in efx_txq_t *etp, 2130 __in uint16_t tci, 2131 __out efx_desc_t *edp); 2132 2133#if EFSYS_OPT_QSTATS 2134 2135#if EFSYS_OPT_NAMES 2136 2137extern const char * 2138efx_tx_qstat_name( 2139 __in efx_nic_t *etp, 2140 __in unsigned int id); 2141 2142#endif /* EFSYS_OPT_NAMES */ 2143 2144extern void 2145efx_tx_qstats_update( 2146 __in efx_txq_t *etp, 2147 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2148 2149#endif /* EFSYS_OPT_QSTATS */ 2150 2151extern void 2152efx_tx_qdestroy( 2153 __in efx_txq_t *etp); 2154 2155 2156/* FILTER */ 2157 2158#if EFSYS_OPT_FILTER 2159 2160#define EFX_ETHER_TYPE_IPV4 0x0800 2161#define EFX_ETHER_TYPE_IPV6 0x86DD 2162 2163#define EFX_IPPROTO_TCP 6 2164#define EFX_IPPROTO_UDP 17 2165 2166typedef enum efx_filter_flag_e { 2167 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 2168 * multiple queues */ 2169 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 2170 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter 2171 * (priority EFX_FILTER_PRI_AUTO). 2172 * May only be set by the filter 2173 * implementation for each type. 2174 * A removal request will 2175 * restore the automatic filter 2176 * in its place. */ 2177 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ 2178 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ 2179} efx_filter_flag_t; 2180 2181typedef enum efx_filter_match_flags_e { 2182 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2183 * address */ 2184 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2185 * address */ 2186 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2187 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2188 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2189 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2190 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2191 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2192 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2193 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2194 * protocol */ 2195 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address 2196 * I/G bit. Used for RX default 2197 * unicast and multicast/ 2198 * broadcast filters. */ 2199} efx_filter_match_flags_t; 2200 2201typedef enum efx_filter_priority_s { 2202 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2203 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2204 * address list or hardware 2205 * requirements. This may only be used 2206 * by the filter implementation for 2207 * each NIC type. */ 2208 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2209 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2210 * client (e.g. SR-IOV, HyperV VMQ etc.) 2211 */ 2212} efx_filter_priority_t; 2213 2214/* 2215 * FIXME: All these fields are assumed to be in little-endian byte order. 2216 * It may be better for some to be big-endian. See bug42804. 2217 */ 2218 2219typedef struct efx_filter_spec_s { 2220 uint32_t efs_match_flags:12; 2221 uint32_t efs_priority:2; 2222 uint32_t efs_flags:6; 2223 uint32_t efs_dmaq_id:12; 2224 uint32_t efs_rss_context; 2225 uint16_t efs_outer_vid; 2226 uint16_t efs_inner_vid; 2227 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2228 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2229 uint16_t efs_ether_type; 2230 uint8_t efs_ip_proto; 2231 uint16_t efs_loc_port; 2232 uint16_t efs_rem_port; 2233 efx_oword_t efs_rem_host; 2234 efx_oword_t efs_loc_host; 2235} efx_filter_spec_t; 2236 2237 2238/* Default values for use in filter specifications */ 2239#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2240#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2241#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2242 2243extern __checkReturn efx_rc_t 2244efx_filter_init( 2245 __in efx_nic_t *enp); 2246 2247extern void 2248efx_filter_fini( 2249 __in efx_nic_t *enp); 2250 2251extern __checkReturn efx_rc_t 2252efx_filter_insert( 2253 __in efx_nic_t *enp, 2254 __inout efx_filter_spec_t *spec); 2255 2256extern __checkReturn efx_rc_t 2257efx_filter_remove( 2258 __in efx_nic_t *enp, 2259 __inout efx_filter_spec_t *spec); 2260 2261extern __checkReturn efx_rc_t 2262efx_filter_restore( 2263 __in efx_nic_t *enp); 2264 2265extern __checkReturn efx_rc_t 2266efx_filter_supported_filters( 2267 __in efx_nic_t *enp, 2268 __out uint32_t *list, 2269 __out size_t *length); 2270 2271extern void 2272efx_filter_spec_init_rx( 2273 __inout efx_filter_spec_t *spec, 2274 __in efx_filter_priority_t priority, 2275 __in efx_filter_flag_t flags, 2276 __in efx_rxq_t *erp); 2277 2278extern void 2279efx_filter_spec_init_tx( 2280 __inout efx_filter_spec_t *spec, 2281 __in efx_txq_t *etp); 2282 2283extern __checkReturn efx_rc_t 2284efx_filter_spec_set_ipv4_local( 2285 __inout efx_filter_spec_t *spec, 2286 __in uint8_t proto, 2287 __in uint32_t host, 2288 __in uint16_t port); 2289 2290extern __checkReturn efx_rc_t 2291efx_filter_spec_set_ipv4_full( 2292 __inout efx_filter_spec_t *spec, 2293 __in uint8_t proto, 2294 __in uint32_t lhost, 2295 __in uint16_t lport, 2296 __in uint32_t rhost, 2297 __in uint16_t rport); 2298 2299extern __checkReturn efx_rc_t 2300efx_filter_spec_set_eth_local( 2301 __inout efx_filter_spec_t *spec, 2302 __in uint16_t vid, 2303 __in const uint8_t *addr); 2304 2305extern __checkReturn efx_rc_t 2306efx_filter_spec_set_uc_def( 2307 __inout efx_filter_spec_t *spec); 2308 2309extern __checkReturn efx_rc_t 2310efx_filter_spec_set_mc_def( 2311 __inout efx_filter_spec_t *spec); 2312 2313#endif /* EFSYS_OPT_FILTER */ 2314 2315/* HASH */ 2316 2317extern __checkReturn uint32_t 2318efx_hash_dwords( 2319 __in_ecount(count) uint32_t const *input, 2320 __in size_t count, 2321 __in uint32_t init); 2322 2323extern __checkReturn uint32_t 2324efx_hash_bytes( 2325 __in_ecount(length) uint8_t const *input, 2326 __in size_t length, 2327 __in uint32_t init); 2328 2329 2330#ifdef __cplusplus 2331} 2332#endif 2333 2334#endif /* _SYS_EFX_H */ 2335