1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: releng/10.3/sys/dev/sdhci/sdhci_pci.c 278535 2015-02-10 21:44:28Z marius $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44 45#include <machine/bus.h> 46#include <machine/resource.h> 47#include <machine/stdarg.h> 48 49#include <dev/mmc/bridge.h> 50#include <dev/mmc/mmcreg.h> 51#include <dev/mmc/mmcbrvar.h> 52 53#include "sdhci.h" 54#include "mmcbr_if.h" 55#include "sdhci_if.h" 56 57/* 58 * PCI registers 59 */ 60 61#define PCI_SDHCI_IFPIO 0x00 62#define PCI_SDHCI_IFDMA 0x01 63#define PCI_SDHCI_IFVENDOR 0x02 64 65#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69/* 70 * RICOH specific PCI registers 71 */ 72#define SDHC_PCI_MODE_KEY 0xf9 73#define SDHC_PCI_MODE 0x150 74#define SDHC_PCI_MODE_SD20 0x10 75#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76#define SDHC_PCI_BASE_FREQ 0xe1 77 78static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83} sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0, 0xffff, NULL, 109 0 } 110}; 111 112struct sdhci_pci_softc { 113 u_int quirks; /* Chip specific quirks */ 114 struct resource *irq_res; /* IRQ resource */ 115 void *intrhand; /* Interrupt handle */ 116 117 int num_slots; /* Number of slots on this controller */ 118 struct sdhci_slot slots[6]; 119 struct resource *mem_res[6]; /* Memory resource */ 120 uint8_t cfg_freq; /* Saved mode */ 121 uint8_t cfg_mode; /* Saved frequency */ 122}; 123 124static int sdhci_enable_msi = 1; 125TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi); 126SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 127 0, "Enable MSI interrupts"); 128 129static uint8_t 130sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 131{ 132 struct sdhci_pci_softc *sc = device_get_softc(dev); 133 134 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 136 return bus_read_1(sc->mem_res[slot->num], off); 137} 138 139static void 140sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 141{ 142 struct sdhci_pci_softc *sc = device_get_softc(dev); 143 144 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 145 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 146 bus_write_1(sc->mem_res[slot->num], off, val); 147} 148 149static uint16_t 150sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 151{ 152 struct sdhci_pci_softc *sc = device_get_softc(dev); 153 154 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 155 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 156 return bus_read_2(sc->mem_res[slot->num], off); 157} 158 159static void 160sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 161{ 162 struct sdhci_pci_softc *sc = device_get_softc(dev); 163 164 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 165 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 166 bus_write_2(sc->mem_res[slot->num], off, val); 167} 168 169static uint32_t 170sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 171{ 172 struct sdhci_pci_softc *sc = device_get_softc(dev); 173 174 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 175 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 176 return bus_read_4(sc->mem_res[slot->num], off); 177} 178 179static void 180sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 181{ 182 struct sdhci_pci_softc *sc = device_get_softc(dev); 183 184 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 185 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 186 bus_write_4(sc->mem_res[slot->num], off, val); 187} 188 189static void 190sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 191 bus_size_t off, uint32_t *data, bus_size_t count) 192{ 193 struct sdhci_pci_softc *sc = device_get_softc(dev); 194 195 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 196} 197 198static void 199sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 200 bus_size_t off, uint32_t *data, bus_size_t count) 201{ 202 struct sdhci_pci_softc *sc = device_get_softc(dev); 203 204 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 205} 206 207static void sdhci_pci_intr(void *arg); 208 209static void 210sdhci_lower_frequency(device_t dev) 211{ 212 struct sdhci_pci_softc *sc = device_get_softc(dev); 213 214 /* 215 * Enable SD2.0 mode. 216 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 217 */ 218 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 219 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 220 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 221 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 222 223 /* 224 * Some SD/MMC cards don't work with the default base 225 * clock frequency of 200 MHz. Lower it to 50 MHz. 226 */ 227 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 228 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 229 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 230 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 231} 232 233static void 234sdhci_restore_frequency(device_t dev) 235{ 236 struct sdhci_pci_softc *sc = device_get_softc(dev); 237 238 /* Restore mode. */ 239 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 240 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 241 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 242 243 /* Restore frequency. */ 244 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 245 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 246 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 247} 248 249static int 250sdhci_pci_probe(device_t dev) 251{ 252 uint32_t model; 253 uint16_t subvendor; 254 uint8_t class, subclass; 255 int i, result; 256 257 model = (uint32_t)pci_get_device(dev) << 16; 258 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 259 subvendor = pci_get_subvendor(dev); 260 class = pci_get_class(dev); 261 subclass = pci_get_subclass(dev); 262 263 result = ENXIO; 264 for (i = 0; sdhci_devices[i].model != 0; i++) { 265 if (sdhci_devices[i].model == model && 266 (sdhci_devices[i].subvendor == 0xffff || 267 sdhci_devices[i].subvendor == subvendor)) { 268 device_set_desc(dev, sdhci_devices[i].desc); 269 result = BUS_PROBE_DEFAULT; 270 break; 271 } 272 } 273 if (result == ENXIO && class == PCIC_BASEPERIPH && 274 subclass == PCIS_BASEPERIPH_SDHC) { 275 device_set_desc(dev, "Generic SD HCI"); 276 result = BUS_PROBE_GENERIC; 277 } 278 279 return (result); 280} 281 282static int 283sdhci_pci_attach(device_t dev) 284{ 285 struct sdhci_pci_softc *sc = device_get_softc(dev); 286 uint32_t model; 287 uint16_t subvendor; 288 int bar, err, rid, slots, i; 289 290 model = (uint32_t)pci_get_device(dev) << 16; 291 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 292 subvendor = pci_get_subvendor(dev); 293 /* Apply chip specific quirks. */ 294 for (i = 0; sdhci_devices[i].model != 0; i++) { 295 if (sdhci_devices[i].model == model && 296 (sdhci_devices[i].subvendor == 0xffff || 297 sdhci_devices[i].subvendor == subvendor)) { 298 sc->quirks = sdhci_devices[i].quirks; 299 break; 300 } 301 } 302 /* Some controllers need to be bumped into the right mode. */ 303 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 304 sdhci_lower_frequency(dev); 305 /* Read slots info from PCI registers. */ 306 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 307 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 308 slots = PCI_SLOT_INFO_SLOTS(slots); 309 if (slots > 6 || bar > 5) { 310 device_printf(dev, "Incorrect slots information (%d, %d).\n", 311 slots, bar); 312 return (EINVAL); 313 } 314 /* Allocate IRQ. */ 315 i = 1; 316 rid = 0; 317 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 318 rid = 1; 319 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 320 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 321 if (sc->irq_res == NULL) { 322 device_printf(dev, "Can't allocate IRQ\n"); 323 pci_release_msi(dev); 324 return (ENOMEM); 325 } 326 /* Scan all slots. */ 327 for (i = 0; i < slots; i++) { 328 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 329 330 /* Allocate memory. */ 331 rid = PCIR_BAR(bar + i); 332 sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 333 &rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 334 if (sc->mem_res[i] == NULL) { 335 device_printf(dev, "Can't allocate memory for slot %d\n", i); 336 continue; 337 } 338 339 if (sdhci_init_slot(dev, slot, i) != 0) 340 continue; 341 342 sc->num_slots++; 343 } 344 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 345 /* Activate the interrupt */ 346 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 347 NULL, sdhci_pci_intr, sc, &sc->intrhand); 348 if (err) 349 device_printf(dev, "Can't setup IRQ\n"); 350 pci_enable_busmaster(dev); 351 /* Process cards detection. */ 352 for (i = 0; i < sc->num_slots; i++) { 353 struct sdhci_slot *slot = &sc->slots[i]; 354 355 sdhci_start_slot(slot); 356 } 357 358 return (0); 359} 360 361static int 362sdhci_pci_detach(device_t dev) 363{ 364 struct sdhci_pci_softc *sc = device_get_softc(dev); 365 int i; 366 367 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 368 bus_release_resource(dev, SYS_RES_IRQ, 369 rman_get_rid(sc->irq_res), sc->irq_res); 370 pci_release_msi(dev); 371 372 for (i = 0; i < sc->num_slots; i++) { 373 struct sdhci_slot *slot = &sc->slots[i]; 374 375 sdhci_cleanup_slot(slot); 376 bus_release_resource(dev, SYS_RES_MEMORY, 377 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 378 } 379 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 380 sdhci_restore_frequency(dev); 381 return (0); 382} 383 384static int 385sdhci_pci_shutdown(device_t dev) 386{ 387 struct sdhci_pci_softc *sc = device_get_softc(dev); 388 389 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 390 sdhci_restore_frequency(dev); 391 return (0); 392} 393 394static int 395sdhci_pci_suspend(device_t dev) 396{ 397 struct sdhci_pci_softc *sc = device_get_softc(dev); 398 int i, err; 399 400 err = bus_generic_suspend(dev); 401 if (err) 402 return (err); 403 for (i = 0; i < sc->num_slots; i++) 404 sdhci_generic_suspend(&sc->slots[i]); 405 return (0); 406} 407 408static int 409sdhci_pci_resume(device_t dev) 410{ 411 struct sdhci_pci_softc *sc = device_get_softc(dev); 412 int i; 413 414 for (i = 0; i < sc->num_slots; i++) 415 sdhci_generic_resume(&sc->slots[i]); 416 return (bus_generic_resume(dev)); 417} 418 419static void 420sdhci_pci_intr(void *arg) 421{ 422 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 423 int i; 424 425 for (i = 0; i < sc->num_slots; i++) { 426 struct sdhci_slot *slot = &sc->slots[i]; 427 sdhci_generic_intr(slot); 428 } 429} 430 431static device_method_t sdhci_methods[] = { 432 /* device_if */ 433 DEVMETHOD(device_probe, sdhci_pci_probe), 434 DEVMETHOD(device_attach, sdhci_pci_attach), 435 DEVMETHOD(device_detach, sdhci_pci_detach), 436 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 437 DEVMETHOD(device_suspend, sdhci_pci_suspend), 438 DEVMETHOD(device_resume, sdhci_pci_resume), 439 440 /* Bus interface */ 441 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 442 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 443 444 /* mmcbr_if */ 445 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 446 DEVMETHOD(mmcbr_request, sdhci_generic_request), 447 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 448 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 449 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 450 451 /* SDHCI registers accessors */ 452 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 453 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 454 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 455 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 456 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 457 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 458 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 459 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 460 461 DEVMETHOD_END 462}; 463 464static driver_t sdhci_pci_driver = { 465 "sdhci_pci", 466 sdhci_methods, 467 sizeof(struct sdhci_pci_softc), 468}; 469static devclass_t sdhci_pci_devclass; 470 471DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 472 NULL); 473MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 474