1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: releng/10.3/sys/dev/ppc/ppc.c 247094 2013-02-21 12:40:52Z glebius $"); 30 31#include "opt_ppc.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/kernel.h> 37#include <sys/lock.h> 38#include <sys/interrupt.h> 39#include <sys/module.h> 40#include <sys/malloc.h> 41#include <sys/mutex.h> 42#include <sys/proc.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <sys/rman.h> 47 48#ifdef __i386__ 49#include <vm/vm.h> 50#include <vm/pmap.h> 51#include <machine/vmparam.h> 52#endif 53 54#include <dev/ppbus/ppbconf.h> 55#include <dev/ppbus/ppb_msq.h> 56 57#include <dev/ppc/ppcvar.h> 58#include <dev/ppc/ppcreg.h> 59 60#include "ppbus_if.h" 61 62static void ppcintr(void *arg); 63 64#define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 65#define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 66 67#define LOG_PPC(function, ppc, string) \ 68 if (bootverbose) printf("%s: %s\n", function, string) 69 70#if defined(__i386__) && defined(PC98) 71#define PC98_IEEE_1284_DISABLE 0x100 72#define PC98_IEEE_1284_PORT 0x140 73#endif 74 75#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 76 77/* 78 * We use critical enter/exit for the simple config locking needed to 79 * detect the devices. We just want to make sure that both of our writes 80 * happen without someone else also writing to those config registers. Since 81 * we just do this at startup, Giant keeps multiple threads from executing, 82 * and critical_enter() then is all that's needed to keep us from being preempted 83 * during the critical sequences with the hardware. 84 * 85 * Note: this doesn't prevent multiple threads from putting the chips into 86 * config mode, but since we only do that to detect the type at startup the 87 * extra overhead isn't needed since Giant protects us from multiple entry 88 * and no other code changes these registers. 89 */ 90#define PPC_CONFIG_LOCK(ppc) critical_enter() 91#define PPC_CONFIG_UNLOCK(ppc) critical_exit() 92 93devclass_t ppc_devclass; 94const char ppc_driver_name[] = "ppc"; 95 96static char *ppc_models[] = { 97 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 98 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 99 "SMC FDC37C935", "PC87303", 0 100}; 101 102/* list of available modes */ 103static char *ppc_avms[] = { 104 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 105 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 106 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 107 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 108}; 109 110/* list of current executing modes 111 * Note that few modes do not actually exist. 112 */ 113static char *ppc_modes[] = { 114 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 115 "EPP", "EPP", "EPP", "ECP", 116 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 117 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 118}; 119 120static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 121 122#ifdef __i386__ 123/* 124 * BIOS printer list - used by BIOS probe. 125 */ 126#define BIOS_PPC_PORTS 0x408 127#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 128#define BIOS_MAX_PPC 4 129#endif 130 131/* 132 * ppc_ecp_sync() XXX 133 */ 134int 135ppc_ecp_sync(device_t dev) 136{ 137 int i, r; 138 struct ppc_data *ppc = DEVTOSOFTC(dev); 139 140 PPC_ASSERT_LOCKED(ppc); 141 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 142 return 0; 143 144 r = r_ecr(ppc); 145 if ((r & 0xe0) != PPC_ECR_EPP) 146 return 0; 147 148 for (i = 0; i < 100; i++) { 149 r = r_ecr(ppc); 150 if (r & 0x1) 151 return 0; 152 DELAY(100); 153 } 154 155 device_printf(dev, "ECP sync failed as data still present in FIFO.\n"); 156 157 return 0; 158} 159 160/* 161 * ppc_detect_fifo() 162 * 163 * Detect parallel port FIFO 164 */ 165static int 166ppc_detect_fifo(struct ppc_data *ppc) 167{ 168 char ecr_sav; 169 char ctr_sav, ctr, cc; 170 short i; 171 172 /* save registers */ 173 ecr_sav = r_ecr(ppc); 174 ctr_sav = r_ctr(ppc); 175 176 /* enter ECP configuration mode, no interrupt, no DMA */ 177 w_ecr(ppc, 0xf4); 178 179 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 180 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 181 182 /* XXX 16 and 32 bits implementations not supported */ 183 if (ppc->ppc_pword != PPC_PWORD_8) { 184 LOG_PPC(__func__, ppc, "PWord not supported"); 185 goto error; 186 } 187 188 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 189 ctr = r_ctr(ppc); 190 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 191 192 /* enter ECP test mode, no interrupt, no DMA */ 193 w_ecr(ppc, 0xd4); 194 195 /* flush the FIFO */ 196 for (i=0; i<1024; i++) { 197 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 198 break; 199 cc = r_fifo(ppc); 200 } 201 202 if (i >= 1024) { 203 LOG_PPC(__func__, ppc, "can't flush FIFO"); 204 goto error; 205 } 206 207 /* enable interrupts, no DMA */ 208 w_ecr(ppc, 0xd0); 209 210 /* determine readIntrThreshold 211 * fill the FIFO until serviceIntr is set 212 */ 213 for (i=0; i<1024; i++) { 214 w_fifo(ppc, (char)i); 215 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 216 /* readThreshold reached */ 217 ppc->ppc_rthr = i+1; 218 } 219 if (r_ecr(ppc) & PPC_FIFO_FULL) { 220 ppc->ppc_fifo = i+1; 221 break; 222 } 223 } 224 225 if (i >= 1024) { 226 LOG_PPC(__func__, ppc, "can't fill FIFO"); 227 goto error; 228 } 229 230 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 231 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 232 w_ecr(ppc, 0xd0); /* enable interrupts */ 233 234 /* determine writeIntrThreshold 235 * empty the FIFO until serviceIntr is set 236 */ 237 for (i=ppc->ppc_fifo; i>0; i--) { 238 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 239 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 240 goto error; 241 } 242 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 243 /* writeIntrThreshold reached */ 244 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 245 } 246 /* if FIFO empty before the last byte, error */ 247 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 248 LOG_PPC(__func__, ppc, "data lost in FIFO"); 249 goto error; 250 } 251 } 252 253 /* FIFO must be empty after the last byte */ 254 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 255 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 256 goto error; 257 } 258 259 w_ctr(ppc, ctr_sav); 260 w_ecr(ppc, ecr_sav); 261 262 return (0); 263 264error: 265 w_ctr(ppc, ctr_sav); 266 w_ecr(ppc, ecr_sav); 267 268 return (EINVAL); 269} 270 271static int 272ppc_detect_port(struct ppc_data *ppc) 273{ 274 275 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 276 w_dtr(ppc, 0xaa); 277 if (r_dtr(ppc) != 0xaa) 278 return (0); 279 280 return (1); 281} 282 283/* 284 * EPP timeout, according to the PC87332 manual 285 * Semantics of clearing EPP timeout bit. 286 * PC87332 - reading SPP_STR does it... 287 * SMC - write 1 to EPP timeout bit XXX 288 * Others - (?) write 0 to EPP timeout bit 289 */ 290static void 291ppc_reset_epp_timeout(struct ppc_data *ppc) 292{ 293 register char r; 294 295 r = r_str(ppc); 296 w_str(ppc, r | 0x1); 297 w_str(ppc, r & 0xfe); 298 299 return; 300} 301 302static int 303ppc_check_epp_timeout(struct ppc_data *ppc) 304{ 305 ppc_reset_epp_timeout(ppc); 306 307 return (!(r_str(ppc) & TIMEOUT)); 308} 309 310/* 311 * Configure current operating mode 312 */ 313static int 314ppc_generic_setmode(struct ppc_data *ppc, int mode) 315{ 316 u_char ecr = 0; 317 318 /* check if mode is available */ 319 if (mode && !(ppc->ppc_avm & mode)) 320 return (EINVAL); 321 322 /* if ECP mode, configure ecr register */ 323 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 324 /* return to byte mode (keeping direction bit), 325 * no interrupt, no DMA to be able to change to 326 * ECP 327 */ 328 w_ecr(ppc, PPC_ECR_RESET); 329 ecr = PPC_DISABLE_INTR; 330 331 if (mode & PPB_EPP) 332 return (EINVAL); 333 else if (mode & PPB_ECP) 334 /* select ECP mode */ 335 ecr |= PPC_ECR_ECP; 336 else if (mode & PPB_PS2) 337 /* select PS2 mode with ECP */ 338 ecr |= PPC_ECR_PS2; 339 else 340 /* select COMPATIBLE/NIBBLE mode */ 341 ecr |= PPC_ECR_STD; 342 343 w_ecr(ppc, ecr); 344 } 345 346 ppc->ppc_mode = mode; 347 348 return (0); 349} 350 351/* 352 * The ppc driver is free to choose options like FIFO or DMA 353 * if ECP mode is available. 354 * 355 * The 'RAW' option allows the upper drivers to force the ppc mode 356 * even with FIFO, DMA available. 357 */ 358static int 359ppc_smclike_setmode(struct ppc_data *ppc, int mode) 360{ 361 u_char ecr = 0; 362 363 /* check if mode is available */ 364 if (mode && !(ppc->ppc_avm & mode)) 365 return (EINVAL); 366 367 /* if ECP mode, configure ecr register */ 368 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 369 /* return to byte mode (keeping direction bit), 370 * no interrupt, no DMA to be able to change to 371 * ECP or EPP mode 372 */ 373 w_ecr(ppc, PPC_ECR_RESET); 374 ecr = PPC_DISABLE_INTR; 375 376 if (mode & PPB_EPP) 377 /* select EPP mode */ 378 ecr |= PPC_ECR_EPP; 379 else if (mode & PPB_ECP) 380 /* select ECP mode */ 381 ecr |= PPC_ECR_ECP; 382 else if (mode & PPB_PS2) 383 /* select PS2 mode with ECP */ 384 ecr |= PPC_ECR_PS2; 385 else 386 /* select COMPATIBLE/NIBBLE mode */ 387 ecr |= PPC_ECR_STD; 388 389 w_ecr(ppc, ecr); 390 } 391 392 ppc->ppc_mode = mode; 393 394 return (0); 395} 396 397#ifdef PPC_PROBE_CHIPSET 398/* 399 * ppc_pc873xx_detect 400 * 401 * Probe for a Natsemi PC873xx-family part. 402 * 403 * References in this function are to the National Semiconductor 404 * PC87332 datasheet TL/C/11930, May 1995 revision. 405 */ 406static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 407static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 408static int pc873xx_irqtab[] = {5, 7, 5, 0}; 409 410static int pc873xx_regstab[] = { 411 PC873_FER, PC873_FAR, PC873_PTR, 412 PC873_FCR, PC873_PCR, PC873_PMC, 413 PC873_TUP, PC873_SID, PC873_PNP0, 414 PC873_PNP1, PC873_LPTBA, -1 415}; 416 417static char *pc873xx_rnametab[] = { 418 "FER", "FAR", "PTR", "FCR", "PCR", 419 "PMC", "TUP", "SID", "PNP0", "PNP1", 420 "LPTBA", NULL 421}; 422 423static int 424ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 425{ 426 static int index = 0; 427 int idport, irq; 428 int ptr, pcr, val, i; 429 430 while ((idport = pc873xx_basetab[index++])) { 431 432 /* XXX should check first to see if this location is already claimed */ 433 434 /* 435 * Pull the 873xx through the power-on ID cycle (2.2,1.). 436 * We can't use this to locate the chip as it may already have 437 * been used by the BIOS. 438 */ 439 (void)inb(idport); (void)inb(idport); 440 (void)inb(idport); (void)inb(idport); 441 442 /* 443 * Read the SID byte. Possible values are : 444 * 445 * 01010xxx PC87334 446 * 0001xxxx PC87332 447 * 01110xxx PC87306 448 * 00110xxx PC87303 449 */ 450 outb(idport, PC873_SID); 451 val = inb(idport + 1); 452 if ((val & 0xf0) == 0x10) { 453 ppc->ppc_model = NS_PC87332; 454 } else if ((val & 0xf8) == 0x70) { 455 ppc->ppc_model = NS_PC87306; 456 } else if ((val & 0xf8) == 0x50) { 457 ppc->ppc_model = NS_PC87334; 458 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 459 documentation, but probing 460 yielded 0x40... */ 461 ppc->ppc_model = NS_PC87303; 462 } else { 463 if (bootverbose && (val != 0xff)) 464 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 465 continue ; /* not recognised */ 466 } 467 468 /* print registers */ 469 if (bootverbose) { 470 printf("PC873xx"); 471 for (i=0; pc873xx_regstab[i] != -1; i++) { 472 outb(idport, pc873xx_regstab[i]); 473 printf(" %s=0x%x", pc873xx_rnametab[i], 474 inb(idport + 1) & 0xff); 475 } 476 printf("\n"); 477 } 478 479 /* 480 * We think we have one. Is it enabled and where we want it to be? 481 */ 482 outb(idport, PC873_FER); 483 val = inb(idport + 1); 484 if (!(val & PC873_PPENABLE)) { 485 if (bootverbose) 486 printf("PC873xx parallel port disabled\n"); 487 continue; 488 } 489 outb(idport, PC873_FAR); 490 val = inb(idport + 1); 491 /* XXX we should create a driver instance for every port found */ 492 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 493 494 /* First try to change the port address to that requested... */ 495 496 switch (ppc->ppc_base) { 497 case 0x378: 498 val &= 0xfc; 499 break; 500 501 case 0x3bc: 502 val &= 0xfd; 503 break; 504 505 case 0x278: 506 val &= 0xfe; 507 break; 508 509 default: 510 val &= 0xfd; 511 break; 512 } 513 514 outb(idport, PC873_FAR); 515 outb(idport + 1, val); 516 outb(idport + 1, val); 517 518 /* Check for success by reading back the value we supposedly 519 wrote and comparing...*/ 520 521 outb(idport, PC873_FAR); 522 val = inb(idport + 1) & 0x3; 523 524 /* If we fail, report the failure... */ 525 526 if (pc873xx_porttab[val] != ppc->ppc_base) { 527 if (bootverbose) 528 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 529 pc873xx_porttab[val], ppc->ppc_base); 530 } 531 continue; 532 } 533 534 outb(idport, PC873_PTR); 535 ptr = inb(idport + 1); 536 537 /* get irq settings */ 538 if (ppc->ppc_base == 0x378) 539 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 540 else 541 irq = pc873xx_irqtab[val]; 542 543 if (bootverbose) 544 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 545 546 /* 547 * Check if irq settings are correct 548 */ 549 if (irq != ppc->ppc_irq) { 550 /* 551 * If the chipset is not locked and base address is 0x378, 552 * we have another chance 553 */ 554 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 555 if (ppc->ppc_irq == 7) { 556 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 557 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 558 } else { 559 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 560 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 561 } 562 if (bootverbose) 563 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 564 } else { 565 if (bootverbose) 566 printf("PC873xx sorry, can't change irq setting\n"); 567 } 568 } else { 569 if (bootverbose) 570 printf("PC873xx irq settings are correct\n"); 571 } 572 573 outb(idport, PC873_PCR); 574 pcr = inb(idport + 1); 575 576 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 577 if (bootverbose) 578 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 579 580 ppc->ppc_avm |= PPB_NIBBLE; 581 if (bootverbose) 582 printf(", NIBBLE"); 583 584 if (pcr & PC873_EPPEN) { 585 ppc->ppc_avm |= PPB_EPP; 586 587 if (bootverbose) 588 printf(", EPP"); 589 590 if (pcr & PC873_EPP19) 591 ppc->ppc_epp = EPP_1_9; 592 else 593 ppc->ppc_epp = EPP_1_7; 594 595 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 596 outb(idport, PC873_PTR); 597 ptr = inb(idport + 1); 598 if (ptr & PC873_EPPRDIR) 599 printf(", Regular mode"); 600 else 601 printf(", Automatic mode"); 602 } 603 } else if (pcr & PC873_ECPEN) { 604 ppc->ppc_avm |= PPB_ECP; 605 if (bootverbose) 606 printf(", ECP"); 607 608 if (pcr & PC873_ECPCLK) { /* XXX */ 609 ppc->ppc_avm |= PPB_PS2; 610 if (bootverbose) 611 printf(", PS/2"); 612 } 613 } else { 614 outb(idport, PC873_PTR); 615 ptr = inb(idport + 1); 616 if (ptr & PC873_EXTENDED) { 617 ppc->ppc_avm |= PPB_SPP; 618 if (bootverbose) 619 printf(", SPP"); 620 } 621 } 622 } else { 623 if (bootverbose) 624 printf("PC873xx unlocked"); 625 626 if (chipset_mode & PPB_ECP) { 627 if ((chipset_mode & PPB_EPP) && bootverbose) 628 printf(", ECP+EPP not supported"); 629 630 pcr &= ~PC873_EPPEN; 631 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 632 outb(idport + 1, pcr); 633 outb(idport + 1, pcr); 634 635 if (bootverbose) 636 printf(", ECP"); 637 638 } else if (chipset_mode & PPB_EPP) { 639 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 640 pcr |= (PC873_EPPEN | PC873_EPP19); 641 outb(idport + 1, pcr); 642 outb(idport + 1, pcr); 643 644 ppc->ppc_epp = EPP_1_9; /* XXX */ 645 646 if (bootverbose) 647 printf(", EPP1.9"); 648 649 /* enable automatic direction turnover */ 650 if (ppc->ppc_model == NS_PC87332) { 651 outb(idport, PC873_PTR); 652 ptr = inb(idport + 1); 653 ptr &= ~PC873_EPPRDIR; 654 outb(idport + 1, ptr); 655 outb(idport + 1, ptr); 656 657 if (bootverbose) 658 printf(", Automatic mode"); 659 } 660 } else { 661 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 662 outb(idport + 1, pcr); 663 outb(idport + 1, pcr); 664 665 /* configure extended bit in PTR */ 666 outb(idport, PC873_PTR); 667 ptr = inb(idport + 1); 668 669 if (chipset_mode & PPB_PS2) { 670 ptr |= PC873_EXTENDED; 671 672 if (bootverbose) 673 printf(", PS/2"); 674 675 } else { 676 /* default to NIBBLE mode */ 677 ptr &= ~PC873_EXTENDED; 678 679 if (bootverbose) 680 printf(", NIBBLE"); 681 } 682 outb(idport + 1, ptr); 683 outb(idport + 1, ptr); 684 } 685 686 ppc->ppc_avm = chipset_mode; 687 } 688 689 if (bootverbose) 690 printf("\n"); 691 692 ppc->ppc_type = PPC_TYPE_GENERIC; 693 ppc_generic_setmode(ppc, chipset_mode); 694 695 return(chipset_mode); 696 } 697 return(-1); 698} 699 700/* 701 * ppc_smc37c66xgt_detect 702 * 703 * SMC FDC37C66xGT configuration. 704 */ 705static int 706ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 707{ 708 int i; 709 u_char r; 710 int type = -1; 711 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 712 713 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 714 715 716#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 717 718 /* 719 * Detection: enter configuration mode and read CRD register. 720 */ 721 PPC_CONFIG_LOCK(ppc); 722 outb(csr, SMC665_iCODE); 723 outb(csr, SMC665_iCODE); 724 PPC_CONFIG_UNLOCK(ppc); 725 726 outb(csr, 0xd); 727 if (inb(cio) == 0x65) { 728 type = SMC_37C665GT; 729 goto config; 730 } 731 732 for (i = 0; i < 2; i++) { 733 PPC_CONFIG_LOCK(ppc); 734 outb(csr, SMC666_iCODE); 735 outb(csr, SMC666_iCODE); 736 PPC_CONFIG_UNLOCK(ppc); 737 738 outb(csr, 0xd); 739 if (inb(cio) == 0x66) { 740 type = SMC_37C666GT; 741 break; 742 } 743 744 /* Another chance, CSR may be hard-configured to be at 0x370 */ 745 csr = SMC666_CSR; 746 } 747 748config: 749 /* 750 * If chipset not found, do not continue. 751 */ 752 if (type == -1) { 753 outb(csr, 0xaa); /* end config mode */ 754 return (-1); 755 } 756 757 /* select CR1 */ 758 outb(csr, 0x1); 759 760 /* read the port's address: bits 0 and 1 of CR1 */ 761 r = inb(cio) & SMC_CR1_ADDR; 762 if (port_address[(int)r] != ppc->ppc_base) { 763 outb(csr, 0xaa); /* end config mode */ 764 return (-1); 765 } 766 767 ppc->ppc_model = type; 768 769 /* 770 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 771 * If SPP mode is detected, try to set ECP+EPP mode 772 */ 773 774 if (bootverbose) { 775 outb(csr, 0x1); 776 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x", 777 inb(cio) & 0xff); 778 779 outb(csr, 0x4); 780 printf(" CR4=0x%x", inb(cio) & 0xff); 781 } 782 783 /* select CR1 */ 784 outb(csr, 0x1); 785 786 if (!chipset_mode) { 787 /* autodetect mode */ 788 789 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 790 if (type == SMC_37C666GT) { 791 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 792 if (bootverbose) 793 printf(" configuration hardwired, supposing " \ 794 "ECP+EPP SPP"); 795 796 } else 797 if ((inb(cio) & SMC_CR1_MODE) == 0) { 798 /* already in extended parallel port mode, read CR4 */ 799 outb(csr, 0x4); 800 r = (inb(cio) & SMC_CR4_EMODE); 801 802 switch (r) { 803 case SMC_SPP: 804 ppc->ppc_avm |= PPB_SPP; 805 if (bootverbose) 806 printf(" SPP"); 807 break; 808 809 case SMC_EPPSPP: 810 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 811 if (bootverbose) 812 printf(" EPP SPP"); 813 break; 814 815 case SMC_ECP: 816 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 817 if (bootverbose) 818 printf(" ECP SPP"); 819 break; 820 821 case SMC_ECPEPP: 822 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 823 if (bootverbose) 824 printf(" ECP+EPP SPP"); 825 break; 826 } 827 } else { 828 /* not an extended port mode */ 829 ppc->ppc_avm |= PPB_SPP; 830 if (bootverbose) 831 printf(" SPP"); 832 } 833 834 } else { 835 /* mode forced */ 836 ppc->ppc_avm = chipset_mode; 837 838 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 839 if (type == SMC_37C666GT) 840 goto end_detect; 841 842 r = inb(cio); 843 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 844 /* do not use ECP when the mode is not forced to */ 845 outb(cio, r | SMC_CR1_MODE); 846 if (bootverbose) 847 printf(" SPP"); 848 } else { 849 /* an extended mode is selected */ 850 outb(cio, r & ~SMC_CR1_MODE); 851 852 /* read CR4 register and reset mode field */ 853 outb(csr, 0x4); 854 r = inb(cio) & ~SMC_CR4_EMODE; 855 856 if (chipset_mode & PPB_ECP) { 857 if (chipset_mode & PPB_EPP) { 858 outb(cio, r | SMC_ECPEPP); 859 if (bootverbose) 860 printf(" ECP+EPP"); 861 } else { 862 outb(cio, r | SMC_ECP); 863 if (bootverbose) 864 printf(" ECP"); 865 } 866 } else { 867 /* PPB_EPP is set */ 868 outb(cio, r | SMC_EPPSPP); 869 if (bootverbose) 870 printf(" EPP SPP"); 871 } 872 } 873 ppc->ppc_avm = chipset_mode; 874 } 875 876 /* set FIFO threshold to 16 */ 877 if (ppc->ppc_avm & PPB_ECP) { 878 /* select CRA */ 879 outb(csr, 0xa); 880 outb(cio, 16); 881 } 882 883end_detect: 884 885 if (bootverbose) 886 printf ("\n"); 887 888 if (ppc->ppc_avm & PPB_EPP) { 889 /* select CR4 */ 890 outb(csr, 0x4); 891 r = inb(cio); 892 893 /* 894 * Set the EPP protocol... 895 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 896 */ 897 if (ppc->ppc_epp == EPP_1_9) 898 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 899 else 900 outb(cio, (r | SMC_CR4_EPPTYPE)); 901 } 902 903 outb(csr, 0xaa); /* end config mode */ 904 905 ppc->ppc_type = PPC_TYPE_SMCLIKE; 906 ppc_smclike_setmode(ppc, chipset_mode); 907 908 return (chipset_mode); 909} 910 911/* 912 * SMC FDC37C935 configuration 913 * Found on many Alpha machines 914 */ 915static int 916ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 917{ 918 int type = -1; 919 920 PPC_CONFIG_LOCK(ppc); 921 outb(SMC935_CFG, 0x55); /* enter config mode */ 922 outb(SMC935_CFG, 0x55); 923 PPC_CONFIG_UNLOCK(ppc); 924 925 outb(SMC935_IND, SMC935_ID); /* check device id */ 926 if (inb(SMC935_DAT) == 0x2) 927 type = SMC_37C935; 928 929 if (type == -1) { 930 outb(SMC935_CFG, 0xaa); /* exit config mode */ 931 return (-1); 932 } 933 934 ppc->ppc_model = type; 935 936 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 937 outb(SMC935_DAT, 3); /* which is logical device 3 */ 938 939 /* set io port base */ 940 outb(SMC935_IND, SMC935_PORTHI); 941 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 942 outb(SMC935_IND, SMC935_PORTLO); 943 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 944 945 if (!chipset_mode) 946 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 947 else { 948 ppc->ppc_avm = chipset_mode; 949 outb(SMC935_IND, SMC935_PPMODE); 950 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 951 952 /* SPP + EPP or just plain SPP */ 953 if (chipset_mode & (PPB_SPP)) { 954 if (chipset_mode & PPB_EPP) { 955 if (ppc->ppc_epp == EPP_1_9) { 956 outb(SMC935_IND, SMC935_PPMODE); 957 outb(SMC935_DAT, SMC935_EPP19SPP); 958 } 959 if (ppc->ppc_epp == EPP_1_7) { 960 outb(SMC935_IND, SMC935_PPMODE); 961 outb(SMC935_DAT, SMC935_EPP17SPP); 962 } 963 } else { 964 outb(SMC935_IND, SMC935_PPMODE); 965 outb(SMC935_DAT, SMC935_SPP); 966 } 967 } 968 969 /* ECP + EPP or just plain ECP */ 970 if (chipset_mode & PPB_ECP) { 971 if (chipset_mode & PPB_EPP) { 972 if (ppc->ppc_epp == EPP_1_9) { 973 outb(SMC935_IND, SMC935_PPMODE); 974 outb(SMC935_DAT, SMC935_ECPEPP19); 975 } 976 if (ppc->ppc_epp == EPP_1_7) { 977 outb(SMC935_IND, SMC935_PPMODE); 978 outb(SMC935_DAT, SMC935_ECPEPP17); 979 } 980 } else { 981 outb(SMC935_IND, SMC935_PPMODE); 982 outb(SMC935_DAT, SMC935_ECP); 983 } 984 } 985 } 986 987 outb(SMC935_CFG, 0xaa); /* exit config mode */ 988 989 ppc->ppc_type = PPC_TYPE_SMCLIKE; 990 ppc_smclike_setmode(ppc, chipset_mode); 991 992 return (chipset_mode); 993} 994 995/* 996 * Winbond W83877F stuff 997 * 998 * EFER: extended function enable register 999 * EFIR: extended function index register 1000 * EFDR: extended function data register 1001 */ 1002#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1003#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1004 1005static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1006static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1007static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1008static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1009 1010static int 1011ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1012{ 1013 int i, j, efer; 1014 unsigned char r, hefere, hefras; 1015 1016 for (i = 0; i < 4; i ++) { 1017 /* first try to enable configuration registers */ 1018 efer = w83877f_efers[i]; 1019 1020 /* write the key to the EFER */ 1021 for (j = 0; j < w83877f_keyiter[i]; j ++) 1022 outb (efer, w83877f_keys[i]); 1023 1024 /* then check HEFERE and HEFRAS bits */ 1025 outb (efir, 0x0c); 1026 hefere = inb(efdr) & WINB_HEFERE; 1027 1028 outb (efir, 0x16); 1029 hefras = inb(efdr) & WINB_HEFRAS; 1030 1031 /* 1032 * HEFRAS HEFERE 1033 * 0 1 write 89h to 250h (power-on default) 1034 * 1 0 write 86h twice to 3f0h 1035 * 1 1 write 87h twice to 3f0h 1036 * 0 0 write 88h to 250h 1037 */ 1038 if ((hefere | hefras) == w83877f_hefs[i]) 1039 goto found; 1040 } 1041 1042 return (-1); /* failed */ 1043 1044found: 1045 /* check base port address - read from CR23 */ 1046 outb(efir, 0x23); 1047 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1048 return (-1); 1049 1050 /* read CHIP ID from CR9/bits0-3 */ 1051 outb(efir, 0x9); 1052 1053 switch (inb(efdr) & WINB_CHIPID) { 1054 case WINB_W83877F_ID: 1055 ppc->ppc_model = WINB_W83877F; 1056 break; 1057 1058 case WINB_W83877AF_ID: 1059 ppc->ppc_model = WINB_W83877AF; 1060 break; 1061 1062 default: 1063 ppc->ppc_model = WINB_UNKNOWN; 1064 } 1065 1066 if (bootverbose) { 1067 /* dump of registers */ 1068 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]); 1069 for (i = 0; i <= 0xd; i ++) { 1070 outb(efir, i); 1071 printf("0x%x ", inb(efdr)); 1072 } 1073 for (i = 0x10; i <= 0x17; i ++) { 1074 outb(efir, i); 1075 printf("0x%x ", inb(efdr)); 1076 } 1077 outb(efir, 0x1e); 1078 printf("0x%x ", inb(efdr)); 1079 for (i = 0x20; i <= 0x29; i ++) { 1080 outb(efir, i); 1081 printf("0x%x ", inb(efdr)); 1082 } 1083 printf("\n"); 1084 } 1085 1086 ppc->ppc_type = PPC_TYPE_GENERIC; 1087 1088 if (!chipset_mode) { 1089 /* autodetect mode */ 1090 1091 /* select CR0 */ 1092 outb(efir, 0x0); 1093 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1094 1095 /* select CR9 */ 1096 outb(efir, 0x9); 1097 r |= (inb(efdr) & WINB_PRTMODS2); 1098 1099 switch (r) { 1100 case WINB_W83757: 1101 if (bootverbose) 1102 device_printf(ppc->ppc_dev, 1103 "W83757 compatible mode\n"); 1104 return (-1); /* generic or SMC-like */ 1105 1106 case WINB_EXTFDC: 1107 case WINB_EXTADP: 1108 case WINB_EXT2FDD: 1109 case WINB_JOYSTICK: 1110 if (bootverbose) 1111 device_printf(ppc->ppc_dev, 1112 "not in parallel port mode\n"); 1113 return (-1); 1114 1115 case (WINB_PARALLEL | WINB_EPP_SPP): 1116 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1117 if (bootverbose) 1118 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1119 break; 1120 1121 case (WINB_PARALLEL | WINB_ECP): 1122 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1123 if (bootverbose) 1124 device_printf(ppc->ppc_dev, "ECP SPP\n"); 1125 break; 1126 1127 case (WINB_PARALLEL | WINB_ECP_EPP): 1128 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1129 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1130 1131 if (bootverbose) 1132 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n"); 1133 break; 1134 default: 1135 printf("%s: unknown case (0x%x)!\n", __func__, r); 1136 } 1137 1138 } else { 1139 /* mode forced */ 1140 1141 /* select CR9 and set PRTMODS2 bit */ 1142 outb(efir, 0x9); 1143 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1144 1145 /* select CR0 and reset PRTMODSx bits */ 1146 outb(efir, 0x0); 1147 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1148 1149 if (chipset_mode & PPB_ECP) { 1150 if (chipset_mode & PPB_EPP) { 1151 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1152 if (bootverbose) 1153 device_printf(ppc->ppc_dev, 1154 "ECP+EPP\n"); 1155 1156 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1157 1158 } else { 1159 outb(efdr, inb(efdr) | WINB_ECP); 1160 if (bootverbose) 1161 device_printf(ppc->ppc_dev, "ECP\n"); 1162 } 1163 } else { 1164 /* select EPP_SPP otherwise */ 1165 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1166 if (bootverbose) 1167 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1168 } 1169 ppc->ppc_avm = chipset_mode; 1170 } 1171 1172 /* exit configuration mode */ 1173 outb(efer, 0xaa); 1174 1175 switch (ppc->ppc_type) { 1176 case PPC_TYPE_SMCLIKE: 1177 ppc_smclike_setmode(ppc, chipset_mode); 1178 break; 1179 default: 1180 ppc_generic_setmode(ppc, chipset_mode); 1181 break; 1182 } 1183 1184 return (chipset_mode); 1185} 1186#endif 1187 1188/* 1189 * ppc_generic_detect 1190 */ 1191static int 1192ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1193{ 1194 /* default to generic */ 1195 ppc->ppc_type = PPC_TYPE_GENERIC; 1196 1197 if (bootverbose) 1198 device_printf(ppc->ppc_dev, "SPP"); 1199 1200 /* first, check for ECP */ 1201 w_ecr(ppc, PPC_ECR_PS2); 1202 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1203 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1204 if (bootverbose) 1205 printf(" ECP "); 1206 1207 /* search for SMC style ECP+EPP mode */ 1208 w_ecr(ppc, PPC_ECR_EPP); 1209 } 1210 1211 /* try to reset EPP timeout bit */ 1212 if (ppc_check_epp_timeout(ppc)) { 1213 ppc->ppc_dtm |= PPB_EPP; 1214 1215 if (ppc->ppc_dtm & PPB_ECP) { 1216 /* SMC like chipset found */ 1217 ppc->ppc_model = SMC_LIKE; 1218 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1219 1220 if (bootverbose) 1221 printf(" ECP+EPP"); 1222 } else { 1223 if (bootverbose) 1224 printf(" EPP"); 1225 } 1226 } else { 1227 /* restore to standard mode */ 1228 w_ecr(ppc, PPC_ECR_STD); 1229 } 1230 1231 /* XXX try to detect NIBBLE and PS2 modes */ 1232 ppc->ppc_dtm |= PPB_NIBBLE; 1233 1234 if (chipset_mode) 1235 ppc->ppc_avm = chipset_mode; 1236 else 1237 ppc->ppc_avm = ppc->ppc_dtm; 1238 1239 if (bootverbose) 1240 printf("\n"); 1241 1242 switch (ppc->ppc_type) { 1243 case PPC_TYPE_SMCLIKE: 1244 ppc_smclike_setmode(ppc, chipset_mode); 1245 break; 1246 default: 1247 ppc_generic_setmode(ppc, chipset_mode); 1248 break; 1249 } 1250 1251 return (chipset_mode); 1252} 1253 1254/* 1255 * ppc_detect() 1256 * 1257 * mode is the mode suggested at boot 1258 */ 1259static int 1260ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1261 1262#ifdef PPC_PROBE_CHIPSET 1263 int i, mode; 1264 1265 /* list of supported chipsets */ 1266 int (*chipset_detect[])(struct ppc_data *, int) = { 1267 ppc_pc873xx_detect, 1268 ppc_smc37c66xgt_detect, 1269 ppc_w83877f_detect, 1270 ppc_smc37c935_detect, 1271 ppc_generic_detect, 1272 NULL 1273 }; 1274#endif 1275 1276 /* if can't find the port and mode not forced return error */ 1277 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1278 return (EIO); /* failed, port not present */ 1279 1280 /* assume centronics compatible mode is supported */ 1281 ppc->ppc_avm = PPB_COMPATIBLE; 1282 1283#ifdef PPC_PROBE_CHIPSET 1284 /* we have to differenciate available chipset modes, 1285 * chipset running modes and IEEE-1284 operating modes 1286 * 1287 * after detection, the port must support running in compatible mode 1288 */ 1289 if (ppc->ppc_flags & 0x40) { 1290 if (bootverbose) 1291 printf("ppc: chipset forced to generic\n"); 1292#endif 1293 1294 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1295 1296#ifdef PPC_PROBE_CHIPSET 1297 } else { 1298 for (i=0; chipset_detect[i] != NULL; i++) { 1299 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1300 ppc->ppc_mode = mode; 1301 break; 1302 } 1303 } 1304 } 1305#endif 1306 1307 /* configure/detect ECP FIFO */ 1308 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1309 ppc_detect_fifo(ppc); 1310 1311 return (0); 1312} 1313 1314/* 1315 * ppc_exec_microseq() 1316 * 1317 * Execute a microsequence. 1318 * Microsequence mechanism is supposed to handle fast I/O operations. 1319 */ 1320int 1321ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1322{ 1323 struct ppc_data *ppc = DEVTOSOFTC(dev); 1324 struct ppb_microseq *mi; 1325 char cc, *p; 1326 int i, iter, len; 1327 int error; 1328 1329 register int reg; 1330 register char mask; 1331 register int accum = 0; 1332 register char *ptr = 0; 1333 1334 struct ppb_microseq *stack = 0; 1335 1336/* microsequence registers are equivalent to PC-like port registers */ 1337 1338#define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1339#define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1340 1341#define INCR_PC (mi ++) /* increment program counter */ 1342 1343 PPC_ASSERT_LOCKED(ppc); 1344 mi = *p_msq; 1345 for (;;) { 1346 switch (mi->opcode) { 1347 case MS_OP_RSET: 1348 cc = r_reg(mi->arg[0].i, ppc); 1349 cc &= (char)mi->arg[2].i; /* clear mask */ 1350 cc |= (char)mi->arg[1].i; /* assert mask */ 1351 w_reg(mi->arg[0].i, ppc, cc); 1352 INCR_PC; 1353 break; 1354 1355 case MS_OP_RASSERT_P: 1356 reg = mi->arg[1].i; 1357 ptr = ppc->ppc_ptr; 1358 1359 if ((len = mi->arg[0].i) == MS_ACCUM) { 1360 accum = ppc->ppc_accum; 1361 for (; accum; accum--) 1362 w_reg(reg, ppc, *ptr++); 1363 ppc->ppc_accum = accum; 1364 } else 1365 for (i=0; i<len; i++) 1366 w_reg(reg, ppc, *ptr++); 1367 ppc->ppc_ptr = ptr; 1368 1369 INCR_PC; 1370 break; 1371 1372 case MS_OP_RFETCH_P: 1373 reg = mi->arg[1].i; 1374 mask = (char)mi->arg[2].i; 1375 ptr = ppc->ppc_ptr; 1376 1377 if ((len = mi->arg[0].i) == MS_ACCUM) { 1378 accum = ppc->ppc_accum; 1379 for (; accum; accum--) 1380 *ptr++ = r_reg(reg, ppc) & mask; 1381 ppc->ppc_accum = accum; 1382 } else 1383 for (i=0; i<len; i++) 1384 *ptr++ = r_reg(reg, ppc) & mask; 1385 ppc->ppc_ptr = ptr; 1386 1387 INCR_PC; 1388 break; 1389 1390 case MS_OP_RFETCH: 1391 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1392 (char)mi->arg[1].i; 1393 INCR_PC; 1394 break; 1395 1396 case MS_OP_RASSERT: 1397 case MS_OP_DELAY: 1398 1399 /* let's suppose the next instr. is the same */ 1400 prefetch: 1401 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1402 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1403 1404 if (mi->opcode == MS_OP_DELAY) { 1405 DELAY(mi->arg[0].i); 1406 INCR_PC; 1407 goto prefetch; 1408 } 1409 break; 1410 1411 case MS_OP_ADELAY: 1412 if (mi->arg[0].i) { 1413 PPC_UNLOCK(ppc); 1414 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1415 PPC_LOCK(ppc); 1416 } 1417 INCR_PC; 1418 break; 1419 1420 case MS_OP_TRIG: 1421 reg = mi->arg[0].i; 1422 iter = mi->arg[1].i; 1423 p = (char *)mi->arg[2].p; 1424 1425 /* XXX delay limited to 255 us */ 1426 for (i=0; i<iter; i++) { 1427 w_reg(reg, ppc, *p++); 1428 DELAY((unsigned char)*p++); 1429 } 1430 INCR_PC; 1431 break; 1432 1433 case MS_OP_SET: 1434 ppc->ppc_accum = mi->arg[0].i; 1435 INCR_PC; 1436 break; 1437 1438 case MS_OP_DBRA: 1439 if (--ppc->ppc_accum > 0) 1440 mi += mi->arg[0].i; 1441 INCR_PC; 1442 break; 1443 1444 case MS_OP_BRSET: 1445 cc = r_str(ppc); 1446 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1447 mi += mi->arg[1].i; 1448 INCR_PC; 1449 break; 1450 1451 case MS_OP_BRCLEAR: 1452 cc = r_str(ppc); 1453 if ((cc & (char)mi->arg[0].i) == 0) 1454 mi += mi->arg[1].i; 1455 INCR_PC; 1456 break; 1457 1458 case MS_OP_BRSTAT: 1459 cc = r_str(ppc); 1460 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1461 (char)mi->arg[0].i) 1462 mi += mi->arg[2].i; 1463 INCR_PC; 1464 break; 1465 1466 case MS_OP_C_CALL: 1467 /* 1468 * If the C call returns !0 then end the microseq. 1469 * The current state of ptr is passed to the C function 1470 */ 1471 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1472 return (error); 1473 1474 INCR_PC; 1475 break; 1476 1477 case MS_OP_PTR: 1478 ppc->ppc_ptr = (char *)mi->arg[0].p; 1479 INCR_PC; 1480 break; 1481 1482 case MS_OP_CALL: 1483 if (stack) 1484 panic("%s: too much calls", __func__); 1485 1486 if (mi->arg[0].p) { 1487 /* store the state of the actual 1488 * microsequence 1489 */ 1490 stack = mi; 1491 1492 /* jump to the new microsequence */ 1493 mi = (struct ppb_microseq *)mi->arg[0].p; 1494 } else 1495 INCR_PC; 1496 1497 break; 1498 1499 case MS_OP_SUBRET: 1500 /* retrieve microseq and pc state before the call */ 1501 mi = stack; 1502 1503 /* reset the stack */ 1504 stack = 0; 1505 1506 /* XXX return code */ 1507 1508 INCR_PC; 1509 break; 1510 1511 case MS_OP_PUT: 1512 case MS_OP_GET: 1513 case MS_OP_RET: 1514 /* can't return to ppb level during the execution 1515 * of a submicrosequence */ 1516 if (stack) 1517 panic("%s: can't return to ppb level", 1518 __func__); 1519 1520 /* update pc for ppb level of execution */ 1521 *p_msq = mi; 1522 1523 /* return to ppb level of execution */ 1524 return (0); 1525 1526 default: 1527 panic("%s: unknown microsequence opcode 0x%x", 1528 __func__, mi->opcode); 1529 } 1530 } 1531 1532 /* unreached */ 1533} 1534 1535static void 1536ppcintr(void *arg) 1537{ 1538 struct ppc_data *ppc = arg; 1539 u_char ctr, ecr, str; 1540 1541 /* 1542 * If we have any child interrupt handlers registered, let 1543 * them handle this interrupt. 1544 * 1545 * XXX: If DMA is in progress should we just complete that w/o 1546 * doing this? 1547 */ 1548 PPC_LOCK(ppc); 1549 if (ppc->ppc_intr_hook != NULL && 1550 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) { 1551 PPC_UNLOCK(ppc); 1552 return; 1553 } 1554 1555 str = r_str(ppc); 1556 ctr = r_ctr(ppc); 1557 ecr = r_ecr(ppc); 1558 1559#if defined(PPC_DEBUG) && PPC_DEBUG > 1 1560 printf("![%x/%x/%x]", ctr, ecr, str); 1561#endif 1562 1563 /* don't use ecp mode with IRQENABLE set */ 1564 if (ctr & IRQENABLE) { 1565 PPC_UNLOCK(ppc); 1566 return; 1567 } 1568 1569 /* interrupts are generated by nFault signal 1570 * only in ECP mode */ 1571 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1572 /* check if ppc driver has programmed the 1573 * nFault interrupt */ 1574 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1575 1576 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1577 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1578 } else { 1579 /* shall be handled by underlying layers XXX */ 1580 PPC_UNLOCK(ppc); 1581 return; 1582 } 1583 } 1584 1585 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1586 /* disable interrupts (should be done by hardware though) */ 1587 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1588 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1589 ecr = r_ecr(ppc); 1590 1591 /* check if DMA completed */ 1592 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1593#ifdef PPC_DEBUG 1594 printf("a"); 1595#endif 1596 /* stop DMA */ 1597 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1598 ecr = r_ecr(ppc); 1599 1600 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1601#ifdef PPC_DEBUG 1602 printf("d"); 1603#endif 1604 ppc->ppc_dmadone(ppc); 1605 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1606 1607 /* wakeup the waiting process */ 1608 wakeup(ppc); 1609 } 1610 } 1611 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1612 1613 /* classic interrupt I/O */ 1614 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1615 } 1616 PPC_UNLOCK(ppc); 1617 1618 return; 1619} 1620 1621int 1622ppc_read(device_t dev, char *buf, int len, int mode) 1623{ 1624 return (EINVAL); 1625} 1626 1627int 1628ppc_write(device_t dev, char *buf, int len, int how) 1629{ 1630 return (EINVAL); 1631} 1632 1633int 1634ppc_reset_epp(device_t dev) 1635{ 1636 struct ppc_data *ppc = DEVTOSOFTC(dev); 1637 1638 PPC_ASSERT_LOCKED(ppc); 1639 ppc_reset_epp_timeout(ppc); 1640 1641 return 0; 1642} 1643 1644int 1645ppc_setmode(device_t dev, int mode) 1646{ 1647 struct ppc_data *ppc = DEVTOSOFTC(dev); 1648 1649 PPC_ASSERT_LOCKED(ppc); 1650 switch (ppc->ppc_type) { 1651 case PPC_TYPE_SMCLIKE: 1652 return (ppc_smclike_setmode(ppc, mode)); 1653 break; 1654 1655 case PPC_TYPE_GENERIC: 1656 default: 1657 return (ppc_generic_setmode(ppc, mode)); 1658 break; 1659 } 1660 1661 /* not reached */ 1662 return (ENXIO); 1663} 1664 1665int 1666ppc_probe(device_t dev, int rid) 1667{ 1668#ifdef __i386__ 1669 static short next_bios_ppc = 0; 1670#ifdef PC98 1671 unsigned int pc98_ieee_mode = 0x00; 1672 unsigned int tmp; 1673#endif 1674#endif 1675 struct ppc_data *ppc; 1676 int error; 1677 u_long port; 1678 1679 /* 1680 * Allocate the ppc_data structure. 1681 */ 1682 ppc = DEVTOSOFTC(dev); 1683 bzero(ppc, sizeof(struct ppc_data)); 1684 1685 ppc->rid_ioport = rid; 1686 1687 /* retrieve ISA parameters */ 1688 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1689 1690#ifdef __i386__ 1691 /* 1692 * If port not specified, use bios list. 1693 */ 1694 if (error) { 1695#ifdef PC98 1696 if (next_bios_ppc == 0) { 1697 /* Use default IEEE-1284 port of NEC PC-98x1 */ 1698 port = PC98_IEEE_1284_PORT; 1699 next_bios_ppc += 1; 1700 if (bootverbose) 1701 device_printf(dev, 1702 "parallel port found at 0x%lx\n", port); 1703 } 1704#else 1705 if ((next_bios_ppc < BIOS_MAX_PPC) && 1706 (*(BIOS_PORTS + next_bios_ppc) != 0)) { 1707 port = *(BIOS_PORTS + next_bios_ppc++); 1708 if (bootverbose) 1709 device_printf(dev, 1710 "parallel port found at 0x%lx\n", port); 1711 } else { 1712 device_printf(dev, "parallel port not found.\n"); 1713 return (ENXIO); 1714 } 1715#endif /* PC98 */ 1716 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1717 IO_LPTSIZE_EXTENDED); 1718 } 1719#endif 1720 1721 /* IO port is mandatory */ 1722 1723 /* Try "extended" IO port range...*/ 1724 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1725 &ppc->rid_ioport, 0, ~0, 1726 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1727 1728 if (ppc->res_ioport != 0) { 1729 if (bootverbose) 1730 device_printf(dev, "using extended I/O port range\n"); 1731 } else { 1732 /* Failed? If so, then try the "normal" IO port range... */ 1733 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1734 &ppc->rid_ioport, 0, ~0, 1735 IO_LPTSIZE_NORMAL, 1736 RF_ACTIVE); 1737 if (ppc->res_ioport != 0) { 1738 if (bootverbose) 1739 device_printf(dev, "using normal I/O port range\n"); 1740 } else { 1741 device_printf(dev, "cannot reserve I/O port range\n"); 1742 goto error; 1743 } 1744 } 1745 1746 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1747 1748 ppc->ppc_flags = device_get_flags(dev); 1749 1750 if (!(ppc->ppc_flags & 0x20)) { 1751 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1752 &ppc->rid_irq, 1753 RF_SHAREABLE); 1754 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1755 &ppc->rid_drq, 1756 RF_ACTIVE); 1757 } 1758 1759 if (ppc->res_irq) 1760 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1761 if (ppc->res_drq) 1762 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1763 1764 ppc->ppc_dev = dev; 1765 ppc->ppc_model = GENERIC; 1766 1767 ppc->ppc_mode = PPB_COMPATIBLE; 1768 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1769 1770 ppc->ppc_type = PPC_TYPE_GENERIC; 1771 1772#if defined(__i386__) && defined(PC98) 1773 /* 1774 * IEEE STD 1284 Function Check and Enable 1775 * for default IEEE-1284 port of NEC PC-98x1 1776 */ 1777 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1778 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1779 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1780 pc98_ieee_mode = tmp; 1781 if ((tmp & 0x10) == 0x10) { 1782 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); 1783 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1784 if ((tmp & 0x10) == 0x10) 1785 goto error; 1786 } else { 1787 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); 1788 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1789 if ((tmp & 0x10) != 0x10) 1790 goto error; 1791 } 1792 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); 1793 } 1794#endif 1795 1796 /* 1797 * Try to detect the chipset and its mode. 1798 */ 1799 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1800 goto error; 1801 1802 return (0); 1803 1804error: 1805#if defined(__i386__) && defined(PC98) 1806 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1807 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1808 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); 1809 } 1810#endif 1811 if (ppc->res_irq != 0) { 1812 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1813 ppc->res_irq); 1814 } 1815 if (ppc->res_ioport != 0) { 1816 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1817 ppc->res_ioport); 1818 } 1819 if (ppc->res_drq != 0) { 1820 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1821 ppc->res_drq); 1822 } 1823 return (ENXIO); 1824} 1825 1826int 1827ppc_attach(device_t dev) 1828{ 1829 struct ppc_data *ppc = DEVTOSOFTC(dev); 1830 int error; 1831 1832 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF); 1833 1834 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1835 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1836 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1837 ppc_epp_protocol[ppc->ppc_epp] : ""); 1838 1839 if (ppc->ppc_fifo) 1840 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1841 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1842 1843 if (ppc->res_irq) { 1844 /* default to the tty mask for registration */ /* XXX */ 1845 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY | 1846 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie); 1847 if (error) { 1848 device_printf(dev, 1849 "failed to register interrupt handler: %d\n", 1850 error); 1851 mtx_destroy(&ppc->ppc_lock); 1852 return (error); 1853 } 1854 } 1855 1856 /* add ppbus as a child of this isa to parallel bridge */ 1857 ppc->ppbus = device_add_child(dev, "ppbus", -1); 1858 1859 /* 1860 * Probe the ppbus and attach devices found. 1861 */ 1862 device_probe_and_attach(ppc->ppbus); 1863 1864 return (0); 1865} 1866 1867int 1868ppc_detach(device_t dev) 1869{ 1870 struct ppc_data *ppc = DEVTOSOFTC(dev); 1871 1872 if (ppc->res_irq == 0) { 1873 return (ENXIO); 1874 } 1875 1876 /* detach & delete all children */ 1877 device_delete_children(dev); 1878 1879 if (ppc->res_irq != 0) { 1880 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1881 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1882 ppc->res_irq); 1883 } 1884 if (ppc->res_ioport != 0) { 1885 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1886 ppc->res_ioport); 1887 } 1888 if (ppc->res_drq != 0) { 1889 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1890 ppc->res_drq); 1891 } 1892 1893 mtx_destroy(&ppc->ppc_lock); 1894 1895 return (0); 1896} 1897 1898u_char 1899ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1900{ 1901 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1902 1903 PPC_ASSERT_LOCKED(ppc); 1904 switch (iop) { 1905 case PPB_OUTSB_EPP: 1906 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1907 break; 1908 case PPB_OUTSW_EPP: 1909 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1910 break; 1911 case PPB_OUTSL_EPP: 1912 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1913 break; 1914 case PPB_INSB_EPP: 1915 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1916 break; 1917 case PPB_INSW_EPP: 1918 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1919 break; 1920 case PPB_INSL_EPP: 1921 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1922 break; 1923 case PPB_RDTR: 1924 return (r_dtr(ppc)); 1925 case PPB_RSTR: 1926 return (r_str(ppc)); 1927 case PPB_RCTR: 1928 return (r_ctr(ppc)); 1929 case PPB_REPP_A: 1930 return (r_epp_A(ppc)); 1931 case PPB_REPP_D: 1932 return (r_epp_D(ppc)); 1933 case PPB_RECR: 1934 return (r_ecr(ppc)); 1935 case PPB_RFIFO: 1936 return (r_fifo(ppc)); 1937 case PPB_WDTR: 1938 w_dtr(ppc, byte); 1939 break; 1940 case PPB_WSTR: 1941 w_str(ppc, byte); 1942 break; 1943 case PPB_WCTR: 1944 w_ctr(ppc, byte); 1945 break; 1946 case PPB_WEPP_A: 1947 w_epp_A(ppc, byte); 1948 break; 1949 case PPB_WEPP_D: 1950 w_epp_D(ppc, byte); 1951 break; 1952 case PPB_WECR: 1953 w_ecr(ppc, byte); 1954 break; 1955 case PPB_WFIFO: 1956 w_fifo(ppc, byte); 1957 break; 1958 default: 1959 panic("%s: unknown I/O operation", __func__); 1960 break; 1961 } 1962 1963 return (0); /* not significative */ 1964} 1965 1966int 1967ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1968{ 1969 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1970 1971 switch (index) { 1972 case PPC_IVAR_EPP_PROTO: 1973 PPC_ASSERT_LOCKED(ppc); 1974 *val = (u_long)ppc->ppc_epp; 1975 break; 1976 case PPC_IVAR_LOCK: 1977 *val = (uintptr_t)&ppc->ppc_lock; 1978 break; 1979 default: 1980 return (ENOENT); 1981 } 1982 1983 return (0); 1984} 1985 1986int 1987ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val) 1988{ 1989 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1990 1991 switch (index) { 1992 case PPC_IVAR_INTR_HANDLER: 1993 PPC_ASSERT_LOCKED(ppc); 1994 if (dev != ppc->ppbus) 1995 return (EINVAL); 1996 if (val == 0) { 1997 ppc->ppc_intr_hook = NULL; 1998 break; 1999 } 2000 if (ppc->ppc_intr_hook != NULL) 2001 return (EBUSY); 2002 ppc->ppc_intr_hook = (void *)val; 2003 ppc->ppc_intr_arg = device_get_softc(dev); 2004 break; 2005 default: 2006 return (ENOENT); 2007 } 2008 2009 return (0); 2010} 2011 2012/* 2013 * We allow child devices to allocate an IRQ resource at rid 0 for their 2014 * interrupt handlers. 2015 */ 2016struct resource * 2017ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 2018 u_long start, u_long end, u_long count, u_int flags) 2019{ 2020 struct ppc_data *ppc = DEVTOSOFTC(bus); 2021 2022 switch (type) { 2023 case SYS_RES_IRQ: 2024 if (*rid == 0) 2025 return (ppc->res_irq); 2026 break; 2027 } 2028 return (NULL); 2029} 2030 2031int 2032ppc_release_resource(device_t bus, device_t child, int type, int rid, 2033 struct resource *r) 2034{ 2035#ifdef INVARIANTS 2036 struct ppc_data *ppc = DEVTOSOFTC(bus); 2037#endif 2038 2039 switch (type) { 2040 case SYS_RES_IRQ: 2041 if (rid == 0) { 2042 KASSERT(r == ppc->res_irq, 2043 ("ppc child IRQ resource mismatch")); 2044 return (0); 2045 } 2046 break; 2047 } 2048 return (EINVAL); 2049} 2050 2051MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2052