1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: releng/10.3/sys/dev/mlx5/driver.h 292196 2015-12-14 10:31:03Z hselasky $ 26 */ 27 28#ifndef MLX5_DRIVER_H 29#define MLX5_DRIVER_H 30 31#include <linux/kernel.h> 32#include <linux/completion.h> 33#include <linux/pci.h> 34#include <linux/cache.h> 35#include <linux/rbtree.h> 36#include <linux/semaphore.h> 37#include <linux/slab.h> 38#include <linux/vmalloc.h> 39#include <linux/radix-tree.h> 40 41#include <dev/mlx5/device.h> 42#include <dev/mlx5/doorbell.h> 43 44enum { 45 MLX5_BOARD_ID_LEN = 64, 46 MLX5_MAX_NAME_LEN = 16, 47}; 48 49enum { 50 /* one minute for the sake of bringup. Generally, commands must always 51 * complete and we may need to increase this timeout value 52 */ 53 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, 54 MLX5_CMD_WQ_MAX_NAME = 32, 55}; 56 57enum { 58 CMD_OWNER_SW = 0x0, 59 CMD_OWNER_HW = 0x1, 60 CMD_STATUS_SUCCESS = 0, 61}; 62 63enum mlx5_sqp_t { 64 MLX5_SQP_SMI = 0, 65 MLX5_SQP_GSI = 1, 66 MLX5_SQP_IEEE_1588 = 2, 67 MLX5_SQP_SNIFFER = 3, 68 MLX5_SQP_SYNC_UMR = 4, 69}; 70 71enum { 72 MLX5_MAX_PORTS = 2, 73}; 74 75enum { 76 MLX5_EQ_VEC_PAGES = 0, 77 MLX5_EQ_VEC_CMD = 1, 78 MLX5_EQ_VEC_ASYNC = 2, 79 MLX5_EQ_VEC_COMP_BASE, 80}; 81 82enum { 83 MLX5_MAX_IRQ_NAME = 32 84}; 85 86enum { 87 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 88 MLX5_ATOMIC_MODE_CX = 2 << 16, 89 MLX5_ATOMIC_MODE_8B = 3 << 16, 90 MLX5_ATOMIC_MODE_16B = 4 << 16, 91 MLX5_ATOMIC_MODE_32B = 5 << 16, 92 MLX5_ATOMIC_MODE_64B = 6 << 16, 93 MLX5_ATOMIC_MODE_128B = 7 << 16, 94 MLX5_ATOMIC_MODE_256B = 8 << 16, 95}; 96 97enum { 98 MLX5_REG_QETCR = 0x4005, 99 MLX5_REG_QPDP = 0x4007, 100 MLX5_REG_QTCT = 0x400A, 101 MLX5_REG_PCAP = 0x5001, 102 MLX5_REG_PMTU = 0x5003, 103 MLX5_REG_PTYS = 0x5004, 104 MLX5_REG_PAOS = 0x5006, 105 MLX5_REG_PFCC = 0x5007, 106 MLX5_REG_PPCNT = 0x5008, 107 MLX5_REG_PMAOS = 0x5012, 108 MLX5_REG_PUDE = 0x5009, 109 MLX5_REG_PPTB = 0x500B, 110 MLX5_REG_PBMC = 0x500C, 111 MLX5_REG_PMPE = 0x5010, 112 MLX5_REG_PELC = 0x500e, 113 MLX5_REG_PVLC = 0x500f, 114 MLX5_REG_PMLP = 0x5002, 115 MLX5_REG_NODE_DESC = 0x6001, 116 MLX5_REG_HOST_ENDIANNESS = 0x7004, 117 MLX5_REG_MCIA = 0x9014, 118}; 119 120enum dbg_rsc_type { 121 MLX5_DBG_RSC_QP, 122 MLX5_DBG_RSC_EQ, 123 MLX5_DBG_RSC_CQ, 124}; 125 126struct mlx5_field_desc { 127 struct dentry *dent; 128 int i; 129}; 130 131struct mlx5_rsc_debug { 132 struct mlx5_core_dev *dev; 133 void *object; 134 enum dbg_rsc_type type; 135 struct dentry *root; 136 struct mlx5_field_desc fields[0]; 137}; 138 139enum mlx5_dev_event { 140 MLX5_DEV_EVENT_SYS_ERROR, 141 MLX5_DEV_EVENT_PORT_UP, 142 MLX5_DEV_EVENT_PORT_DOWN, 143 MLX5_DEV_EVENT_PORT_INITIALIZED, 144 MLX5_DEV_EVENT_LID_CHANGE, 145 MLX5_DEV_EVENT_PKEY_CHANGE, 146 MLX5_DEV_EVENT_GUID_CHANGE, 147 MLX5_DEV_EVENT_CLIENT_REREG, 148 MLX5_DEV_EVENT_VPORT_CHANGE, 149}; 150 151enum mlx5_port_status { 152 MLX5_PORT_UP = 1 << 0, 153 MLX5_PORT_DOWN = 1 << 1, 154}; 155 156enum mlx5_link_mode { 157 MLX5_1000BASE_CX_SGMII = 0, 158 MLX5_1000BASE_KX = 1, 159 MLX5_10GBASE_CX4 = 2, 160 MLX5_10GBASE_KX4 = 3, 161 MLX5_10GBASE_KR = 4, 162 MLX5_20GBASE_KR2 = 5, 163 MLX5_40GBASE_CR4 = 6, 164 MLX5_40GBASE_KR4 = 7, 165 MLX5_56GBASE_R4 = 8, 166 MLX5_10GBASE_CR = 12, 167 MLX5_10GBASE_SR = 13, 168 MLX5_10GBASE_ER = 14, 169 MLX5_40GBASE_SR4 = 15, 170 MLX5_40GBASE_LR4 = 16, 171 MLX5_100GBASE_CR4 = 20, 172 MLX5_100GBASE_SR4 = 21, 173 MLX5_100GBASE_KR4 = 22, 174 MLX5_100GBASE_LR4 = 23, 175 MLX5_100BASE_TX = 24, 176 MLX5_1000BASE_T = 25, 177 MLX5_10GBASE_T = 26, 178 MLX5_25GBASE_CR = 27, 179 MLX5_25GBASE_KR = 28, 180 MLX5_25GBASE_SR = 29, 181 MLX5_50GBASE_CR2 = 30, 182 MLX5_50GBASE_KR2 = 31, 183 MLX5_LINK_MODES_NUMBER, 184}; 185 186#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 187 188struct mlx5_uuar_info { 189 struct mlx5_uar *uars; 190 int num_uars; 191 int num_low_latency_uuars; 192 unsigned long *bitmap; 193 unsigned int *count; 194 struct mlx5_bf *bfs; 195 196 /* 197 * protect uuar allocation data structs 198 */ 199 struct mutex lock; 200 u32 ver; 201}; 202 203struct mlx5_bf { 204 void __iomem *reg; 205 void __iomem *regreg; 206 int buf_size; 207 struct mlx5_uar *uar; 208 unsigned long offset; 209 int need_lock; 210 /* protect blue flame buffer selection when needed 211 */ 212 spinlock_t lock; 213 214 /* serialize 64 bit writes when done as two 32 bit accesses 215 */ 216 spinlock_t lock32; 217 int uuarn; 218}; 219 220struct mlx5_cmd_first { 221 __be32 data[4]; 222}; 223 224struct mlx5_cmd_msg { 225 struct list_head list; 226 struct cache_ent *cache; 227 u32 len; 228 struct mlx5_cmd_first first; 229 struct mlx5_cmd_mailbox *next; 230}; 231 232struct mlx5_cmd_debug { 233 struct dentry *dbg_root; 234 struct dentry *dbg_in; 235 struct dentry *dbg_out; 236 struct dentry *dbg_outlen; 237 struct dentry *dbg_status; 238 struct dentry *dbg_run; 239 void *in_msg; 240 void *out_msg; 241 u8 status; 242 u16 inlen; 243 u16 outlen; 244}; 245 246struct cache_ent { 247 /* protect block chain allocations 248 */ 249 spinlock_t lock; 250 struct list_head head; 251}; 252 253struct cmd_msg_cache { 254 struct cache_ent large; 255 struct cache_ent med; 256 257}; 258 259struct mlx5_cmd_stats { 260 u64 sum; 261 u64 n; 262 struct dentry *root; 263 struct dentry *avg; 264 struct dentry *count; 265 /* protect command average calculations */ 266 spinlock_t lock; 267}; 268 269struct mlx5_cmd { 270 void *cmd_alloc_buf; 271 dma_addr_t alloc_dma; 272 int alloc_size; 273 void *cmd_buf; 274 dma_addr_t dma; 275 u16 cmdif_rev; 276 u8 log_sz; 277 u8 log_stride; 278 int max_reg_cmds; 279 int events; 280 u32 __iomem *vector; 281 282 /* protect command queue allocations 283 */ 284 spinlock_t alloc_lock; 285 286 /* protect token allocations 287 */ 288 spinlock_t token_lock; 289 u8 token; 290 unsigned long bitmask; 291 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 292 struct workqueue_struct *wq; 293 struct semaphore sem; 294 struct semaphore pages_sem; 295 int mode; 296 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 297 struct pci_pool *pool; 298 struct mlx5_cmd_debug dbg; 299 struct cmd_msg_cache cache; 300 int checksum_disabled; 301 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 302 int moving_to_polling; 303}; 304 305struct mlx5_port_caps { 306 int gid_table_len; 307 int pkey_table_len; 308 u8 ext_port_cap; 309}; 310 311struct mlx5_cmd_mailbox { 312 void *buf; 313 dma_addr_t dma; 314 struct mlx5_cmd_mailbox *next; 315}; 316 317struct mlx5_buf_list { 318 void *buf; 319 dma_addr_t map; 320}; 321 322struct mlx5_buf { 323 struct mlx5_buf_list direct; 324 struct mlx5_buf_list *page_list; 325 int nbufs; 326 int npages; 327 int size; 328 u8 page_shift; 329}; 330 331struct mlx5_eq { 332 struct mlx5_core_dev *dev; 333 __be32 __iomem *doorbell; 334 u32 cons_index; 335 struct mlx5_buf buf; 336 int size; 337 u8 irqn; 338 u8 eqn; 339 int nent; 340 u64 mask; 341 struct list_head list; 342 int index; 343 struct mlx5_rsc_debug *dbg; 344}; 345 346struct mlx5_core_psv { 347 u32 psv_idx; 348 struct psv_layout { 349 u32 pd; 350 u16 syndrome; 351 u16 reserved; 352 u16 bg; 353 u16 app_tag; 354 u32 ref_tag; 355 } psv; 356}; 357 358struct mlx5_core_sig_ctx { 359 struct mlx5_core_psv psv_memory; 360 struct mlx5_core_psv psv_wire; 361#if (__FreeBSD_version >= 1100000) 362 struct ib_sig_err err_item; 363#endif 364 bool sig_status_checked; 365 bool sig_err_exists; 366 u32 sigerr_count; 367}; 368 369struct mlx5_core_mr { 370 u64 iova; 371 u64 size; 372 u32 key; 373 u32 pd; 374}; 375 376enum mlx5_res_type { 377 MLX5_RES_QP, 378 MLX5_RES_SRQ, 379 MLX5_RES_XSRQ, 380}; 381 382struct mlx5_core_rsc_common { 383 enum mlx5_res_type res; 384 atomic_t refcount; 385 struct completion free; 386}; 387 388struct mlx5_core_srq { 389 struct mlx5_core_rsc_common common; /* must be first */ 390 u32 srqn; 391 int max; 392 int max_gs; 393 int max_avail_gather; 394 int wqe_shift; 395 void (*event)(struct mlx5_core_srq *, int); 396 atomic_t refcount; 397 struct completion free; 398}; 399 400struct mlx5_eq_table { 401 void __iomem *update_ci; 402 void __iomem *update_arm_ci; 403 struct list_head comp_eqs_list; 404 struct mlx5_eq pages_eq; 405 struct mlx5_eq async_eq; 406 struct mlx5_eq cmd_eq; 407 int num_comp_vectors; 408 /* protect EQs list 409 */ 410 spinlock_t lock; 411}; 412 413struct mlx5_uar { 414 u32 index; 415 struct list_head bf_list; 416 unsigned free_bf_bmap; 417 void __iomem *bf_map; 418 void __iomem *map; 419}; 420 421 422struct mlx5_core_health { 423 struct mlx5_health_buffer __iomem *health; 424 __be32 __iomem *health_counter; 425 struct timer_list timer; 426 struct list_head list; 427 u32 prev; 428 int miss_counter; 429}; 430 431#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 432 433struct mlx5_cq_linear_array_entry { 434 spinlock_t lock; 435 struct mlx5_core_cq * volatile cq; 436}; 437 438struct mlx5_cq_table { 439 /* protect radix tree 440 */ 441 spinlock_t lock; 442 struct radix_tree_root tree; 443 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 444}; 445 446struct mlx5_qp_table { 447 /* protect radix tree 448 */ 449 spinlock_t lock; 450 struct radix_tree_root tree; 451}; 452 453struct mlx5_srq_table { 454 /* protect radix tree 455 */ 456 spinlock_t lock; 457 struct radix_tree_root tree; 458}; 459 460struct mlx5_mr_table { 461 /* protect radix tree 462 */ 463 rwlock_t lock; 464 struct radix_tree_root tree; 465}; 466 467struct mlx5_irq_info { 468 char name[MLX5_MAX_IRQ_NAME]; 469}; 470 471struct mlx5_priv { 472 char name[MLX5_MAX_NAME_LEN]; 473 struct mlx5_eq_table eq_table; 474 struct msix_entry *msix_arr; 475 struct mlx5_irq_info *irq_info; 476 struct mlx5_uuar_info uuari; 477 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 478 479 struct io_mapping *bf_mapping; 480 481 /* pages stuff */ 482 struct workqueue_struct *pg_wq; 483 struct rb_root page_root; 484 int fw_pages; 485 int reg_pages; 486 struct list_head free_list; 487 488 struct mlx5_core_health health; 489 490 struct mlx5_srq_table srq_table; 491 492 /* start: qp staff */ 493 struct mlx5_qp_table qp_table; 494 struct dentry *qp_debugfs; 495 struct dentry *eq_debugfs; 496 struct dentry *cq_debugfs; 497 struct dentry *cmdif_debugfs; 498 /* end: qp staff */ 499 500 /* start: cq staff */ 501 struct mlx5_cq_table cq_table; 502 /* end: cq staff */ 503 504 /* start: mr staff */ 505 struct mlx5_mr_table mr_table; 506 /* end: mr staff */ 507 508 /* start: alloc staff */ 509 int numa_node; 510 511 struct mutex pgdir_mutex; 512 struct list_head pgdir_list; 513 /* end: alloc staff */ 514 struct dentry *dbg_root; 515 516 /* protect mkey key part */ 517 spinlock_t mkey_lock; 518 u8 mkey_key; 519 520 struct list_head dev_list; 521 struct list_head ctx_list; 522 spinlock_t ctx_lock; 523}; 524 525struct mlx5_special_contexts { 526 int resd_lkey; 527}; 528 529struct mlx5_core_dev { 530 struct pci_dev *pdev; 531 char board_id[MLX5_BOARD_ID_LEN]; 532 struct mlx5_cmd cmd; 533 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 534 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 535 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 536 struct mlx5_init_seg __iomem *iseg; 537 void (*event) (struct mlx5_core_dev *dev, 538 enum mlx5_dev_event event, 539 unsigned long param); 540 struct mlx5_priv priv; 541 struct mlx5_profile *profile; 542 atomic_t num_qps; 543 u32 issi; 544 struct mlx5_special_contexts special_contexts; 545}; 546 547enum { 548 MLX5_WOL_DISABLE = 0, 549 MLX5_WOL_SECURED_MAGIC = 1 << 1, 550 MLX5_WOL_MAGIC = 1 << 2, 551 MLX5_WOL_ARP = 1 << 3, 552 MLX5_WOL_BROADCAST = 1 << 4, 553 MLX5_WOL_MULTICAST = 1 << 5, 554 MLX5_WOL_UNICAST = 1 << 6, 555 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 556}; 557 558struct mlx5_db { 559 __be32 *db; 560 union { 561 struct mlx5_db_pgdir *pgdir; 562 struct mlx5_ib_user_db_page *user_page; 563 } u; 564 dma_addr_t dma; 565 int index; 566}; 567 568struct mlx5_net_counters { 569 u64 packets; 570 u64 octets; 571}; 572 573struct mlx5_ptys_reg { 574 u8 local_port; 575 u8 proto_mask; 576 u32 eth_proto_cap; 577 u16 ib_link_width_cap; 578 u16 ib_proto_cap; 579 u32 eth_proto_admin; 580 u16 ib_link_width_admin; 581 u16 ib_proto_admin; 582 u32 eth_proto_oper; 583 u16 ib_link_width_oper; 584 u16 ib_proto_oper; 585 u32 eth_proto_lp_advertise; 586}; 587 588struct mlx5_pvlc_reg { 589 u8 local_port; 590 u8 vl_hw_cap; 591 u8 vl_admin; 592 u8 vl_operational; 593}; 594 595struct mlx5_pmtu_reg { 596 u8 local_port; 597 u16 max_mtu; 598 u16 admin_mtu; 599 u16 oper_mtu; 600}; 601 602struct mlx5_vport_counters { 603 struct mlx5_net_counters received_errors; 604 struct mlx5_net_counters transmit_errors; 605 struct mlx5_net_counters received_ib_unicast; 606 struct mlx5_net_counters transmitted_ib_unicast; 607 struct mlx5_net_counters received_ib_multicast; 608 struct mlx5_net_counters transmitted_ib_multicast; 609 struct mlx5_net_counters received_eth_broadcast; 610 struct mlx5_net_counters transmitted_eth_broadcast; 611 struct mlx5_net_counters received_eth_unicast; 612 struct mlx5_net_counters transmitted_eth_unicast; 613 struct mlx5_net_counters received_eth_multicast; 614 struct mlx5_net_counters transmitted_eth_multicast; 615}; 616 617enum { 618 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 619}; 620 621enum { 622 MLX5_COMP_EQ_SIZE = 1024, 623}; 624 625enum { 626 MLX5_PTYS_IB = 1 << 0, 627 MLX5_PTYS_EN = 1 << 2, 628}; 629 630struct mlx5_db_pgdir { 631 struct list_head list; 632 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 633 __be32 *db_page; 634 dma_addr_t db_dma; 635}; 636 637typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 638 639struct mlx5_cmd_work_ent { 640 struct mlx5_cmd_msg *in; 641 struct mlx5_cmd_msg *out; 642 void *uout; 643 int uout_size; 644 mlx5_cmd_cbk_t callback; 645 void *context; 646 int idx; 647 struct completion done; 648 struct mlx5_cmd *cmd; 649 struct work_struct work; 650 struct mlx5_cmd_layout *lay; 651 int ret; 652 int page_queue; 653 u8 status; 654 u8 token; 655 u64 ts1; 656 u64 ts2; 657 u16 op; 658}; 659 660struct mlx5_pas { 661 u64 pa; 662 u8 log_sz; 663}; 664 665static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 666{ 667 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) 668 return buf->direct.buf + offset; 669 else 670 return buf->page_list[offset >> PAGE_SHIFT].buf + 671 (offset & (PAGE_SIZE - 1)); 672} 673 674 675extern struct workqueue_struct *mlx5_core_wq; 676 677#define STRUCT_FIELD(header, field) \ 678 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 679 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 680 681static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 682{ 683 return pci_get_drvdata(pdev); 684} 685 686extern struct dentry *mlx5_debugfs_root; 687 688static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 689{ 690 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 691} 692 693static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 694{ 695 return ioread32be(&dev->iseg->fw_rev) >> 16; 696} 697 698static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 699{ 700 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 701} 702 703static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 704{ 705 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 706} 707 708static inline int mlx5_get_gid_table_len(u16 param) 709{ 710 if (param > 4) { 711 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 712 return 0; 713 } 714 715 return 8 * (1 << param); 716} 717 718static inline void *mlx5_vzalloc(unsigned long size) 719{ 720 void *rtn; 721 722 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 723 return rtn; 724} 725 726static inline u32 mlx5_base_mkey(const u32 key) 727{ 728 return key & 0xffffff00u; 729} 730 731int mlx5_cmd_init(struct mlx5_core_dev *dev); 732void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 733void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 734void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 735int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 736int mlx5_cmd_status_to_err_v2(void *ptr); 737int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 738 enum mlx5_cap_mode cap_mode); 739int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 740 int out_size); 741int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 742 void *out, int out_size, mlx5_cmd_cbk_t callback, 743 void *context); 744int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 745int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 746int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 747int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 748int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 749void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 750void mlx5_health_cleanup(void); 751void __init mlx5_health_init(void); 752void mlx5_start_health_poll(struct mlx5_core_dev *dev); 753void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 754int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, int max_direct, 755 struct mlx5_buf *buf, int node); 756int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 757 struct mlx5_buf *buf); 758void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 759int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 760 struct mlx5_create_srq_mbox_in *in, int inlen, 761 int is_xrc); 762int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 763int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 764 struct mlx5_query_srq_mbox_out *out); 765int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 766int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 767 u16 lwm, int is_srq); 768void mlx5_init_mr_table(struct mlx5_core_dev *dev); 769void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 770int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 771 struct mlx5_create_mkey_mbox_in *in, int inlen, 772 mlx5_cmd_cbk_t callback, void *context, 773 struct mlx5_create_mkey_mbox_out *out); 774int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 775int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 776 struct mlx5_query_mkey_mbox_out *out, int outlen); 777int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 778 u32 *mkey); 779int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 780int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 781int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, 782 u16 opmod, u8 port); 783void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 784void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 785int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 786void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 787void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 788 s32 npages); 789int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 790int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 791void mlx5_register_debugfs(void); 792void mlx5_unregister_debugfs(void); 793int mlx5_eq_init(struct mlx5_core_dev *dev); 794void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 795void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 796void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 797void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 798void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 799struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 800void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); 801void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 802int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 803 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 804int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 805int mlx5_start_eqs(struct mlx5_core_dev *dev); 806int mlx5_stop_eqs(struct mlx5_core_dev *dev); 807int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 808int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 809int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 810 811int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 812void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 813int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 814 int size_in, void *data_out, int size_out, 815 u16 reg_num, int arg, int write); 816 817int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 818int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 819 int ptys_size, int proto_mask); 820int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 821 u32 *proto_cap, int proto_mask); 822int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 823 u32 *proto_admin, int proto_mask); 824int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 825 int proto_mask); 826int mlx5_set_port_status(struct mlx5_core_dev *dev, 827 enum mlx5_port_status status); 828int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 829int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port, 830 u32 rx_pause, u32 tx_pause); 831int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 832 u32 *rx_pause, u32 *tx_pause); 833 834int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 835int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 836int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 837 838int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 839int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 840 int device_addr, int size, int module_num, u32 *data, 841 int *size_read); 842 843int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 844void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 845int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 846 struct mlx5_query_eq_mbox_out *out, int outlen); 847int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 848void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 849int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 850void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 851int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 852int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 853 int node); 854void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 855 856const char *mlx5_command_str(int command); 857int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 858void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 859int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 860 int npsvs, u32 *sig_index); 861int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 862void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 863u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 864int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 865int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 866int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 867 struct mlx5_pvlc_reg *pvlc, int write); 868int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 869 struct mlx5_ptys_reg *ptys, int write); 870int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 871 struct mlx5_pmtu_reg *pmtu, int write); 872int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 873int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 874int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 875 int priority, int *is_enable); 876int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 877 int priority, int enable); 878int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 879 void *out, int out_size); 880int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 881 void *in, int in_size); 882int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 883 void *out, int out_size); 884static inline u32 mlx5_mkey_to_idx(u32 mkey) 885{ 886 return mkey >> 8; 887} 888 889static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 890{ 891 return mkey_idx << 8; 892} 893 894static inline u8 mlx5_mkey_variant(u32 mkey) 895{ 896 return mkey & 0xff; 897} 898 899enum { 900 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 901 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 902}; 903 904enum { 905 MAX_MR_CACHE_ENTRIES = 16, 906}; 907 908enum { 909 MLX5_INTERFACE_PROTOCOL_IB = 0, 910 MLX5_INTERFACE_PROTOCOL_ETH = 1, 911}; 912 913struct mlx5_interface { 914 void * (*add)(struct mlx5_core_dev *dev); 915 void (*remove)(struct mlx5_core_dev *dev, void *context); 916 void (*event)(struct mlx5_core_dev *dev, void *context, 917 enum mlx5_dev_event event, unsigned long param); 918 void * (*get_dev)(void *context); 919 int protocol; 920 struct list_head list; 921}; 922 923void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 924int mlx5_register_interface(struct mlx5_interface *intf); 925void mlx5_unregister_interface(struct mlx5_interface *intf); 926 927struct mlx5_profile { 928 u64 mask; 929 u8 log_max_qp; 930 struct { 931 int size; 932 int limit; 933 } mr_cache[MAX_MR_CACHE_ENTRIES]; 934}; 935 936 937#define MLX5_EEPROM_MAX_BYTES 32 938#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 939#define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 940#define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 941#endif /* MLX5_DRIVER_H */ 942