1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: releng/10.3/sys/dev/ixgbe/ixgbe_vf.c 295524 2016-02-11 16:16:10Z sbruno $*/ 34 35 36#include "ixgbe_api.h" 37#include "ixgbe_type.h" 38#include "ixgbe_vf.h" 39 40#ifndef IXGBE_VFWRITE_REG 41#define IXGBE_VFWRITE_REG IXGBE_WRITE_REG 42#endif 43#ifndef IXGBE_VFREAD_REG 44#define IXGBE_VFREAD_REG IXGBE_READ_REG 45#endif 46 47/** 48 * ixgbe_init_ops_vf - Initialize the pointers for vf 49 * @hw: pointer to hardware structure 50 * 51 * This will assign function pointers, adapter-specific functions can 52 * override the assignment of generic function pointers by assigning 53 * their own adapter-specific function pointers. 54 * Does not touch the hardware. 55 **/ 56s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw) 57{ 58 /* MAC */ 59 hw->mac.ops.init_hw = ixgbe_init_hw_vf; 60 hw->mac.ops.reset_hw = ixgbe_reset_hw_vf; 61 hw->mac.ops.start_hw = ixgbe_start_hw_vf; 62 /* Cannot clear stats on VF */ 63 hw->mac.ops.clear_hw_cntrs = NULL; 64 hw->mac.ops.get_media_type = NULL; 65 hw->mac.ops.get_mac_addr = ixgbe_get_mac_addr_vf; 66 hw->mac.ops.stop_adapter = ixgbe_stop_adapter_vf; 67 hw->mac.ops.get_bus_info = NULL; 68 69 /* Link */ 70 hw->mac.ops.setup_link = ixgbe_setup_mac_link_vf; 71 hw->mac.ops.check_link = ixgbe_check_mac_link_vf; 72 hw->mac.ops.get_link_capabilities = NULL; 73 74 /* RAR, Multicast, VLAN */ 75 hw->mac.ops.set_rar = ixgbe_set_rar_vf; 76 hw->mac.ops.set_uc_addr = ixgbevf_set_uc_addr_vf; 77 hw->mac.ops.init_rx_addrs = NULL; 78 hw->mac.ops.update_mc_addr_list = ixgbe_update_mc_addr_list_vf; 79 hw->mac.ops.enable_mc = NULL; 80 hw->mac.ops.disable_mc = NULL; 81 hw->mac.ops.clear_vfta = NULL; 82 hw->mac.ops.set_vfta = ixgbe_set_vfta_vf; 83 84 hw->mac.max_tx_queues = 1; 85 hw->mac.max_rx_queues = 1; 86 87 hw->mbx.ops.init_params = ixgbe_init_mbx_params_vf; 88 89 return IXGBE_SUCCESS; 90} 91 92/* ixgbe_virt_clr_reg - Set register to default (power on) state. 93 * @hw: pointer to hardware structure 94 */ 95static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw) 96{ 97 int i; 98 u32 vfsrrctl; 99 u32 vfdca_rxctrl; 100 u32 vfdca_txctrl; 101 102 /* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */ 103 vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 104 vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 105 106 /* DCA_RXCTRL default value */ 107 vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN | 108 IXGBE_DCA_RXCTRL_DATA_WRO_EN | 109 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 110 111 /* DCA_TXCTRL default value */ 112 vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN | 113 IXGBE_DCA_TXCTRL_DESC_WRO_EN | 114 IXGBE_DCA_TXCTRL_DATA_RRO_EN; 115 116 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); 117 118 for (i = 0; i < 7; i++) { 119 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0); 120 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0); 121 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0); 122 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl); 123 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0); 124 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0); 125 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0); 126 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0); 127 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0); 128 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl); 129 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl); 130 } 131 132 IXGBE_WRITE_FLUSH(hw); 133} 134 135/** 136 * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx 137 * @hw: pointer to hardware structure 138 * 139 * Starts the hardware by filling the bus info structure and media type, clears 140 * all on chip counters, initializes receive address registers, multicast 141 * table, VLAN filter table, calls routine to set up link and flow control 142 * settings, and leaves transmit and receive units disabled and uninitialized 143 **/ 144s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw) 145{ 146 /* Clear adapter stopped flag */ 147 hw->adapter_stopped = FALSE; 148 149 return IXGBE_SUCCESS; 150} 151 152/** 153 * ixgbe_init_hw_vf - virtual function hardware initialization 154 * @hw: pointer to hardware structure 155 * 156 * Initialize the hardware by resetting the hardware and then starting 157 * the hardware 158 **/ 159s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw) 160{ 161 s32 status = hw->mac.ops.start_hw(hw); 162 163 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 164 165 return status; 166} 167 168/** 169 * ixgbe_reset_hw_vf - Performs hardware reset 170 * @hw: pointer to hardware structure 171 * 172 * Resets the hardware by reseting the transmit and receive units, masks and 173 * clears all interrupts. 174 **/ 175s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw) 176{ 177 struct ixgbe_mbx_info *mbx = &hw->mbx; 178 u32 timeout = IXGBE_VF_INIT_TIMEOUT; 179 s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR; 180 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN]; 181 u8 *addr = (u8 *)(&msgbuf[1]); 182 183 DEBUGFUNC("ixgbevf_reset_hw_vf"); 184 185 /* Call adapter stop to disable tx/rx and clear interrupts */ 186 hw->mac.ops.stop_adapter(hw); 187 188 /* reset the api version */ 189 hw->api_version = ixgbe_mbox_api_10; 190 191 DEBUGOUT("Issuing a function level reset to MAC\n"); 192 193 IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST); 194 IXGBE_WRITE_FLUSH(hw); 195 196 msec_delay(50); 197 198 /* we cannot reset while the RSTI / RSTD bits are asserted */ 199 while (!mbx->ops.check_for_rst(hw, 0) && timeout) { 200 timeout--; 201 usec_delay(5); 202 } 203 204 if (!timeout) 205 return IXGBE_ERR_RESET_FAILED; 206 207 /* Reset VF registers to initial values */ 208 ixgbe_virt_clr_reg(hw); 209 210 /* mailbox timeout can now become active */ 211 mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT; 212 213 msgbuf[0] = IXGBE_VF_RESET; 214 mbx->ops.write_posted(hw, msgbuf, 1, 0); 215 216 msec_delay(10); 217 218 /* 219 * set our "perm_addr" based on info provided by PF 220 * also set up the mc_filter_type which is piggy backed 221 * on the mac address in word 3 222 */ 223 ret_val = mbx->ops.read_posted(hw, msgbuf, 224 IXGBE_VF_PERMADDR_MSG_LEN, 0); 225 if (ret_val) 226 return ret_val; 227 228 if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) && 229 msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK)) 230 return IXGBE_ERR_INVALID_MAC_ADDR; 231 232 memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 233 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD]; 234 235 return ret_val; 236} 237 238/** 239 * ixgbe_stop_adapter_vf - Generic stop Tx/Rx units 240 * @hw: pointer to hardware structure 241 * 242 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 243 * disables transmit and receive units. The adapter_stopped flag is used by 244 * the shared code and drivers to determine if the adapter is in a stopped 245 * state and should not touch the hardware. 246 **/ 247s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw) 248{ 249 u32 reg_val; 250 u16 i; 251 252 /* 253 * Set the adapter_stopped flag so other driver functions stop touching 254 * the hardware 255 */ 256 hw->adapter_stopped = TRUE; 257 258 /* Clear interrupt mask to stop from interrupts being generated */ 259 IXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 260 261 /* Clear any pending interrupts, flush previous writes */ 262 IXGBE_VFREAD_REG(hw, IXGBE_VTEICR); 263 264 /* Disable the transmit unit. Each queue must be disabled. */ 265 for (i = 0; i < hw->mac.max_tx_queues; i++) 266 IXGBE_VFWRITE_REG(hw, IXGBE_VFTXDCTL(i), IXGBE_TXDCTL_SWFLSH); 267 268 /* Disable the receive unit by stopping each queue */ 269 for (i = 0; i < hw->mac.max_rx_queues; i++) { 270 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i)); 271 reg_val &= ~IXGBE_RXDCTL_ENABLE; 272 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); 273 } 274 /* Clear packet split and pool config */ 275 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); 276 277 /* flush all queues disables */ 278 IXGBE_WRITE_FLUSH(hw); 279 msec_delay(2); 280 281 return IXGBE_SUCCESS; 282} 283 284/** 285 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 286 * @hw: pointer to hardware structure 287 * @mc_addr: the multicast address 288 * 289 * Extracts the 12 bits, from a multicast address, to determine which 290 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 291 * incoming rx multicast addresses, to determine the bit-vector to check in 292 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 293 * by the MO field of the MCSTCTRL. The MO field is set during initialization 294 * to mc_filter_type. 295 **/ 296static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 297{ 298 u32 vector = 0; 299 300 switch (hw->mac.mc_filter_type) { 301 case 0: /* use bits [47:36] of the address */ 302 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 303 break; 304 case 1: /* use bits [46:35] of the address */ 305 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 306 break; 307 case 2: /* use bits [45:34] of the address */ 308 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 309 break; 310 case 3: /* use bits [43:32] of the address */ 311 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 312 break; 313 default: /* Invalid mc_filter_type */ 314 DEBUGOUT("MC filter type param set incorrectly\n"); 315 ASSERT(0); 316 break; 317 } 318 319 /* vector can only be 12-bits or boundary will be exceeded */ 320 vector &= 0xFFF; 321 return vector; 322} 323 324static void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, 325 u32 *msg, u16 size) 326{ 327 struct ixgbe_mbx_info *mbx = &hw->mbx; 328 u32 retmsg[IXGBE_VFMAILBOX_SIZE]; 329 s32 retval = mbx->ops.write_posted(hw, msg, size, 0); 330 331 if (!retval) 332 mbx->ops.read_posted(hw, retmsg, size, 0); 333} 334 335/** 336 * ixgbe_set_rar_vf - set device MAC address 337 * @hw: pointer to hardware structure 338 * @index: Receive address register to write 339 * @addr: Address to put into receive address register 340 * @vmdq: VMDq "set" or "pool" index 341 * @enable_addr: set flag that address is active 342 **/ 343s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 344 u32 enable_addr) 345{ 346 struct ixgbe_mbx_info *mbx = &hw->mbx; 347 u32 msgbuf[3]; 348 u8 *msg_addr = (u8 *)(&msgbuf[1]); 349 s32 ret_val; 350 UNREFERENCED_3PARAMETER(vmdq, enable_addr, index); 351 352 memset(msgbuf, 0, 12); 353 msgbuf[0] = IXGBE_VF_SET_MAC_ADDR; 354 memcpy(msg_addr, addr, 6); 355 ret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0); 356 357 if (!ret_val) 358 ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0); 359 360 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; 361 362 /* if nacked the address was rejected, use "perm_addr" */ 363 if (!ret_val && 364 (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK))) 365 ixgbe_get_mac_addr_vf(hw, hw->mac.addr); 366 367 return ret_val; 368} 369 370/** 371 * ixgbe_update_mc_addr_list_vf - Update Multicast addresses 372 * @hw: pointer to the HW structure 373 * @mc_addr_list: array of multicast addresses to program 374 * @mc_addr_count: number of multicast addresses to program 375 * @next: caller supplied function to return next address in list 376 * 377 * Updates the Multicast Table Array. 378 **/ 379s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list, 380 u32 mc_addr_count, ixgbe_mc_addr_itr next, 381 bool clear) 382{ 383 struct ixgbe_mbx_info *mbx = &hw->mbx; 384 u32 msgbuf[IXGBE_VFMAILBOX_SIZE]; 385 u16 *vector_list = (u16 *)&msgbuf[1]; 386 u32 vector; 387 u32 cnt, i; 388 u32 vmdq; 389 390 UNREFERENCED_1PARAMETER(clear); 391 392 DEBUGFUNC("ixgbe_update_mc_addr_list_vf"); 393 394 /* Each entry in the list uses 1 16 bit word. We have 30 395 * 16 bit words available in our HW msg buffer (minus 1 for the 396 * msg type). That's 30 hash values if we pack 'em right. If 397 * there are more than 30 MC addresses to add then punt the 398 * extras for now and then add code to handle more than 30 later. 399 * It would be unusual for a server to request that many multi-cast 400 * addresses except for in large enterprise network environments. 401 */ 402 403 DEBUGOUT1("MC Addr Count = %d\n", mc_addr_count); 404 405 cnt = (mc_addr_count > 30) ? 30 : mc_addr_count; 406 msgbuf[0] = IXGBE_VF_SET_MULTICAST; 407 msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT; 408 409 for (i = 0; i < cnt; i++) { 410 vector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq)); 411 DEBUGOUT1("Hash value = 0x%03X\n", vector); 412 vector_list[i] = (u16)vector; 413 } 414 415 return mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE, 0); 416} 417 418/** 419 * ixgbe_set_vfta_vf - Set/Unset vlan filter table address 420 * @hw: pointer to the HW structure 421 * @vlan: 12 bit VLAN ID 422 * @vind: unused by VF drivers 423 * @vlan_on: if TRUE then set bit, else clear bit 424 **/ 425s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 426{ 427 struct ixgbe_mbx_info *mbx = &hw->mbx; 428 u32 msgbuf[2]; 429 s32 ret_val; 430 UNREFERENCED_1PARAMETER(vind); 431 432 msgbuf[0] = IXGBE_VF_SET_VLAN; 433 msgbuf[1] = vlan; 434 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */ 435 msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT; 436 437 ret_val = mbx->ops.write_posted(hw, msgbuf, 2, 0); 438 if (!ret_val) 439 ret_val = mbx->ops.read_posted(hw, msgbuf, 1, 0); 440 441 if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK)) 442 return IXGBE_SUCCESS; 443 444 return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK); 445} 446 447/** 448 * ixgbe_get_num_of_tx_queues_vf - Get number of TX queues 449 * @hw: pointer to hardware structure 450 * 451 * Returns the number of transmit queues for the given adapter. 452 **/ 453u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw) 454{ 455 UNREFERENCED_1PARAMETER(hw); 456 return IXGBE_VF_MAX_TX_QUEUES; 457} 458 459/** 460 * ixgbe_get_num_of_rx_queues_vf - Get number of RX queues 461 * @hw: pointer to hardware structure 462 * 463 * Returns the number of receive queues for the given adapter. 464 **/ 465u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw) 466{ 467 UNREFERENCED_1PARAMETER(hw); 468 return IXGBE_VF_MAX_RX_QUEUES; 469} 470 471/** 472 * ixgbe_get_mac_addr_vf - Read device MAC address 473 * @hw: pointer to the HW structure 474 **/ 475s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr) 476{ 477 int i; 478 479 for (i = 0; i < IXGBE_ETH_LENGTH_OF_ADDRESS; i++) 480 mac_addr[i] = hw->mac.perm_addr[i]; 481 482 return IXGBE_SUCCESS; 483} 484 485s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr) 486{ 487 struct ixgbe_mbx_info *mbx = &hw->mbx; 488 u32 msgbuf[3]; 489 u8 *msg_addr = (u8 *)(&msgbuf[1]); 490 s32 ret_val; 491 492 memset(msgbuf, 0, sizeof(msgbuf)); 493 /* 494 * If index is one then this is the start of a new list and needs 495 * indication to the PF so it can do it's own list management. 496 * If it is zero then that tells the PF to just clear all of 497 * this VF's macvlans and there is no new list. 498 */ 499 msgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT; 500 msgbuf[0] |= IXGBE_VF_SET_MACVLAN; 501 if (addr) 502 memcpy(msg_addr, addr, 6); 503 ret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0); 504 505 if (!ret_val) 506 ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0); 507 508 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; 509 510 if (!ret_val) 511 if (msgbuf[0] == (IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK)) 512 ret_val = IXGBE_ERR_OUT_OF_MEM; 513 514 return ret_val; 515} 516 517/** 518 * ixgbe_setup_mac_link_vf - Setup MAC link settings 519 * @hw: pointer to hardware structure 520 * @speed: new link speed 521 * @autoneg: TRUE if autonegotiation enabled 522 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 523 * 524 * Set the link speed in the AUTOC register and restarts link. 525 **/ 526s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed, 527 bool autoneg_wait_to_complete) 528{ 529 UNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete); 530 return IXGBE_SUCCESS; 531} 532 533/** 534 * ixgbe_check_mac_link_vf - Get link/speed status 535 * @hw: pointer to hardware structure 536 * @speed: pointer to link speed 537 * @link_up: TRUE is link is up, FALSE otherwise 538 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 539 * 540 * Reads the links register to determine if link is up and the current speed 541 **/ 542s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 543 bool *link_up, bool autoneg_wait_to_complete) 544{ 545 struct ixgbe_mbx_info *mbx = &hw->mbx; 546 struct ixgbe_mac_info *mac = &hw->mac; 547 s32 ret_val = IXGBE_SUCCESS; 548 u32 links_reg; 549 u32 in_msg = 0; 550 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 551 552 /* If we were hit with a reset drop the link */ 553 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 554 mac->get_link_status = TRUE; 555 556 if (!mac->get_link_status) 557 goto out; 558 559 /* if link status is down no point in checking to see if pf is up */ 560 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 561 if (!(links_reg & IXGBE_LINKS_UP)) 562 goto out; 563 564 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 565 * before the link status is correct 566 */ 567 if (mac->type == ixgbe_mac_82599_vf) { 568 int i; 569 570 for (i = 0; i < 5; i++) { 571 usec_delay(100); 572 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 573 574 if (!(links_reg & IXGBE_LINKS_UP)) 575 goto out; 576 } 577 } 578 579 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 580 case IXGBE_LINKS_SPEED_10G_82599: 581 *speed = IXGBE_LINK_SPEED_10GB_FULL; 582 break; 583 case IXGBE_LINKS_SPEED_1G_82599: 584 *speed = IXGBE_LINK_SPEED_1GB_FULL; 585 break; 586 case IXGBE_LINKS_SPEED_100_82599: 587 *speed = IXGBE_LINK_SPEED_100_FULL; 588 break; 589 } 590 591 /* if the read failed it could just be a mailbox collision, best wait 592 * until we are called again and don't report an error 593 */ 594 if (mbx->ops.read(hw, &in_msg, 1, 0)) 595 goto out; 596 597 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 598 /* msg is not CTS and is NACK we must have lost CTS status */ 599 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 600 ret_val = -1; 601 goto out; 602 } 603 604 /* the pf is talking, if we timed out in the past we reinit */ 605 if (!mbx->timeout) { 606 ret_val = -1; 607 goto out; 608 } 609 610 /* if we passed all the tests above then the link is up and we no 611 * longer need to check for link 612 */ 613 mac->get_link_status = FALSE; 614 615out: 616 *link_up = !mac->get_link_status; 617 return ret_val; 618} 619 620/** 621 * ixgbevf_rlpml_set_vf - Set the maximum receive packet length 622 * @hw: pointer to the HW structure 623 * @max_size: value to assign to max frame size 624 **/ 625void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size) 626{ 627 u32 msgbuf[2]; 628 629 msgbuf[0] = IXGBE_VF_SET_LPE; 630 msgbuf[1] = max_size; 631 ixgbevf_write_msg_read_ack(hw, msgbuf, 2); 632} 633 634/** 635 * ixgbevf_negotiate_api_version - Negotiate supported API version 636 * @hw: pointer to the HW structure 637 * @api: integer containing requested API version 638 **/ 639int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api) 640{ 641 int err; 642 u32 msg[3]; 643 644 /* Negotiate the mailbox API version */ 645 msg[0] = IXGBE_VF_API_NEGOTIATE; 646 msg[1] = api; 647 msg[2] = 0; 648 err = hw->mbx.ops.write_posted(hw, msg, 3, 0); 649 650 if (!err) 651 err = hw->mbx.ops.read_posted(hw, msg, 3, 0); 652 653 if (!err) { 654 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS; 655 656 /* Store value and return 0 on success */ 657 if (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) { 658 hw->api_version = api; 659 return 0; 660 } 661 662 err = IXGBE_ERR_INVALID_ARGUMENT; 663 } 664 665 return err; 666} 667 668int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, 669 unsigned int *default_tc) 670{ 671 int err; 672 u32 msg[5]; 673 674 /* do nothing if API doesn't support ixgbevf_get_queues */ 675 switch (hw->api_version) { 676 case ixgbe_mbox_api_11: 677 break; 678 default: 679 return 0; 680 } 681 682 /* Fetch queue configuration from the PF */ 683 msg[0] = IXGBE_VF_GET_QUEUES; 684 msg[1] = msg[2] = msg[3] = msg[4] = 0; 685 err = hw->mbx.ops.write_posted(hw, msg, 5, 0); 686 687 if (!err) 688 err = hw->mbx.ops.read_posted(hw, msg, 5, 0); 689 690 if (!err) { 691 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS; 692 693 /* 694 * if we we didn't get an ACK there must have been 695 * some sort of mailbox error so we should treat it 696 * as such 697 */ 698 if (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK)) 699 return IXGBE_ERR_MBX; 700 701 /* record and validate values from message */ 702 hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES]; 703 if (hw->mac.max_tx_queues == 0 || 704 hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES) 705 hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES; 706 707 hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES]; 708 if (hw->mac.max_rx_queues == 0 || 709 hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES) 710 hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES; 711 712 *num_tcs = msg[IXGBE_VF_TRANS_VLAN]; 713 /* in case of unknown state assume we cannot tag frames */ 714 if (*num_tcs > hw->mac.max_rx_queues) 715 *num_tcs = 1; 716 717 *default_tc = msg[IXGBE_VF_DEF_QUEUE]; 718 /* default to queue 0 on out-of-bounds queue number */ 719 if (*default_tc >= hw->mac.max_tx_queues) 720 *default_tc = 0; 721 } 722 723 return err; 724} 725