1/* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/radeon/si.c 282199 2015-04-28 19:35:05Z dumbbell $"); 27 28#include <dev/drm2/drmP.h> 29#include "radeon.h" 30#include "radeon_asic.h" 31#include <dev/drm2/radeon/radeon_drm.h> 32#include "sid.h" 33#include "atom.h" 34#include "si_blit_shaders.h" 35 36#define SI_PFP_UCODE_SIZE 2144 37#define SI_PM4_UCODE_SIZE 2144 38#define SI_CE_UCODE_SIZE 2144 39#define SI_RLC_UCODE_SIZE 2048 40#define SI_MC_UCODE_SIZE 7769 41 42#ifdef __linux__ 43MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); 44MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 45MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 46MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 47MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 48MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 49MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 50MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 51MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 52MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 53MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 54MODULE_FIRMWARE("radeon/VERDE_me.bin"); 55MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 56MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 57MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 58#endif 59 60#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */ 61extern int r600_ih_ring_alloc(struct radeon_device *rdev); 62extern void r600_ih_ring_fini(struct radeon_device *rdev); 63extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 64extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 65extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 66extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 67#endif 68 69/* get temperature in millidegrees */ 70int si_get_temp(struct radeon_device *rdev) 71{ 72 u32 temp; 73 int actual_temp = 0; 74 75 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 76 CTF_TEMP_SHIFT; 77 78 if (temp & 0x200) 79 actual_temp = 255; 80 else 81 actual_temp = temp & 0x1ff; 82 83 actual_temp = (actual_temp * 1000); 84 85 return actual_temp; 86} 87 88#define TAHITI_IO_MC_REGS_SIZE 36 89 90static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 91 {0x0000006f, 0x03044000}, 92 {0x00000070, 0x0480c018}, 93 {0x00000071, 0x00000040}, 94 {0x00000072, 0x01000000}, 95 {0x00000074, 0x000000ff}, 96 {0x00000075, 0x00143400}, 97 {0x00000076, 0x08ec0800}, 98 {0x00000077, 0x040000cc}, 99 {0x00000079, 0x00000000}, 100 {0x0000007a, 0x21000409}, 101 {0x0000007c, 0x00000000}, 102 {0x0000007d, 0xe8000000}, 103 {0x0000007e, 0x044408a8}, 104 {0x0000007f, 0x00000003}, 105 {0x00000080, 0x00000000}, 106 {0x00000081, 0x01000000}, 107 {0x00000082, 0x02000000}, 108 {0x00000083, 0x00000000}, 109 {0x00000084, 0xe3f3e4f4}, 110 {0x00000085, 0x00052024}, 111 {0x00000087, 0x00000000}, 112 {0x00000088, 0x66036603}, 113 {0x00000089, 0x01000000}, 114 {0x0000008b, 0x1c0a0000}, 115 {0x0000008c, 0xff010000}, 116 {0x0000008e, 0xffffefff}, 117 {0x0000008f, 0xfff3efff}, 118 {0x00000090, 0xfff3efbf}, 119 {0x00000094, 0x00101101}, 120 {0x00000095, 0x00000fff}, 121 {0x00000096, 0x00116fff}, 122 {0x00000097, 0x60010000}, 123 {0x00000098, 0x10010000}, 124 {0x00000099, 0x00006000}, 125 {0x0000009a, 0x00001000}, 126 {0x0000009f, 0x00a77400} 127}; 128 129static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 130 {0x0000006f, 0x03044000}, 131 {0x00000070, 0x0480c018}, 132 {0x00000071, 0x00000040}, 133 {0x00000072, 0x01000000}, 134 {0x00000074, 0x000000ff}, 135 {0x00000075, 0x00143400}, 136 {0x00000076, 0x08ec0800}, 137 {0x00000077, 0x040000cc}, 138 {0x00000079, 0x00000000}, 139 {0x0000007a, 0x21000409}, 140 {0x0000007c, 0x00000000}, 141 {0x0000007d, 0xe8000000}, 142 {0x0000007e, 0x044408a8}, 143 {0x0000007f, 0x00000003}, 144 {0x00000080, 0x00000000}, 145 {0x00000081, 0x01000000}, 146 {0x00000082, 0x02000000}, 147 {0x00000083, 0x00000000}, 148 {0x00000084, 0xe3f3e4f4}, 149 {0x00000085, 0x00052024}, 150 {0x00000087, 0x00000000}, 151 {0x00000088, 0x66036603}, 152 {0x00000089, 0x01000000}, 153 {0x0000008b, 0x1c0a0000}, 154 {0x0000008c, 0xff010000}, 155 {0x0000008e, 0xffffefff}, 156 {0x0000008f, 0xfff3efff}, 157 {0x00000090, 0xfff3efbf}, 158 {0x00000094, 0x00101101}, 159 {0x00000095, 0x00000fff}, 160 {0x00000096, 0x00116fff}, 161 {0x00000097, 0x60010000}, 162 {0x00000098, 0x10010000}, 163 {0x00000099, 0x00006000}, 164 {0x0000009a, 0x00001000}, 165 {0x0000009f, 0x00a47400} 166}; 167 168static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 169 {0x0000006f, 0x03044000}, 170 {0x00000070, 0x0480c018}, 171 {0x00000071, 0x00000040}, 172 {0x00000072, 0x01000000}, 173 {0x00000074, 0x000000ff}, 174 {0x00000075, 0x00143400}, 175 {0x00000076, 0x08ec0800}, 176 {0x00000077, 0x040000cc}, 177 {0x00000079, 0x00000000}, 178 {0x0000007a, 0x21000409}, 179 {0x0000007c, 0x00000000}, 180 {0x0000007d, 0xe8000000}, 181 {0x0000007e, 0x044408a8}, 182 {0x0000007f, 0x00000003}, 183 {0x00000080, 0x00000000}, 184 {0x00000081, 0x01000000}, 185 {0x00000082, 0x02000000}, 186 {0x00000083, 0x00000000}, 187 {0x00000084, 0xe3f3e4f4}, 188 {0x00000085, 0x00052024}, 189 {0x00000087, 0x00000000}, 190 {0x00000088, 0x66036603}, 191 {0x00000089, 0x01000000}, 192 {0x0000008b, 0x1c0a0000}, 193 {0x0000008c, 0xff010000}, 194 {0x0000008e, 0xffffefff}, 195 {0x0000008f, 0xfff3efff}, 196 {0x00000090, 0xfff3efbf}, 197 {0x00000094, 0x00101101}, 198 {0x00000095, 0x00000fff}, 199 {0x00000096, 0x00116fff}, 200 {0x00000097, 0x60010000}, 201 {0x00000098, 0x10010000}, 202 {0x00000099, 0x00006000}, 203 {0x0000009a, 0x00001000}, 204 {0x0000009f, 0x00a37400} 205}; 206 207/* ucode loading */ 208static int si_mc_load_microcode(struct radeon_device *rdev) 209{ 210 const __be32 *fw_data; 211 u32 running, blackout = 0; 212 const u32 *io_mc_regs; 213 int i, ucode_size, regs_size; 214 215 if (!rdev->mc_fw) 216 return -EINVAL; 217 218 switch (rdev->family) { 219 case CHIP_TAHITI: 220 io_mc_regs = &tahiti_io_mc_regs[0][0]; 221 ucode_size = SI_MC_UCODE_SIZE; 222 regs_size = TAHITI_IO_MC_REGS_SIZE; 223 break; 224 case CHIP_PITCAIRN: 225 io_mc_regs = &pitcairn_io_mc_regs[0][0]; 226 ucode_size = SI_MC_UCODE_SIZE; 227 regs_size = TAHITI_IO_MC_REGS_SIZE; 228 break; 229 case CHIP_VERDE: 230 default: 231 io_mc_regs = &verde_io_mc_regs[0][0]; 232 ucode_size = SI_MC_UCODE_SIZE; 233 regs_size = TAHITI_IO_MC_REGS_SIZE; 234 break; 235 } 236 237 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 238 239 if (running == 0) { 240 if (running) { 241 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 242 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 243 } 244 245 /* reset the engine and set to writable */ 246 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 247 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 248 249 /* load mc io regs */ 250 for (i = 0; i < regs_size; i++) { 251 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 252 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 253 } 254 /* load the MC ucode */ 255 fw_data = (const __be32 *)rdev->mc_fw->data; 256 for (i = 0; i < ucode_size; i++) 257 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 258 259 /* put the engine back into the active state */ 260 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 261 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 262 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 263 264 /* wait for training to complete */ 265 for (i = 0; i < rdev->usec_timeout; i++) { 266 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 267 break; 268 udelay(1); 269 } 270 for (i = 0; i < rdev->usec_timeout; i++) { 271 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 272 break; 273 udelay(1); 274 } 275 276 if (running) 277 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 278 } 279 280 return 0; 281} 282 283static int si_init_microcode(struct radeon_device *rdev) 284{ 285 const char *chip_name; 286 const char *rlc_chip_name; 287 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 288 char fw_name[30]; 289 int err; 290 291 DRM_DEBUG("\n"); 292 293 switch (rdev->family) { 294 case CHIP_TAHITI: 295 chip_name = "TAHITI"; 296 rlc_chip_name = "TAHITI"; 297 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 298 me_req_size = SI_PM4_UCODE_SIZE * 4; 299 ce_req_size = SI_CE_UCODE_SIZE * 4; 300 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 301 mc_req_size = SI_MC_UCODE_SIZE * 4; 302 break; 303 case CHIP_PITCAIRN: 304 chip_name = "PITCAIRN"; 305 rlc_chip_name = "PITCAIRN"; 306 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 307 me_req_size = SI_PM4_UCODE_SIZE * 4; 308 ce_req_size = SI_CE_UCODE_SIZE * 4; 309 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 310 mc_req_size = SI_MC_UCODE_SIZE * 4; 311 break; 312 case CHIP_VERDE: 313 chip_name = "VERDE"; 314 rlc_chip_name = "VERDE"; 315 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 316 me_req_size = SI_PM4_UCODE_SIZE * 4; 317 ce_req_size = SI_CE_UCODE_SIZE * 4; 318 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 319 mc_req_size = SI_MC_UCODE_SIZE * 4; 320 break; 321 default: panic("%s: Unsupported family %d", __func__, rdev->family); 322 } 323 324 DRM_INFO("Loading %s Microcode\n", chip_name); 325 err = 0; 326 327 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 328 rdev->pfp_fw = firmware_get(fw_name); 329 if (rdev->pfp_fw == NULL) { 330 err = -ENOENT; 331 goto out; 332 } 333 if (rdev->pfp_fw->datasize != pfp_req_size) { 334 DRM_ERROR( 335 "si_cp: Bogus length %zu in firmware \"%s\"\n", 336 rdev->pfp_fw->datasize, fw_name); 337 err = -EINVAL; 338 goto out; 339 } 340 341 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 342 rdev->me_fw = firmware_get(fw_name); 343 if (rdev->me_fw == NULL) { 344 err = -ENOENT; 345 goto out; 346 } 347 if (rdev->me_fw->datasize != me_req_size) { 348 DRM_ERROR( 349 "si_cp: Bogus length %zu in firmware \"%s\"\n", 350 rdev->me_fw->datasize, fw_name); 351 err = -EINVAL; 352 } 353 354 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", chip_name); 355 rdev->ce_fw = firmware_get(fw_name); 356 if (rdev->ce_fw == NULL) { 357 err = -ENOENT; 358 goto out; 359 } 360 if (rdev->ce_fw->datasize != ce_req_size) { 361 DRM_ERROR( 362 "si_cp: Bogus length %zu in firmware \"%s\"\n", 363 rdev->ce_fw->datasize, fw_name); 364 err = -EINVAL; 365 } 366 367 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", rlc_chip_name); 368 rdev->rlc_fw = firmware_get(fw_name); 369 if (rdev->rlc_fw == NULL) { 370 err = -ENOENT; 371 goto out; 372 } 373 if (rdev->rlc_fw->datasize != rlc_req_size) { 374 DRM_ERROR( 375 "si_rlc: Bogus length %zu in firmware \"%s\"\n", 376 rdev->rlc_fw->datasize, fw_name); 377 err = -EINVAL; 378 } 379 380 snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name); 381 rdev->mc_fw = firmware_get(fw_name); 382 if (rdev->mc_fw == NULL) { 383 err = -ENOENT; 384 goto out; 385 } 386 if (rdev->mc_fw->datasize != mc_req_size) { 387 DRM_ERROR( 388 "si_mc: Bogus length %zu in firmware \"%s\"\n", 389 rdev->mc_fw->datasize, fw_name); 390 err = -EINVAL; 391 } 392 393out: 394 if (err) { 395 if (err != -EINVAL) 396 DRM_ERROR( 397 "si_cp: Failed to load firmware \"%s\"\n", 398 fw_name); 399 if (rdev->pfp_fw != NULL) { 400 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 401 rdev->pfp_fw = NULL; 402 } 403 if (rdev->me_fw != NULL) { 404 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 405 rdev->me_fw = NULL; 406 } 407 if (rdev->ce_fw != NULL) { 408 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD); 409 rdev->ce_fw = NULL; 410 } 411 if (rdev->rlc_fw != NULL) { 412 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 413 rdev->rlc_fw = NULL; 414 } 415 if (rdev->mc_fw != NULL) { 416 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD); 417 rdev->mc_fw = NULL; 418 } 419 } 420 return err; 421} 422 423/** 424 * si_fini_microcode - drop the firmwares image references 425 * 426 * @rdev: radeon_device pointer 427 * 428 * Drop the pfp, me, rlc, mc and ce firmware image references. 429 * Called at driver shutdown. 430 */ 431static void si_fini_microcode(struct radeon_device *rdev) 432{ 433 434 if (rdev->pfp_fw != NULL) { 435 firmware_put(rdev->pfp_fw, FIRMWARE_UNLOAD); 436 rdev->pfp_fw = NULL; 437 } 438 439 if (rdev->me_fw != NULL) { 440 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD); 441 rdev->me_fw = NULL; 442 } 443 444 if (rdev->rlc_fw != NULL) { 445 firmware_put(rdev->rlc_fw, FIRMWARE_UNLOAD); 446 rdev->rlc_fw = NULL; 447 } 448 449 if (rdev->mc_fw != NULL) { 450 firmware_put(rdev->mc_fw, FIRMWARE_UNLOAD); 451 rdev->mc_fw = NULL; 452 } 453 454 if (rdev->ce_fw != NULL) { 455 firmware_put(rdev->ce_fw, FIRMWARE_UNLOAD); 456 rdev->ce_fw = NULL; 457 } 458} 459 460/* watermark setup */ 461static u32 dce6_line_buffer_adjust(struct radeon_device *rdev, 462 struct radeon_crtc *radeon_crtc, 463 struct drm_display_mode *mode, 464 struct drm_display_mode *other_mode) 465{ 466 u32 tmp; 467 /* 468 * Line Buffer Setup 469 * There are 3 line buffers, each one shared by 2 display controllers. 470 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 471 * the display controllers. The paritioning is done via one of four 472 * preset allocations specified in bits 21:20: 473 * 0 - half lb 474 * 2 - whole lb, other crtc must be disabled 475 */ 476 /* this can get tricky if we have two large displays on a paired group 477 * of crtcs. Ideally for multiple large displays we'd assign them to 478 * non-linked crtcs for maximum line buffer allocation. 479 */ 480 if (radeon_crtc->base.enabled && mode) { 481 if (other_mode) 482 tmp = 0; /* 1/2 */ 483 else 484 tmp = 2; /* whole */ 485 } else 486 tmp = 0; 487 488 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, 489 DC_LB_MEMORY_CONFIG(tmp)); 490 491 if (radeon_crtc->base.enabled && mode) { 492 switch (tmp) { 493 case 0: 494 default: 495 return 4096 * 2; 496 case 2: 497 return 8192 * 2; 498 } 499 } 500 501 /* controller not enabled, so no lb used */ 502 return 0; 503} 504 505static u32 si_get_number_of_dram_channels(struct radeon_device *rdev) 506{ 507 u32 tmp = RREG32(MC_SHARED_CHMAP); 508 509 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 510 case 0: 511 default: 512 return 1; 513 case 1: 514 return 2; 515 case 2: 516 return 4; 517 case 3: 518 return 8; 519 case 4: 520 return 3; 521 case 5: 522 return 6; 523 case 6: 524 return 10; 525 case 7: 526 return 12; 527 case 8: 528 return 16; 529 } 530} 531 532struct dce6_wm_params { 533 u32 dram_channels; /* number of dram channels */ 534 u32 yclk; /* bandwidth per dram data pin in kHz */ 535 u32 sclk; /* engine clock in kHz */ 536 u32 disp_clk; /* display clock in kHz */ 537 u32 src_width; /* viewport width */ 538 u32 active_time; /* active display time in ns */ 539 u32 blank_time; /* blank time in ns */ 540 bool interlaced; /* mode is interlaced */ 541 fixed20_12 vsc; /* vertical scale ratio */ 542 u32 num_heads; /* number of active crtcs */ 543 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 544 u32 lb_size; /* line buffer allocated to pipe */ 545 u32 vtaps; /* vertical scaler taps */ 546}; 547 548static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) 549{ 550 /* Calculate raw DRAM Bandwidth */ 551 fixed20_12 dram_efficiency; /* 0.7 */ 552 fixed20_12 yclk, dram_channels, bandwidth; 553 fixed20_12 a; 554 555 a.full = dfixed_const(1000); 556 yclk.full = dfixed_const(wm->yclk); 557 yclk.full = dfixed_div(yclk, a); 558 dram_channels.full = dfixed_const(wm->dram_channels * 4); 559 a.full = dfixed_const(10); 560 dram_efficiency.full = dfixed_const(7); 561 dram_efficiency.full = dfixed_div(dram_efficiency, a); 562 bandwidth.full = dfixed_mul(dram_channels, yclk); 563 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 564 565 return dfixed_trunc(bandwidth); 566} 567 568static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) 569{ 570 /* Calculate DRAM Bandwidth and the part allocated to display. */ 571 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 572 fixed20_12 yclk, dram_channels, bandwidth; 573 fixed20_12 a; 574 575 a.full = dfixed_const(1000); 576 yclk.full = dfixed_const(wm->yclk); 577 yclk.full = dfixed_div(yclk, a); 578 dram_channels.full = dfixed_const(wm->dram_channels * 4); 579 a.full = dfixed_const(10); 580 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 581 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 582 bandwidth.full = dfixed_mul(dram_channels, yclk); 583 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 584 585 return dfixed_trunc(bandwidth); 586} 587 588static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) 589{ 590 /* Calculate the display Data return Bandwidth */ 591 fixed20_12 return_efficiency; /* 0.8 */ 592 fixed20_12 sclk, bandwidth; 593 fixed20_12 a; 594 595 a.full = dfixed_const(1000); 596 sclk.full = dfixed_const(wm->sclk); 597 sclk.full = dfixed_div(sclk, a); 598 a.full = dfixed_const(10); 599 return_efficiency.full = dfixed_const(8); 600 return_efficiency.full = dfixed_div(return_efficiency, a); 601 a.full = dfixed_const(32); 602 bandwidth.full = dfixed_mul(a, sclk); 603 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 604 605 return dfixed_trunc(bandwidth); 606} 607 608static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) 609{ 610 return 32; 611} 612 613static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) 614{ 615 /* Calculate the DMIF Request Bandwidth */ 616 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 617 fixed20_12 disp_clk, sclk, bandwidth; 618 fixed20_12 a, b1, b2; 619 u32 min_bandwidth; 620 621 a.full = dfixed_const(1000); 622 disp_clk.full = dfixed_const(wm->disp_clk); 623 disp_clk.full = dfixed_div(disp_clk, a); 624 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); 625 b1.full = dfixed_mul(a, disp_clk); 626 627 a.full = dfixed_const(1000); 628 sclk.full = dfixed_const(wm->sclk); 629 sclk.full = dfixed_div(sclk, a); 630 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); 631 b2.full = dfixed_mul(a, sclk); 632 633 a.full = dfixed_const(10); 634 disp_clk_request_efficiency.full = dfixed_const(8); 635 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 636 637 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2)); 638 639 a.full = dfixed_const(min_bandwidth); 640 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency); 641 642 return dfixed_trunc(bandwidth); 643} 644 645static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) 646{ 647 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 648 u32 dram_bandwidth = dce6_dram_bandwidth(wm); 649 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); 650 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); 651 652 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 653} 654 655static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) 656{ 657 /* Calculate the display mode Average Bandwidth 658 * DisplayMode should contain the source and destination dimensions, 659 * timing, etc. 660 */ 661 fixed20_12 bpp; 662 fixed20_12 line_time; 663 fixed20_12 src_width; 664 fixed20_12 bandwidth; 665 fixed20_12 a; 666 667 a.full = dfixed_const(1000); 668 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 669 line_time.full = dfixed_div(line_time, a); 670 bpp.full = dfixed_const(wm->bytes_per_pixel); 671 src_width.full = dfixed_const(wm->src_width); 672 bandwidth.full = dfixed_mul(src_width, bpp); 673 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 674 bandwidth.full = dfixed_div(bandwidth, line_time); 675 676 return dfixed_trunc(bandwidth); 677} 678 679static u32 dce6_latency_watermark(struct dce6_wm_params *wm) 680{ 681 /* First calcualte the latency in ns */ 682 u32 mc_latency = 2000; /* 2000 ns. */ 683 u32 available_bandwidth = dce6_available_bandwidth(wm); 684 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 685 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 686 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 687 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 688 (wm->num_heads * cursor_line_pair_return_time); 689 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 690 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 691 u32 tmp, dmif_size = 12288; 692 fixed20_12 a, b, c; 693 694 if (wm->num_heads == 0) 695 return 0; 696 697 a.full = dfixed_const(2); 698 b.full = dfixed_const(1); 699 if ((wm->vsc.full > a.full) || 700 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 701 (wm->vtaps >= 5) || 702 ((wm->vsc.full >= a.full) && wm->interlaced)) 703 max_src_lines_per_dst_line = 4; 704 else 705 max_src_lines_per_dst_line = 2; 706 707 a.full = dfixed_const(available_bandwidth); 708 b.full = dfixed_const(wm->num_heads); 709 a.full = dfixed_div(a, b); 710 711 b.full = dfixed_const(mc_latency + 512); 712 c.full = dfixed_const(wm->disp_clk); 713 b.full = dfixed_div(b, c); 714 715 c.full = dfixed_const(dmif_size); 716 b.full = dfixed_div(c, b); 717 718 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 719 720 b.full = dfixed_const(1000); 721 c.full = dfixed_const(wm->disp_clk); 722 b.full = dfixed_div(c, b); 723 c.full = dfixed_const(wm->bytes_per_pixel); 724 b.full = dfixed_mul(b, c); 725 726 lb_fill_bw = min(tmp, dfixed_trunc(b)); 727 728 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 729 b.full = dfixed_const(1000); 730 c.full = dfixed_const(lb_fill_bw); 731 b.full = dfixed_div(c, b); 732 a.full = dfixed_div(a, b); 733 line_fill_time = dfixed_trunc(a); 734 735 if (line_fill_time < wm->active_time) 736 return latency; 737 else 738 return latency + (line_fill_time - wm->active_time); 739 740} 741 742static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 743{ 744 if (dce6_average_bandwidth(wm) <= 745 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) 746 return true; 747 else 748 return false; 749}; 750 751static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 752{ 753 if (dce6_average_bandwidth(wm) <= 754 (dce6_available_bandwidth(wm) / wm->num_heads)) 755 return true; 756 else 757 return false; 758}; 759 760static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) 761{ 762 u32 lb_partitions = wm->lb_size / wm->src_width; 763 u32 line_time = wm->active_time + wm->blank_time; 764 u32 latency_tolerant_lines; 765 u32 latency_hiding; 766 fixed20_12 a; 767 768 a.full = dfixed_const(1); 769 if (wm->vsc.full > a.full) 770 latency_tolerant_lines = 1; 771 else { 772 if (lb_partitions <= (wm->vtaps + 1)) 773 latency_tolerant_lines = 1; 774 else 775 latency_tolerant_lines = 2; 776 } 777 778 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 779 780 if (dce6_latency_watermark(wm) <= latency_hiding) 781 return true; 782 else 783 return false; 784} 785 786static void dce6_program_watermarks(struct radeon_device *rdev, 787 struct radeon_crtc *radeon_crtc, 788 u32 lb_size, u32 num_heads) 789{ 790 struct drm_display_mode *mode = &radeon_crtc->base.mode; 791 struct dce6_wm_params wm; 792 u32 pixel_period; 793 u32 line_time = 0; 794 u32 latency_watermark_a = 0, latency_watermark_b = 0; 795 u32 priority_a_mark = 0, priority_b_mark = 0; 796 u32 priority_a_cnt = PRIORITY_OFF; 797 u32 priority_b_cnt = PRIORITY_OFF; 798 u32 tmp, arb_control3; 799 fixed20_12 a, b, c; 800 801 if (radeon_crtc->base.enabled && num_heads && mode) { 802 pixel_period = 1000000 / (u32)mode->clock; 803 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 804 priority_a_cnt = 0; 805 priority_b_cnt = 0; 806 807 wm.yclk = rdev->pm.current_mclk * 10; 808 wm.sclk = rdev->pm.current_sclk * 10; 809 wm.disp_clk = mode->clock; 810 wm.src_width = mode->crtc_hdisplay; 811 wm.active_time = mode->crtc_hdisplay * pixel_period; 812 wm.blank_time = line_time - wm.active_time; 813 wm.interlaced = false; 814 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 815 wm.interlaced = true; 816 wm.vsc = radeon_crtc->vsc; 817 wm.vtaps = 1; 818 if (radeon_crtc->rmx_type != RMX_OFF) 819 wm.vtaps = 2; 820 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 821 wm.lb_size = lb_size; 822 if (rdev->family == CHIP_ARUBA) 823 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 824 else 825 wm.dram_channels = si_get_number_of_dram_channels(rdev); 826 wm.num_heads = num_heads; 827 828 /* set for high clocks */ 829 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535); 830 /* set for low clocks */ 831 /* wm.yclk = low clk; wm.sclk = low clk */ 832 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535); 833 834 /* possibly force display priority to high */ 835 /* should really do this at mode validation time... */ 836 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 837 !dce6_average_bandwidth_vs_available_bandwidth(&wm) || 838 !dce6_check_latency_hiding(&wm) || 839 (rdev->disp_priority == 2)) { 840 DRM_DEBUG_KMS("force priority to high\n"); 841 priority_a_cnt |= PRIORITY_ALWAYS_ON; 842 priority_b_cnt |= PRIORITY_ALWAYS_ON; 843 } 844 845 a.full = dfixed_const(1000); 846 b.full = dfixed_const(mode->clock); 847 b.full = dfixed_div(b, a); 848 c.full = dfixed_const(latency_watermark_a); 849 c.full = dfixed_mul(c, b); 850 c.full = dfixed_mul(c, radeon_crtc->hsc); 851 c.full = dfixed_div(c, a); 852 a.full = dfixed_const(16); 853 c.full = dfixed_div(c, a); 854 priority_a_mark = dfixed_trunc(c); 855 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 856 857 a.full = dfixed_const(1000); 858 b.full = dfixed_const(mode->clock); 859 b.full = dfixed_div(b, a); 860 c.full = dfixed_const(latency_watermark_b); 861 c.full = dfixed_mul(c, b); 862 c.full = dfixed_mul(c, radeon_crtc->hsc); 863 c.full = dfixed_div(c, a); 864 a.full = dfixed_const(16); 865 c.full = dfixed_div(c, a); 866 priority_b_mark = dfixed_trunc(c); 867 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 868 } 869 870 /* select wm A */ 871 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 872 tmp = arb_control3; 873 tmp &= ~LATENCY_WATERMARK_MASK(3); 874 tmp |= LATENCY_WATERMARK_MASK(1); 875 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 876 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 877 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 878 LATENCY_HIGH_WATERMARK(line_time))); 879 /* select wm B */ 880 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 881 tmp &= ~LATENCY_WATERMARK_MASK(3); 882 tmp |= LATENCY_WATERMARK_MASK(2); 883 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 884 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 885 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 886 LATENCY_HIGH_WATERMARK(line_time))); 887 /* restore original selection */ 888 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); 889 890 /* write the priority marks */ 891 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 892 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 893 894} 895 896void dce6_bandwidth_update(struct radeon_device *rdev) 897{ 898 struct drm_display_mode *mode0 = NULL; 899 struct drm_display_mode *mode1 = NULL; 900 u32 num_heads = 0, lb_size; 901 int i; 902 903 radeon_update_display_priority(rdev); 904 905 for (i = 0; i < rdev->num_crtc; i++) { 906 if (rdev->mode_info.crtcs[i]->base.enabled) 907 num_heads++; 908 } 909 for (i = 0; i < rdev->num_crtc; i += 2) { 910 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 911 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 912 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 913 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 914 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 915 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 916 } 917} 918 919/* 920 * Core functions 921 */ 922static void si_tiling_mode_table_init(struct radeon_device *rdev) 923{ 924 const u32 num_tile_mode_states = 32; 925 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 926 927 switch (rdev->config.si.mem_row_size_in_kb) { 928 case 1: 929 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 930 break; 931 case 2: 932 default: 933 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 934 break; 935 case 4: 936 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 937 break; 938 } 939 940 if ((rdev->family == CHIP_TAHITI) || 941 (rdev->family == CHIP_PITCAIRN)) { 942 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 943 switch (reg_offset) { 944 case 0: /* non-AA compressed depth or any compressed stencil */ 945 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 946 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 947 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 948 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 949 NUM_BANKS(ADDR_SURF_16_BANK) | 950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 953 break; 954 case 1: /* 2xAA/4xAA compressed depth only */ 955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 956 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 957 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 958 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 959 NUM_BANKS(ADDR_SURF_16_BANK) | 960 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 963 break; 964 case 2: /* 8xAA compressed depth only */ 965 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 966 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 967 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 968 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 969 NUM_BANKS(ADDR_SURF_16_BANK) | 970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 973 break; 974 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 975 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 976 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 977 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 979 NUM_BANKS(ADDR_SURF_16_BANK) | 980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 983 break; 984 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 986 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 987 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 989 NUM_BANKS(ADDR_SURF_16_BANK) | 990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 993 break; 994 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 996 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 997 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 998 TILE_SPLIT(split_equal_to_row_size) | 999 NUM_BANKS(ADDR_SURF_16_BANK) | 1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1003 break; 1004 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1006 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1008 TILE_SPLIT(split_equal_to_row_size) | 1009 NUM_BANKS(ADDR_SURF_16_BANK) | 1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1013 break; 1014 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1015 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1016 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1017 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1018 TILE_SPLIT(split_equal_to_row_size) | 1019 NUM_BANKS(ADDR_SURF_16_BANK) | 1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1023 break; 1024 case 8: /* 1D and 1D Array Surfaces */ 1025 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1026 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1027 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1029 NUM_BANKS(ADDR_SURF_16_BANK) | 1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1033 break; 1034 case 9: /* Displayable maps. */ 1035 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1036 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1037 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1039 NUM_BANKS(ADDR_SURF_16_BANK) | 1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1043 break; 1044 case 10: /* Display 8bpp. */ 1045 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1046 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1049 NUM_BANKS(ADDR_SURF_16_BANK) | 1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1053 break; 1054 case 11: /* Display 16bpp. */ 1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1056 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1057 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1059 NUM_BANKS(ADDR_SURF_16_BANK) | 1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1063 break; 1064 case 12: /* Display 32bpp. */ 1065 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1066 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1067 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1068 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1069 NUM_BANKS(ADDR_SURF_16_BANK) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1073 break; 1074 case 13: /* Thin. */ 1075 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1076 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1079 NUM_BANKS(ADDR_SURF_16_BANK) | 1080 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1083 break; 1084 case 14: /* Thin 8 bpp. */ 1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1086 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1089 NUM_BANKS(ADDR_SURF_16_BANK) | 1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1093 break; 1094 case 15: /* Thin 16 bpp. */ 1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1096 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1099 NUM_BANKS(ADDR_SURF_16_BANK) | 1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1103 break; 1104 case 16: /* Thin 32 bpp. */ 1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1106 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1109 NUM_BANKS(ADDR_SURF_16_BANK) | 1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1113 break; 1114 case 17: /* Thin 64 bpp. */ 1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1116 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1118 TILE_SPLIT(split_equal_to_row_size) | 1119 NUM_BANKS(ADDR_SURF_16_BANK) | 1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1123 break; 1124 case 21: /* 8 bpp PRT. */ 1125 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1126 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1127 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1128 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1129 NUM_BANKS(ADDR_SURF_16_BANK) | 1130 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1133 break; 1134 case 22: /* 16 bpp PRT */ 1135 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1136 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1137 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1138 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1139 NUM_BANKS(ADDR_SURF_16_BANK) | 1140 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1143 break; 1144 case 23: /* 32 bpp PRT */ 1145 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1146 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1147 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1148 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1149 NUM_BANKS(ADDR_SURF_16_BANK) | 1150 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1153 break; 1154 case 24: /* 64 bpp PRT */ 1155 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1156 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1157 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1158 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1159 NUM_BANKS(ADDR_SURF_16_BANK) | 1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1163 break; 1164 case 25: /* 128 bpp PRT */ 1165 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1166 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1168 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1169 NUM_BANKS(ADDR_SURF_8_BANK) | 1170 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1173 break; 1174 default: 1175 gb_tile_moden = 0; 1176 break; 1177 } 1178 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1179 } 1180 } else if (rdev->family == CHIP_VERDE) { 1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1182 switch (reg_offset) { 1183 case 0: /* non-AA compressed depth or any compressed stencil */ 1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1185 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1186 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1187 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1188 NUM_BANKS(ADDR_SURF_16_BANK) | 1189 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1192 break; 1193 case 1: /* 2xAA/4xAA compressed depth only */ 1194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1195 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1196 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1197 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1198 NUM_BANKS(ADDR_SURF_16_BANK) | 1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1202 break; 1203 case 2: /* 8xAA compressed depth only */ 1204 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1205 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1206 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1207 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1208 NUM_BANKS(ADDR_SURF_16_BANK) | 1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1212 break; 1213 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1214 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1215 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1216 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1218 NUM_BANKS(ADDR_SURF_16_BANK) | 1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1222 break; 1223 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1225 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1228 NUM_BANKS(ADDR_SURF_16_BANK) | 1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1232 break; 1233 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1234 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1235 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1237 TILE_SPLIT(split_equal_to_row_size) | 1238 NUM_BANKS(ADDR_SURF_16_BANK) | 1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1242 break; 1243 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1245 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1247 TILE_SPLIT(split_equal_to_row_size) | 1248 NUM_BANKS(ADDR_SURF_16_BANK) | 1249 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1252 break; 1253 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1255 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1257 TILE_SPLIT(split_equal_to_row_size) | 1258 NUM_BANKS(ADDR_SURF_16_BANK) | 1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1262 break; 1263 case 8: /* 1D and 1D Array Surfaces */ 1264 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1265 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1268 NUM_BANKS(ADDR_SURF_16_BANK) | 1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1272 break; 1273 case 9: /* Displayable maps. */ 1274 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1275 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1278 NUM_BANKS(ADDR_SURF_16_BANK) | 1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1282 break; 1283 case 10: /* Display 8bpp. */ 1284 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1285 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1288 NUM_BANKS(ADDR_SURF_16_BANK) | 1289 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1292 break; 1293 case 11: /* Display 16bpp. */ 1294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1295 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1296 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1298 NUM_BANKS(ADDR_SURF_16_BANK) | 1299 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1300 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1301 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1302 break; 1303 case 12: /* Display 32bpp. */ 1304 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1305 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1306 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1307 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1308 NUM_BANKS(ADDR_SURF_16_BANK) | 1309 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1312 break; 1313 case 13: /* Thin. */ 1314 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1315 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1316 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1318 NUM_BANKS(ADDR_SURF_16_BANK) | 1319 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1322 break; 1323 case 14: /* Thin 8 bpp. */ 1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1325 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1326 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1327 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1328 NUM_BANKS(ADDR_SURF_16_BANK) | 1329 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1332 break; 1333 case 15: /* Thin 16 bpp. */ 1334 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1335 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1336 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1338 NUM_BANKS(ADDR_SURF_16_BANK) | 1339 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1342 break; 1343 case 16: /* Thin 32 bpp. */ 1344 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1345 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1346 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1348 NUM_BANKS(ADDR_SURF_16_BANK) | 1349 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1352 break; 1353 case 17: /* Thin 64 bpp. */ 1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1355 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1356 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1357 TILE_SPLIT(split_equal_to_row_size) | 1358 NUM_BANKS(ADDR_SURF_16_BANK) | 1359 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1362 break; 1363 case 21: /* 8 bpp PRT. */ 1364 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1365 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1366 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1367 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1368 NUM_BANKS(ADDR_SURF_16_BANK) | 1369 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1372 break; 1373 case 22: /* 16 bpp PRT */ 1374 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1375 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1376 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1378 NUM_BANKS(ADDR_SURF_16_BANK) | 1379 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1382 break; 1383 case 23: /* 32 bpp PRT */ 1384 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1385 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1386 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1387 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1388 NUM_BANKS(ADDR_SURF_16_BANK) | 1389 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1392 break; 1393 case 24: /* 64 bpp PRT */ 1394 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1395 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1396 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1397 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1398 NUM_BANKS(ADDR_SURF_16_BANK) | 1399 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1402 break; 1403 case 25: /* 128 bpp PRT */ 1404 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1405 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1406 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1408 NUM_BANKS(ADDR_SURF_8_BANK) | 1409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1412 break; 1413 default: 1414 gb_tile_moden = 0; 1415 break; 1416 } 1417 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1418 } 1419 } else 1420 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1421} 1422 1423static void si_select_se_sh(struct radeon_device *rdev, 1424 u32 se_num, u32 sh_num) 1425{ 1426 u32 data = INSTANCE_BROADCAST_WRITES; 1427 1428 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1429 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 1430 else if (se_num == 0xffffffff) 1431 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 1432 else if (sh_num == 0xffffffff) 1433 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 1434 else 1435 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 1436 WREG32(GRBM_GFX_INDEX, data); 1437} 1438 1439static u32 si_create_bitmask(u32 bit_width) 1440{ 1441 u32 i, mask = 0; 1442 1443 for (i = 0; i < bit_width; i++) { 1444 mask <<= 1; 1445 mask |= 1; 1446 } 1447 return mask; 1448} 1449 1450static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh) 1451{ 1452 u32 data, mask; 1453 1454 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1455 if (data & 1) 1456 data &= INACTIVE_CUS_MASK; 1457 else 1458 data = 0; 1459 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1460 1461 data >>= INACTIVE_CUS_SHIFT; 1462 1463 mask = si_create_bitmask(cu_per_sh); 1464 1465 return ~data & mask; 1466} 1467 1468static void si_setup_spi(struct radeon_device *rdev, 1469 u32 se_num, u32 sh_per_se, 1470 u32 cu_per_sh) 1471{ 1472 int i, j, k; 1473 u32 data, mask, active_cu; 1474 1475 for (i = 0; i < se_num; i++) { 1476 for (j = 0; j < sh_per_se; j++) { 1477 si_select_se_sh(rdev, i, j); 1478 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1479 active_cu = si_get_cu_enabled(rdev, cu_per_sh); 1480 1481 mask = 1; 1482 for (k = 0; k < 16; k++) { 1483 mask <<= k; 1484 if (active_cu & mask) { 1485 data &= ~mask; 1486 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1487 break; 1488 } 1489 } 1490 } 1491 } 1492 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1493} 1494 1495static u32 si_get_rb_disabled(struct radeon_device *rdev, 1496 u32 max_rb_num, u32 se_num, 1497 u32 sh_per_se) 1498{ 1499 u32 data, mask; 1500 1501 data = RREG32(CC_RB_BACKEND_DISABLE); 1502 if (data & 1) 1503 data &= BACKEND_DISABLE_MASK; 1504 else 1505 data = 0; 1506 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 1507 1508 data >>= BACKEND_DISABLE_SHIFT; 1509 1510 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se); 1511 1512 return data & mask; 1513} 1514 1515static void si_setup_rb(struct radeon_device *rdev, 1516 u32 se_num, u32 sh_per_se, 1517 u32 max_rb_num) 1518{ 1519 int i, j; 1520 u32 data, mask; 1521 u32 disabled_rbs = 0; 1522 u32 enabled_rbs = 0; 1523 1524 for (i = 0; i < se_num; i++) { 1525 for (j = 0; j < sh_per_se; j++) { 1526 si_select_se_sh(rdev, i, j); 1527 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 1528 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1529 } 1530 } 1531 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1532 1533 mask = 1; 1534 for (i = 0; i < max_rb_num; i++) { 1535 if (!(disabled_rbs & mask)) 1536 enabled_rbs |= mask; 1537 mask <<= 1; 1538 } 1539 1540 for (i = 0; i < se_num; i++) { 1541 si_select_se_sh(rdev, i, 0xffffffff); 1542 data = 0; 1543 for (j = 0; j < sh_per_se; j++) { 1544 switch (enabled_rbs & 3) { 1545 case 1: 1546 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 1547 break; 1548 case 2: 1549 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); 1550 break; 1551 case 3: 1552 default: 1553 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); 1554 break; 1555 } 1556 enabled_rbs >>= 2; 1557 } 1558 WREG32(PA_SC_RASTER_CONFIG, data); 1559 } 1560 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1561} 1562 1563static void si_gpu_init(struct radeon_device *rdev) 1564{ 1565 u32 gb_addr_config = 0; 1566 u32 mc_shared_chmap, mc_arb_ramcfg; 1567 u32 sx_debug_1; 1568 u32 hdp_host_path_cntl; 1569 u32 tmp; 1570 int i, j; 1571 1572 switch (rdev->family) { 1573 case CHIP_TAHITI: 1574 rdev->config.si.max_shader_engines = 2; 1575 rdev->config.si.max_tile_pipes = 12; 1576 rdev->config.si.max_cu_per_sh = 8; 1577 rdev->config.si.max_sh_per_se = 2; 1578 rdev->config.si.max_backends_per_se = 4; 1579 rdev->config.si.max_texture_channel_caches = 12; 1580 rdev->config.si.max_gprs = 256; 1581 rdev->config.si.max_gs_threads = 32; 1582 rdev->config.si.max_hw_contexts = 8; 1583 1584 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1585 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1586 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1587 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1588 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1589 break; 1590 case CHIP_PITCAIRN: 1591 rdev->config.si.max_shader_engines = 2; 1592 rdev->config.si.max_tile_pipes = 8; 1593 rdev->config.si.max_cu_per_sh = 5; 1594 rdev->config.si.max_sh_per_se = 2; 1595 rdev->config.si.max_backends_per_se = 4; 1596 rdev->config.si.max_texture_channel_caches = 8; 1597 rdev->config.si.max_gprs = 256; 1598 rdev->config.si.max_gs_threads = 32; 1599 rdev->config.si.max_hw_contexts = 8; 1600 1601 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1602 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1603 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1604 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1605 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1606 break; 1607 case CHIP_VERDE: 1608 default: 1609 rdev->config.si.max_shader_engines = 1; 1610 rdev->config.si.max_tile_pipes = 4; 1611 rdev->config.si.max_cu_per_sh = 2; 1612 rdev->config.si.max_sh_per_se = 2; 1613 rdev->config.si.max_backends_per_se = 4; 1614 rdev->config.si.max_texture_channel_caches = 4; 1615 rdev->config.si.max_gprs = 256; 1616 rdev->config.si.max_gs_threads = 32; 1617 rdev->config.si.max_hw_contexts = 8; 1618 1619 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1620 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1621 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1622 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1623 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1624 break; 1625 } 1626 1627 /* Initialize HDP */ 1628 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1629 WREG32((0x2c14 + j), 0x00000000); 1630 WREG32((0x2c18 + j), 0x00000000); 1631 WREG32((0x2c1c + j), 0x00000000); 1632 WREG32((0x2c20 + j), 0x00000000); 1633 WREG32((0x2c24 + j), 0x00000000); 1634 } 1635 1636 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1637 1638 evergreen_fix_pci_max_read_req_size(rdev); 1639 1640 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1641 1642 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1643 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1644 1645 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1646 rdev->config.si.mem_max_burst_length_bytes = 256; 1647 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1648 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1649 if (rdev->config.si.mem_row_size_in_kb > 4) 1650 rdev->config.si.mem_row_size_in_kb = 4; 1651 /* XXX use MC settings? */ 1652 rdev->config.si.shader_engine_tile_size = 32; 1653 rdev->config.si.num_gpus = 1; 1654 rdev->config.si.multi_gpu_tile_size = 64; 1655 1656 /* fix up row size */ 1657 gb_addr_config &= ~ROW_SIZE_MASK; 1658 switch (rdev->config.si.mem_row_size_in_kb) { 1659 case 1: 1660 default: 1661 gb_addr_config |= ROW_SIZE(0); 1662 break; 1663 case 2: 1664 gb_addr_config |= ROW_SIZE(1); 1665 break; 1666 case 4: 1667 gb_addr_config |= ROW_SIZE(2); 1668 break; 1669 } 1670 1671 /* setup tiling info dword. gb_addr_config is not adequate since it does 1672 * not have bank info, so create a custom tiling dword. 1673 * bits 3:0 num_pipes 1674 * bits 7:4 num_banks 1675 * bits 11:8 group_size 1676 * bits 15:12 row_size 1677 */ 1678 rdev->config.si.tile_config = 0; 1679 switch (rdev->config.si.num_tile_pipes) { 1680 case 1: 1681 rdev->config.si.tile_config |= (0 << 0); 1682 break; 1683 case 2: 1684 rdev->config.si.tile_config |= (1 << 0); 1685 break; 1686 case 4: 1687 rdev->config.si.tile_config |= (2 << 0); 1688 break; 1689 case 8: 1690 default: 1691 /* XXX what about 12? */ 1692 rdev->config.si.tile_config |= (3 << 0); 1693 break; 1694 } 1695 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1696 case 0: /* four banks */ 1697 rdev->config.si.tile_config |= 0 << 4; 1698 break; 1699 case 1: /* eight banks */ 1700 rdev->config.si.tile_config |= 1 << 4; 1701 break; 1702 case 2: /* sixteen banks */ 1703 default: 1704 rdev->config.si.tile_config |= 2 << 4; 1705 break; 1706 } 1707 rdev->config.si.tile_config |= 1708 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1709 rdev->config.si.tile_config |= 1710 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1711 1712 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1713 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1714 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1715 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1716 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1717 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1718 1719 si_tiling_mode_table_init(rdev); 1720 1721 si_setup_rb(rdev, rdev->config.si.max_shader_engines, 1722 rdev->config.si.max_sh_per_se, 1723 rdev->config.si.max_backends_per_se); 1724 1725 si_setup_spi(rdev, rdev->config.si.max_shader_engines, 1726 rdev->config.si.max_sh_per_se, 1727 rdev->config.si.max_cu_per_sh); 1728 1729 1730 /* set HW defaults for 3D engine */ 1731 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1732 ROQ_IB2_START(0x2b))); 1733 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1734 1735 sx_debug_1 = RREG32(SX_DEBUG_1); 1736 WREG32(SX_DEBUG_1, sx_debug_1); 1737 1738 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1739 1740 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | 1741 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | 1742 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | 1743 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); 1744 1745 WREG32(VGT_NUM_INSTANCES, 1); 1746 1747 WREG32(CP_PERFMON_CNTL, 0); 1748 1749 WREG32(SQ_CONFIG, 0); 1750 1751 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1752 FORCE_EOV_MAX_REZ_CNT(255))); 1753 1754 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1755 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1756 1757 WREG32(VGT_GS_VERTEX_REUSE, 16); 1758 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1759 1760 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1761 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1762 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1763 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1764 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1765 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1766 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1767 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1768 1769 tmp = RREG32(HDP_MISC_CNTL); 1770 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1771 WREG32(HDP_MISC_CNTL, tmp); 1772 1773 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1774 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1775 1776 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1777 1778 udelay(50); 1779} 1780 1781/* 1782 * GPU scratch registers helpers function. 1783 */ 1784static void si_scratch_init(struct radeon_device *rdev) 1785{ 1786 int i; 1787 1788 rdev->scratch.num_reg = 7; 1789 rdev->scratch.reg_base = SCRATCH_REG0; 1790 for (i = 0; i < rdev->scratch.num_reg; i++) { 1791 rdev->scratch.free[i] = true; 1792 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 1793 } 1794} 1795 1796void si_fence_ring_emit(struct radeon_device *rdev, 1797 struct radeon_fence *fence) 1798{ 1799 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1800 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1801 1802 /* flush read cache over gart */ 1803 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1804 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1805 radeon_ring_write(ring, 0); 1806 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1807 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1808 PACKET3_TC_ACTION_ENA | 1809 PACKET3_SH_KCACHE_ACTION_ENA | 1810 PACKET3_SH_ICACHE_ACTION_ENA); 1811 radeon_ring_write(ring, 0xFFFFFFFF); 1812 radeon_ring_write(ring, 0); 1813 radeon_ring_write(ring, 10); /* poll interval */ 1814 /* EVENT_WRITE_EOP - flush caches, send int */ 1815 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1816 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1817 radeon_ring_write(ring, addr & 0xffffffff); 1818 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1819 radeon_ring_write(ring, fence->seq); 1820 radeon_ring_write(ring, 0); 1821} 1822 1823/* 1824 * IB stuff 1825 */ 1826void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1827{ 1828 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1829 u32 header; 1830 1831 if (ib->is_const_ib) { 1832 /* set switch buffer packet before const IB */ 1833 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1834 radeon_ring_write(ring, 0); 1835 1836 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1837 } else { 1838 u32 next_rptr; 1839 if (ring->rptr_save_reg) { 1840 next_rptr = ring->wptr + 3 + 4 + 8; 1841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1842 radeon_ring_write(ring, ((ring->rptr_save_reg - 1843 PACKET3_SET_CONFIG_REG_START) >> 2)); 1844 radeon_ring_write(ring, next_rptr); 1845 } else if (rdev->wb.enabled) { 1846 next_rptr = ring->wptr + 5 + 4 + 8; 1847 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1848 radeon_ring_write(ring, (1 << 8)); 1849 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1850 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 1851 radeon_ring_write(ring, next_rptr); 1852 } 1853 1854 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1855 } 1856 1857 radeon_ring_write(ring, header); 1858 radeon_ring_write(ring, 1859#ifdef __BIG_ENDIAN 1860 (2 << 0) | 1861#endif 1862 (ib->gpu_addr & 0xFFFFFFFC)); 1863 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1864 radeon_ring_write(ring, ib->length_dw | 1865 (ib->vm ? (ib->vm->id << 24) : 0)); 1866 1867 if (!ib->is_const_ib) { 1868 /* flush read cache over gart for this vmid */ 1869 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1870 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1871 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); 1872 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1873 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1874 PACKET3_TC_ACTION_ENA | 1875 PACKET3_SH_KCACHE_ACTION_ENA | 1876 PACKET3_SH_ICACHE_ACTION_ENA); 1877 radeon_ring_write(ring, 0xFFFFFFFF); 1878 radeon_ring_write(ring, 0); 1879 radeon_ring_write(ring, 10); /* poll interval */ 1880 } 1881} 1882 1883/* 1884 * CP. 1885 */ 1886static void si_cp_enable(struct radeon_device *rdev, bool enable) 1887{ 1888 if (enable) 1889 WREG32(CP_ME_CNTL, 0); 1890 else { 1891 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1892 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1893 WREG32(SCRATCH_UMSK, 0); 1894 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1895 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1896 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1897 } 1898 udelay(50); 1899} 1900 1901static int si_cp_load_microcode(struct radeon_device *rdev) 1902{ 1903 const __be32 *fw_data; 1904 int i; 1905 1906 if (!rdev->me_fw || !rdev->pfp_fw) 1907 return -EINVAL; 1908 1909 si_cp_enable(rdev, false); 1910 1911 /* PFP */ 1912 fw_data = (const __be32 *)rdev->pfp_fw->data; 1913 WREG32(CP_PFP_UCODE_ADDR, 0); 1914 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) 1915 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1916 WREG32(CP_PFP_UCODE_ADDR, 0); 1917 1918 /* CE */ 1919 fw_data = (const __be32 *)rdev->ce_fw->data; 1920 WREG32(CP_CE_UCODE_ADDR, 0); 1921 for (i = 0; i < SI_CE_UCODE_SIZE; i++) 1922 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); 1923 WREG32(CP_CE_UCODE_ADDR, 0); 1924 1925 /* ME */ 1926 fw_data = (const __be32 *)rdev->me_fw->data; 1927 WREG32(CP_ME_RAM_WADDR, 0); 1928 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) 1929 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1930 WREG32(CP_ME_RAM_WADDR, 0); 1931 1932 WREG32(CP_PFP_UCODE_ADDR, 0); 1933 WREG32(CP_CE_UCODE_ADDR, 0); 1934 WREG32(CP_ME_RAM_WADDR, 0); 1935 WREG32(CP_ME_RAM_RADDR, 0); 1936 return 0; 1937} 1938 1939static int si_cp_start(struct radeon_device *rdev) 1940{ 1941 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1942 int r, i; 1943 1944 r = radeon_ring_lock(rdev, ring, 7 + 4); 1945 if (r) { 1946 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1947 return r; 1948 } 1949 /* init the CP */ 1950 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1951 radeon_ring_write(ring, 0x1); 1952 radeon_ring_write(ring, 0x0); 1953 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); 1954 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1955 radeon_ring_write(ring, 0); 1956 radeon_ring_write(ring, 0); 1957 1958 /* init the CE partitions */ 1959 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1960 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1961 radeon_ring_write(ring, 0xc000); 1962 radeon_ring_write(ring, 0xe000); 1963 radeon_ring_unlock_commit(rdev, ring); 1964 1965 si_cp_enable(rdev, true); 1966 1967 r = radeon_ring_lock(rdev, ring, si_default_size + 10); 1968 if (r) { 1969 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1970 return r; 1971 } 1972 1973 /* setup clear context state */ 1974 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1975 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1976 1977 for (i = 0; i < si_default_size; i++) 1978 radeon_ring_write(ring, si_default_state[i]); 1979 1980 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1981 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1982 1983 /* set clear context state */ 1984 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1985 radeon_ring_write(ring, 0); 1986 1987 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1988 radeon_ring_write(ring, 0x00000316); 1989 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1990 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 1991 1992 radeon_ring_unlock_commit(rdev, ring); 1993 1994 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { 1995 ring = &rdev->ring[i]; 1996 r = radeon_ring_lock(rdev, ring, 2); 1997 1998 /* clear the compute context state */ 1999 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 2000 radeon_ring_write(ring, 0); 2001 2002 radeon_ring_unlock_commit(rdev, ring); 2003 } 2004 2005 return 0; 2006} 2007 2008static void si_cp_fini(struct radeon_device *rdev) 2009{ 2010 struct radeon_ring *ring; 2011 si_cp_enable(rdev, false); 2012 2013 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2014 radeon_ring_fini(rdev, ring); 2015 radeon_scratch_free(rdev, ring->rptr_save_reg); 2016 2017 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2018 radeon_ring_fini(rdev, ring); 2019 radeon_scratch_free(rdev, ring->rptr_save_reg); 2020 2021 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2022 radeon_ring_fini(rdev, ring); 2023 radeon_scratch_free(rdev, ring->rptr_save_reg); 2024} 2025 2026static int si_cp_resume(struct radeon_device *rdev) 2027{ 2028 struct radeon_ring *ring; 2029 u32 tmp; 2030 u32 rb_bufsz; 2031 int r; 2032 2033 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 2034 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 2035 SOFT_RESET_PA | 2036 SOFT_RESET_VGT | 2037 SOFT_RESET_SPI | 2038 SOFT_RESET_SX)); 2039 RREG32(GRBM_SOFT_RESET); 2040 mdelay(15); 2041 WREG32(GRBM_SOFT_RESET, 0); 2042 RREG32(GRBM_SOFT_RESET); 2043 2044 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2045 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2046 2047 /* Set the write pointer delay */ 2048 WREG32(CP_RB_WPTR_DELAY, 0); 2049 2050 WREG32(CP_DEBUG, 0); 2051 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2052 2053 /* ring 0 - compute and gfx */ 2054 /* Set ring buffer size */ 2055 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2056 rb_bufsz = drm_order(ring->ring_size / 8); 2057 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2058#ifdef __BIG_ENDIAN 2059 tmp |= BUF_SWAP_32BIT; 2060#endif 2061 WREG32(CP_RB0_CNTL, tmp); 2062 2063 /* Initialize the ring buffer's read and write pointers */ 2064 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 2065 ring->wptr = 0; 2066 WREG32(CP_RB0_WPTR, ring->wptr); 2067 2068 /* set the wb address whether it's enabled or not */ 2069 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 2070 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2071 2072 if (rdev->wb.enabled) 2073 WREG32(SCRATCH_UMSK, 0xff); 2074 else { 2075 tmp |= RB_NO_UPDATE; 2076 WREG32(SCRATCH_UMSK, 0); 2077 } 2078 2079 mdelay(1); 2080 WREG32(CP_RB0_CNTL, tmp); 2081 2082 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 2083 2084 ring->rptr = RREG32(CP_RB0_RPTR); 2085 2086 /* ring1 - compute only */ 2087 /* Set ring buffer size */ 2088 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2089 rb_bufsz = drm_order(ring->ring_size / 8); 2090 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2091#ifdef __BIG_ENDIAN 2092 tmp |= BUF_SWAP_32BIT; 2093#endif 2094 WREG32(CP_RB1_CNTL, tmp); 2095 2096 /* Initialize the ring buffer's read and write pointers */ 2097 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 2098 ring->wptr = 0; 2099 WREG32(CP_RB1_WPTR, ring->wptr); 2100 2101 /* set the wb address whether it's enabled or not */ 2102 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 2103 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 2104 2105 mdelay(1); 2106 WREG32(CP_RB1_CNTL, tmp); 2107 2108 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 2109 2110 ring->rptr = RREG32(CP_RB1_RPTR); 2111 2112 /* ring2 - compute only */ 2113 /* Set ring buffer size */ 2114 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2115 rb_bufsz = drm_order(ring->ring_size / 8); 2116 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2117#ifdef __BIG_ENDIAN 2118 tmp |= BUF_SWAP_32BIT; 2119#endif 2120 WREG32(CP_RB2_CNTL, tmp); 2121 2122 /* Initialize the ring buffer's read and write pointers */ 2123 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 2124 ring->wptr = 0; 2125 WREG32(CP_RB2_WPTR, ring->wptr); 2126 2127 /* set the wb address whether it's enabled or not */ 2128 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 2129 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 2130 2131 mdelay(1); 2132 WREG32(CP_RB2_CNTL, tmp); 2133 2134 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 2135 2136 ring->rptr = RREG32(CP_RB2_RPTR); 2137 2138 /* start the rings */ 2139 si_cp_start(rdev); 2140 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 2141 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; 2142 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; 2143 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 2144 if (r) { 2145 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2146 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2147 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2148 return r; 2149 } 2150 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); 2151 if (r) { 2152 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2153 } 2154 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); 2155 if (r) { 2156 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2157 } 2158 2159 return 0; 2160} 2161 2162bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2163{ 2164 u32 srbm_status; 2165 u32 grbm_status, grbm_status2; 2166 u32 grbm_status_se0, grbm_status_se1; 2167 2168 srbm_status = RREG32(SRBM_STATUS); 2169 grbm_status = RREG32(GRBM_STATUS); 2170 grbm_status2 = RREG32(GRBM_STATUS2); 2171 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2172 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2173 if (!(grbm_status & GUI_ACTIVE)) { 2174 radeon_ring_lockup_update(ring); 2175 return false; 2176 } 2177 /* force CP activities */ 2178 radeon_ring_force_activity(rdev, ring); 2179 return radeon_ring_test_lockup(rdev, ring); 2180} 2181 2182static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) 2183{ 2184 u32 grbm_reset = 0; 2185 2186 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2187 return; 2188 2189 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2190 RREG32(GRBM_STATUS)); 2191 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2192 RREG32(GRBM_STATUS2)); 2193 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2194 RREG32(GRBM_STATUS_SE0)); 2195 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2196 RREG32(GRBM_STATUS_SE1)); 2197 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2198 RREG32(SRBM_STATUS)); 2199 2200 /* Disable CP parsing/prefetching */ 2201 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2202 2203 /* reset all the gfx blocks */ 2204 grbm_reset = (SOFT_RESET_CP | 2205 SOFT_RESET_CB | 2206 SOFT_RESET_DB | 2207 SOFT_RESET_GDS | 2208 SOFT_RESET_PA | 2209 SOFT_RESET_SC | 2210 SOFT_RESET_BCI | 2211 SOFT_RESET_SPI | 2212 SOFT_RESET_SX | 2213 SOFT_RESET_TC | 2214 SOFT_RESET_TA | 2215 SOFT_RESET_VGT | 2216 SOFT_RESET_IA); 2217 2218 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2219 WREG32(GRBM_SOFT_RESET, grbm_reset); 2220 (void)RREG32(GRBM_SOFT_RESET); 2221 udelay(50); 2222 WREG32(GRBM_SOFT_RESET, 0); 2223 (void)RREG32(GRBM_SOFT_RESET); 2224 2225 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2226 RREG32(GRBM_STATUS)); 2227 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2228 RREG32(GRBM_STATUS2)); 2229 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2230 RREG32(GRBM_STATUS_SE0)); 2231 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2232 RREG32(GRBM_STATUS_SE1)); 2233 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2234 RREG32(SRBM_STATUS)); 2235} 2236 2237static void si_gpu_soft_reset_dma(struct radeon_device *rdev) 2238{ 2239 u32 tmp; 2240 2241 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2242 return; 2243 2244 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2245 RREG32(DMA_STATUS_REG)); 2246 2247 /* dma0 */ 2248 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 2249 tmp &= ~DMA_RB_ENABLE; 2250 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 2251 2252 /* dma1 */ 2253 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 2254 tmp &= ~DMA_RB_ENABLE; 2255 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 2256 2257 /* Reset dma */ 2258 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); 2259 RREG32(SRBM_SOFT_RESET); 2260 udelay(50); 2261 WREG32(SRBM_SOFT_RESET, 0); 2262 2263 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2264 RREG32(DMA_STATUS_REG)); 2265} 2266 2267static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2268{ 2269 struct evergreen_mc_save save; 2270 2271 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2272 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 2273 2274 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2275 reset_mask &= ~RADEON_RESET_DMA; 2276 2277 if (reset_mask == 0) 2278 return 0; 2279 2280 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2281 2282 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 2283 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 2284 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 2285 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 2286 2287 evergreen_mc_stop(rdev, &save); 2288 if (radeon_mc_wait_for_idle(rdev)) { 2289 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2290 } 2291 2292 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2293 si_gpu_soft_reset_gfx(rdev); 2294 2295 if (reset_mask & RADEON_RESET_DMA) 2296 si_gpu_soft_reset_dma(rdev); 2297 2298 /* Wait a little for things to settle down */ 2299 udelay(50); 2300 2301 evergreen_mc_resume(rdev, &save); 2302 return 0; 2303} 2304 2305int si_asic_reset(struct radeon_device *rdev) 2306{ 2307 return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2308 RADEON_RESET_COMPUTE | 2309 RADEON_RESET_DMA)); 2310} 2311 2312/* MC */ 2313static void si_mc_program(struct radeon_device *rdev) 2314{ 2315 struct evergreen_mc_save save; 2316 u32 tmp; 2317 int i, j; 2318 2319 /* Initialize HDP */ 2320 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2321 WREG32((0x2c14 + j), 0x00000000); 2322 WREG32((0x2c18 + j), 0x00000000); 2323 WREG32((0x2c1c + j), 0x00000000); 2324 WREG32((0x2c20 + j), 0x00000000); 2325 WREG32((0x2c24 + j), 0x00000000); 2326 } 2327 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 2328 2329 evergreen_mc_stop(rdev, &save); 2330 if (radeon_mc_wait_for_idle(rdev)) { 2331 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2332 } 2333 /* Lockout access through VGA aperture*/ 2334 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 2335 /* Update configuration */ 2336 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 2337 rdev->mc.vram_start >> 12); 2338 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 2339 rdev->mc.vram_end >> 12); 2340 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 2341 rdev->vram_scratch.gpu_addr >> 12); 2342 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 2343 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 2344 WREG32(MC_VM_FB_LOCATION, tmp); 2345 /* XXX double check these! */ 2346 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 2347 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 2348 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 2349 WREG32(MC_VM_AGP_BASE, 0); 2350 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 2351 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 2352 if (radeon_mc_wait_for_idle(rdev)) { 2353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2354 } 2355 evergreen_mc_resume(rdev, &save); 2356 /* we need to own VRAM, so turn off the VGA renderer here 2357 * to stop it overwriting our objects */ 2358 rv515_vga_render_disable(rdev); 2359} 2360 2361/* SI MC address space is 40 bits */ 2362static void si_vram_location(struct radeon_device *rdev, 2363 struct radeon_mc *mc, u64 base) 2364{ 2365 mc->vram_start = base; 2366 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) { 2367 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 2368 mc->real_vram_size = mc->aper_size; 2369 mc->mc_vram_size = mc->aper_size; 2370 } 2371 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 2372 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n", 2373 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, 2374 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); 2375} 2376 2377static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 2378{ 2379 u64 size_af, size_bf; 2380 2381 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 2382 size_bf = mc->vram_start & ~mc->gtt_base_align; 2383 if (size_bf > size_af) { 2384 if (mc->gtt_size > size_bf) { 2385 dev_warn(rdev->dev, "limiting GTT\n"); 2386 mc->gtt_size = size_bf; 2387 } 2388 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 2389 } else { 2390 if (mc->gtt_size > size_af) { 2391 dev_warn(rdev->dev, "limiting GTT\n"); 2392 mc->gtt_size = size_af; 2393 } 2394 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 2395 } 2396 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 2397 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n", 2398 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end); 2399} 2400 2401static void si_vram_gtt_location(struct radeon_device *rdev, 2402 struct radeon_mc *mc) 2403{ 2404 if (mc->mc_vram_size > 0xFFC0000000ULL) { 2405 /* leave room for at least 1024M GTT */ 2406 dev_warn(rdev->dev, "limiting VRAM\n"); 2407 mc->real_vram_size = 0xFFC0000000ULL; 2408 mc->mc_vram_size = 0xFFC0000000ULL; 2409 } 2410 si_vram_location(rdev, &rdev->mc, 0); 2411 rdev->mc.gtt_base_align = 0; 2412 si_gtt_location(rdev, mc); 2413} 2414 2415static int si_mc_init(struct radeon_device *rdev) 2416{ 2417 u32 tmp; 2418 int chansize, numchan; 2419 2420 /* Get VRAM informations */ 2421 rdev->mc.vram_is_ddr = true; 2422 tmp = RREG32(MC_ARB_RAMCFG); 2423 if (tmp & CHANSIZE_OVERRIDE) { 2424 chansize = 16; 2425 } else if (tmp & CHANSIZE_MASK) { 2426 chansize = 64; 2427 } else { 2428 chansize = 32; 2429 } 2430 tmp = RREG32(MC_SHARED_CHMAP); 2431 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2432 case 0: 2433 default: 2434 numchan = 1; 2435 break; 2436 case 1: 2437 numchan = 2; 2438 break; 2439 case 2: 2440 numchan = 4; 2441 break; 2442 case 3: 2443 numchan = 8; 2444 break; 2445 case 4: 2446 numchan = 3; 2447 break; 2448 case 5: 2449 numchan = 6; 2450 break; 2451 case 6: 2452 numchan = 10; 2453 break; 2454 case 7: 2455 numchan = 12; 2456 break; 2457 case 8: 2458 numchan = 16; 2459 break; 2460 } 2461 rdev->mc.vram_width = numchan * chansize; 2462 /* Could aper size report 0 ? */ 2463 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 2464 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 2465 /* size in MB on si */ 2466 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2467 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2468 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2469 si_vram_gtt_location(rdev, &rdev->mc); 2470 radeon_update_bandwidth_info(rdev); 2471 2472 return 0; 2473} 2474 2475/* 2476 * GART 2477 */ 2478void si_pcie_gart_tlb_flush(struct radeon_device *rdev) 2479{ 2480 /* flush hdp cache */ 2481 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 2482 2483 /* bits 0-15 are the VM contexts0-15 */ 2484 WREG32(VM_INVALIDATE_REQUEST, 1); 2485} 2486 2487static int si_pcie_gart_enable(struct radeon_device *rdev) 2488{ 2489 int r, i; 2490 2491 if (rdev->gart.robj == NULL) { 2492 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 2493 return -EINVAL; 2494 } 2495 r = radeon_gart_table_vram_pin(rdev); 2496 if (r) 2497 return r; 2498 radeon_gart_restore(rdev); 2499 /* Setup TLB control */ 2500 WREG32(MC_VM_MX_L1_TLB_CNTL, 2501 (0xA << 7) | 2502 ENABLE_L1_TLB | 2503 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2504 ENABLE_ADVANCED_DRIVER_MODEL | 2505 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2506 /* Setup L2 cache */ 2507 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 2508 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2509 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2510 EFFECTIVE_L2_QUEUE_SIZE(7) | 2511 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2512 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 2513 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2514 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2515 /* setup context0 */ 2516 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 2517 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 2518 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 2519 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 2520 (u32)(rdev->dummy_page.addr >> 12)); 2521 WREG32(VM_CONTEXT0_CNTL2, 0); 2522 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 2523 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 2524 2525 WREG32(0x15D4, 0); 2526 WREG32(0x15D8, 0); 2527 WREG32(0x15DC, 0); 2528 2529 /* empty context1-15 */ 2530 /* set vm size, must be a multiple of 4 */ 2531 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2532 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2533 /* Assign the pt base to something valid for now; the pts used for 2534 * the VMs are determined by the application and setup and assigned 2535 * on the fly in the vm part of radeon_gart.c 2536 */ 2537 for (i = 1; i < 16; i++) { 2538 if (i < 8) 2539 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2540 rdev->gart.table_addr >> 12); 2541 else 2542 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), 2543 rdev->gart.table_addr >> 12); 2544 } 2545 2546 /* enable context1-15 */ 2547 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2548 (u32)(rdev->dummy_page.addr >> 12)); 2549 WREG32(VM_CONTEXT1_CNTL2, 4); 2550 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 2551 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2552 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2553 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2554 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2555 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 2556 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 2557 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 2558 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 2559 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 2560 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 2561 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2562 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 2563 2564 si_pcie_gart_tlb_flush(rdev); 2565 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 2566 (unsigned)(rdev->mc.gtt_size >> 20), 2567 (unsigned long long)rdev->gart.table_addr); 2568 rdev->gart.ready = true; 2569 return 0; 2570} 2571 2572static void si_pcie_gart_disable(struct radeon_device *rdev) 2573{ 2574 /* Disable all tables */ 2575 WREG32(VM_CONTEXT0_CNTL, 0); 2576 WREG32(VM_CONTEXT1_CNTL, 0); 2577 /* Setup TLB control */ 2578 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2579 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2580 /* Setup L2 cache */ 2581 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2582 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2583 EFFECTIVE_L2_QUEUE_SIZE(7) | 2584 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2585 WREG32(VM_L2_CNTL2, 0); 2586 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2587 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2588 radeon_gart_table_vram_unpin(rdev); 2589} 2590 2591static void si_pcie_gart_fini(struct radeon_device *rdev) 2592{ 2593 si_pcie_gart_disable(rdev); 2594 radeon_gart_table_vram_free(rdev); 2595 radeon_gart_fini(rdev); 2596} 2597 2598/* vm parser */ 2599static bool si_vm_reg_valid(u32 reg) 2600{ 2601 /* context regs are fine */ 2602 if (reg >= 0x28000) 2603 return true; 2604 2605 /* check config regs */ 2606 switch (reg) { 2607 case GRBM_GFX_INDEX: 2608 case CP_STRMOUT_CNTL: 2609 case VGT_VTX_VECT_EJECT_REG: 2610 case VGT_CACHE_INVALIDATION: 2611 case VGT_ESGS_RING_SIZE: 2612 case VGT_GSVS_RING_SIZE: 2613 case VGT_GS_VERTEX_REUSE: 2614 case VGT_PRIMITIVE_TYPE: 2615 case VGT_INDEX_TYPE: 2616 case VGT_NUM_INDICES: 2617 case VGT_NUM_INSTANCES: 2618 case VGT_TF_RING_SIZE: 2619 case VGT_HS_OFFCHIP_PARAM: 2620 case VGT_TF_MEMORY_BASE: 2621 case PA_CL_ENHANCE: 2622 case PA_SU_LINE_STIPPLE_VALUE: 2623 case PA_SC_LINE_STIPPLE_STATE: 2624 case PA_SC_ENHANCE: 2625 case SQC_CACHES: 2626 case SPI_STATIC_THREAD_MGMT_1: 2627 case SPI_STATIC_THREAD_MGMT_2: 2628 case SPI_STATIC_THREAD_MGMT_3: 2629 case SPI_PS_MAX_WAVE_ID: 2630 case SPI_CONFIG_CNTL: 2631 case SPI_CONFIG_CNTL_1: 2632 case TA_CNTL_AUX: 2633 return true; 2634 default: 2635 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 2636 return false; 2637 } 2638} 2639 2640static int si_vm_packet3_ce_check(struct radeon_device *rdev, 2641 u32 *ib, struct radeon_cs_packet *pkt) 2642{ 2643 switch (pkt->opcode) { 2644 case PACKET3_NOP: 2645 case PACKET3_SET_BASE: 2646 case PACKET3_SET_CE_DE_COUNTERS: 2647 case PACKET3_LOAD_CONST_RAM: 2648 case PACKET3_WRITE_CONST_RAM: 2649 case PACKET3_WRITE_CONST_RAM_OFFSET: 2650 case PACKET3_DUMP_CONST_RAM: 2651 case PACKET3_INCREMENT_CE_COUNTER: 2652 case PACKET3_WAIT_ON_DE_COUNTER: 2653 case PACKET3_CE_WRITE: 2654 break; 2655 default: 2656 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); 2657 return -EINVAL; 2658 } 2659 return 0; 2660} 2661 2662static int si_vm_packet3_gfx_check(struct radeon_device *rdev, 2663 u32 *ib, struct radeon_cs_packet *pkt) 2664{ 2665 u32 idx = pkt->idx + 1; 2666 u32 idx_value = ib[idx]; 2667 u32 start_reg, end_reg, reg, i; 2668 u32 command, info; 2669 2670 switch (pkt->opcode) { 2671 case PACKET3_NOP: 2672 case PACKET3_SET_BASE: 2673 case PACKET3_CLEAR_STATE: 2674 case PACKET3_INDEX_BUFFER_SIZE: 2675 case PACKET3_DISPATCH_DIRECT: 2676 case PACKET3_DISPATCH_INDIRECT: 2677 case PACKET3_ALLOC_GDS: 2678 case PACKET3_WRITE_GDS_RAM: 2679 case PACKET3_ATOMIC_GDS: 2680 case PACKET3_ATOMIC: 2681 case PACKET3_OCCLUSION_QUERY: 2682 case PACKET3_SET_PREDICATION: 2683 case PACKET3_COND_EXEC: 2684 case PACKET3_PRED_EXEC: 2685 case PACKET3_DRAW_INDIRECT: 2686 case PACKET3_DRAW_INDEX_INDIRECT: 2687 case PACKET3_INDEX_BASE: 2688 case PACKET3_DRAW_INDEX_2: 2689 case PACKET3_CONTEXT_CONTROL: 2690 case PACKET3_INDEX_TYPE: 2691 case PACKET3_DRAW_INDIRECT_MULTI: 2692 case PACKET3_DRAW_INDEX_AUTO: 2693 case PACKET3_DRAW_INDEX_IMMD: 2694 case PACKET3_NUM_INSTANCES: 2695 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2696 case PACKET3_STRMOUT_BUFFER_UPDATE: 2697 case PACKET3_DRAW_INDEX_OFFSET_2: 2698 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 2699 case PACKET3_DRAW_INDEX_INDIRECT_MULTI: 2700 case PACKET3_MPEG_INDEX: 2701 case PACKET3_WAIT_REG_MEM: 2702 case PACKET3_MEM_WRITE: 2703 case PACKET3_PFP_SYNC_ME: 2704 case PACKET3_SURFACE_SYNC: 2705 case PACKET3_EVENT_WRITE: 2706 case PACKET3_EVENT_WRITE_EOP: 2707 case PACKET3_EVENT_WRITE_EOS: 2708 case PACKET3_SET_CONTEXT_REG: 2709 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2710 case PACKET3_SET_SH_REG: 2711 case PACKET3_SET_SH_REG_OFFSET: 2712 case PACKET3_INCREMENT_DE_COUNTER: 2713 case PACKET3_WAIT_ON_CE_COUNTER: 2714 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2715 case PACKET3_ME_WRITE: 2716 break; 2717 case PACKET3_COPY_DATA: 2718 if ((idx_value & 0xf00) == 0) { 2719 reg = ib[idx + 3] * 4; 2720 if (!si_vm_reg_valid(reg)) 2721 return -EINVAL; 2722 } 2723 break; 2724 case PACKET3_WRITE_DATA: 2725 if ((idx_value & 0xf00) == 0) { 2726 start_reg = ib[idx + 1] * 4; 2727 if (idx_value & 0x10000) { 2728 if (!si_vm_reg_valid(start_reg)) 2729 return -EINVAL; 2730 } else { 2731 for (i = 0; i < (pkt->count - 2); i++) { 2732 reg = start_reg + (4 * i); 2733 if (!si_vm_reg_valid(reg)) 2734 return -EINVAL; 2735 } 2736 } 2737 } 2738 break; 2739 case PACKET3_COND_WRITE: 2740 if (idx_value & 0x100) { 2741 reg = ib[idx + 5] * 4; 2742 if (!si_vm_reg_valid(reg)) 2743 return -EINVAL; 2744 } 2745 break; 2746 case PACKET3_COPY_DW: 2747 if (idx_value & 0x2) { 2748 reg = ib[idx + 3] * 4; 2749 if (!si_vm_reg_valid(reg)) 2750 return -EINVAL; 2751 } 2752 break; 2753 case PACKET3_SET_CONFIG_REG: 2754 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2755 end_reg = 4 * pkt->count + start_reg - 4; 2756 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2757 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2758 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2759 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2760 return -EINVAL; 2761 } 2762 for (i = 0; i < pkt->count; i++) { 2763 reg = start_reg + (4 * i); 2764 if (!si_vm_reg_valid(reg)) 2765 return -EINVAL; 2766 } 2767 break; 2768 case PACKET3_CP_DMA: 2769 command = ib[idx + 4]; 2770 info = ib[idx + 1]; 2771 if (command & PACKET3_CP_DMA_CMD_SAS) { 2772 /* src address space is register */ 2773 if (((info & 0x60000000) >> 29) == 0) { 2774 start_reg = idx_value << 2; 2775 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2776 reg = start_reg; 2777 if (!si_vm_reg_valid(reg)) { 2778 DRM_ERROR("CP DMA Bad SRC register\n"); 2779 return -EINVAL; 2780 } 2781 } else { 2782 for (i = 0; i < (command & 0x1fffff); i++) { 2783 reg = start_reg + (4 * i); 2784 if (!si_vm_reg_valid(reg)) { 2785 DRM_ERROR("CP DMA Bad SRC register\n"); 2786 return -EINVAL; 2787 } 2788 } 2789 } 2790 } 2791 } 2792 if (command & PACKET3_CP_DMA_CMD_DAS) { 2793 /* dst address space is register */ 2794 if (((info & 0x00300000) >> 20) == 0) { 2795 start_reg = ib[idx + 2]; 2796 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2797 reg = start_reg; 2798 if (!si_vm_reg_valid(reg)) { 2799 DRM_ERROR("CP DMA Bad DST register\n"); 2800 return -EINVAL; 2801 } 2802 } else { 2803 for (i = 0; i < (command & 0x1fffff); i++) { 2804 reg = start_reg + (4 * i); 2805 if (!si_vm_reg_valid(reg)) { 2806 DRM_ERROR("CP DMA Bad DST register\n"); 2807 return -EINVAL; 2808 } 2809 } 2810 } 2811 } 2812 } 2813 break; 2814 default: 2815 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); 2816 return -EINVAL; 2817 } 2818 return 0; 2819} 2820 2821static int si_vm_packet3_compute_check(struct radeon_device *rdev, 2822 u32 *ib, struct radeon_cs_packet *pkt) 2823{ 2824 u32 idx = pkt->idx + 1; 2825 u32 idx_value = ib[idx]; 2826 u32 start_reg, reg, i; 2827 2828 switch (pkt->opcode) { 2829 case PACKET3_NOP: 2830 case PACKET3_SET_BASE: 2831 case PACKET3_CLEAR_STATE: 2832 case PACKET3_DISPATCH_DIRECT: 2833 case PACKET3_DISPATCH_INDIRECT: 2834 case PACKET3_ALLOC_GDS: 2835 case PACKET3_WRITE_GDS_RAM: 2836 case PACKET3_ATOMIC_GDS: 2837 case PACKET3_ATOMIC: 2838 case PACKET3_OCCLUSION_QUERY: 2839 case PACKET3_SET_PREDICATION: 2840 case PACKET3_COND_EXEC: 2841 case PACKET3_PRED_EXEC: 2842 case PACKET3_CONTEXT_CONTROL: 2843 case PACKET3_STRMOUT_BUFFER_UPDATE: 2844 case PACKET3_WAIT_REG_MEM: 2845 case PACKET3_MEM_WRITE: 2846 case PACKET3_PFP_SYNC_ME: 2847 case PACKET3_SURFACE_SYNC: 2848 case PACKET3_EVENT_WRITE: 2849 case PACKET3_EVENT_WRITE_EOP: 2850 case PACKET3_EVENT_WRITE_EOS: 2851 case PACKET3_SET_CONTEXT_REG: 2852 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2853 case PACKET3_SET_SH_REG: 2854 case PACKET3_SET_SH_REG_OFFSET: 2855 case PACKET3_INCREMENT_DE_COUNTER: 2856 case PACKET3_WAIT_ON_CE_COUNTER: 2857 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2858 case PACKET3_ME_WRITE: 2859 break; 2860 case PACKET3_COPY_DATA: 2861 if ((idx_value & 0xf00) == 0) { 2862 reg = ib[idx + 3] * 4; 2863 if (!si_vm_reg_valid(reg)) 2864 return -EINVAL; 2865 } 2866 break; 2867 case PACKET3_WRITE_DATA: 2868 if ((idx_value & 0xf00) == 0) { 2869 start_reg = ib[idx + 1] * 4; 2870 if (idx_value & 0x10000) { 2871 if (!si_vm_reg_valid(start_reg)) 2872 return -EINVAL; 2873 } else { 2874 for (i = 0; i < (pkt->count - 2); i++) { 2875 reg = start_reg + (4 * i); 2876 if (!si_vm_reg_valid(reg)) 2877 return -EINVAL; 2878 } 2879 } 2880 } 2881 break; 2882 case PACKET3_COND_WRITE: 2883 if (idx_value & 0x100) { 2884 reg = ib[idx + 5] * 4; 2885 if (!si_vm_reg_valid(reg)) 2886 return -EINVAL; 2887 } 2888 break; 2889 case PACKET3_COPY_DW: 2890 if (idx_value & 0x2) { 2891 reg = ib[idx + 3] * 4; 2892 if (!si_vm_reg_valid(reg)) 2893 return -EINVAL; 2894 } 2895 break; 2896 default: 2897 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); 2898 return -EINVAL; 2899 } 2900 return 0; 2901} 2902 2903int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 2904{ 2905 int ret = 0; 2906 u32 idx = 0; 2907 struct radeon_cs_packet pkt; 2908 2909 do { 2910 pkt.idx = idx; 2911 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 2912 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 2913 pkt.one_reg_wr = 0; 2914 switch (pkt.type) { 2915 case PACKET_TYPE0: 2916 dev_err(rdev->dev, "Packet0 not allowed!\n"); 2917 ret = -EINVAL; 2918 break; 2919 case PACKET_TYPE2: 2920 idx += 1; 2921 break; 2922 case PACKET_TYPE3: 2923 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2924 if (ib->is_const_ib) 2925 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 2926 else { 2927 switch (ib->ring) { 2928 case RADEON_RING_TYPE_GFX_INDEX: 2929 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); 2930 break; 2931 case CAYMAN_RING_TYPE_CP1_INDEX: 2932 case CAYMAN_RING_TYPE_CP2_INDEX: 2933 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); 2934 break; 2935 default: 2936 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); 2937 ret = -EINVAL; 2938 break; 2939 } 2940 } 2941 idx += pkt.count + 2; 2942 break; 2943 default: 2944 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 2945 ret = -EINVAL; 2946 break; 2947 } 2948 if (ret) 2949 break; 2950 } while (idx < ib->length_dw); 2951 2952 return ret; 2953} 2954 2955/* 2956 * vm 2957 */ 2958int si_vm_init(struct radeon_device *rdev) 2959{ 2960 /* number of VMs */ 2961 rdev->vm_manager.nvm = 16; 2962 /* base offset of vram pages */ 2963 rdev->vm_manager.vram_base_offset = 0; 2964 2965 return 0; 2966} 2967 2968void si_vm_fini(struct radeon_device *rdev) 2969{ 2970} 2971 2972/** 2973 * si_vm_set_page - update the page tables using the CP 2974 * 2975 * @rdev: radeon_device pointer 2976 * @pe: addr of the page entry 2977 * @addr: dst addr to write into pe 2978 * @count: number of page entries to update 2979 * @incr: increase next addr by incr bytes 2980 * @flags: access flags 2981 * 2982 * Update the page tables using the CP (cayman-si). 2983 */ 2984void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 2985 uint64_t addr, unsigned count, 2986 uint32_t incr, uint32_t flags) 2987{ 2988 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; 2989 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 2990 uint64_t value; 2991 unsigned ndw; 2992 2993 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { 2994 while (count) { 2995 ndw = 2 + count * 2; 2996 if (ndw > 0x3FFE) 2997 ndw = 0x3FFE; 2998 2999 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); 3000 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3001 WRITE_DATA_DST_SEL(1))); 3002 radeon_ring_write(ring, pe); 3003 radeon_ring_write(ring, upper_32_bits(pe)); 3004 for (; ndw > 2; ndw -= 2, --count, pe += 8) { 3005 if (flags & RADEON_VM_PAGE_SYSTEM) { 3006 value = radeon_vm_map_gart(rdev, addr); 3007 value &= 0xFFFFFFFFFFFFF000ULL; 3008 } else if (flags & RADEON_VM_PAGE_VALID) { 3009 value = addr; 3010 } else { 3011 value = 0; 3012 } 3013 addr += incr; 3014 value |= r600_flags; 3015 radeon_ring_write(ring, value); 3016 radeon_ring_write(ring, upper_32_bits(value)); 3017 } 3018 } 3019 } else { 3020 /* DMA */ 3021 if (flags & RADEON_VM_PAGE_SYSTEM) { 3022 while (count) { 3023 ndw = count * 2; 3024 if (ndw > 0xFFFFE) 3025 ndw = 0xFFFFE; 3026 3027 /* for non-physically contiguous pages (system) */ 3028 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw)); 3029 radeon_ring_write(ring, pe); 3030 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3031 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 3032 if (flags & RADEON_VM_PAGE_SYSTEM) { 3033 value = radeon_vm_map_gart(rdev, addr); 3034 value &= 0xFFFFFFFFFFFFF000ULL; 3035 } else if (flags & RADEON_VM_PAGE_VALID) { 3036 value = addr; 3037 } else { 3038 value = 0; 3039 } 3040 addr += incr; 3041 value |= r600_flags; 3042 radeon_ring_write(ring, value); 3043 radeon_ring_write(ring, upper_32_bits(value)); 3044 } 3045 } 3046 } else { 3047 while (count) { 3048 ndw = count * 2; 3049 if (ndw > 0xFFFFE) 3050 ndw = 0xFFFFE; 3051 3052 if (flags & RADEON_VM_PAGE_VALID) 3053 value = addr; 3054 else 3055 value = 0; 3056 /* for physically contiguous pages (vram) */ 3057 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw)); 3058 radeon_ring_write(ring, pe); /* dst addr */ 3059 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3060 radeon_ring_write(ring, r600_flags); /* mask */ 3061 radeon_ring_write(ring, 0); 3062 radeon_ring_write(ring, value); /* value */ 3063 radeon_ring_write(ring, upper_32_bits(value)); 3064 radeon_ring_write(ring, incr); /* increment size */ 3065 radeon_ring_write(ring, 0); 3066 pe += ndw * 4; 3067 addr += (ndw / 2) * incr; 3068 count -= ndw / 2; 3069 } 3070 } 3071 } 3072} 3073 3074void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3075{ 3076 struct radeon_ring *ring = &rdev->ring[ridx]; 3077 3078 if (vm == NULL) 3079 return; 3080 3081 /* write new base address */ 3082 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3083 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3084 WRITE_DATA_DST_SEL(0))); 3085 3086 if (vm->id < 8) { 3087 radeon_ring_write(ring, 3088 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 3089 } else { 3090 radeon_ring_write(ring, 3091 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 3092 } 3093 radeon_ring_write(ring, 0); 3094 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3095 3096 /* flush hdp cache */ 3097 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3098 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3099 WRITE_DATA_DST_SEL(0))); 3100 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 3101 radeon_ring_write(ring, 0); 3102 radeon_ring_write(ring, 0x1); 3103 3104 /* bits 0-15 are the VM contexts0-15 */ 3105 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3106 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3107 WRITE_DATA_DST_SEL(0))); 3108 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 3109 radeon_ring_write(ring, 0); 3110 radeon_ring_write(ring, 1 << vm->id); 3111 3112 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3113 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3114 radeon_ring_write(ring, 0x0); 3115} 3116 3117void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3118{ 3119 struct radeon_ring *ring = &rdev->ring[ridx]; 3120 3121 if (vm == NULL) 3122 return; 3123 3124 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3125 if (vm->id < 8) { 3126 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); 3127 } else { 3128 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2)); 3129 } 3130 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3131 3132 /* flush hdp cache */ 3133 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3134 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3135 radeon_ring_write(ring, 1); 3136 3137 /* bits 0-7 are the VM contexts0-7 */ 3138 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3139 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); 3140 radeon_ring_write(ring, 1 << vm->id); 3141} 3142 3143/* 3144 * RLC 3145 */ 3146void si_rlc_fini(struct radeon_device *rdev) 3147{ 3148 int r; 3149 3150 /* save restore block */ 3151 if (rdev->rlc.save_restore_obj) { 3152 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3153 if (unlikely(r != 0)) 3154 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); 3155 radeon_bo_unpin(rdev->rlc.save_restore_obj); 3156 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3157 3158 radeon_bo_unref(&rdev->rlc.save_restore_obj); 3159 rdev->rlc.save_restore_obj = NULL; 3160 } 3161 3162 /* clear state block */ 3163 if (rdev->rlc.clear_state_obj) { 3164 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3165 if (unlikely(r != 0)) 3166 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); 3167 radeon_bo_unpin(rdev->rlc.clear_state_obj); 3168 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3169 3170 radeon_bo_unref(&rdev->rlc.clear_state_obj); 3171 rdev->rlc.clear_state_obj = NULL; 3172 } 3173} 3174 3175int si_rlc_init(struct radeon_device *rdev) 3176{ 3177 int r; 3178 3179 /* save restore block */ 3180 if (rdev->rlc.save_restore_obj == NULL) { 3181 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3182 RADEON_GEM_DOMAIN_VRAM, NULL, 3183 &rdev->rlc.save_restore_obj); 3184 if (r) { 3185 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 3186 return r; 3187 } 3188 } 3189 3190 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3191 if (unlikely(r != 0)) { 3192 si_rlc_fini(rdev); 3193 return r; 3194 } 3195 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, 3196 &rdev->rlc.save_restore_gpu_addr); 3197 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3198 if (r) { 3199 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); 3200 si_rlc_fini(rdev); 3201 return r; 3202 } 3203 3204 /* clear state block */ 3205 if (rdev->rlc.clear_state_obj == NULL) { 3206 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3207 RADEON_GEM_DOMAIN_VRAM, NULL, 3208 &rdev->rlc.clear_state_obj); 3209 if (r) { 3210 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 3211 si_rlc_fini(rdev); 3212 return r; 3213 } 3214 } 3215 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3216 if (unlikely(r != 0)) { 3217 si_rlc_fini(rdev); 3218 return r; 3219 } 3220 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, 3221 &rdev->rlc.clear_state_gpu_addr); 3222 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3223 if (r) { 3224 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); 3225 si_rlc_fini(rdev); 3226 return r; 3227 } 3228 3229 return 0; 3230} 3231 3232static void si_rlc_stop(struct radeon_device *rdev) 3233{ 3234 WREG32(RLC_CNTL, 0); 3235} 3236 3237static void si_rlc_start(struct radeon_device *rdev) 3238{ 3239 WREG32(RLC_CNTL, RLC_ENABLE); 3240} 3241 3242static int si_rlc_resume(struct radeon_device *rdev) 3243{ 3244 u32 i; 3245 const __be32 *fw_data; 3246 3247 if (!rdev->rlc_fw) 3248 return -EINVAL; 3249 3250 si_rlc_stop(rdev); 3251 3252 WREG32(RLC_RL_BASE, 0); 3253 WREG32(RLC_RL_SIZE, 0); 3254 WREG32(RLC_LB_CNTL, 0); 3255 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 3256 WREG32(RLC_LB_CNTR_INIT, 0); 3257 3258 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3259 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3260 3261 WREG32(RLC_MC_CNTL, 0); 3262 WREG32(RLC_UCODE_CNTL, 0); 3263 3264 fw_data = (const __be32 *)rdev->rlc_fw->data; 3265 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { 3266 WREG32(RLC_UCODE_ADDR, i); 3267 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3268 } 3269 WREG32(RLC_UCODE_ADDR, 0); 3270 3271 si_rlc_start(rdev); 3272 3273 return 0; 3274} 3275 3276static void si_enable_interrupts(struct radeon_device *rdev) 3277{ 3278 u32 ih_cntl = RREG32(IH_CNTL); 3279 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3280 3281 ih_cntl |= ENABLE_INTR; 3282 ih_rb_cntl |= IH_RB_ENABLE; 3283 WREG32(IH_CNTL, ih_cntl); 3284 WREG32(IH_RB_CNTL, ih_rb_cntl); 3285 rdev->ih.enabled = true; 3286} 3287 3288static void si_disable_interrupts(struct radeon_device *rdev) 3289{ 3290 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3291 u32 ih_cntl = RREG32(IH_CNTL); 3292 3293 ih_rb_cntl &= ~IH_RB_ENABLE; 3294 ih_cntl &= ~ENABLE_INTR; 3295 WREG32(IH_RB_CNTL, ih_rb_cntl); 3296 WREG32(IH_CNTL, ih_cntl); 3297 /* set rptr, wptr to 0 */ 3298 WREG32(IH_RB_RPTR, 0); 3299 WREG32(IH_RB_WPTR, 0); 3300 rdev->ih.enabled = false; 3301 rdev->ih.rptr = 0; 3302} 3303 3304static void si_disable_interrupt_state(struct radeon_device *rdev) 3305{ 3306 u32 tmp; 3307 3308 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3309 WREG32(CP_INT_CNTL_RING1, 0); 3310 WREG32(CP_INT_CNTL_RING2, 0); 3311 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3312 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); 3313 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3314 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 3315 WREG32(GRBM_INT_CNTL, 0); 3316 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3317 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3318 if (rdev->num_crtc >= 4) { 3319 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3320 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3321 } 3322 if (rdev->num_crtc >= 6) { 3323 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3324 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3325 } 3326 3327 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3328 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3329 if (rdev->num_crtc >= 4) { 3330 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3331 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3332 } 3333 if (rdev->num_crtc >= 6) { 3334 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3335 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3336 } 3337 3338 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3339 3340 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3341 WREG32(DC_HPD1_INT_CONTROL, tmp); 3342 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3343 WREG32(DC_HPD2_INT_CONTROL, tmp); 3344 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3345 WREG32(DC_HPD3_INT_CONTROL, tmp); 3346 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3347 WREG32(DC_HPD4_INT_CONTROL, tmp); 3348 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3349 WREG32(DC_HPD5_INT_CONTROL, tmp); 3350 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3351 WREG32(DC_HPD6_INT_CONTROL, tmp); 3352 3353} 3354 3355static int si_irq_init(struct radeon_device *rdev) 3356{ 3357 int ret = 0; 3358 int rb_bufsz; 3359 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3360 3361 /* allocate ring */ 3362 ret = r600_ih_ring_alloc(rdev); 3363 if (ret) 3364 return ret; 3365 3366 /* disable irqs */ 3367 si_disable_interrupts(rdev); 3368 3369 /* init rlc */ 3370 ret = si_rlc_resume(rdev); 3371 if (ret) { 3372 r600_ih_ring_fini(rdev); 3373 return ret; 3374 } 3375 3376 /* setup interrupt control */ 3377 /* set dummy read address to ring address */ 3378 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3379 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3380 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3381 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3382 */ 3383 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3384 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3385 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3386 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3387 3388 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3389 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3390 3391 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3392 IH_WPTR_OVERFLOW_CLEAR | 3393 (rb_bufsz << 1)); 3394 3395 if (rdev->wb.enabled) 3396 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3397 3398 /* set the writeback address whether it's enabled or not */ 3399 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3400 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3401 3402 WREG32(IH_RB_CNTL, ih_rb_cntl); 3403 3404 /* set rptr, wptr to 0 */ 3405 WREG32(IH_RB_RPTR, 0); 3406 WREG32(IH_RB_WPTR, 0); 3407 3408 /* Default settings for IH_CNTL (disabled at first) */ 3409 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 3410 /* RPTR_REARM only works if msi's are enabled */ 3411 if (rdev->msi_enabled) 3412 ih_cntl |= RPTR_REARM; 3413 WREG32(IH_CNTL, ih_cntl); 3414 3415 /* force the active interrupt state to all disabled */ 3416 si_disable_interrupt_state(rdev); 3417 3418 pci_enable_busmaster(rdev->dev); 3419 3420 /* enable irqs */ 3421 si_enable_interrupts(rdev); 3422 3423 return ret; 3424} 3425 3426int si_irq_set(struct radeon_device *rdev) 3427{ 3428 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3429 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 3430 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 3431 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 3432 u32 grbm_int_cntl = 0; 3433 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 3434 u32 dma_cntl, dma_cntl1; 3435 3436 if (!rdev->irq.installed) { 3437 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 3438 return -EINVAL; 3439 } 3440 /* don't enable anything if the ih is disabled */ 3441 if (!rdev->ih.enabled) { 3442 si_disable_interrupts(rdev); 3443 /* force the active interrupt state to all disabled */ 3444 si_disable_interrupt_state(rdev); 3445 return 0; 3446 } 3447 3448 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3449 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3450 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3451 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3452 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3453 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3454 3455 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3456 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3457 3458 /* enable CP interrupts on all rings */ 3459 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3460 DRM_DEBUG("si_irq_set: sw int gfx\n"); 3461 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3462 } 3463 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { 3464 DRM_DEBUG("si_irq_set: sw int cp1\n"); 3465 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 3466 } 3467 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { 3468 DRM_DEBUG("si_irq_set: sw int cp2\n"); 3469 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 3470 } 3471 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3472 DRM_DEBUG("si_irq_set: sw int dma\n"); 3473 dma_cntl |= TRAP_ENABLE; 3474 } 3475 3476 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { 3477 DRM_DEBUG("si_irq_set: sw int dma1\n"); 3478 dma_cntl1 |= TRAP_ENABLE; 3479 } 3480 if (rdev->irq.crtc_vblank_int[0] || 3481 atomic_read(&rdev->irq.pflip[0])) { 3482 DRM_DEBUG("si_irq_set: vblank 0\n"); 3483 crtc1 |= VBLANK_INT_MASK; 3484 } 3485 if (rdev->irq.crtc_vblank_int[1] || 3486 atomic_read(&rdev->irq.pflip[1])) { 3487 DRM_DEBUG("si_irq_set: vblank 1\n"); 3488 crtc2 |= VBLANK_INT_MASK; 3489 } 3490 if (rdev->irq.crtc_vblank_int[2] || 3491 atomic_read(&rdev->irq.pflip[2])) { 3492 DRM_DEBUG("si_irq_set: vblank 2\n"); 3493 crtc3 |= VBLANK_INT_MASK; 3494 } 3495 if (rdev->irq.crtc_vblank_int[3] || 3496 atomic_read(&rdev->irq.pflip[3])) { 3497 DRM_DEBUG("si_irq_set: vblank 3\n"); 3498 crtc4 |= VBLANK_INT_MASK; 3499 } 3500 if (rdev->irq.crtc_vblank_int[4] || 3501 atomic_read(&rdev->irq.pflip[4])) { 3502 DRM_DEBUG("si_irq_set: vblank 4\n"); 3503 crtc5 |= VBLANK_INT_MASK; 3504 } 3505 if (rdev->irq.crtc_vblank_int[5] || 3506 atomic_read(&rdev->irq.pflip[5])) { 3507 DRM_DEBUG("si_irq_set: vblank 5\n"); 3508 crtc6 |= VBLANK_INT_MASK; 3509 } 3510 if (rdev->irq.hpd[0]) { 3511 DRM_DEBUG("si_irq_set: hpd 1\n"); 3512 hpd1 |= DC_HPDx_INT_EN; 3513 } 3514 if (rdev->irq.hpd[1]) { 3515 DRM_DEBUG("si_irq_set: hpd 2\n"); 3516 hpd2 |= DC_HPDx_INT_EN; 3517 } 3518 if (rdev->irq.hpd[2]) { 3519 DRM_DEBUG("si_irq_set: hpd 3\n"); 3520 hpd3 |= DC_HPDx_INT_EN; 3521 } 3522 if (rdev->irq.hpd[3]) { 3523 DRM_DEBUG("si_irq_set: hpd 4\n"); 3524 hpd4 |= DC_HPDx_INT_EN; 3525 } 3526 if (rdev->irq.hpd[4]) { 3527 DRM_DEBUG("si_irq_set: hpd 5\n"); 3528 hpd5 |= DC_HPDx_INT_EN; 3529 } 3530 if (rdev->irq.hpd[5]) { 3531 DRM_DEBUG("si_irq_set: hpd 6\n"); 3532 hpd6 |= DC_HPDx_INT_EN; 3533 } 3534 3535 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3536 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); 3537 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); 3538 3539 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); 3540 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); 3541 3542 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3543 3544 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 3545 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 3546 if (rdev->num_crtc >= 4) { 3547 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 3548 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 3549 } 3550 if (rdev->num_crtc >= 6) { 3551 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 3552 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 3553 } 3554 3555 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 3556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 3557 if (rdev->num_crtc >= 4) { 3558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 3559 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 3560 } 3561 if (rdev->num_crtc >= 6) { 3562 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 3563 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 3564 } 3565 3566 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3567 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3568 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3569 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3570 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3571 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3572 3573 return 0; 3574} 3575 3576static inline void si_irq_ack(struct radeon_device *rdev) 3577{ 3578 u32 tmp; 3579 3580 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3581 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3582 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 3583 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 3584 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 3585 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 3586 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 3587 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 3588 if (rdev->num_crtc >= 4) { 3589 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 3590 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 3591 } 3592 if (rdev->num_crtc >= 6) { 3593 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 3594 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 3595 } 3596 3597 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 3598 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3599 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 3600 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 3602 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 3603 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 3604 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 3605 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 3606 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 3607 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 3608 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 3609 3610 if (rdev->num_crtc >= 4) { 3611 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 3612 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3613 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 3614 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3615 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 3616 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 3617 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 3618 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 3619 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 3620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 3621 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 3622 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 3623 } 3624 3625 if (rdev->num_crtc >= 6) { 3626 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 3627 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3628 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 3629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3630 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 3631 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 3632 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 3633 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 3634 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 3635 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 3636 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 3637 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 3638 } 3639 3640 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3641 tmp = RREG32(DC_HPD1_INT_CONTROL); 3642 tmp |= DC_HPDx_INT_ACK; 3643 WREG32(DC_HPD1_INT_CONTROL, tmp); 3644 } 3645 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3646 tmp = RREG32(DC_HPD2_INT_CONTROL); 3647 tmp |= DC_HPDx_INT_ACK; 3648 WREG32(DC_HPD2_INT_CONTROL, tmp); 3649 } 3650 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3651 tmp = RREG32(DC_HPD3_INT_CONTROL); 3652 tmp |= DC_HPDx_INT_ACK; 3653 WREG32(DC_HPD3_INT_CONTROL, tmp); 3654 } 3655 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3656 tmp = RREG32(DC_HPD4_INT_CONTROL); 3657 tmp |= DC_HPDx_INT_ACK; 3658 WREG32(DC_HPD4_INT_CONTROL, tmp); 3659 } 3660 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3661 tmp = RREG32(DC_HPD5_INT_CONTROL); 3662 tmp |= DC_HPDx_INT_ACK; 3663 WREG32(DC_HPD5_INT_CONTROL, tmp); 3664 } 3665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3666 tmp = RREG32(DC_HPD5_INT_CONTROL); 3667 tmp |= DC_HPDx_INT_ACK; 3668 WREG32(DC_HPD6_INT_CONTROL, tmp); 3669 } 3670} 3671 3672static void si_irq_disable(struct radeon_device *rdev) 3673{ 3674 si_disable_interrupts(rdev); 3675 /* Wait and acknowledge irq */ 3676 mdelay(1); 3677 si_irq_ack(rdev); 3678 si_disable_interrupt_state(rdev); 3679} 3680 3681static void si_irq_suspend(struct radeon_device *rdev) 3682{ 3683 si_irq_disable(rdev); 3684 si_rlc_stop(rdev); 3685} 3686 3687static void si_irq_fini(struct radeon_device *rdev) 3688{ 3689 si_irq_suspend(rdev); 3690 r600_ih_ring_fini(rdev); 3691} 3692 3693static inline u32 si_get_ih_wptr(struct radeon_device *rdev) 3694{ 3695 u32 wptr, tmp; 3696 3697 if (rdev->wb.enabled) 3698 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3699 else 3700 wptr = RREG32(IH_RB_WPTR); 3701 3702 if (wptr & RB_OVERFLOW) { 3703 /* When a ring buffer overflow happen start parsing interrupt 3704 * from the last not overwritten vector (wptr + 16). Hopefully 3705 * this should allow us to catchup. 3706 */ 3707 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3708 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3709 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3710 tmp = RREG32(IH_RB_CNTL); 3711 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3712 WREG32(IH_RB_CNTL, tmp); 3713 } 3714 return (wptr & rdev->ih.ptr_mask); 3715} 3716 3717/* SI IV Ring 3718 * Each IV ring entry is 128 bits: 3719 * [7:0] - interrupt source id 3720 * [31:8] - reserved 3721 * [59:32] - interrupt source data 3722 * [63:60] - reserved 3723 * [71:64] - RINGID 3724 * [79:72] - VMID 3725 * [127:80] - reserved 3726 */ 3727irqreturn_t si_irq_process(struct radeon_device *rdev) 3728{ 3729 u32 wptr; 3730 u32 rptr; 3731 u32 src_id, src_data, ring_id; 3732 u32 ring_index; 3733 bool queue_hotplug = false; 3734 3735 if (!rdev->ih.enabled || rdev->shutdown) 3736 return IRQ_NONE; 3737 3738 wptr = si_get_ih_wptr(rdev); 3739 3740restart_ih: 3741 /* is somebody else already processing irqs? */ 3742 if (atomic_xchg(&rdev->ih.lock, 1)) 3743 return IRQ_NONE; 3744 3745 rptr = rdev->ih.rptr; 3746 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3747 3748 /* Order reading of wptr vs. reading of IH ring data */ 3749 rmb(); 3750 3751 /* display interrupts */ 3752 si_irq_ack(rdev); 3753 3754 while (rptr != wptr) { 3755 /* wptr/rptr are in bytes! */ 3756 ring_index = rptr / 4; 3757 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3758 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3759 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; 3760 3761 switch (src_id) { 3762 case 1: /* D1 vblank/vline */ 3763 switch (src_data) { 3764 case 0: /* D1 vblank */ 3765 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 3766 if (rdev->irq.crtc_vblank_int[0]) { 3767 drm_handle_vblank(rdev->ddev, 0); 3768 rdev->pm.vblank_sync = true; 3769 DRM_WAKEUP(&rdev->irq.vblank_queue); 3770 } 3771 if (atomic_read(&rdev->irq.pflip[0])) 3772 radeon_crtc_handle_flip(rdev, 0); 3773 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3774 DRM_DEBUG("IH: D1 vblank\n"); 3775 } 3776 break; 3777 case 1: /* D1 vline */ 3778 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 3779 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3780 DRM_DEBUG("IH: D1 vline\n"); 3781 } 3782 break; 3783 default: 3784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3785 break; 3786 } 3787 break; 3788 case 2: /* D2 vblank/vline */ 3789 switch (src_data) { 3790 case 0: /* D2 vblank */ 3791 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 3792 if (rdev->irq.crtc_vblank_int[1]) { 3793 drm_handle_vblank(rdev->ddev, 1); 3794 rdev->pm.vblank_sync = true; 3795 DRM_WAKEUP(&rdev->irq.vblank_queue); 3796 } 3797 if (atomic_read(&rdev->irq.pflip[1])) 3798 radeon_crtc_handle_flip(rdev, 1); 3799 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 3800 DRM_DEBUG("IH: D2 vblank\n"); 3801 } 3802 break; 3803 case 1: /* D2 vline */ 3804 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 3805 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 3806 DRM_DEBUG("IH: D2 vline\n"); 3807 } 3808 break; 3809 default: 3810 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3811 break; 3812 } 3813 break; 3814 case 3: /* D3 vblank/vline */ 3815 switch (src_data) { 3816 case 0: /* D3 vblank */ 3817 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 3818 if (rdev->irq.crtc_vblank_int[2]) { 3819 drm_handle_vblank(rdev->ddev, 2); 3820 rdev->pm.vblank_sync = true; 3821 DRM_WAKEUP(&rdev->irq.vblank_queue); 3822 } 3823 if (atomic_read(&rdev->irq.pflip[2])) 3824 radeon_crtc_handle_flip(rdev, 2); 3825 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 3826 DRM_DEBUG("IH: D3 vblank\n"); 3827 } 3828 break; 3829 case 1: /* D3 vline */ 3830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 3831 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 3832 DRM_DEBUG("IH: D3 vline\n"); 3833 } 3834 break; 3835 default: 3836 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3837 break; 3838 } 3839 break; 3840 case 4: /* D4 vblank/vline */ 3841 switch (src_data) { 3842 case 0: /* D4 vblank */ 3843 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 3844 if (rdev->irq.crtc_vblank_int[3]) { 3845 drm_handle_vblank(rdev->ddev, 3); 3846 rdev->pm.vblank_sync = true; 3847 DRM_WAKEUP(&rdev->irq.vblank_queue); 3848 } 3849 if (atomic_read(&rdev->irq.pflip[3])) 3850 radeon_crtc_handle_flip(rdev, 3); 3851 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 3852 DRM_DEBUG("IH: D4 vblank\n"); 3853 } 3854 break; 3855 case 1: /* D4 vline */ 3856 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 3857 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 3858 DRM_DEBUG("IH: D4 vline\n"); 3859 } 3860 break; 3861 default: 3862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3863 break; 3864 } 3865 break; 3866 case 5: /* D5 vblank/vline */ 3867 switch (src_data) { 3868 case 0: /* D5 vblank */ 3869 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 3870 if (rdev->irq.crtc_vblank_int[4]) { 3871 drm_handle_vblank(rdev->ddev, 4); 3872 rdev->pm.vblank_sync = true; 3873 DRM_WAKEUP(&rdev->irq.vblank_queue); 3874 } 3875 if (atomic_read(&rdev->irq.pflip[4])) 3876 radeon_crtc_handle_flip(rdev, 4); 3877 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 3878 DRM_DEBUG("IH: D5 vblank\n"); 3879 } 3880 break; 3881 case 1: /* D5 vline */ 3882 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 3883 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 3884 DRM_DEBUG("IH: D5 vline\n"); 3885 } 3886 break; 3887 default: 3888 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3889 break; 3890 } 3891 break; 3892 case 6: /* D6 vblank/vline */ 3893 switch (src_data) { 3894 case 0: /* D6 vblank */ 3895 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 3896 if (rdev->irq.crtc_vblank_int[5]) { 3897 drm_handle_vblank(rdev->ddev, 5); 3898 rdev->pm.vblank_sync = true; 3899 DRM_WAKEUP(&rdev->irq.vblank_queue); 3900 } 3901 if (atomic_read(&rdev->irq.pflip[5])) 3902 radeon_crtc_handle_flip(rdev, 5); 3903 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 3904 DRM_DEBUG("IH: D6 vblank\n"); 3905 } 3906 break; 3907 case 1: /* D6 vline */ 3908 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 3909 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 3910 DRM_DEBUG("IH: D6 vline\n"); 3911 } 3912 break; 3913 default: 3914 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3915 break; 3916 } 3917 break; 3918 case 42: /* HPD hotplug */ 3919 switch (src_data) { 3920 case 0: 3921 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3922 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 3923 queue_hotplug = true; 3924 DRM_DEBUG("IH: HPD1\n"); 3925 } 3926 break; 3927 case 1: 3928 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3929 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 3930 queue_hotplug = true; 3931 DRM_DEBUG("IH: HPD2\n"); 3932 } 3933 break; 3934 case 2: 3935 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3936 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 3937 queue_hotplug = true; 3938 DRM_DEBUG("IH: HPD3\n"); 3939 } 3940 break; 3941 case 3: 3942 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3943 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 3944 queue_hotplug = true; 3945 DRM_DEBUG("IH: HPD4\n"); 3946 } 3947 break; 3948 case 4: 3949 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3950 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 3951 queue_hotplug = true; 3952 DRM_DEBUG("IH: HPD5\n"); 3953 } 3954 break; 3955 case 5: 3956 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3957 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 3958 queue_hotplug = true; 3959 DRM_DEBUG("IH: HPD6\n"); 3960 } 3961 break; 3962 default: 3963 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3964 break; 3965 } 3966 break; 3967 case 146: 3968 case 147: 3969 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 3970 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 3971 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3972 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3973 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3974 /* reset addr and status */ 3975 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 3976 break; 3977 case 176: /* RINGID0 CP_INT */ 3978 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3979 break; 3980 case 177: /* RINGID1 CP_INT */ 3981 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3982 break; 3983 case 178: /* RINGID2 CP_INT */ 3984 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3985 break; 3986 case 181: /* CP EOP event */ 3987 DRM_DEBUG("IH: CP EOP\n"); 3988 switch (ring_id) { 3989 case 0: 3990 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3991 break; 3992 case 1: 3993 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3994 break; 3995 case 2: 3996 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3997 break; 3998 } 3999 break; 4000 case 224: /* DMA trap event */ 4001 DRM_DEBUG("IH: DMA trap\n"); 4002 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4003 break; 4004 case 233: /* GUI IDLE */ 4005 DRM_DEBUG("IH: GUI idle\n"); 4006 break; 4007 case 244: /* DMA trap event */ 4008 DRM_DEBUG("IH: DMA1 trap\n"); 4009 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4010 break; 4011 default: 4012 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4013 break; 4014 } 4015 4016 /* wptr/rptr are in bytes! */ 4017 rptr += 16; 4018 rptr &= rdev->ih.ptr_mask; 4019 } 4020 if (queue_hotplug) 4021 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 4022 rdev->ih.rptr = rptr; 4023 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4024 atomic_set(&rdev->ih.lock, 0); 4025 4026 /* make sure wptr hasn't changed while processing */ 4027 wptr = si_get_ih_wptr(rdev); 4028 if (wptr != rptr) 4029 goto restart_ih; 4030 4031 return IRQ_HANDLED; 4032} 4033 4034/** 4035 * si_copy_dma - copy pages using the DMA engine 4036 * 4037 * @rdev: radeon_device pointer 4038 * @src_offset: src GPU address 4039 * @dst_offset: dst GPU address 4040 * @num_gpu_pages: number of GPU pages to xfer 4041 * @fence: radeon fence object 4042 * 4043 * Copy GPU paging using the DMA engine (SI). 4044 * Used by the radeon ttm implementation to move pages if 4045 * registered as the asic copy callback. 4046 */ 4047int si_copy_dma(struct radeon_device *rdev, 4048 uint64_t src_offset, uint64_t dst_offset, 4049 unsigned num_gpu_pages, 4050 struct radeon_fence **fence) 4051{ 4052 struct radeon_semaphore *sem = NULL; 4053 int ring_index = rdev->asic->copy.dma_ring_index; 4054 struct radeon_ring *ring = &rdev->ring[ring_index]; 4055 u32 size_in_bytes, cur_size_in_bytes; 4056 int i, num_loops; 4057 int r = 0; 4058 4059 r = radeon_semaphore_create(rdev, &sem); 4060 if (r) { 4061 DRM_ERROR("radeon: moving bo (%d).\n", r); 4062 return r; 4063 } 4064 4065 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 4066 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff); 4067 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); 4068 if (r) { 4069 DRM_ERROR("radeon: moving bo (%d).\n", r); 4070 radeon_semaphore_free(rdev, &sem, NULL); 4071 return r; 4072 } 4073 4074 if (radeon_fence_need_sync(*fence, ring->idx)) { 4075 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 4076 ring->idx); 4077 radeon_fence_note_sync(*fence, ring->idx); 4078 } else { 4079 radeon_semaphore_free(rdev, &sem, NULL); 4080 } 4081 4082 for (i = 0; i < num_loops; i++) { 4083 cur_size_in_bytes = size_in_bytes; 4084 if (cur_size_in_bytes > 0xFFFFF) 4085 cur_size_in_bytes = 0xFFFFF; 4086 size_in_bytes -= cur_size_in_bytes; 4087 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); 4088 radeon_ring_write(ring, dst_offset & 0xffffffff); 4089 radeon_ring_write(ring, src_offset & 0xffffffff); 4090 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 4091 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 4092 src_offset += cur_size_in_bytes; 4093 dst_offset += cur_size_in_bytes; 4094 } 4095 4096 r = radeon_fence_emit(rdev, fence, ring->idx); 4097 if (r) { 4098 radeon_ring_unlock_undo(rdev, ring); 4099 return r; 4100 } 4101 4102 radeon_ring_unlock_commit(rdev, ring); 4103 radeon_semaphore_free(rdev, &sem, *fence); 4104 4105 return r; 4106} 4107 4108/* 4109 * startup/shutdown callbacks 4110 */ 4111static int si_startup(struct radeon_device *rdev) 4112{ 4113 struct radeon_ring *ring; 4114 int r; 4115 4116 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 4117 !rdev->rlc_fw || !rdev->mc_fw) { 4118 r = si_init_microcode(rdev); 4119 if (r) { 4120 DRM_ERROR("Failed to load firmware!\n"); 4121 return r; 4122 } 4123 } 4124 4125 r = si_mc_load_microcode(rdev); 4126 if (r) { 4127 DRM_ERROR("Failed to load MC firmware!\n"); 4128 return r; 4129 } 4130 4131 r = r600_vram_scratch_init(rdev); 4132 if (r) 4133 return r; 4134 4135 si_mc_program(rdev); 4136 r = si_pcie_gart_enable(rdev); 4137 if (r) 4138 return r; 4139 si_gpu_init(rdev); 4140 4141#if 0 4142 r = evergreen_blit_init(rdev); 4143 if (r) { 4144 r600_blit_fini(rdev); 4145 rdev->asic->copy = NULL; 4146 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 4147 } 4148#endif 4149 /* allocate rlc buffers */ 4150 r = si_rlc_init(rdev); 4151 if (r) { 4152 DRM_ERROR("Failed to init rlc BOs!\n"); 4153 return r; 4154 } 4155 4156 /* allocate wb buffer */ 4157 r = radeon_wb_init(rdev); 4158 if (r) 4159 return r; 4160 4161 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 4162 if (r) { 4163 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4164 return r; 4165 } 4166 4167 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4168 if (r) { 4169 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4170 return r; 4171 } 4172 4173 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4174 if (r) { 4175 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4176 return r; 4177 } 4178 4179 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 4180 if (r) { 4181 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4182 return r; 4183 } 4184 4185 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4186 if (r) { 4187 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4188 return r; 4189 } 4190 4191 /* Enable IRQ */ 4192 r = si_irq_init(rdev); 4193 if (r) { 4194 DRM_ERROR("radeon: IH init failed (%d).\n", r); 4195 radeon_irq_kms_fini(rdev); 4196 return r; 4197 } 4198 si_irq_set(rdev); 4199 4200 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4201 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 4202 CP_RB0_RPTR, CP_RB0_WPTR, 4203 0, 0xfffff, RADEON_CP_PACKET2); 4204 if (r) 4205 return r; 4206 4207 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4208 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 4209 CP_RB1_RPTR, CP_RB1_WPTR, 4210 0, 0xfffff, RADEON_CP_PACKET2); 4211 if (r) 4212 return r; 4213 4214 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4215 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 4216 CP_RB2_RPTR, CP_RB2_WPTR, 4217 0, 0xfffff, RADEON_CP_PACKET2); 4218 if (r) 4219 return r; 4220 4221 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4222 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 4223 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, 4224 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, 4225 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4226 if (r) 4227 return r; 4228 4229 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4230 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 4231 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, 4232 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, 4233 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4234 if (r) 4235 return r; 4236 4237 r = si_cp_load_microcode(rdev); 4238 if (r) 4239 return r; 4240 r = si_cp_resume(rdev); 4241 if (r) 4242 return r; 4243 4244 r = cayman_dma_resume(rdev); 4245 if (r) 4246 return r; 4247 4248 r = radeon_ib_pool_init(rdev); 4249 if (r) { 4250 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4251 return r; 4252 } 4253 4254 r = radeon_vm_manager_init(rdev); 4255 if (r) { 4256 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 4257 return r; 4258 } 4259 4260 return 0; 4261} 4262 4263int si_resume(struct radeon_device *rdev) 4264{ 4265 int r; 4266 4267 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 4268 * posting will perform necessary task to bring back GPU into good 4269 * shape. 4270 */ 4271 /* post card */ 4272 atom_asic_init(rdev->mode_info.atom_context); 4273 4274 rdev->accel_working = true; 4275 r = si_startup(rdev); 4276 if (r) { 4277 DRM_ERROR("si startup failed on resume\n"); 4278 rdev->accel_working = false; 4279 return r; 4280 } 4281 4282 return r; 4283 4284} 4285 4286int si_suspend(struct radeon_device *rdev) 4287{ 4288 radeon_vm_manager_fini(rdev); 4289 si_cp_enable(rdev, false); 4290 cayman_dma_stop(rdev); 4291 si_irq_suspend(rdev); 4292 radeon_wb_disable(rdev); 4293 si_pcie_gart_disable(rdev); 4294 return 0; 4295} 4296 4297/* Plan is to move initialization in that function and use 4298 * helper function so that radeon_device_init pretty much 4299 * do nothing more than calling asic specific function. This 4300 * should also allow to remove a bunch of callback function 4301 * like vram_info. 4302 */ 4303int si_init(struct radeon_device *rdev) 4304{ 4305 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4306 int r; 4307 4308 /* Read BIOS */ 4309 if (!radeon_get_bios(rdev)) { 4310 if (ASIC_IS_AVIVO(rdev)) 4311 return -EINVAL; 4312 } 4313 /* Must be an ATOMBIOS */ 4314 if (!rdev->is_atom_bios) { 4315 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 4316 return -EINVAL; 4317 } 4318 r = radeon_atombios_init(rdev); 4319 if (r) 4320 return r; 4321 4322 /* Post card if necessary */ 4323 if (!radeon_card_posted(rdev)) { 4324 if (!rdev->bios) { 4325 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 4326 return -EINVAL; 4327 } 4328 DRM_INFO("GPU not posted. posting now...\n"); 4329 atom_asic_init(rdev->mode_info.atom_context); 4330 } 4331 /* Initialize scratch registers */ 4332 si_scratch_init(rdev); 4333 /* Initialize surface registers */ 4334 radeon_surface_init(rdev); 4335 /* Initialize clocks */ 4336 radeon_get_clock_info(rdev->ddev); 4337 4338 /* Fence driver */ 4339 r = radeon_fence_driver_init(rdev); 4340 if (r) 4341 return r; 4342 4343 /* initialize memory controller */ 4344 r = si_mc_init(rdev); 4345 if (r) 4346 return r; 4347 /* Memory manager */ 4348 r = radeon_bo_init(rdev); 4349 if (r) 4350 return r; 4351 4352 r = radeon_irq_kms_init(rdev); 4353 if (r) 4354 return r; 4355 4356 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4357 ring->ring_obj = NULL; 4358 r600_ring_init(rdev, ring, 1024 * 1024); 4359 4360 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4361 ring->ring_obj = NULL; 4362 r600_ring_init(rdev, ring, 1024 * 1024); 4363 4364 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4365 ring->ring_obj = NULL; 4366 r600_ring_init(rdev, ring, 1024 * 1024); 4367 4368 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4369 ring->ring_obj = NULL; 4370 r600_ring_init(rdev, ring, 64 * 1024); 4371 4372 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4373 ring->ring_obj = NULL; 4374 r600_ring_init(rdev, ring, 64 * 1024); 4375 4376 rdev->ih.ring_obj = NULL; 4377 r600_ih_ring_init(rdev, 64 * 1024); 4378 4379 r = r600_pcie_gart_init(rdev); 4380 if (r) 4381 return r; 4382 4383 rdev->accel_working = true; 4384 r = si_startup(rdev); 4385 if (r) { 4386 dev_err(rdev->dev, "disabling GPU acceleration\n"); 4387 si_cp_fini(rdev); 4388 cayman_dma_fini(rdev); 4389 si_irq_fini(rdev); 4390 si_rlc_fini(rdev); 4391 radeon_wb_fini(rdev); 4392 radeon_ib_pool_fini(rdev); 4393 radeon_vm_manager_fini(rdev); 4394 radeon_irq_kms_fini(rdev); 4395 si_pcie_gart_fini(rdev); 4396 rdev->accel_working = false; 4397 } 4398 4399 /* Don't start up if the MC ucode is missing. 4400 * The default clocks and voltages before the MC ucode 4401 * is loaded are not suffient for advanced operations. 4402 */ 4403 if (!rdev->mc_fw) { 4404 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 4405 return -EINVAL; 4406 } 4407 4408 return 0; 4409} 4410 4411void si_fini(struct radeon_device *rdev) 4412{ 4413#if 0 4414 r600_blit_fini(rdev); 4415#endif 4416 si_cp_fini(rdev); 4417 cayman_dma_fini(rdev); 4418 si_irq_fini(rdev); 4419 si_rlc_fini(rdev); 4420 radeon_wb_fini(rdev); 4421 radeon_vm_manager_fini(rdev); 4422 radeon_ib_pool_fini(rdev); 4423 radeon_irq_kms_fini(rdev); 4424 si_pcie_gart_fini(rdev); 4425 r600_vram_scratch_fini(rdev); 4426 radeon_gem_fini(rdev); 4427 radeon_fence_driver_fini(rdev); 4428 radeon_bo_fini(rdev); 4429 radeon_atombios_fini(rdev); 4430 si_fini_microcode(rdev); 4431 free(rdev->bios, DRM_MEM_DRIVER); 4432 rdev->bios = NULL; 4433} 4434 4435/** 4436 * si_get_gpu_clock - return GPU clock counter snapshot 4437 * 4438 * @rdev: radeon_device pointer 4439 * 4440 * Fetches a GPU clock counter snapshot (SI). 4441 * Returns the 64 bit clock counter snapshot. 4442 */ 4443uint64_t si_get_gpu_clock(struct radeon_device *rdev) 4444{ 4445 uint64_t clock; 4446 4447 sx_xlock(&rdev->gpu_clock_mutex); 4448 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4449 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4450 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4451 sx_xunlock(&rdev->gpu_clock_mutex); 4452 return clock; 4453} 4454