1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian K��nig 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/radeon/radeon_ring.c 282199 2015-04-28 19:35:05Z dumbbell $"); 32 33#include <dev/drm2/drmP.h> 34#include <dev/drm2/radeon/radeon_drm.h> 35#include "radeon_reg.h" 36#include "radeon.h" 37#include "atom.h" 38 39#ifdef FREEBSD_WIP 40/* 41 * IB 42 * IBs (Indirect Buffers) and areas of GPU accessible memory where 43 * commands are stored. You can put a pointer to the IB in the 44 * command ring and the hw will fetch the commands from the IB 45 * and execute them. Generally userspace acceleration drivers 46 * produce command buffers which are send to the kernel and 47 * put in IBs for execution by the requested ring. 48 */ 49static int radeon_debugfs_sa_init(struct radeon_device *rdev); 50#endif /* FREEBSD_WIP */ 51 52/** 53 * radeon_ib_get - request an IB (Indirect Buffer) 54 * 55 * @rdev: radeon_device pointer 56 * @ring: ring index the IB is associated with 57 * @ib: IB object returned 58 * @size: requested IB size 59 * 60 * Request an IB (all asics). IBs are allocated using the 61 * suballocator. 62 * Returns 0 on success, error on failure. 63 */ 64int radeon_ib_get(struct radeon_device *rdev, int ring, 65 struct radeon_ib *ib, struct radeon_vm *vm, 66 unsigned size) 67{ 68 int i, r; 69 70 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); 71 if (r) { 72 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); 73 return r; 74 } 75 76 r = radeon_semaphore_create(rdev, &ib->semaphore); 77 if (r) { 78 return r; 79 } 80 81 ib->ring = ring; 82 ib->fence = NULL; 83 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); 84 ib->vm = vm; 85 if (vm) { 86 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address 87 * space and soffset is the offset inside the pool bo 88 */ 89 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; 90 } else { 91 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); 92 } 93 ib->is_const_ib = false; 94 for (i = 0; i < RADEON_NUM_RINGS; ++i) 95 ib->sync_to[i] = NULL; 96 97 return 0; 98} 99 100/** 101 * radeon_ib_free - free an IB (Indirect Buffer) 102 * 103 * @rdev: radeon_device pointer 104 * @ib: IB object to free 105 * 106 * Free an IB (all asics). 107 */ 108void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) 109{ 110 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); 111 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); 112 radeon_fence_unref(&ib->fence); 113} 114 115/** 116 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 117 * 118 * @rdev: radeon_device pointer 119 * @ib: IB object to schedule 120 * @const_ib: Const IB to schedule (SI only) 121 * 122 * Schedule an IB on the associated ring (all asics). 123 * Returns 0 on success, error on failure. 124 * 125 * On SI, there are two parallel engines fed from the primary ring, 126 * the CE (Constant Engine) and the DE (Drawing Engine). Since 127 * resource descriptors have moved to memory, the CE allows you to 128 * prime the caches while the DE is updating register state so that 129 * the resource descriptors will be already in cache when the draw is 130 * processed. To accomplish this, the userspace driver submits two 131 * IBs, one for the CE and one for the DE. If there is a CE IB (called 132 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 133 * to SI there was just a DE IB. 134 */ 135int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 136 struct radeon_ib *const_ib) 137{ 138 struct radeon_ring *ring = &rdev->ring[ib->ring]; 139 bool need_sync = false; 140 int i, r = 0; 141 142 if (!ib->length_dw || !ring->ready) { 143 /* TODO: Nothings in the ib we should report. */ 144 dev_err(rdev->dev, "couldn't schedule ib\n"); 145 return -EINVAL; 146 } 147 148 /* 64 dwords should be enough for fence too */ 149 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); 150 if (r) { 151 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 152 return r; 153 } 154 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 155 struct radeon_fence *fence = ib->sync_to[i]; 156 if (radeon_fence_need_sync(fence, ib->ring)) { 157 need_sync = true; 158 radeon_semaphore_sync_rings(rdev, ib->semaphore, 159 fence->ring, ib->ring); 160 radeon_fence_note_sync(fence, ib->ring); 161 } 162 } 163 /* immediately free semaphore when we don't need to sync */ 164 if (!need_sync) { 165 radeon_semaphore_free(rdev, &ib->semaphore, NULL); 166 } 167 /* if we can't remember our last VM flush then flush now! */ 168 /* XXX figure out why we have to flush for every IB */ 169 if (ib->vm /*&& !ib->vm->last_flush*/) { 170 radeon_ring_vm_flush(rdev, ib->ring, ib->vm); 171 } 172 if (const_ib) { 173 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); 174 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); 175 } 176 radeon_ring_ib_execute(rdev, ib->ring, ib); 177 r = radeon_fence_emit(rdev, &ib->fence, ib->ring); 178 if (r) { 179 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); 180 radeon_ring_unlock_undo(rdev, ring); 181 return r; 182 } 183 if (const_ib) { 184 const_ib->fence = radeon_fence_ref(ib->fence); 185 } 186 /* we just flushed the VM, remember that */ 187 if (ib->vm && !ib->vm->last_flush) { 188 ib->vm->last_flush = radeon_fence_ref(ib->fence); 189 } 190 radeon_ring_unlock_commit(rdev, ring); 191 return 0; 192} 193 194/** 195 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool 196 * 197 * @rdev: radeon_device pointer 198 * 199 * Initialize the suballocator to manage a pool of memory 200 * for use as IBs (all asics). 201 * Returns 0 on success, error on failure. 202 */ 203int radeon_ib_pool_init(struct radeon_device *rdev) 204{ 205 int r; 206 207 if (rdev->ib_pool_ready) { 208 return 0; 209 } 210 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 211 RADEON_IB_POOL_SIZE*64*1024, 212 RADEON_GEM_DOMAIN_GTT); 213 if (r) { 214 return r; 215 } 216 217 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); 218 if (r) { 219 return r; 220 } 221 222 rdev->ib_pool_ready = true; 223#ifdef FREEBSD_WIP 224 if (radeon_debugfs_sa_init(rdev)) { 225 dev_err(rdev->dev, "failed to register debugfs file for SA\n"); 226 } 227#endif /* FREEBSD_WIP */ 228 return 0; 229} 230 231/** 232 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool 233 * 234 * @rdev: radeon_device pointer 235 * 236 * Tear down the suballocator managing the pool of memory 237 * for use as IBs (all asics). 238 */ 239void radeon_ib_pool_fini(struct radeon_device *rdev) 240{ 241 if (rdev->ib_pool_ready) { 242 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); 243 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); 244 rdev->ib_pool_ready = false; 245 } 246} 247 248/** 249 * radeon_ib_ring_tests - test IBs on the rings 250 * 251 * @rdev: radeon_device pointer 252 * 253 * Test an IB (Indirect Buffer) on each ring. 254 * If the test fails, disable the ring. 255 * Returns 0 on success, error if the primary GFX ring 256 * IB test fails. 257 */ 258int radeon_ib_ring_tests(struct radeon_device *rdev) 259{ 260 unsigned i; 261 int r; 262 263 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 264 struct radeon_ring *ring = &rdev->ring[i]; 265 266 if (!ring->ready) 267 continue; 268 269 r = radeon_ib_test(rdev, i, ring); 270 if (r) { 271 ring->ready = false; 272 273 if (i == RADEON_RING_TYPE_GFX_INDEX) { 274 /* oh, oh, that's really bad */ 275 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); 276 rdev->accel_working = false; 277 return r; 278 279 } else { 280 /* still not good, but we can live with it */ 281 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); 282 } 283 } 284 } 285 return 0; 286} 287 288#ifdef FREEBSD_WIP 289/* 290 * Rings 291 * Most engines on the GPU are fed via ring buffers. Ring 292 * buffers are areas of GPU accessible memory that the host 293 * writes commands into and the GPU reads commands out of. 294 * There is a rptr (read pointer) that determines where the 295 * GPU is currently reading, and a wptr (write pointer) 296 * which determines where the host has written. When the 297 * pointers are equal, the ring is idle. When the host 298 * writes commands to the ring buffer, it increments the 299 * wptr. The GPU then starts fetching commands and executes 300 * them until the pointers are equal again. 301 */ 302static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); 303#endif /* FREEBSD_WIP */ 304 305/** 306 * radeon_ring_write - write a value to the ring 307 * 308 * @ring: radeon_ring structure holding ring information 309 * @v: dword (dw) value to write 310 * 311 * Write a value to the requested ring buffer (all asics). 312 */ 313void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 314{ 315#if DRM_DEBUG_CODE 316 if (ring->count_dw <= 0) { 317 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 318 } 319#endif 320 ring->ring[ring->wptr++] = v; 321 ring->wptr &= ring->ptr_mask; 322 ring->count_dw--; 323 ring->ring_free_dw--; 324} 325 326/** 327 * radeon_ring_supports_scratch_reg - check if the ring supports 328 * writing to scratch registers 329 * 330 * @rdev: radeon_device pointer 331 * @ring: radeon_ring structure holding ring information 332 * 333 * Check if a specific ring supports writing to scratch registers (all asics). 334 * Returns true if the ring supports writing to scratch regs, false if not. 335 */ 336bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 337 struct radeon_ring *ring) 338{ 339 switch (ring->idx) { 340 case RADEON_RING_TYPE_GFX_INDEX: 341 case CAYMAN_RING_TYPE_CP1_INDEX: 342 case CAYMAN_RING_TYPE_CP2_INDEX: 343 return true; 344 default: 345 return false; 346 } 347} 348 349/** 350 * radeon_ring_free_size - update the free size 351 * 352 * @rdev: radeon_device pointer 353 * @ring: radeon_ring structure holding ring information 354 * 355 * Update the free dw slots in the ring buffer (all asics). 356 */ 357void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) 358{ 359 u32 rptr; 360 361 if (rdev->wb.enabled) 362 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 363 else 364 rptr = RREG32(ring->rptr_reg); 365 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 366 /* This works because ring_size is a power of 2 */ 367 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); 368 ring->ring_free_dw -= ring->wptr; 369 ring->ring_free_dw &= ring->ptr_mask; 370 if (!ring->ring_free_dw) { 371 ring->ring_free_dw = ring->ring_size / 4; 372 } 373} 374 375/** 376 * radeon_ring_alloc - allocate space on the ring buffer 377 * 378 * @rdev: radeon_device pointer 379 * @ring: radeon_ring structure holding ring information 380 * @ndw: number of dwords to allocate in the ring buffer 381 * 382 * Allocate @ndw dwords in the ring buffer (all asics). 383 * Returns 0 on success, error on failure. 384 */ 385int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 386{ 387 int r; 388 389 /* make sure we aren't trying to allocate more space than there is on the ring */ 390 if (ndw > (ring->ring_size / 4)) 391 return -ENOMEM; 392 /* Align requested size with padding so unlock_commit can 393 * pad safely */ 394 ndw = (ndw + ring->align_mask) & ~ring->align_mask; 395 while (ndw > (ring->ring_free_dw - 1)) { 396 radeon_ring_free_size(rdev, ring); 397 if (ndw < ring->ring_free_dw) { 398 break; 399 } 400 r = radeon_fence_wait_next_locked(rdev, ring->idx); 401 if (r) 402 return r; 403 } 404 ring->count_dw = ndw; 405 ring->wptr_old = ring->wptr; 406 return 0; 407} 408 409/** 410 * radeon_ring_lock - lock the ring and allocate space on it 411 * 412 * @rdev: radeon_device pointer 413 * @ring: radeon_ring structure holding ring information 414 * @ndw: number of dwords to allocate in the ring buffer 415 * 416 * Lock the ring and allocate @ndw dwords in the ring buffer 417 * (all asics). 418 * Returns 0 on success, error on failure. 419 */ 420int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) 421{ 422 int r; 423 424 sx_xlock(&rdev->ring_lock); 425 r = radeon_ring_alloc(rdev, ring, ndw); 426 if (r) { 427 sx_xunlock(&rdev->ring_lock); 428 return r; 429 } 430 return 0; 431} 432 433/** 434 * radeon_ring_commit - tell the GPU to execute the new 435 * commands on the ring buffer 436 * 437 * @rdev: radeon_device pointer 438 * @ring: radeon_ring structure holding ring information 439 * 440 * Update the wptr (write pointer) to tell the GPU to 441 * execute new commands on the ring buffer (all asics). 442 */ 443void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) 444{ 445 /* We pad to match fetch size */ 446 while (ring->wptr & ring->align_mask) { 447 radeon_ring_write(ring, ring->nop); 448 } 449 DRM_MEMORYBARRIER(); 450 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); 451 (void)RREG32(ring->wptr_reg); 452} 453 454/** 455 * radeon_ring_unlock_commit - tell the GPU to execute the new 456 * commands on the ring buffer and unlock it 457 * 458 * @rdev: radeon_device pointer 459 * @ring: radeon_ring structure holding ring information 460 * 461 * Call radeon_ring_commit() then unlock the ring (all asics). 462 */ 463void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) 464{ 465 radeon_ring_commit(rdev, ring); 466 sx_xunlock(&rdev->ring_lock); 467} 468 469/** 470 * radeon_ring_undo - reset the wptr 471 * 472 * @ring: radeon_ring structure holding ring information 473 * 474 * Reset the driver's copy of the wptr (all asics). 475 */ 476void radeon_ring_undo(struct radeon_ring *ring) 477{ 478 ring->wptr = ring->wptr_old; 479} 480 481/** 482 * radeon_ring_unlock_undo - reset the wptr and unlock the ring 483 * 484 * @ring: radeon_ring structure holding ring information 485 * 486 * Call radeon_ring_undo() then unlock the ring (all asics). 487 */ 488void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) 489{ 490 radeon_ring_undo(ring); 491 sx_xunlock(&rdev->ring_lock); 492} 493 494/** 495 * radeon_ring_force_activity - add some nop packets to the ring 496 * 497 * @rdev: radeon_device pointer 498 * @ring: radeon_ring structure holding ring information 499 * 500 * Add some nop packets to the ring to force activity (all asics). 501 * Used for lockup detection to see if the rptr is advancing. 502 */ 503void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) 504{ 505 int r; 506 507 radeon_ring_free_size(rdev, ring); 508 if (ring->rptr == ring->wptr) { 509 r = radeon_ring_alloc(rdev, ring, 1); 510 if (!r) { 511 radeon_ring_write(ring, ring->nop); 512 radeon_ring_commit(rdev, ring); 513 } 514 } 515} 516 517/** 518 * radeon_ring_lockup_update - update lockup variables 519 * 520 * @ring: radeon_ring structure holding ring information 521 * 522 * Update the last rptr value and timestamp (all asics). 523 */ 524void radeon_ring_lockup_update(struct radeon_ring *ring) 525{ 526 ring->last_rptr = ring->rptr; 527 ring->last_activity = jiffies; 528} 529 530/** 531 * radeon_ring_test_lockup() - check if ring is lockedup by recording information 532 * @rdev: radeon device structure 533 * @ring: radeon_ring structure holding ring information 534 * 535 * We don't need to initialize the lockup tracking information as we will either 536 * have CP rptr to a different value of jiffies wrap around which will force 537 * initialization of the lockup tracking informations. 538 * 539 * A possible false positivie is if we get call after while and last_cp_rptr == 540 * the current CP rptr, even if it's unlikely it might happen. To avoid this 541 * if the elapsed time since last call is bigger than 2 second than we return 542 * false and update the tracking information. Due to this the caller must call 543 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported 544 * the fencing code should be cautious about that. 545 * 546 * Caller should write to the ring to force CP to do something so we don't get 547 * false positive when CP is just gived nothing to do. 548 * 549 **/ 550bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 551{ 552 unsigned long cjiffies, elapsed; 553 uint32_t rptr; 554 555 cjiffies = jiffies; 556 if (!time_after(cjiffies, ring->last_activity)) { 557 /* likely a wrap around */ 558 radeon_ring_lockup_update(ring); 559 return false; 560 } 561 rptr = RREG32(ring->rptr_reg); 562 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 563 if (ring->rptr != ring->last_rptr) { 564 /* CP is still working no lockup */ 565 radeon_ring_lockup_update(ring); 566 return false; 567 } 568 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); 569 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { 570 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 571 return true; 572 } 573 /* give a chance to the GPU ... */ 574 return false; 575} 576 577/** 578 * radeon_ring_backup - Back up the content of a ring 579 * 580 * @rdev: radeon_device pointer 581 * @ring: the ring we want to back up 582 * 583 * Saves all unprocessed commits from a ring, returns the number of dwords saved. 584 */ 585unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 586 uint32_t **data) 587{ 588 unsigned size, ptr, i; 589 590 /* just in case lock the ring */ 591 sx_xlock(&rdev->ring_lock); 592 *data = NULL; 593 594 if (ring->ring_obj == NULL) { 595 sx_xunlock(&rdev->ring_lock); 596 return 0; 597 } 598 599 /* it doesn't make sense to save anything if all fences are signaled */ 600 if (!radeon_fence_count_emitted(rdev, ring->idx)) { 601 sx_xunlock(&rdev->ring_lock); 602 return 0; 603 } 604 605 /* calculate the number of dw on the ring */ 606 if (ring->rptr_save_reg) 607 ptr = RREG32(ring->rptr_save_reg); 608 else if (rdev->wb.enabled) 609 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); 610 else { 611 /* no way to read back the next rptr */ 612 sx_xunlock(&rdev->ring_lock); 613 return 0; 614 } 615 616 size = ring->wptr + (ring->ring_size / 4); 617 size -= ptr; 618 size &= ring->ptr_mask; 619 if (size == 0) { 620 sx_xunlock(&rdev->ring_lock); 621 return 0; 622 } 623 624 /* and then save the content of the ring */ 625 *data = malloc(size * sizeof(uint32_t), DRM_MEM_DRIVER, M_NOWAIT); 626 if (!*data) { 627 sx_xunlock(&rdev->ring_lock); 628 return 0; 629 } 630 for (i = 0; i < size; ++i) { 631 (*data)[i] = ring->ring[ptr++]; 632 ptr &= ring->ptr_mask; 633 } 634 635 sx_xunlock(&rdev->ring_lock); 636 return size; 637} 638 639/** 640 * radeon_ring_restore - append saved commands to the ring again 641 * 642 * @rdev: radeon_device pointer 643 * @ring: ring to append commands to 644 * @size: number of dwords we want to write 645 * @data: saved commands 646 * 647 * Allocates space on the ring and restore the previously saved commands. 648 */ 649int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 650 unsigned size, uint32_t *data) 651{ 652 int i, r; 653 654 if (!size || !data) 655 return 0; 656 657 /* restore the saved ring content */ 658 r = radeon_ring_lock(rdev, ring, size); 659 if (r) 660 return r; 661 662 for (i = 0; i < size; ++i) { 663 radeon_ring_write(ring, data[i]); 664 } 665 666 radeon_ring_unlock_commit(rdev, ring); 667 free(data, DRM_MEM_DRIVER); 668 return 0; 669} 670 671/** 672 * radeon_ring_init - init driver ring struct. 673 * 674 * @rdev: radeon_device pointer 675 * @ring: radeon_ring structure holding ring information 676 * @ring_size: size of the ring 677 * @rptr_offs: offset of the rptr writeback location in the WB buffer 678 * @rptr_reg: MMIO offset of the rptr register 679 * @wptr_reg: MMIO offset of the wptr register 680 * @ptr_reg_shift: bit offset of the rptr/wptr values 681 * @ptr_reg_mask: bit mask of the rptr/wptr values 682 * @nop: nop packet for this ring 683 * 684 * Initialize the driver information for the selected ring (all asics). 685 * Returns 0 on success, error on failure. 686 */ 687int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 688 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 689 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) 690{ 691 int r; 692 void *ring_ptr; /* FreeBSD: to please GCC 4.2. */ 693 694 ring->ring_size = ring_size; 695 ring->rptr_offs = rptr_offs; 696 ring->rptr_reg = rptr_reg; 697 ring->wptr_reg = wptr_reg; 698 ring->ptr_reg_shift = ptr_reg_shift; 699 ring->ptr_reg_mask = ptr_reg_mask; 700 ring->nop = nop; 701 /* Allocate ring buffer */ 702 if (ring->ring_obj == NULL) { 703 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, 704 RADEON_GEM_DOMAIN_GTT, 705 NULL, &ring->ring_obj); 706 if (r) { 707 dev_err(rdev->dev, "(%d) ring create failed\n", r); 708 return r; 709 } 710 r = radeon_bo_reserve(ring->ring_obj, false); 711 if (unlikely(r != 0)) { 712 radeon_bo_unref(&ring->ring_obj); 713 return r; 714 } 715 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, 716 &ring->gpu_addr); 717 if (r) { 718 radeon_bo_unreserve(ring->ring_obj); 719 radeon_bo_unref(&ring->ring_obj); 720 dev_err(rdev->dev, "(%d) ring pin failed\n", r); 721 return r; 722 } 723 ring_ptr = &ring->ring; 724 r = radeon_bo_kmap(ring->ring_obj, 725 ring_ptr); 726 radeon_bo_unreserve(ring->ring_obj); 727 if (r) { 728 dev_err(rdev->dev, "(%d) ring map failed\n", r); 729 radeon_bo_unref(&ring->ring_obj); 730 return r; 731 } 732 } 733 ring->ptr_mask = (ring->ring_size / 4) - 1; 734 ring->ring_free_dw = ring->ring_size / 4; 735 if (rdev->wb.enabled) { 736 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); 737 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; 738 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; 739 } 740#ifdef FREEBSD_WIP 741 if (radeon_debugfs_ring_init(rdev, ring)) { 742 DRM_ERROR("Failed to register debugfs file for rings !\n"); 743 } 744#endif /* FREEBSD_WIP */ 745 radeon_ring_lockup_update(ring); 746 return 0; 747} 748 749/** 750 * radeon_ring_fini - tear down the driver ring struct. 751 * 752 * @rdev: radeon_device pointer 753 * @ring: radeon_ring structure holding ring information 754 * 755 * Tear down the driver information for the selected ring (all asics). 756 */ 757void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) 758{ 759 int r; 760 struct radeon_bo *ring_obj; 761 762 sx_xlock(&rdev->ring_lock); 763 ring_obj = ring->ring_obj; 764 ring->ready = false; 765 ring->ring = NULL; 766 ring->ring_obj = NULL; 767 sx_xunlock(&rdev->ring_lock); 768 769 if (ring_obj) { 770 r = radeon_bo_reserve(ring_obj, false); 771 if (likely(r == 0)) { 772 radeon_bo_kunmap(ring_obj); 773 radeon_bo_unpin(ring_obj); 774 radeon_bo_unreserve(ring_obj); 775 } 776 radeon_bo_unref(&ring_obj); 777 } 778} 779 780/* 781 * Debugfs info 782 */ 783#if defined(CONFIG_DEBUG_FS) 784 785static int radeon_debugfs_ring_info(struct seq_file *m, void *data) 786{ 787 struct drm_info_node *node = (struct drm_info_node *) m->private; 788 struct drm_device *dev = node->minor->dev; 789 struct radeon_device *rdev = dev->dev_private; 790 int ridx = *(int*)node->info_ent->data; 791 struct radeon_ring *ring = &rdev->ring[ridx]; 792 unsigned count, i, j; 793 u32 tmp; 794 795 radeon_ring_free_size(rdev, ring); 796 count = (ring->ring_size / 4) - ring->ring_free_dw; 797 tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; 798 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); 799 tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; 800 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); 801 if (ring->rptr_save_reg) { 802 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, 803 RREG32(ring->rptr_save_reg)); 804 } 805 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); 806 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); 807 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); 808 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); 809 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 810 seq_printf(m, "%u dwords in ring\n", count); 811 /* print 8 dw before current rptr as often it's the last executed 812 * packet that is the root issue 813 */ 814 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 815 for (j = 0; j <= (count + 32); j++) { 816 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); 817 i = (i + 1) & ring->ptr_mask; 818 } 819 return 0; 820} 821 822static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 823static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 824static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 825static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; 826static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 827 828static struct drm_info_list radeon_debugfs_ring_info_list[] = { 829 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, 830 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, 831 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, 832 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, 833 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, 834}; 835 836static int radeon_debugfs_sa_info(struct seq_file *m, void *data) 837{ 838 struct drm_info_node *node = (struct drm_info_node *) m->private; 839 struct drm_device *dev = node->minor->dev; 840 struct radeon_device *rdev = dev->dev_private; 841 842 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); 843 844 return 0; 845 846} 847 848static struct drm_info_list radeon_debugfs_sa_list[] = { 849 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, 850}; 851 852#endif 853 854#ifdef FREEBSD_WIP 855static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) 856{ 857#if defined(CONFIG_DEBUG_FS) 858 unsigned i; 859 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { 860 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; 861 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; 862 unsigned r; 863 864 if (&rdev->ring[ridx] != ring) 865 continue; 866 867 r = radeon_debugfs_add_files(rdev, info, 1); 868 if (r) 869 return r; 870 } 871#endif 872 return 0; 873} 874 875static int radeon_debugfs_sa_init(struct radeon_device *rdev) 876{ 877#if defined(CONFIG_DEBUG_FS) 878 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); 879#else 880 return 0; 881#endif 882} 883#endif /* FREEBSD_WIP */ 884