if_casreg.h revision 194246
1194246Smarius/*- 2194246Smarius * Copyright (C) 2001 Eduardo Horvath. 3194246Smarius * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org> 4194246Smarius * All rights reserved. 5194246Smarius * 6194246Smarius * Redistribution and use in source and binary forms, with or without 7194246Smarius * modification, are permitted provided that the following conditions 8194246Smarius * are met: 9194246Smarius * 1. Redistributions of source code must retain the above copyright 10194246Smarius * notice, this list of conditions and the following disclaimer. 11194246Smarius * 2. Redistributions in binary form must reproduce the above copyright 12194246Smarius * notice, this list of conditions and the following disclaimer in the 13194246Smarius * documentation and/or other materials provided with the distribution. 14194246Smarius * 15194246Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16194246Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17194246Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18194246Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19194246Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20194246Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21194246Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22194246Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23194246Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24194246Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25194246Smarius * SUCH DAMAGE. 26194246Smarius * 27194246Smarius * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp 28194246Smarius * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius 29194246Smarius * 30194246Smarius * $FreeBSD: head/sys/dev/cas/if_casreg.h 194246 2009-06-15 18:22:41Z marius $ 31194246Smarius */ 32194246Smarius 33194246Smarius#ifndef _IF_CASREG_H 34194246Smarius#define _IF_CASREG_H 35194246Smarius 36194246Smarius/* 37194246Smarius * register definitions for Sun Cassini/Cassini+ and National Semiconductor 38194246Smarius * DP83065 Saturn Gigabit Ethernet controllers 39194246Smarius */ 40194246Smarius 41194246Smarius/* global resources */ 42194246Smarius#define CAS_CAW 0x0004 /* core arbitration weight */ 43194246Smarius#define CAS_INF_BURST 0x0008 /* infinite burst enable */ 44194246Smarius#define CAS_STATUS 0x000c /* interrupt status */ 45194246Smarius#define CAS_INTMASK 0x0010 /* interrupt mask */ 46194246Smarius#define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */ 47194246Smarius#define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */ 48194246Smarius#define CAS_ERROR_STATUS 0x1000 /* PCI error status */ 49194246Smarius#define CAS_ERROR_MASK 0x1004 /* PCI error mask */ 50194246Smarius#define CAS_BIM_CONF 0x1008 /* BIM configuration */ 51194246Smarius#define CAS_BIM_DIAG 0x100c /* BIM diagnostic */ 52194246Smarius#define CAS_RESET 0x1010 /* software reset */ 53194246Smarius#define CAS_BIM_LDEV_OEN 0x1020 /* BIM local device output enable */ 54194246Smarius#define CAS_BIM_BUF_ADDR 0x1024 /* BIM buffer address */ 55194246Smarius#define CAS_BIM_BUF_DATA_LO 0x1028 /* BIM buffer data low */ 56194246Smarius#define CAS_BIM_BUF_DATA_HI 0x102c /* BIM buffer data high */ 57194246Smarius#define CAS_BIM_RAM_BIST 0x1030 /* BIM RAM BIST control/status */ 58194246Smarius#define CAS_PROBE_MUX_SELECT 0x1034 /* PROBE MUX SELECT */ 59194246Smarius#define CAS_INTMASK2 0x1038 /* interrupt mask 2 for INTB */ 60194246Smarius#define CAS_STATUS2 0x103c /* interrupt status 2 for INTB */ 61194246Smarius#define CAS_CLEAR_ALIAS2 0x1040 /* clear mask alias 2 for INTB */ 62194246Smarius#define CAS_STATUS_ALIAS2 0x1044 /* interrupt status alias 2 for INTB */ 63194246Smarius#define CAS_INTMASK3 0x1048 /* interrupt mask 3 for INTC */ 64194246Smarius#define CAS_STATUS3 0x104c /* interrupt status 3 for INTC */ 65194246Smarius#define CAS_CLEAR_ALIAS3 0x1050 /* clear mask alias 3 for INTC */ 66194246Smarius#define CAS_STATUS_ALIAS3 0x1054 /* interrupt status alias 3 for INTC */ 67194246Smarius#define CAS_INTMASK4 0x1058 /* interrupt mask 4 for INTD */ 68194246Smarius#define CAS_STATUS4 0x105c /* interrupt status 4 for INTD */ 69194246Smarius#define CAS_CLEAR_ALIAS4 0x1060 /* clear mask alias 4 for INTD */ 70194246Smarius#define CAS_STATUS_ALIAS4 0x1064 /* interrupt status alias 4 for INTD */ 71194246Smarius 72194246Smarius#define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */ 73194246Smarius#define CAS_CAW_RX_WGHT_SHFT 0 /* ...weighted round robin */ 74194246Smarius#define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */ 75194246Smarius#define CAS_CAW_TX_WGHT_SHFT 2 /* ...weighted round robin */ 76194246Smarius#define CAS_CAW_RR_DIS 0x00000010 /* weighted round robin dis. */ 77194246Smarius 78194246Smarius#define CAS_INF_BURST_EN 0x00000001 /* Allow bursts > cachline. */ 79194246Smarius 80194246Smarius/* 81194246Smarius * shared interrupt bits for CAS_STATUS, CAS_INTMASK, CAS_CLEAR_ALIAS and 82194246Smarius * CAS_STATUS_ALIAS 83194246Smarius * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies 84194246Smarius * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS. 85194246Smarius */ 86194246Smarius#define CAS_INTR_TX_INT_ME 0x00000001 /* Frame w/ INT_ME set sent. */ 87194246Smarius#define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */ 88194246Smarius#define CAS_INTR_TX_DONE 0x00000004 /* Any TX frame transferred. */ 89194246Smarius#define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */ 90194246Smarius#define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */ 91194246Smarius#define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */ 92194246Smarius#define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */ 93194246Smarius#define CAS_INTR_RX_COMP_FULL 0x00000080 /* RX completion ring full */ 94194246Smarius#define CAS_INTR_RX_BUF_AEMPTY 0x00000100 /* RX desc. ring almost empty */ 95194246Smarius#define CAS_INTR_RX_COMP_AFULL 0x00000200 /* RX cmpl. ring almost full */ 96194246Smarius#define CAS_INTR_RX_LEN_MMATCH 0x00000400 /* length field mismatch */ 97194246Smarius#define CAS_INTR_SUMMARY 0x00001000 /* summary interrupt bit */ 98194246Smarius#define CAS_INTR_PCS_INT 0x00002000 /* PCS interrupt */ 99194246Smarius#define CAS_INTR_TX_MAC_INT 0x00004000 /* TX MAC interrupt */ 100194246Smarius#define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */ 101194246Smarius#define CAS_INTR_MAC_CTRL_INT 0x00010000 /* MAC control interrupt */ 102194246Smarius#define CAS_INTR_MIF 0x00020000 /* MIF interrupt */ 103194246Smarius#define CAS_INTR_PCI_ERROR_INT 0x00040000 /* PCI error interrupt */ 104194246Smarius 105194246Smarius#define CAS_STATUS_TX_COMP3_MASK 0xfff80000 /* TX completion 3 */ 106194246Smarius#define CAS_STATUS_TX_COMP3_SHFT 19 107194246Smarius 108194246Smarius/* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */ 109194246Smarius#define CAS_ERROR_DTRTO 0x00000002 /* delayed trans. timeout */ 110194246Smarius#define CAS_ERROR_OTHER 0x00000004 /* errors (see PCIR_STATUS) */ 111194246Smarius#define CAS_ERROR_DMAW_ZERO 0x00000008 /* zero count DMA write */ 112194246Smarius#define CAS_ERROR_DMAR_ZERO 0x00000010 /* zero count DMA read */ 113194246Smarius#define CAS_ERROR_RTRTO 0x00000020 /* 255 retries exceeded */ 114194246Smarius 115194246Smarius#define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */ 116194246Smarius#define CAS_BIM_CONF_M66EN 0x00000008 /* PCI clock is 66MHz (ro). */ 117194246Smarius#define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */ 118194246Smarius#define CAS_BIM_CONF_DPAR_EN 0x00000020 /* parity error intr. enable */ 119194246Smarius#define CAS_BIM_CONF_RMA_EN 0x00000040 /* master abort intr. enable */ 120194246Smarius#define CAS_BIM_CONF_RTA_EN 0x00000080 /* target abort intr. enable */ 121194246Smarius#define CAS_BIM_CONF_DIS_BIM 0x00000200 /* Stop PCI DMA transactions. */ 122194246Smarius#define CAS_BIM_CONF_BIM_DIS 0x00000400 /* BIM was stopped (ro). */ 123194246Smarius#define CAS_BIM_CONF_BLOCK_PERR 0x00000800 /* Block PERR# to PCI bus. */ 124194246Smarius 125194246Smarius#define CAS_BIM_DIAG_BRST_SM 0x0000007f /* burst ctrl. state machine */ 126194246Smarius#define CAS_BIM_DIAG_MSTR_SM 0x3fffff00 127194246Smarius 128194246Smarius#define CAS_RESET_TX 0x00000001 /* Reset TX DMA engine. */ 129194246Smarius#define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */ 130194246Smarius#define CAS_RESET_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 131194246Smarius#define CAS_RESET_PCS_DIS 0x00000008 /* PCS reset disable */ 132194246Smarius#define CAS_RESET_BREQ_SM 0x00007f00 /* breq state machine */ 133194246Smarius#define CAS_RESET_PCIARB 0x00070000 /* PCI arbitration state */ 134194246Smarius#define CAS_RESET_RDPCI 0x00300000 /* read PCI state */ 135194246Smarius#define CAS_RESET_RDARB 0x00c00000 /* read arbitration state */ 136194246Smarius#define CAS_RESET_WRPCI 0x06000000 /* write PCI state */ 137194246Smarius#define CAS_RESET_WRARB 0x38000000 /* write arbitration state */ 138194246Smarius 139194246Smarius#define CAS_BIM_LDEV_OEN_PAD 0x00000001 /* addr. bus, RW and OE */ 140194246Smarius#define CAS_BIM_LDEV_OEN_PROM 0x00000002 /* PROM chip select */ 141194246Smarius#define CAS_BIM_LDEV_OEN_EXT 0x00000004 /* secondary local bus device */ 142194246Smarius#define CAS_BIM_LDEV_OEN_SOFT_0 0x00000008 /* soft. progr. ctrl. bit 0 */ 143194246Smarius#define CAS_BIM_LDEV_OEN_SOFT_1 0x00000010 /* soft. progr. ctrl. bit 1 */ 144194246Smarius#define CAS_BIM_LDEV_OEN_HWRST 0x00000020 /* hw. reset (Cassini+ only) */ 145194246Smarius 146194246Smarius#define CAS_BIM_BUF_ADDR_INDEX 0x0000003f /* buffer entry index */ 147194246Smarius#define CAS_BIM_BUF_ADDR_RDWR 0x00000040 /* 0: read, 1: write access */ 148194246Smarius 149194246Smarius#define CAS_BIM_RAM_BIST_START 0x00000001 /* Start BIST on read buffer. */ 150194246Smarius#define CAS_BIM_RAM_BIST_SUM 0x00000004 /* read buffer pass summary */ 151194246Smarius#define CAS_BIM_RAM_BIST_LO 0x00000010 /* read buf. low bank passes */ 152194246Smarius#define CAS_BIM_RAM_BIST_HI 0x00000020 /* read buf. high bank passes */ 153194246Smarius 154194246Smarius#define CAS_PROBE_MUX_SELECT_LO 0x0000000f /* P_A[7:0] */ 155194246Smarius#define CAS_PROBE_MUX_SELECT_HI 0x000000f0 /* P_A[15:8] */ 156194246Smarius#define CAS_PROBE_MUX_SELECT_SB 0x000000f0 /* txdma_wr address and size */ 157194246Smarius#define CAS_PROBE_MUX_SELECT_EN 0xf0000000 /* enable probe on P_A[15:0] */ 158194246Smarius 159194246Smarius/* 160194246Smarius * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4] 161194246Smarius * and CAS_STATUS_ALIAS[2-4]. 162194246Smarius * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which 163194246Smarius * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4]. 164194246Smarius */ 165194246Smarius#define CAS_INTRN_RX_DONE 0x00000001 /* >=1 RX frames transferred. */ 166194246Smarius#define CAS_INTRN_RX_COMP_FULL 0x00000002 /* RX completion ring full */ 167194246Smarius#define CAS_INTRN_RX_COMP_AFULL 0x00000004 /* RX cmpl. ring almost full */ 168194246Smarius#define CAS_INTRN_RX_BUF_NA 0x00000008 /* RX buffer not available */ 169194246Smarius#define CAS_INTRN_RX_BUF_AEMPTY 0x00000010 /* RX desc. ring almost empty */ 170194246Smarius 171194246Smarius/* INTn enable bit for CAS_INTMASK[2-4] */ 172194246Smarius#define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */ 173194246Smarius 174194246Smarius/* TX DMA registers */ 175194246Smarius#define CAS_TX_CONF 0x2004 /* TX configuration */ 176194246Smarius#define CAS_TX_FIFO_WR 0x2014 /* FIFO write pointer */ 177194246Smarius#define CAS_TX_FIFO_SDWR 0x2018 /* FIFO shadow write pointer */ 178194246Smarius#define CAS_TX_FIFO_RD 0x201c /* FIFO read pointer */ 179194246Smarius#define CAS_TX_FIFO_SDRD 0x2020 /* FIFO shadow read pointer */ 180194246Smarius#define CAS_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 181194246Smarius#define CAS_TX_SM1 0x2028 /* TX state machine 1 */ 182194246Smarius#define CAS_TX_SM2 0x202c /* TX state machine 2 */ 183194246Smarius#define CAS_TX_DATA_PTR_LO 0x2030 /* TX data pointer low */ 184194246Smarius#define CAS_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ 185194246Smarius#define CAS_TX_KICK1 0x2038 /* TX kick 1 */ 186194246Smarius#define CAS_TX_KICK2 0x203c /* TX kick 2 */ 187194246Smarius#define CAS_TX_KICK3 0x2040 /* TX kick 3 */ 188194246Smarius#define CAS_TX_KICK4 0x2044 /* TX kick 4 */ 189194246Smarius#define CAS_TX_COMP1 0x2048 /* TX completion 1 */ 190194246Smarius#define CAS_TX_COMP2 0x204c /* TX completion 2 */ 191194246Smarius#define CAS_TX_COMP3 0x2050 /* TX completion 3 */ 192194246Smarius#define CAS_TX_COMP4 0x2054 /* TX completion 4 */ 193194246Smarius#define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */ 194194246Smarius#define CAS_TX_COMPWB_BASE_HI 0x205c /* TX completion writeback base high */ 195194246Smarius#define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */ 196194246Smarius#define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */ 197194246Smarius#define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */ 198194246Smarius#define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */ 199194246Smarius#define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */ 200194246Smarius#define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */ 201194246Smarius#define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */ 202194246Smarius#define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */ 203194246Smarius#define CAS_TX_MAXBURST1 0x2080 /* TX MaxBurst 1 */ 204194246Smarius#define CAS_TX_MAXBURST2 0x2084 /* TX MaxBurst 2 */ 205194246Smarius#define CAS_TX_MAXBURST3 0x2088 /* TX MaxBurst 3 */ 206194246Smarius#define CAS_TX_MAXBURST4 0x208c /* TX MaxBurst 4 */ 207194246Smarius#define CAS_TX_FIFO_ADDR 0x2104 /* TX FIFO address */ 208194246Smarius#define CAS_TX_FIFO_TAG 0x2108 /* TX FIFO tag */ 209194246Smarius#define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */ 210194246Smarius#define CAS_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data highT1 */ 211194246Smarius#define CAS_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data highT0 */ 212194246Smarius#define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size in 64 byte multiples */ 213194246Smarius#define CAS_TX_RAM_BIST 0x211c /* TX RAM BIST control/status */ 214194246Smarius 215194246Smarius#define CAS_TX_CONF_TXDMA_EN 0x00000001 /* TX DMA enable */ 216194246Smarius#define CAS_TX_CONF_FIFO_PIO 0x00000002 /* Allow TX FIFO PIO access. */ 217194246Smarius#define CAS_TX_CONF_DESC1_MASK 0x0000003c /* TX descriptor ring 1 size */ 218194246Smarius#define CAS_TX_CONF_DESC1_SHFT 2 219194246Smarius#define CAS_TX_CONF_DESC2_MASK 0x000003c0 /* TX descriptor ring 2 size */ 220194246Smarius#define CAS_TX_CONF_DESC2_SHFT 6 221194246Smarius#define CAS_TX_CONF_DESC3_MASK 0x00003c00 /* TX descriptor ring 3 size */ 222194246Smarius#define CAS_TX_CONF_DESC3_SHFT 10 223194246Smarius#define CAS_TX_CONF_DESC4_MASK 0x0003c000 /* TX descriptor ring 4 size */ 224194246Smarius#define CAS_TX_CONF_DESC4_SHFT 14 225194246Smarius#define CAS_TX_CONF_PACED 0x00100000 /* ALL intr. on FIFO empty */ 226194246Smarius#define CAS_TX_CONF_RDPP_DIS 0x01000000 /* Should always be set. */ 227194246Smarius#define CAS_TX_CONF_COMPWB_Q1 0x02000000 /* Completion writeback... */ 228194246Smarius#define CAS_TX_CONF_COMPWB_Q2 0x04000000 /* ...happens at the end... */ 229194246Smarius#define CAS_TX_CONF_COMPWB_Q3 0x08000000 /* ...of every packet in... */ 230194246Smarius#define CAS_TX_CONF_COMPWB_Q4 0x10000000 /* ...queue n. */ 231194246Smarius#define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */ 232194246Smarius#define CAS_TX_CONF_CTX_MASK 0xc0000000 /* test port selection */ 233194246Smarius#define CAS_TX_CONF_CTX_SHFT 30 234194246Smarius 235194246Smarius#define CAS_TX_COMPWB_ALIGN 2048 /* TX compl. W/B alignment */ 236194246Smarius 237194246Smarius#define CAS_TX_DESC_ALIGN 2048 /* TX descriptor alignment */ 238194246Smarius 239194246Smarius/* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */ 240194246Smarius#define CAS_DESC_32 0x0 /* 32 descriptors */ 241194246Smarius#define CAS_DESC_64 0x1 /* 64 descriptors */ 242194246Smarius#define CAS_DESC_128 0x2 /* 128 descriptors */ 243194246Smarius#define CAS_DESC_256 0x3 /* 256 descriptors */ 244194246Smarius#define CAS_DESC_512 0x4 /* 512 descriptors */ 245194246Smarius#define CAS_DESC_1K 0x5 /* 1k descriptors */ 246194246Smarius#define CAS_DESC_2K 0x6 /* 2k descriptors */ 247194246Smarius#define CAS_DESC_4K 0x7 /* 4k descriptors */ 248194246Smarius#define CAS_DESC_8K 0x8 /* 8k descriptors */ 249194246Smarius 250194246Smarius#define CAS_TX_SM1_CHAIN 0x000003ff /* chaining state machine */ 251194246Smarius#define CAS_TX_SM1_CKSUM 0x00000c00 /* checksum state machine */ 252194246Smarius#define CAS_TX_SM1_TX_FIFO_LOAD 0x0003f000 /* TX FIFO load state machine */ 253194246Smarius#define CAS_TX_SM1_TX_FIFO_UNLD 0x003c0000 /* TX FIFO unload state mach. */ 254194246Smarius#define CAS_TX_SM1_CACHE_CTRL 0x03c00000 /* cache control state mach. */ 255194246Smarius#define CAS_TX_SM1_CBQARB 0x03c00000 /* CBQ arbiter state machine */ 256194246Smarius 257194246Smarius#define CAS_TX_SM2_COMPWB 0x00000007 /* compl. WB state machine */ 258194246Smarius#define CAS_TX_SM2_SUB_LOAD 0x00000038 /* sub load state machine */ 259194246Smarius#define CAS_TX_SM2_KICK 0x000000c0 /* kick state machine */ 260194246Smarius 261194246Smarius#define CAS_TX_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */ 262194246Smarius#define CAS_TX_RAM_BIST_SUMMARY 0x00000002 /* All RAM okay */ 263194246Smarius#define CAS_TX_RAM_BIST_RAM32B 0x00000004 /* RAM32B okay */ 264194246Smarius#define CAS_TX_RAM_BIST_RAM33B 0x00000008 /* RAM33B okay */ 265194246Smarius#define CAS_TX_RAM_BIST_RAM32A 0x00000010 /* RAM32A okay */ 266194246Smarius#define CAS_TX_RAM_BIST_RAM33A 0x00000020 /* RAM33A okay */ 267194246Smarius#define CAS_TX_RAM_BIST_SM 0x000001c0 /* RAM BIST state machine */ 268194246Smarius 269194246Smarius/* RX DMA registers */ 270194246Smarius#define CAS_RX_CONF 0x4000 /* RX configuration */ 271194246Smarius#define CAS_RX_PSZ 0x4004 /* RX page size */ 272194246Smarius#define CAS_RX_FIFO_WR 0x4008 /* RX FIFO write pointer */ 273194246Smarius#define CAS_RX_FIFO_RD 0x400c /* RX FIFO read pointer */ 274194246Smarius#define CAS_RX_IPP_WR 0x4010 /* RX IPP FIFO write pointer */ 275194246Smarius#define CAS_RX_IPP_SDWR 0x4014 /* RX IPP FIFO shadow write pointer */ 276194246Smarius#define CAS_RX_IPP_RD 0x4018 /* RX IPP FIFO read pointer */ 277194246Smarius#define CAS_RX_DEBUG 0x401c /* RX debug */ 278194246Smarius#define CAS_RX_PTHRS 0x4020 /* RX PAUSE threshold */ 279194246Smarius#define CAS_RX_KICK 0x4024 /* RX kick */ 280194246Smarius#define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */ 281194246Smarius#define CAS_RX_DESC_BASE_HI 0x402c /* RX descriptor ring base high */ 282194246Smarius#define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */ 283194246Smarius#define CAS_RX_COMP_BASE_HI 0x4034 /* RX completion ring base high */ 284194246Smarius#define CAS_RX_COMP 0x4038 /* RX completion */ 285194246Smarius#define CAS_RX_COMP_HEAD 0x403c /* RX completion head */ 286194246Smarius#define CAS_RX_COMP_TAIL 0x4040 /* RX completion tail */ 287194246Smarius#define CAS_RX_BLANK 0x4044 /* RX blanking for ISR read */ 288194246Smarius#define CAS_RX_AEMPTY_THRS 0x4048 /* RX almost empty threshold */ 289194246Smarius#define CAS_RX_RED 0x4048 /* RX random early detection enable */ 290194246Smarius#define CAS_RX_FF 0x4050 /* RX FIFO fullness */ 291194246Smarius#define CAS_RX_IPP_PKT_CNT 0x4054 /* RX IPP packet counter */ 292194246Smarius#define CAS_RX_WORKING_DMA_LO 0x4058 /* RX working DMA pointer low */ 293194246Smarius#define CAS_RX_WORKING_DMA_HI 0x405c /* RX working DMA pointer high */ 294194246Smarius#define CAS_RX_BIST 0x4060 /* RX BIST */ 295194246Smarius#define CAS_RX_CTRL_FIFO_WR 0x4064 /* RX control FIFO write pointer */ 296194246Smarius#define CAS_RX_CTRL_FIFO_RD 0x4068 /* RX control FIFO read pointer */ 297194246Smarius#define CAS_RX_BLANK_ALIAS 0x406c /* RX blanking for ISR read alias */ 298194246Smarius#define CAS_RX_FIFO_ADDR 0x4080 /* RX FIFO address */ 299194246Smarius#define CAS_RX_FIFO_TAG 0x4084 /* RX FIFO tag */ 300194246Smarius#define CAS_RX_FIFO_DATA_LO 0x4088 /* RX FIFO data low */ 301194246Smarius#define CAS_RX_FIFO_DATA_HI_T0 0x408c /* RX FIFO data highT0 */ 302194246Smarius#define CAS_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data highT1 */ 303194246Smarius#define CAS_RX_CTRL_FIFO 0x4094 /* RX control FIFO and batching FIFO */ 304194246Smarius#define CAS_RX_CTRL_FIFO_LO 0x4098 /* RX control FIFO data low */ 305194246Smarius#define CAS_RX_CTRL_FIFO_MD 0x409c /* RX control FIFO data mid */ 306194246Smarius#define CAS_RX_CTRL_FIFO_HI 0x4100 /* RX control FIFO data high, flowID */ 307194246Smarius#define CAS_RX_IPP_ADDR 0x4104 /* RX IPP FIFO address */ 308194246Smarius#define CAS_RX_IPP_TAG 0x4108 /* RX IPP FIFO tag */ 309194246Smarius#define CAS_RX_IPP_DATA_LO 0x410c /* RX IPP FIFO data low */ 310194246Smarius#define CAS_RX_IPP_DATA_HI_T0 0x4110 /* RX IPP FIFO data highT0 */ 311194246Smarius#define CAS_RX_IPP_DATA_HI_T1 0x4114 /* RX IPP FIFO data highT1 */ 312194246Smarius#define CAS_RX_HDR_PAGE_LO 0x4118 /* RX header page pointer low */ 313194246Smarius#define CAS_RX_HDR_PAGE_HIGH 0x411c /* RX header page pointer high */ 314194246Smarius#define CAS_RX_MTU_PAGE_LO 0x4120 /* RX MTU page pointer low */ 315194246Smarius#define CAS_RX_MTU_PAGE_HIGH 0x4124 /* RX MTU page pointer high */ 316194246Smarius#define CAS_RX_REAS_DMA_ADDR 0x4128 /* RX reassembly DMA table address */ 317194246Smarius#define CAS_RX_REAS_DMA_DATA_LO 0x412c /* RX reassembly DMA table data low */ 318194246Smarius#define CAS_RX_REAS_DMA_DATA_MD 0x4130 /* RX reassembly DMA table data mid */ 319194246Smarius#define CAS_RX_REAS_DMA_DATA_HI 0x4134 /* RX reassembly DMA table data high */ 320194246Smarius/* The rest of the RX DMA registers are Cassini+/Saturn only. */ 321194246Smarius#define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */ 322194246Smarius#define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */ 323194246Smarius#define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */ 324194246Smarius#define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */ 325194246Smarius#define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */ 326194246Smarius#define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */ 327194246Smarius#define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */ 328194246Smarius#define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */ 329194246Smarius#define CAS_RX_KICK2 0x4220 /* RX kick 2 */ 330194246Smarius#define CAS_RX_COMP2 0x4224 /* RX completion 2 */ 331194246Smarius#define CAS_RX_COMP_HEAD2 0x4228 /* RX completion head 2 */ 332194246Smarius#define CAS_RX_COMP_TAIL2 0x422c /* RX completion tail 2 */ 333194246Smarius#define CAS_RX_COMP_HEAD3 0x4230 /* RX completion head 3 */ 334194246Smarius#define CAS_RX_COMP_TAIL3 0x4234 /* RX completion tail 3 */ 335194246Smarius#define CAS_RX_COMP_HEAD4 0x4238 /* RX completion head 4 */ 336194246Smarius#define CAS_RX_COMP_TAIL4 0x423c /* RX completion tail 4 */ 337194246Smarius#define CAS_RX_AEMPTY_THRS2 0x4048 /* RX almost empty threshold 2 */ 338194246Smarius 339194246Smarius#define CAS_RX_CONF_RXDMA_EN 0x00000001 /* RX DMA enable */ 340194246Smarius#define CAS_RX_CONF_DESC_MASK 0x0000001e /* RX descriptor ring size */ 341194246Smarius#define CAS_RX_CONF_DESC_SHFT 1 342194246Smarius#define CAS_RX_CONF_COMP_MASK 0x000001e0 /* RX complition ring size */ 343194246Smarius#define CAS_RX_CONF_COMP_SHFT 5 344194246Smarius#define CAS_RX_CONF_BATCH_DIS 0x00000200 /* descriptor batching dis. */ 345194246Smarius#define CAS_RX_CONF_SOFF_MASK 0x00001c00 /* swivel offset */ 346194246Smarius#define CAS_RX_CONF_SOFF_SHFT 10 347194246Smarius/* The RX descriptor ring 2 is Cassini+/Saturn only. */ 348194246Smarius#define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */ 349194246Smarius#define CAS_RX_CONF_DESC2_SHFT 16 350194246Smarius 351194246Smarius#define CAS_RX_CONF_COMP_128 0x0 /* 128 descriptors */ 352194246Smarius#define CAS_RX_CONF_COMP_256 0x1 /* 256 descriptors */ 353194246Smarius#define CAS_RX_CONF_COMP_512 0x2 /* 512 descriptors */ 354194246Smarius#define CAS_RX_CONF_COMP_1K 0x3 /* 1k descriptors */ 355194246Smarius#define CAS_RX_CONF_COMP_2K 0x4 /* 2k descriptors */ 356194246Smarius#define CAS_RX_CONF_COMP_4K 0x5 /* 4k descriptors */ 357194246Smarius#define CAS_RX_CONF_COMP_8K 0x6 /* 8k descriptors */ 358194246Smarius#define CAS_RX_CONF_COMP_16K 0x7 /* 16k descriptors */ 359194246Smarius#define CAS_RX_CONF_COMP_32K 0x8 /* 32k descriptors */ 360194246Smarius 361194246Smarius#define CAS_RX_PSZ_MASK 0x00000003 /* RX page size */ 362194246Smarius#define CAS_RX_PSZ_SHFT 0 363194246Smarius#define CAS_RX_PSZ_MB_CNT_MASK 0x00007800 /* number of MTU buffers */ 364194246Smarius#define CAS_RX_PSZ_MB_CNT_SHFT 11 365194246Smarius#define CAS_RX_PSZ_MB_STRD_MASK 0x18000000 /* MTU buffer stride */ 366194246Smarius#define CAS_RX_PSZ_MB_STRD_SHFT 27 367194246Smarius#define CAS_RX_PSZ_MB_OFF_MASK 0xc0000000 /* MTU buffer offset */ 368194246Smarius#define CAS_RX_PSZ_MB_OFF_SHFT 30 369194246Smarius 370194246Smarius#define CAS_RX_PSZ_2K 0x0 /* page size 2Kbyte */ 371194246Smarius#define CAS_RX_PSZ_4K 0x1 /* page size 4Kbyte */ 372194246Smarius#define CAS_RX_PSZ_8K 0x2 /* page size 8Kbyte */ 373194246Smarius#define CAS_RX_PSZ_16K 0x3 /* page size 16Kbyte*/ 374194246Smarius 375194246Smarius#define CAS_RX_PSZ_MB_STRD_1K 0x0 /* MTU buffer stride 1Kbyte */ 376194246Smarius#define CAS_RX_PSZ_MB_STRD_2K 0x1 /* MTU buffer stride 2Kbyte */ 377194246Smarius#define CAS_RX_PSZ_MB_STRD_4K 0x2 /* MTU buffer stride 4Kbyte */ 378194246Smarius#define CAS_RX_PSZ_MB_STRD_8K 0x3 /* MTU buffer stride 8Kbyte */ 379194246Smarius 380194246Smarius#define CAS_RX_PSZ_MB_OFF_0 0x0 /* MTU buf. offset 0 bytes */ 381194246Smarius#define CAS_RX_PSZ_MB_OFF_64 0x1 /* MTU buf. offset 64 bytes */ 382194246Smarius#define CAS_RX_PSZ_MB_OFF_96 0x2 /* MTU buf. offset 96 bytes */ 383194246Smarius#define CAS_RX_PSZ_MB_OFF_128 0x3 /* MTU buf. offset 128 bytes */ 384194246Smarius 385194246Smarius#define CAS_RX_DESC_ALIGN 8192 /* RX descriptor alignment */ 386194246Smarius 387194246Smarius#define CAS_RX_COMP_ALIGN 8192 /* RX complition alignment */ 388194246Smarius 389194246Smarius/* The RX PAUSE thresholds are specified in multiples of 64 bytes. */ 390194246Smarius#define CAS_RX_PTHRS_XOFF_MASK 0x000001ff /* XOFF PAUSE */ 391194246Smarius#define CAS_RX_PTHRS_XOFF_SHFT 0 392194246Smarius#define CAS_RX_PTHRS_XON_MASK 0x001ff000 /* XON PAUSE */ 393194246Smarius#define CAS_RX_PTHRS_XON_SHFT 12 394194246Smarius 395194246Smarius/* 396194246Smarius * CAS_RX_BLANK and CAS_RX_BLANK_ALIAS bits 397194246Smarius * CAS_RX_BLANK is loaded each time CAS_STATUS is read and CAS_RX_BLANK_ALIAS 398194246Smarius * is read each time CAS_STATUS_ALIAS is read. The blanking time is specified 399194246Smarius * in multiples of 512 core ticks (which runs at 125MHz). 400194246Smarius */ 401194246Smarius#define CAS_RX_BLANK_PKTS_MASK 0x000001ff /* RX blanking packets */ 402194246Smarius#define CAS_RX_BLANK_PKTS_SHFT 0 403194246Smarius#define CAS_RX_BLANK_TIME_MASK 0x3ffff000 /* RX blanking time */ 404194246Smarius#define CAS_RX_BLANK_TIME_SHFT 12 405194246Smarius 406194246Smarius/* CAS_RX_AEMPTY_THRS and CAS_RX_AEMPTY_THRS2 bits */ 407194246Smarius#define CAS_RX_AEMPTY_THRS_MASK 0x00001fff /* RX_BUF_AEMPTY threshold */ 408194246Smarius#define CAS_RX_AEMPTY_THRS_SHFT 0 409194246Smarius#define CAS_RX_AEMPTY_COMP_MASK 0x0fffe000 /* RX_COMP_AFULL threshold */ 410194246Smarius#define CAS_RX_AEMPTY_COMP_SHFT 13 411194246Smarius 412194246Smarius/* The RX random early detection probability is in 12.5% granularity. */ 413194246Smarius#define CAS_RX_RED_4K_6K_MASK 0x000000ff /* 4K < FIFO threshold < 6K */ 414194246Smarius#define CAS_RX_RED_4K_6K_SHFT 0 415194246Smarius#define CAS_RX_RED_6K_8K_MASK 0x0000ff00 /* 6K < FIFO threshold < 8K */ 416194246Smarius#define CAS_RX_RED_6K_8K_SHFT 8 417194246Smarius#define CAS_RX_RED_8K_10K_MASK 0x00ff0000 /* 8K < FIFO threshold < 10K */ 418194246Smarius#define CAS_RX_RED_8K_10K_SHFT 16 419194246Smarius#define CAS_RX_RED_10K_12K_MASK 0xff000000 /* 10K < FIFO threshold < 12K */ 420194246Smarius#define CAS_RX_RED_10K_12K_SHFT 24 421194246Smarius 422194246Smarius/* CAS_RX_FF_IPP_MASK and CAS_RX_FF_FIFO_MASK are in 8 bytes granularity. */ 423194246Smarius#define CAS_RX_FF_PKT_MASK 0x000000ff /* # of packets in RX FIFO */ 424194246Smarius#define CAS_RX_FF_PKT_SHFT 0 425194246Smarius#define CAS_RX_FF_IPP_MASK 0x0007ff00 /* IPP FIFO level */ 426194246Smarius#define CAS_RX_FF_IPP_SHFT 8 427194246Smarius#define CAS_RX_FF_FIFO_MASK 0x3ff80000 /* RX FIFO level */ 428194246Smarius#define CAS_RX_FF_FIFO_SHFT 19 429194246Smarius 430194246Smarius#define CAS_RX_BIST_START 0x00000001 /* Start BIST process. */ 431194246Smarius#define CAS_RX_BIST_SUMMARY 0x00000002 /* All okay */ 432194246Smarius#define CAS_RX_BIST_SM 0x00007800 /* BIST state machine */ 433194246Smarius#define CAS_RX_BIST_REAS_27 0x00008000 /* Reas 27 okay */ 434194246Smarius#define CAS_RX_BIST_REAS_26B 0x00010000 /* Reas 26B okay */ 435194246Smarius#define CAS_RX_BIST_REAS_26A 0x00020000 /* Reas 26A okay */ 436194246Smarius#define CAS_RX_BIST_CTRL_33 0x00040000 /* Control FIFO 33 okay */ 437194246Smarius#define CAS_RX_BIST_CTRL_32 0x00080000 /* Control FIFO 32 okay */ 438194246Smarius#define CAS_RX_BIST_IPP_33C 0x00100000 /* IPP 33C okay */ 439194246Smarius#define CAS_RX_BIST_IPP_32C 0x00200000 /* IPP 32C okay */ 440194246Smarius#define CAS_RX_BIST_IPP_33B 0x00400000 /* IPP 33B okay */ 441194246Smarius#define CAS_RX_BIST_IPP_32B 0x00800000 /* IPP 32B okay */ 442194246Smarius#define CAS_RX_BIST_IPP_33A 0x01000000 /* IPP 33A okay */ 443194246Smarius#define CAS_RX_BIST_IPP_32A 0x02000000 /* IPP 32A okay */ 444194246Smarius#define CAS_RX_BIST_33C 0x04000000 /* 33C okay */ 445194246Smarius#define CAS_RX_BIST_32C 0x08000000 /* 32C okay */ 446194246Smarius#define CAS_RX_BIST_33B 0x10000000 /* 33B okay */ 447194246Smarius#define CAS_RX_BIST_32B 0x20000000 /* 32B okay */ 448194246Smarius#define CAS_RX_BIST_33A 0x40000000 /* 33A okay */ 449194246Smarius#define CAS_RX_BIST_32A 0x80000000 /* 32A okay */ 450194246Smarius 451194246Smarius#define CAS_RX_REAS_DMA_ADDR_LC 0x0000003f /* reas. table location sel. */ 452194246Smarius 453194246Smarius/* header parser registers */ 454194246Smarius#define CAS_HP_CONF 0x4140 /* HP configuration */ 455194246Smarius#define CAS_HP_IR_ADDR 0x4144 /* HP instruction RAM address */ 456194246Smarius#define CAS_HP_IR_DATA_LO 0x4148 /* HP instruction RAM data low */ 457194246Smarius#define CAS_HP_IR_DATA_MD 0x414c /* HP instruction RAM data mid */ 458194246Smarius#define CAS_HP_IR_DATA_HI 0x4150 /* HP instruction RAM data high */ 459194246Smarius#define CAS_HP_DR_FDB 0x4154 /* HP data RAM and flow DB address */ 460194246Smarius#define CAS_HP_DR_DATA 0x4158 /* HP data RAM data */ 461194246Smarius#define CAS_HP_FLOW_DB1 0x415c /* HP flow database 1 */ 462194246Smarius#define CAS_HP_FLOW_DB2 0x4160 /* HP flow database 2 */ 463194246Smarius#define CAS_HP_FLOW_DB3 0x4164 /* HP flow database 3 */ 464194246Smarius#define CAS_HP_FLOW_DB4 0x4168 /* HP flow database 4 */ 465194246Smarius#define CAS_HP_FLOW_DB5 0x416c /* HP flow database 5 */ 466194246Smarius#define CAS_HP_FLOW_DB6 0x4170 /* HP flow database 6 */ 467194246Smarius#define CAS_HP_FLOW_DB7 0x4174 /* HP flow database 7 */ 468194246Smarius#define CAS_HP_FLOW_DB8 0x4178 /* HP flow database 8 */ 469194246Smarius#define CAS_HP_FLOW_DB9 0x417c /* HP flow database 9 */ 470194246Smarius#define CAS_HP_FLOW_DB10 0x4180 /* HP flow database 10 */ 471194246Smarius#define CAS_HP_FLOW_DB11 0x4184 /* HP flow database 11 */ 472194246Smarius#define CAS_HP_FLOW_DB12 0x4188 /* HP flow database 12 */ 473194246Smarius#define CAS_HP_SM 0x418c /* HP state machine */ 474194246Smarius#define CAS_HP_STATUS1 0x4190 /* HP status 1 */ 475194246Smarius#define CAS_HP_STATUS2 0x4194 /* HP status 2 */ 476194246Smarius#define CAS_HP_STATUS3 0x4198 /* HP status 3 */ 477194246Smarius#define CAS_HP_RAM_BIST 0x419c /* HP RAM BIST */ 478194246Smarius 479194246Smarius#define CAS_HP_CONF_PARSE_EN 0x00000001 /* header parsing enable */ 480194246Smarius#define CAS_HP_CONF_NCPU_MASK 0x000000fc /* #CPUs (0x0: 64) */ 481194246Smarius#define CAS_HP_CONF_NCPU_SHFT 2 482194246Smarius#define CAS_HP_CONF_SINC_DIS 0x00000100 /* SYN inc. seq. number dis. */ 483194246Smarius#define CAS_HP_CONF_TPT_MASK 0x000ffe00 /* TCP payload threshold */ 484194246Smarius#define CAS_HP_CONF_TPT_SHFT 9 485194246Smarius 486194246Smarius#define CAS_HP_DR_FDB_DR_MASK 0x0000001f /* data RAM location sel. */ 487194246Smarius#define CAS_HP_DR_FDB_DR_SHFT 0 488194246Smarius#define CAS_HP_DR_FDB_FDB_MASK 0x00003f00 /* flow DB location sel. */ 489194246Smarius#define CAS_HP_DR_FDB_FDB_SHFT 8 490194246Smarius 491194246Smarius#define CAS_HP_STATUS1_OP_MASK 0x00000007 /* HRP opcode */ 492194246Smarius#define CAS_HP_STATUS1_OP_SHFT 0 493194246Smarius#define CAS_HP_STATUS1_LB_MASK 0x000001f8 /* load balancing CPU number */ 494194246Smarius#define CAS_HP_STATUS1_LB_SHFT 3 495194246Smarius#define CAS_HP_STATUS1_L3O_MASK 0x0000fe00 /* layer 3 offset */ 496194246Smarius#define CAS_HP_STATUS1_L3O_SHFT 9 497194246Smarius#define CAS_HP_STATUS1_SAP_MASK 0xffff0000 /* ethertype */ 498194246Smarius#define CAS_HP_STATUS1_SAP_SHFT 16 499194246Smarius 500194246Smarius#define CAS_HP_STATUS2_TSZ_MASK 0x0000ffff /* TCP payload size */ 501194246Smarius#define CAS_HP_STATUS2_TSZ_SHFT 0 502194246Smarius#define CAS_HP_STATUS2_TO_MASK 0x007f0000 /* TCP payload offset */ 503194246Smarius#define CAS_HP_STATUS2_TO_SHFT 16 504194246Smarius#define CAS_HP_STATUS2_FID_MASK 0x1f800000 /* flow ID */ 505194246Smarius#define CAS_HP_STATUS2_FID_SHFT 23 506194246Smarius#define CAS_HP_STATUS2_AR2_MASK 0xe0000000 /* accu_R2[6:4] */ 507194246Smarius#define CAS_HP_STATUS2_AR2_SHFT 29 508194246Smarius 509194246Smarius#define CAS_HP_STATUS3_TCP_NCHK 0x00000001 /* TCP no payload check */ 510194246Smarius#define CAS_HP_STATUS3_TCP_CHK 0x00000002 /* TCP payload check */ 511194246Smarius#define CAS_HP_STATUS3_SYN_FLAG 0x00000004 /* SYN flag */ 512194246Smarius#define CAS_HP_STATUS3_TCP_FLAG 0x00000008 /* TCP flag check */ 513194246Smarius#define CAS_HP_STATUS3_CTRL_PF 0x00000010 /* control packet flag */ 514194246Smarius#define CAS_HP_STATUS3_NASSIST 0x00000020 /* no assist */ 515194246Smarius#define CAS_HP_STATUS3_MASK_PT 0x00000040 /* Mask payload threshold. */ 516194246Smarius#define CAS_HP_STATUS3_FRC_TPC 0x00000080 /* Force TCP payload check. */ 517194246Smarius#define CAS_HP_STATUS3_MASK_DLZ 0x00000100 /* Mask data length equal 0. */ 518194246Smarius#define CAS_HP_STATUS3_FRC_TNPC 0x00000200 /* Force TCP no payload chk. */ 519194246Smarius#define CAS_HP_STATUS3_JMBHS_EN 0x00000400 /* jumbo header split enable */ 520194246Smarius#define CAS_HP_STATUS3_BWO_REAS 0x00000800 /* batching w/o reassembly */ 521194246Smarius#define CAS_HP_STATUS3_FRC_DROP 0x00001000 /* force drop */ 522194246Smarius#define CAS_HP_STATUS3_AR1_MASK 0x000fe000 /* accu_R1 */ 523194246Smarius#define CAS_HP_STATUS3_AR1_SHFT 13 524194246Smarius#define CAS_HP_STATUS3_CSO_MASK 0x07f00000 /* checksum start offset */ 525194246Smarius#define CAS_HP_STATUS3_CSO_SHFT 19 526194246Smarius#define CAS_HP_STATUS3_AR2_MASK 0xf0000000 /* accu_R2[3:0] */ 527194246Smarius#define CAS_HP_STATUS3_AR2_SHFT 28 528194246Smarius 529194246Smarius#define CAS_HP_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */ 530194246Smarius#define CAS_HP_RAM_BIST_SUMMARY 0x00000002 /* all RAM okay */ 531194246Smarius#define CAS_HP_RAM_BIST_TCPSEQ 0x00020000 /* TCP seqeunce RAM okay */ 532194246Smarius#define CAS_HP_RAM_BIST_FID31 0x00040000 /* flow ID RAM3 bank 1 okay */ 533194246Smarius#define CAS_HP_RAM_BIST_FID21 0x00080000 /* flow ID RAM2 bank 1 okay */ 534194246Smarius#define CAS_HP_RAM_BIST_FID11 0x00100000 /* flow ID RAM1 bank 1 okay */ 535194246Smarius#define CAS_HP_RAM_BIST_FID01 0x00200000 /* flow ID RAM0 bank 1 okay */ 536194246Smarius#define CAS_HP_RAM_BIST_FID30 0x00400000 /* flow ID RAM3 bank 0 okay */ 537194246Smarius#define CAS_HP_RAM_BIST_FID20 0x00800000 /* flow ID RAM2 bank 0 okay */ 538194246Smarius#define CAS_HP_RAM_BIST_FID10 0x01000000 /* flow ID RAM1 bank 0 okay */ 539194246Smarius#define CAS_HP_RAM_BIST_FID00 0x02000000 /* flow ID RAM0 bank 0 okay */ 540194246Smarius#define CAS_HP_RAM_BIST_AGE1 0x04000000 /* aging RAM1 okay */ 541194246Smarius#define CAS_HP_RAM_BIST_AGE0 0x08000000 /* aging RAM0 okay */ 542194246Smarius#define CAS_HP_RAM_BIST_IR2 0x10000000 /* instruction RAM2 okay */ 543194246Smarius#define CAS_HP_RAM_BIST_IR1 0x20000000 /* instruction RAM1 okay */ 544194246Smarius#define CAS_HP_RAM_BIST_IR0 0x40000000 /* instruction RAM0 okay */ 545194246Smarius#define CAS_HP_RAM_BIST_DR 0x80000000 /* data RAM okay */ 546194246Smarius 547194246Smarius/* MAC registers */ 548194246Smarius#define CAS_MAC_TXRESET 0x6000 /* TX MAC software reset command */ 549194246Smarius#define CAS_MAC_RXRESET 0x6004 /* RX MAC software reset command */ 550194246Smarius#define CAS_MAC_SPC 0x6008 /* send PAUSE command */ 551194246Smarius#define CAS_MAC_TX_STATUS 0x6010 /* TX MAC status */ 552194246Smarius#define CAS_MAC_RX_STATUS 0x6014 /* RX MAC status */ 553194246Smarius#define CAS_MAC_CTRL_STATUS 0x6018 /* MAC control status */ 554194246Smarius#define CAS_MAC_TX_MASK 0x6020 /* TX MAC mask */ 555194246Smarius#define CAS_MAC_RX_MASK 0x6024 /* RX MAC mask */ 556194246Smarius#define CAS_MAC_CTRL_MASK 0x6028 /* MAC control mask */ 557194246Smarius#define CAS_MAC_TX_CONF 0x6030 /* TX MAC configuration */ 558194246Smarius#define CAS_MAC_RX_CONF 0x6034 /* RX MAC configuration */ 559194246Smarius#define CAS_MAC_CTRL_CONF 0x6038 /* MAC control configuration */ 560194246Smarius#define CAS_MAC_XIF_CONF 0x603c /* XIF configuration */ 561194246Smarius#define CAS_MAC_IPG0 0x6040 /* inter packet gap 0 */ 562194246Smarius#define CAS_MAC_IPG1 0x6044 /* inter packet gap 1 */ 563194246Smarius#define CAS_MAC_IPG2 0x6048 /* inter packet gap 2 */ 564194246Smarius#define CAS_MAC_SLOT_TIME 0x604c /* slot time */ 565194246Smarius#define CAS_MAC_MIN_FRAME 0x6050 /* minimum frame size */ 566194246Smarius#define CAS_MAC_MAX_BF 0x6054 /* maximum bust and frame size */ 567194246Smarius#define CAS_MAC_PREAMBLE_LEN 0x6058 /* PA size */ 568194246Smarius#define CAS_MAC_JAM_SIZE 0x605c /* jam size */ 569194246Smarius#define CAS_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit */ 570194246Smarius#define CAS_MAC_CTRL_TYPE 0x6064 /* MAC control type */ 571194246Smarius#define CAS_MAC_ADDR0 0x6080 /* MAC address 0 */ 572194246Smarius#define CAS_MAC_ADDR1 0x6084 /* MAC address 1 */ 573194246Smarius#define CAS_MAC_ADDR2 0x6088 /* MAC address 2 */ 574194246Smarius#define CAS_MAC_ADDR3 0x608c /* MAC address 3 */ 575194246Smarius#define CAS_MAC_ADDR4 0x6090 /* MAC address 4 */ 576194246Smarius#define CAS_MAC_ADDR5 0x6094 /* MAC address 5 */ 577194246Smarius#define CAS_MAC_ADDR6 0x6098 /* MAC address 6 */ 578194246Smarius#define CAS_MAC_ADDR7 0x609c /* MAC address 7 */ 579194246Smarius#define CAS_MAC_ADDR8 0x60a0 /* MAC address 8 */ 580194246Smarius#define CAS_MAC_ADDR9 0x60a4 /* MAC address 9 */ 581194246Smarius#define CAS_MAC_ADDR10 0x60a8 /* MAC address 10 */ 582194246Smarius#define CAS_MAC_ADDR11 0x60ac /* MAC address 11 */ 583194246Smarius#define CAS_MAC_ADDR12 0x60b0 /* MAC address 12 */ 584194246Smarius#define CAS_MAC_ADDR13 0x60b4 /* MAC address 13 */ 585194246Smarius#define CAS_MAC_ADDR14 0x60b8 /* MAC address 14 */ 586194246Smarius#define CAS_MAC_ADDR15 0x60bc /* MAC address 15 */ 587194246Smarius#define CAS_MAC_ADDR16 0x60c0 /* MAC address 16 */ 588194246Smarius#define CAS_MAC_ADDR17 0x60c4 /* MAC address 17 */ 589194246Smarius#define CAS_MAC_ADDR18 0x60c8 /* MAC address 18 */ 590194246Smarius#define CAS_MAC_ADDR19 0x60cc /* MAC address 19 */ 591194246Smarius#define CAS_MAC_ADDR20 0x60d0 /* MAC address 20 */ 592194246Smarius#define CAS_MAC_ADDR21 0x60d4 /* MAC address 21 */ 593194246Smarius#define CAS_MAC_ADDR22 0x60d8 /* MAC address 22 */ 594194246Smarius#define CAS_MAC_ADDR23 0x60dc /* MAC address 23 */ 595194246Smarius#define CAS_MAC_ADDR24 0x60e0 /* MAC address 24 */ 596194246Smarius#define CAS_MAC_ADDR25 0x60e4 /* MAC address 25 */ 597194246Smarius#define CAS_MAC_ADDR26 0x60e8 /* MAC address 26 */ 598194246Smarius#define CAS_MAC_ADDR27 0x60ec /* MAC address 27 */ 599194246Smarius#define CAS_MAC_ADDR28 0x60f0 /* MAC address 28 */ 600194246Smarius#define CAS_MAC_ADDR29 0x60f4 /* MAC address 29 */ 601194246Smarius#define CAS_MAC_ADDR30 0x60f8 /* MAC address 30 */ 602194246Smarius#define CAS_MAC_ADDR31 0x60fc /* MAC address 31 */ 603194246Smarius#define CAS_MAC_ADDR32 0x6100 /* MAC address 32 */ 604194246Smarius#define CAS_MAC_ADDR33 0x6104 /* MAC address 33 */ 605194246Smarius#define CAS_MAC_ADDR34 0x6108 /* MAC address 34 */ 606194246Smarius#define CAS_MAC_ADDR35 0x610c /* MAC address 35 */ 607194246Smarius#define CAS_MAC_ADDR36 0x6110 /* MAC address 36 */ 608194246Smarius#define CAS_MAC_ADDR37 0x6114 /* MAC address 37 */ 609194246Smarius#define CAS_MAC_ADDR38 0x6118 /* MAC address 38 */ 610194246Smarius#define CAS_MAC_ADDR39 0x611c /* MAC address 39 */ 611194246Smarius#define CAS_MAC_ADDR40 0x6120 /* MAC address 40 */ 612194246Smarius#define CAS_MAC_ADDR41 0x6124 /* MAC address 41 */ 613194246Smarius#define CAS_MAC_ADDR42 0x6128 /* MAC address 42 */ 614194246Smarius#define CAS_MAC_ADDR43 0x612c /* MAC address 43 */ 615194246Smarius#define CAS_MAC_ADDR44 0x6130 /* MAC address 44 */ 616194246Smarius#define CAS_MAC_AFILTER0 0x614c /* address filter 0 */ 617194246Smarius#define CAS_MAC_AFILTER1 0x6150 /* address filter 1 */ 618194246Smarius#define CAS_MAC_AFILTER2 0x6154 /* address filter 2 */ 619194246Smarius#define CAS_MAC_AFILTER_MASK1_2 0x6158 /* address filter 2 & 1 mask*/ 620194246Smarius#define CAS_MAC_AFILTER_MASK0 0x615c /* address filter 0 mask */ 621194246Smarius#define CAS_MAC_HASH0 0x6160 /* hash table 0 */ 622194246Smarius#define CAS_MAC_HASH1 0x6164 /* hash table 1 */ 623194246Smarius#define CAS_MAC_HASH2 0x6168 /* hash table 2 */ 624194246Smarius#define CAS_MAC_HASH3 0x616c /* hash table 3 */ 625194246Smarius#define CAS_MAC_HASH4 0x6170 /* hash table 4 */ 626194246Smarius#define CAS_MAC_HASH5 0x6174 /* hash table 5 */ 627194246Smarius#define CAS_MAC_HASH6 0x6178 /* hash table 6 */ 628194246Smarius#define CAS_MAC_HASH7 0x617c /* hash table 7 */ 629194246Smarius#define CAS_MAC_HASH8 0x6180 /* hash table 8 */ 630194246Smarius#define CAS_MAC_HASH9 0x6184 /* hash table 9 */ 631194246Smarius#define CAS_MAC_HASH10 0x6188 /* hash table 10 */ 632194246Smarius#define CAS_MAC_HASH11 0x618c /* hash table 11 */ 633194246Smarius#define CAS_MAC_HASH12 0x6190 /* hash table 12 */ 634194246Smarius#define CAS_MAC_HASH13 0x6194 /* hash table 13 */ 635194246Smarius#define CAS_MAC_HASH14 0x6198 /* hash table 14 */ 636194246Smarius#define CAS_MAC_HASH15 0x619c /* hash table 15 */ 637194246Smarius#define CAS_MAC_NORM_COLL_CNT 0x61a0 /* normal collision counter */ 638194246Smarius#define CAS_MAC_FIRST_COLL_CNT 0x61a4 /* 1st attempt suc. collision counter */ 639194246Smarius#define CAS_MAC_EXCESS_COLL_CNT 0x61a8 /* excess collision counter */ 640194246Smarius#define CAS_MAC_LATE_COLL_CNT 0x61ac /* late collision counter */ 641194246Smarius#define CAS_MAC_DEFER_TMR_CNT 0x61b0 /* defer timer */ 642194246Smarius#define CAS_MAC_PEAK_ATTEMPTS 0x61b4 /* peak attempts */ 643194246Smarius#define CAS_MAC_RX_FRAME_COUNT 0x61b8 /* receive frame counter */ 644194246Smarius#define CAS_MAC_RX_LEN_ERR_CNT 0x61bc /* length error counter */ 645194246Smarius#define CAS_MAC_RX_ALIGN_ERR 0x61c0 /* alignment error counter */ 646194246Smarius#define CAS_MAC_RX_CRC_ERR_CNT 0x61c4 /* FCS error counter */ 647194246Smarius#define CAS_MAC_RX_CODE_VIOL 0x61c8 /* RX code violation error counter */ 648194246Smarius#define CAS_MAC_RANDOM_SEED 0x61cc /* random number seed */ 649194246Smarius#define CAS_MAC_MAC_STATE 0x61d0 /* MAC state machine */ 650194246Smarius 651194246Smarius#define CAS_MAC_SPC_TIME_MASK 0x0000ffff /* PAUSE time value */ 652194246Smarius#define CAS_MAC_SPC_TIME_SHFT 0 653194246Smarius#define CAS_MAC_SPC_SEND 0x00010000 /* Send PAUSE frame. */ 654194246Smarius 655194246Smarius/* CAS_MAC_TX_STATUS and CAS_MAC_TX_MASK register bits */ 656194246Smarius#define CAS_MAC_TX_FRAME_XMTD 0x00000001 /* Frame transmitted. */ 657194246Smarius#define CAS_MAC_TX_UNDERRUN 0x00000002 /* TX data starvation */ 658194246Smarius#define CAS_MAC_TX_MAX_PKT_ERR 0x00000004 /* frame > CAS_MAC_MAX_FRAME */ 659194246Smarius#define CAS_MAC_TX_NCC_EXP 0x00000008 /* normal coll. counter wrap */ 660194246Smarius#define CAS_MAC_TX_ECC_EXP 0x00000010 /* excess coll. counter wrap */ 661194246Smarius#define CAS_MAC_TX_LCC_EXP 0x00000020 /* late coll. counter wrap */ 662194246Smarius#define CAS_MAC_TX_FCC_EXP 0x00000040 /* 1st coll. counter wrap */ 663194246Smarius#define CAS_MAC_TX_DEFER_EXP 0x00000080 /* defer timer wrap */ 664194246Smarius#define CAS_MAC_TX_PEAK_EXP 0x00000100 /* peak attempts counter wrap */ 665194246Smarius 666194246Smarius/* CAS_MAC_RX_STATUS and CAS_MAC_RX_MASK register bits */ 667194246Smarius#define CAS_MAC_RX_FRAME_RCVD 0x00000001 /* Frame received. */ 668194246Smarius#define CAS_MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 669194246Smarius#define CAS_MAC_RX_FRAME_EXP 0x00000004 /* RX frame counter wrap */ 670194246Smarius#define CAS_MAC_RX_ALIGN_EXP 0x00000008 /* alignment error cntr. wrap */ 671194246Smarius#define CAS_MAC_RX_CRC_EXP 0x00000010 /* CRC error counter wrap */ 672194246Smarius#define CAS_MAC_RX_LEN_EXP 0x00000020 /* length error counter wrap */ 673194246Smarius#define CAS_MAC_RX_VIOL_EXP 0x00000040 /* code violation cntr. wrap */ 674194246Smarius 675194246Smarius/* CAS_MAC_CTRL_STATUS and CAS_MAC_CTRL_MASK register bits */ 676194246Smarius#define CAS_MAC_CTRL_PAUSE_RCVD 0x00000001 /* PAUSE received. */ 677194246Smarius#define CAS_MAC_CTRL_PAUSE 0x00000002 /* PAUSE state entered. */ 678194246Smarius#define CAS_MAC_CTRL_NON_PAUSE 0x00000004 /* PAUSE state left. */ 679194246Smarius 680194246Smarius#define CAS_MAC_CTRL_STATUS_PT_MASK 0xffff0000 /* PAUSE time */ 681194246Smarius#define CAS_MAC_CTRL_STATUS_PT_SHFT 16 682194246Smarius 683194246Smarius#define CAS_MAC_TX_CONF_EN 0x00000001 /* TX enable */ 684194246Smarius#define CAS_MAC_TX_CONF_ICARR 0x00000002 /* Ignore carrier sense. */ 685194246Smarius#define CAS_MAC_TX_CONF_ICOLLIS 0x00000004 /* Ignore collisions. */ 686194246Smarius#define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */ 687194246Smarius#define CAS_MAC_TX_CONF_NGU 0x00000010 /* Never give up. */ 688194246Smarius#define CAS_MAC_TX_CONF_NGUL 0x00000020 /* never give up limit */ 689194246Smarius#define CAS_MAC_TX_CONF_NBOFF 0x00000040 /* Disable backoff algorithm. */ 690194246Smarius#define CAS_MAC_TX_CONF_SDOWN 0x00000080 /* CSMA/CD slow down */ 691194246Smarius#define CAS_MAC_TX_CONF_NO_FCS 0x00000100 /* Don't generate FCS. */ 692194246Smarius#define CAS_MAC_TX_CONF_CARR 0x00000200 /* carrier extension enable */ 693194246Smarius 694194246Smarius#define CAS_MAC_RX_CONF_EN 0x00000001 /* RX enable */ 695194246Smarius#define CAS_MAC_RX_CONF_STRPPAD 0x00000002 /* Must not be set. */ 696194246Smarius#define CAS_MAC_RX_CONF_STRPFCS 0x00000004 /* Strip FCS bytes. */ 697194246Smarius#define CAS_MAC_RX_CONF_PROMISC 0x00000008 /* promiscuous mode enable */ 698194246Smarius#define CAS_MAC_RX_CONF_PGRP 0x00000010 /* promiscuous group mode en. */ 699194246Smarius#define CAS_MAC_RX_CONF_HFILTER 0x00000020 /* hash filter enable */ 700194246Smarius#define CAS_MAC_RX_CONF_AFILTER 0x00000040 /* address filter enable */ 701194246Smarius#define CAS_MAC_RX_CONF_DIS_DOE 0x00000080 /* disable discard on error */ 702194246Smarius#define CAS_MAC_RX_CONF_CARR 0x00000100 /* carrier extension enable */ 703194246Smarius 704194246Smarius#define CAS_MAC_CTRL_CONF_TXP 0x00000001 /* send PAUSE enable */ 705194246Smarius#define CAS_MAC_CTRL_CONF_RXP 0x00000002 /* receive PAUSE enable */ 706194246Smarius#define CAS_MAC_CTRL_CONF_PASSP 0x00000004 /* Pass PAUSE up to RX DMA. */ 707194246Smarius 708194246Smarius#define CAS_MAC_XIF_CONF_TX_OE 0x00000001 /* MII TX output drivers en. */ 709194246Smarius#define CAS_MAC_XIF_CONF_ILBK 0x00000002 /* MII internal loopback en. */ 710194246Smarius#define CAS_MAC_XIF_CONF_NOECHO 0x00000004 /* Disable echo. */ 711194246Smarius#define CAS_MAC_XIF_CONF_GMII 0x00000008 /* GMII (vs. MII) mode enable */ 712194246Smarius#define CAS_MAC_XIF_CONF_BUF_OE 0x00000010 /* MII_BUF_OE enable */ 713194246Smarius#define CAS_MAC_XIF_CONF_LNKLED 0x00000020 /* Force LINKLED# active. */ 714194246Smarius#define CAS_MAC_XIF_CONF_FDXLED 0x00000040 /* Force FDPLXLED# active. */ 715194246Smarius 716194246Smarius/* 717194246Smarius * The value of CAS_MAC_SLOT_TIME specifies the PAUSE time unit and depends 718194246Smarius * on whether carrier extension is enabled. 719194246Smarius */ 720194246Smarius#define CAS_MAC_SLOT_TIME_CARR 0x200 /* slot time for carr. ext. */ 721194246Smarius#define CAS_MAC_SLOT_TIME_NORM 0x40 /* slot time otherwise */ 722194246Smarius 723194246Smarius#define CAS_MAC_MAX_BF_FRM_MASK 0x00007fff /* maximum frame size */ 724194246Smarius#define CAS_MAC_MAX_BF_FRM_SHFT 0 725194246Smarius#define CAS_MAC_MAX_BF_BST_MASK 0x3fff0000 /* maximum burst size */ 726194246Smarius#define CAS_MAC_MAX_BF_BST_SHFT 16 727194246Smarius 728194246Smarius/* 729194246Smarius * MIF registers 730194246Smarius * The bit-bang registers use the low bit only. 731194246Smarius */ 732194246Smarius#define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */ 733194246Smarius#define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */ 734194246Smarius#define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */ 735194246Smarius#define CAS_MIF_FRAME 0x620c /* MIF frame/output */ 736194246Smarius#define CAS_MIF_CONF 0x6210 /* MIF configuration */ 737194246Smarius#define CAS_MIF_MASK 0x6214 /* MIF mask */ 738194246Smarius#define CAS_MIF_STATUS 0x6218 /* MIF status */ 739194246Smarius#define CAS_MIF_SM 0x621c /* MIF state machine */ 740194246Smarius 741194246Smarius#define CAS_MIF_FRAME_DATA 0x0000ffff /* instruction payload */ 742194246Smarius#define CAS_MIF_FRAME_TA_LSB 0x00010000 /* turn around LSB */ 743194246Smarius#define CAS_MIF_FRAME_TA_MSB 0x00020000 /* turn around MSB */ 744194246Smarius#define CAS_MIF_FRAME_REG_MASK 0x007c0000 /* register address */ 745194246Smarius#define CAS_MIF_FRAME_REG_SHFT 18 746194246Smarius#define CAS_MIF_FRAME_PHY_MASK 0x0f800000 /* PHY address */ 747194246Smarius#define CAS_MIF_FRAME_PHY_SHFT 23 748194246Smarius#define CAS_MIF_FRAME_OP_WRITE 0x10000000 /* write opcode */ 749194246Smarius#define CAS_MIF_FRAME_OP_READ 0x20000000 /* read opcode */ 750194246Smarius#define CAS_MIF_FRAME_OP_MASK \ 751194246Smarius (CAS_MIF_FRAME_OP_WRITE | CAS_MIF_FRAME_OP_READ) 752194246Smarius#define CAS_MIF_FRAME_ST 0x40000000 /* start of frame */ 753194246Smarius#define CAS_MIF_FRAME_ST_MASK 0xc0000000 /* start of frame */ 754194246Smarius 755194246Smarius#define CAS_MIF_FRAME_READ \ 756194246Smarius (CAS_MIF_FRAME_TA_MSB | CAS_MIF_FRAME_OP_READ | CAS_MIF_FRAME_ST) 757194246Smarius#define CAS_MIF_FRAME_WRITE \ 758194246Smarius (CAS_MIF_FRAME_TA_MSB | CAS_MIF_FRAME_OP_WRITE | CAS_MIF_FRAME_ST) 759194246Smarius 760194246Smarius#define CAS_MIF_CONF_PHY_SELECT 0x00000001 /* PHY select, 0: MDIO_0 */ 761194246Smarius#define CAS_MIF_CONF_POLL_EN 0x00000002 /* polling mechanism enable */ 762194246Smarius#define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */ 763194246Smarius#define CAS_MIF_CONF_PREG_MASK 0x000000f8 /* polled register */ 764194246Smarius#define CAS_MIF_CONF_PREG_SHFT 3 765194246Smarius#define CAS_MIF_CONF_MDI0 0x00000100 /* MDIO_0 data/attached */ 766194246Smarius#define CAS_MIF_CONF_MDI1 0x00000200 /* MDIO_1 data/attached */ 767194246Smarius#define CAS_MIF_CONF_PPHY_MASK 0x00007c00 /* polled PHY */ 768194246Smarius#define CAS_MIF_CONF_PPHY_SHFT 10 769194246Smarius 770194246Smarius/* CAS_MIF_MASK and CAS_MIF_STATUS bits */ 771194246Smarius#define CAS_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 772194246Smarius#define CAS_MIF_POLL_STATUS_SHFT 0 773194246Smarius#define CAS_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 774194246Smarius#define CAS_MIF_POLL_DATA_SHFT 8 775194246Smarius 776194246Smarius#define CAS_MIF_SM_CTRL_MASK 0x00000007 /* ctrl. state machine state */ 777194246Smarius#define CAS_MIF_SM_CTRL_SHFT 0 778194246Smarius#define CAS_MIF_SM_EXEC_MASK 0x00000060 /* exec. state machine state */ 779194246Smarius 780194246Smarius/* PCS/Serialink registers */ 781194246Smarius#define CAS_PCS_CTRL 0x9000 /* PCS MII control (PCS "BMCR") */ 782194246Smarius#define CAS_PCS_STATUS 0x9004 /* PCS MII status (PCS "BMSR") */ 783194246Smarius#define CAS_PCS_ANAR 0x9008 /* PCS MII advertisement */ 784194246Smarius#define CAS_PCS_ANLPAR 0x900c /* PCS MII link partner ability */ 785194246Smarius#define CAS_PCS_CONF 0x9010 /* PCS configuration */ 786194246Smarius#define CAS_PCS_SM 0x9014 /* PCS state machine */ 787194246Smarius#define CAS_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */ 788194246Smarius#define CAS_PCS_DATAPATH 0x9050 /* datapath mode */ 789194246Smarius#define CAS_PCS_SERDES_CTRL 0x9054 /* SERDES control */ 790194246Smarius#define CAS_PCS_OUTPUT_SELECT 0x9058 /* shared output select */ 791194246Smarius#define CAS_PCS_SERDES_STATUS 0x905c /* SERDES state */ 792194246Smarius#define CAS_PCS_PKT_CNT 0x9060 /* PCS packet counter */ 793194246Smarius 794194246Smarius#define CAS_PCS_CTRL_1000M 0x00000040 /* 1000Mbps speed select */ 795194246Smarius#define CAS_PCS_CTRL_COLL_TEST 0x00000080 /* collision test */ 796194246Smarius#define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */ 797194246Smarius#define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */ 798194246Smarius#define CAS_PCS_CTRL_ISOLATE 0x00000400 /* isolate PHY from MII */ 799194246Smarius#define CAS_PCS_CTRL_POWERDOWN 0x00000800 /* power down */ 800194246Smarius#define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */ 801194246Smarius#define CAS_PCS_CTRL_10_100M 0x00002000 /* 10/100Mbps speed select */ 802194246Smarius#define CAS_PCS_CTRL_RESET 0x00008000 /* Reset PCS. */ 803194246Smarius 804194246Smarius#define CAS_PCS_STATUS_EXTCAP 0x00000001 /* extended capability */ 805194246Smarius#define CAS_PCS_STATUS_JABBER 0x00000002 /* jabber condition detected */ 806194246Smarius#define CAS_PCS_STATUS_LINK 0x00000004 /* link status */ 807194246Smarius#define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */ 808194246Smarius#define CAS_PCS_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 809194246Smarius#define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 810194246Smarius#define CAS_PCS_STATUS_EXTENDED 0x00000100 /* extended status */ 811194246Smarius 812194246Smarius/* CAS_PCS_ANAR and CAS_PCS_ANLPAR register bits */ 813194246Smarius#define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */ 814194246Smarius#define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */ 815194246Smarius#define CAS_PCS_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 816194246Smarius#define CAS_PCS_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 817194246Smarius#define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 818194246Smarius#define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 819194246Smarius#define CAS_PCS_ANEG_RFLT_MASK \ 820194246Smarius (CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 821194246Smarius#define CAS_PCS_ANEG_ACK 0x00004000 /* acknowledge */ 822194246Smarius#define CAS_PCS_ANEG_NEXT_PAGE 0x00008000 /* next page */ 823194246Smarius 824194246Smarius#define CAS_PCS_CONF_EN 0x00000001 /* Enable PCS. */ 825194246Smarius#define CAS_PCS_CONF_SDO 0x00000002 /* signal detect override */ 826194246Smarius#define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */ 827194246Smarius#define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */ 828194246Smarius#define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */ 829194246Smarius#define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */ 830194246Smarius#define CAS_PCS_CONF_JS_MASK (CAS_PCS_CONF_JS_HF | CAS_PCS_CONF_JS_LF) 831194246Smarius#define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */ 832194246Smarius 833194246Smarius#define CAS_PCS_SM_TX_CTRL_MASK 0x0000000f /* TX control state */ 834194246Smarius#define CAS_PCS_SM_TX_CTRL_SHFT 0 835194246Smarius#define CAS_PCS_SM_RX_CTRL_MASK 0x000000f0 /* RX control state */ 836194246Smarius#define CAS_PCS_SM_RX_CTRL_SHFT 4 837194246Smarius#define CAS_PCS_SM_WSYNC_MASK 0x00000700 /* word sync. state */ 838194246Smarius#define CAS_PCS_SM_WSYNC_SHFT 8 839194246Smarius#define CAS_PCS_SM_SEQ_MASK 0x00001800 /* sequence detection state */ 840194246Smarius#define CAS_PCS_SM_SEQ_SHFT 11 841194246Smarius#define CAS_PCS_SM_LINK_UP 0x00016000 842194246Smarius#define CAS_PCS_SM_LINK_MASK 0x0001e000 /* link configuration state */ 843194246Smarius#define CAS_PCS_SM_LINK_SHFT 13 844194246Smarius#define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */ 845194246Smarius#define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */ 846194246Smarius#define CAS_PCS_SM_LOS 0x00400000 /* loss of signal */ 847194246Smarius#define CAS_PCS_SM_NLINK_BREAK 0x01000000 /* no link due to breaklink */ 848194246Smarius#define CAS_PCS_SM_NLINK_SERDES 0x02000000 /* no link due to SERDES */ 849194246Smarius#define CAS_PCS_SM_NLINK_C 0x04000000 /* no link due to bad C codes */ 850194246Smarius#define CAS_PCS_SM_NLINK_SYNC 0x08000000 /* no link due to word sync. */ 851194246Smarius#define CAS_PCS_SM_NLINK_WAIT_C 0x10000000 /* no link, waiting for ack. */ 852194246Smarius#define CAS_PCS_SM_NLINK_NIDLE 0x20000000 /* no link due to no idle */ 853194246Smarius 854194246Smarius/* 855194246Smarius * CAS_PCS_INTR_STATUS has no corresponding mask register. It can only 856194246Smarius * be masked with CAS_INTR_PCS_INT. 857194246Smarius */ 858194246Smarius#define CAS_PCS_INTR_LINK 0x00000004 /* link status change */ 859194246Smarius 860194246Smarius#define CAS_PCS_DATAPATH_MII 0x00000001 /* GMII/MII and MAC loopback */ 861194246Smarius#define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 862194246Smarius 863194246Smarius#define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */ 864194246Smarius#define CAS_PCS_SERDES_CTRL_ESD 0x00000002 /* En. sync char. detection. */ 865194246Smarius#define CAS_PCS_SERDES_CTRL_LR 0x00000004 /* Lock to reference clock. */ 866194246Smarius 867194246Smarius#define CAS_PCS_SERDES_STATUS_T 0x00000000 /* Undergoing test. */ 868194246Smarius#define CAS_PCS_SERDES_STATUS_L 0x00000001 /* Waiting 500us w/ lockrefn. */ 869194246Smarius#define CAS_PCS_SERDES_STATUS_C 0x00000002 /* Waiting for comma detect. */ 870194246Smarius#define CAS_PCS_SERDES_STATUS_S 0x00000003 /* Receive data is sync. */ 871194246Smarius 872194246Smarius#define CAS_PCS_PKT_CNT_TX_MASK 0x000007ff /* TX packets */ 873194246Smarius#define CAS_PCS_PKT_CNT_TX_SHFT 0 874194246Smarius#define CAS_PCS_PKT_CNT_RX_MASK 0x07ff0000 /* RX packets */ 875194246Smarius#define CAS_PCS_PKT_CNT_RX_SHFT 16 876194246Smarius 877194246Smarius/* 878194246Smarius * PCI expansion ROM runtime access 879194246Smarius * Cassinis and Saturn map a 1MB space for the PCI expansion ROM as the 880194246Smarius * second half of the first register bank, although they only support up 881194246Smarius * to 64KB ROMs. 882194246Smarius */ 883194246Smarius#define CAS_PCI_ROM_OFFSET 0x100000 884194246Smarius#define CAS_PCI_ROM_SIZE 0x10000 885194246Smarius 886194246Smarius/* secondary local bus device */ 887194246Smarius#define CAS_SEC_LBDEV_OFFSET 0x180000 888194246Smarius#define CAS_SEC_LBDE_SIZE 0x7ffff 889194246Smarius 890194246Smarius/* wired PHY addresses */ 891194246Smarius#define CAS_PHYAD_INTERNAL 1 892194246Smarius#define CAS_PHYAD_EXTERNAL 0 893194246Smarius 894194246Smarius/* wired RX FIFO size in bytes */ 895194246Smarius#define CAS_RX_FIFO_SIZE 16 * 1024 896194246Smarius 897194246Smarius/* 898194246Smarius * descriptor ring structures 899194246Smarius */ 900194246Smariusstruct cas_desc { 901194246Smarius uint64_t cd_flags; 902194246Smarius uint64_t cd_buf_ptr; 903194246Smarius}; 904194246Smarius 905194246Smarius/* 906194246Smarius * transmit flags 907194246Smarius * CAS_TD_CKSUM_START_MASK, CAS_TD_CKSUM_STUFF_MASK, CAS_TD_CKSUM_EN and 908194246Smarius * CAS_TD_INT_ME only need to be set in 1st descriptor of a frame. 909194246Smarius */ 910194246Smarius#define CAS_TD_BUF_LEN_MASK 0x0000000000003fffULL /* buffer length */ 911194246Smarius#define CAS_TD_BUF_LEN_SHFT 0 912194246Smarius#define CAS_TD_CKSUM_START_MASK 0x00000000001f8000ULL /* checksum start... */ 913194246Smarius#define CAS_TD_CKSUM_START_SHFT 15 /* ...offset */ 914194246Smarius#define CAS_TD_CKSUM_STUFF_MASK 0x000000001fe00000ULL /* checksum stuff... */ 915194246Smarius#define CAS_TD_CKSUM_STUFF_SHFT 21 /* ...offset */ 916194246Smarius#define CAS_TD_CKSUM_EN 0x0000000020000000ULL /* checksum enable */ 917194246Smarius#define CAS_TD_END_OF_FRAME 0x0000000040000000ULL /* last desc. of pkt. */ 918194246Smarius#define CAS_TD_START_OF_FRAME 0x0000000080000000ULL /* 1st desc. of pkt. */ 919194246Smarius#define CAS_TD_INT_ME 0x0000000100000000ULL /* intr. when in FIFO */ 920194246Smarius#define CAS_TD_NO_CRC 0x0000000200000000ULL /* Don't insert CRC. */ 921194246Smarius 922194246Smarius/* receive flags */ 923194246Smarius#define CAS_RD_BUF_INDEX_MASK 0x0000000000003fffULL /* data buffer index */ 924194246Smarius#define CAS_RD_BUF_INDEX_SHFT 0 925194246Smarius 926194246Smarius/* 927194246Smarius * receive completion ring structure 928194246Smarius */ 929194246Smariusstruct cas_rx_comp { 930194246Smarius uint64_t crc_word1; 931194246Smarius uint64_t crc_word2; 932194246Smarius uint64_t crc_word3; 933194246Smarius uint64_t crc_word4; 934194246Smarius}; 935194246Smarius 936194246Smarius#define CAS_RC1_DATA_SIZE_MASK 0x0000000007ffe000ULL /* pkt. data length */ 937194246Smarius#define CAS_RC1_DATA_SIZE_SHFT 13 938194246Smarius#define CAS_RC1_DATA_OFF_MASK 0x000001fff8000000ULL /* data buffer offset */ 939194246Smarius#define CAS_RC1_DATA_OFF_SHFT 27 940194246Smarius#define CAS_RC1_DATA_INDEX_MASK 0x007ffe0000000000ULL /* data buffer index */ 941194246Smarius#define CAS_RC1_DATA_INDEX_SHFT 41 942194246Smarius#define CAS_RC1_SKIP_MASK 0x0180000000000000ULL /* entries to skip */ 943194246Smarius#define CAS_RC1_SKIP_SHFT 55 944194246Smarius#define CAS_RC1_RELEASE_NEXT 0x0200000000000000ULL /* last in reas. buf. */ 945194246Smarius#define CAS_RC1_SPLIT_PKT 0x0400000000000000ULL /* used 2 reas. buf. */ 946194246Smarius#define CAS_RC1_RELEASE_FLOW 0x0800000000000000ULL /* last pkt. of flow */ 947194246Smarius#define CAS_RC1_RELEASE_DATA 0x1000000000000000ULL /* reas. buf. full */ 948194246Smarius#define CAS_RC1_RELEASE_HDR 0x2000000000000000ULL /* header buf. full */ 949194246Smarius#define CAS_RC1_TYPE_HW 0x0000000000000000ULL /* owned by hardware */ 950194246Smarius#define CAS_RC1_TYPE_RSFB 0x4000000000000000ULL /* stale flow buf... */ 951194246Smarius#define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */ 952194246Smarius#define CAS_RC1_TYPE_RFP 0xc000000000000000ULL /* flow packet... */ 953194246Smarius#define CAS_RC1_TYPE_MASK CAS_RC1_TYPE_RFP /* ...release */ 954194246Smarius#define CAS_RC1_TYPE_SHFT 62 955194246Smarius 956194246Smarius#define CAS_RC2_NEXT_INDEX_MASK 0x00000007ffe00000ULL /* next buf. of pkt. */ 957194246Smarius#define CAS_RC2_NEXT_INDEX_SHFT 21 958194246Smarius#define CAS_RC2_HDR_SIZE_MASK 0x00000ff800000000ULL /* header length */ 959194246Smarius#define CAS_RC2_HDR_SIZE_SHFT 35 960194246Smarius#define CAS_RC2_HDR_OFF_MASK 0x0003f00000000000ULL /* header buf. offset */ 961194246Smarius#define CAS_RC2_HDR_OFF_SHFT 44 962194246Smarius#define CAS_RC2_HDR_INDEX_MASK 0xfffc000000000000ULL /* header buf. index */ 963194246Smarius#define CAS_RC2_HDR_INDEX_SHFT 50 964194246Smarius 965194246Smarius#define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */ 966194246Smarius#define CAS_RC3_JUMBO_PKT 0x0000000000000002ULL /* pkt. > 1522 bytes */ 967194246Smarius#define CAS_RC3_JMBHS_EN 0x0000000000000004ULL /* jmb. hdr. spl. en. */ 968194246Smarius#define CAS_RC3_CSO_MASK 0x000000000007f000ULL /* checksum start... */ 969194246Smarius#define CAS_RC3_CSO_SHFT 12 /* ...offset */ 970194246Smarius#define CAS_RC3_FLOWID_MASK 0x0000000001f80000ULL /* flow ID of pkt. */ 971194246Smarius#define CAS_RC3_FLOWID_SHFT 19 972194246Smarius#define CAS_RC3_OP_MASK 0x000000000e000000ULL /* opcode */ 973194246Smarius#define CAS_RC3_OP_SHFT 25 974194246Smarius#define CAS_RC3_FRC_FLAG 0x0000000010000000ULL /* op. 2 batch. lkhd. */ 975194246Smarius#define CAS_RC3_NASSIST 0x0000000020000000ULL /* no assist */ 976194246Smarius#define CAS_RC3_LB_MASK 0x000001f800000000ULL /* load balancing key */ 977194246Smarius#define CAS_RC3_LB_SHFT 35 978194246Smarius#define CAS_RC3_L3HO_MASK 0x0000fe0000000000ULL /* layer 3 hdr. off. */ 979194246Smarius#define CAS_RC3_L3HO_SHFT 41 980194246Smarius#define CAS_RC3_PLUS_ENC_PKT 0x0000020000000000ULL /* IPsec AH/ESP pkt. */ 981194246Smarius#define CAS_RC3_PLUS_L3HO_MASK 0x0000fc0000000000ULL /* layer 3 hdr. off. */ 982194246Smarius#define CAS_RC3_PLUS_L3HO_SHFT 42 983194246Smarius#define CAS_RC3_SAP_MASK 0xffff000000000000ULL /* ethertype */ 984194246Smarius#define CAS_RC3_SAP_SHFT 48 985194246Smarius 986194246Smarius#define CAS_RC4_TCP_CSUM_MASK 0x000000000000ffffULL /* TCP checksum */ 987194246Smarius#define CAS_RC4_TCP_CSUM_SHFT 0 988194246Smarius#define CAS_RC4_PKT_LEN_MASK 0x000000003fff0000ULL /* entire pkt. length */ 989194246Smarius#define CAS_RC4_PKT_LEN_SHFT 16 990194246Smarius#define CAS_RC4_PAM_MASK 0x00000003c0000000ULL /* mcast. addr. match */ 991194246Smarius#define CAS_RC4_PAM_SHFT 30 992194246Smarius#define CAS_RC4_ZERO 0x0000080000000000ULL /* owned by software */ 993194246Smarius#define CAS_RC4_HASH_VAL_MASK 0x0ffff00000000000ULL /* mcast. addr. hash */ 994194246Smarius#define CAS_RC4_HASH_VAL_SHFT 44 995194246Smarius#define CAS_RC4_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 996194246Smarius#define CAS_RC4_BAD 0x4000000000000000ULL /* CRC error */ 997194246Smarius#define CAS_RC4_LEN_MMATCH 0x8000000000000000ULL /* length field mism. */ 998194246Smarius 999194246Smarius#define CAS_GET(reg, bits) (((reg) & (bits ## _MASK)) >> (bits ## _SHFT)) 1000194246Smarius#define CAS_SET(val, bits) (((val) << (bits ## _SHFT)) & (bits ## _MASK)) 1001194246Smarius 1002194246Smarius#endif 1003