if_casreg.h revision 194246
1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp 28 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius 29 * 30 * $FreeBSD: head/sys/dev/cas/if_casreg.h 194246 2009-06-15 18:22:41Z marius $ 31 */ 32 33#ifndef _IF_CASREG_H 34#define _IF_CASREG_H 35 36/* 37 * register definitions for Sun Cassini/Cassini+ and National Semiconductor 38 * DP83065 Saturn Gigabit Ethernet controllers 39 */ 40 41/* global resources */ 42#define CAS_CAW 0x0004 /* core arbitration weight */ 43#define CAS_INF_BURST 0x0008 /* infinite burst enable */ 44#define CAS_STATUS 0x000c /* interrupt status */ 45#define CAS_INTMASK 0x0010 /* interrupt mask */ 46#define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */ 47#define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */ 48#define CAS_ERROR_STATUS 0x1000 /* PCI error status */ 49#define CAS_ERROR_MASK 0x1004 /* PCI error mask */ 50#define CAS_BIM_CONF 0x1008 /* BIM configuration */ 51#define CAS_BIM_DIAG 0x100c /* BIM diagnostic */ 52#define CAS_RESET 0x1010 /* software reset */ 53#define CAS_BIM_LDEV_OEN 0x1020 /* BIM local device output enable */ 54#define CAS_BIM_BUF_ADDR 0x1024 /* BIM buffer address */ 55#define CAS_BIM_BUF_DATA_LO 0x1028 /* BIM buffer data low */ 56#define CAS_BIM_BUF_DATA_HI 0x102c /* BIM buffer data high */ 57#define CAS_BIM_RAM_BIST 0x1030 /* BIM RAM BIST control/status */ 58#define CAS_PROBE_MUX_SELECT 0x1034 /* PROBE MUX SELECT */ 59#define CAS_INTMASK2 0x1038 /* interrupt mask 2 for INTB */ 60#define CAS_STATUS2 0x103c /* interrupt status 2 for INTB */ 61#define CAS_CLEAR_ALIAS2 0x1040 /* clear mask alias 2 for INTB */ 62#define CAS_STATUS_ALIAS2 0x1044 /* interrupt status alias 2 for INTB */ 63#define CAS_INTMASK3 0x1048 /* interrupt mask 3 for INTC */ 64#define CAS_STATUS3 0x104c /* interrupt status 3 for INTC */ 65#define CAS_CLEAR_ALIAS3 0x1050 /* clear mask alias 3 for INTC */ 66#define CAS_STATUS_ALIAS3 0x1054 /* interrupt status alias 3 for INTC */ 67#define CAS_INTMASK4 0x1058 /* interrupt mask 4 for INTD */ 68#define CAS_STATUS4 0x105c /* interrupt status 4 for INTD */ 69#define CAS_CLEAR_ALIAS4 0x1060 /* clear mask alias 4 for INTD */ 70#define CAS_STATUS_ALIAS4 0x1064 /* interrupt status alias 4 for INTD */ 71 72#define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */ 73#define CAS_CAW_RX_WGHT_SHFT 0 /* ...weighted round robin */ 74#define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */ 75#define CAS_CAW_TX_WGHT_SHFT 2 /* ...weighted round robin */ 76#define CAS_CAW_RR_DIS 0x00000010 /* weighted round robin dis. */ 77 78#define CAS_INF_BURST_EN 0x00000001 /* Allow bursts > cachline. */ 79 80/* 81 * shared interrupt bits for CAS_STATUS, CAS_INTMASK, CAS_CLEAR_ALIAS and 82 * CAS_STATUS_ALIAS 83 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies 84 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS. 85 */ 86#define CAS_INTR_TX_INT_ME 0x00000001 /* Frame w/ INT_ME set sent. */ 87#define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */ 88#define CAS_INTR_TX_DONE 0x00000004 /* Any TX frame transferred. */ 89#define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */ 90#define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */ 91#define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */ 92#define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */ 93#define CAS_INTR_RX_COMP_FULL 0x00000080 /* RX completion ring full */ 94#define CAS_INTR_RX_BUF_AEMPTY 0x00000100 /* RX desc. ring almost empty */ 95#define CAS_INTR_RX_COMP_AFULL 0x00000200 /* RX cmpl. ring almost full */ 96#define CAS_INTR_RX_LEN_MMATCH 0x00000400 /* length field mismatch */ 97#define CAS_INTR_SUMMARY 0x00001000 /* summary interrupt bit */ 98#define CAS_INTR_PCS_INT 0x00002000 /* PCS interrupt */ 99#define CAS_INTR_TX_MAC_INT 0x00004000 /* TX MAC interrupt */ 100#define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */ 101#define CAS_INTR_MAC_CTRL_INT 0x00010000 /* MAC control interrupt */ 102#define CAS_INTR_MIF 0x00020000 /* MIF interrupt */ 103#define CAS_INTR_PCI_ERROR_INT 0x00040000 /* PCI error interrupt */ 104 105#define CAS_STATUS_TX_COMP3_MASK 0xfff80000 /* TX completion 3 */ 106#define CAS_STATUS_TX_COMP3_SHFT 19 107 108/* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */ 109#define CAS_ERROR_DTRTO 0x00000002 /* delayed trans. timeout */ 110#define CAS_ERROR_OTHER 0x00000004 /* errors (see PCIR_STATUS) */ 111#define CAS_ERROR_DMAW_ZERO 0x00000008 /* zero count DMA write */ 112#define CAS_ERROR_DMAR_ZERO 0x00000010 /* zero count DMA read */ 113#define CAS_ERROR_RTRTO 0x00000020 /* 255 retries exceeded */ 114 115#define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */ 116#define CAS_BIM_CONF_M66EN 0x00000008 /* PCI clock is 66MHz (ro). */ 117#define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */ 118#define CAS_BIM_CONF_DPAR_EN 0x00000020 /* parity error intr. enable */ 119#define CAS_BIM_CONF_RMA_EN 0x00000040 /* master abort intr. enable */ 120#define CAS_BIM_CONF_RTA_EN 0x00000080 /* target abort intr. enable */ 121#define CAS_BIM_CONF_DIS_BIM 0x00000200 /* Stop PCI DMA transactions. */ 122#define CAS_BIM_CONF_BIM_DIS 0x00000400 /* BIM was stopped (ro). */ 123#define CAS_BIM_CONF_BLOCK_PERR 0x00000800 /* Block PERR# to PCI bus. */ 124 125#define CAS_BIM_DIAG_BRST_SM 0x0000007f /* burst ctrl. state machine */ 126#define CAS_BIM_DIAG_MSTR_SM 0x3fffff00 127 128#define CAS_RESET_TX 0x00000001 /* Reset TX DMA engine. */ 129#define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */ 130#define CAS_RESET_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 131#define CAS_RESET_PCS_DIS 0x00000008 /* PCS reset disable */ 132#define CAS_RESET_BREQ_SM 0x00007f00 /* breq state machine */ 133#define CAS_RESET_PCIARB 0x00070000 /* PCI arbitration state */ 134#define CAS_RESET_RDPCI 0x00300000 /* read PCI state */ 135#define CAS_RESET_RDARB 0x00c00000 /* read arbitration state */ 136#define CAS_RESET_WRPCI 0x06000000 /* write PCI state */ 137#define CAS_RESET_WRARB 0x38000000 /* write arbitration state */ 138 139#define CAS_BIM_LDEV_OEN_PAD 0x00000001 /* addr. bus, RW and OE */ 140#define CAS_BIM_LDEV_OEN_PROM 0x00000002 /* PROM chip select */ 141#define CAS_BIM_LDEV_OEN_EXT 0x00000004 /* secondary local bus device */ 142#define CAS_BIM_LDEV_OEN_SOFT_0 0x00000008 /* soft. progr. ctrl. bit 0 */ 143#define CAS_BIM_LDEV_OEN_SOFT_1 0x00000010 /* soft. progr. ctrl. bit 1 */ 144#define CAS_BIM_LDEV_OEN_HWRST 0x00000020 /* hw. reset (Cassini+ only) */ 145 146#define CAS_BIM_BUF_ADDR_INDEX 0x0000003f /* buffer entry index */ 147#define CAS_BIM_BUF_ADDR_RDWR 0x00000040 /* 0: read, 1: write access */ 148 149#define CAS_BIM_RAM_BIST_START 0x00000001 /* Start BIST on read buffer. */ 150#define CAS_BIM_RAM_BIST_SUM 0x00000004 /* read buffer pass summary */ 151#define CAS_BIM_RAM_BIST_LO 0x00000010 /* read buf. low bank passes */ 152#define CAS_BIM_RAM_BIST_HI 0x00000020 /* read buf. high bank passes */ 153 154#define CAS_PROBE_MUX_SELECT_LO 0x0000000f /* P_A[7:0] */ 155#define CAS_PROBE_MUX_SELECT_HI 0x000000f0 /* P_A[15:8] */ 156#define CAS_PROBE_MUX_SELECT_SB 0x000000f0 /* txdma_wr address and size */ 157#define CAS_PROBE_MUX_SELECT_EN 0xf0000000 /* enable probe on P_A[15:0] */ 158 159/* 160 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4] 161 * and CAS_STATUS_ALIAS[2-4]. 162 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which 163 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4]. 164 */ 165#define CAS_INTRN_RX_DONE 0x00000001 /* >=1 RX frames transferred. */ 166#define CAS_INTRN_RX_COMP_FULL 0x00000002 /* RX completion ring full */ 167#define CAS_INTRN_RX_COMP_AFULL 0x00000004 /* RX cmpl. ring almost full */ 168#define CAS_INTRN_RX_BUF_NA 0x00000008 /* RX buffer not available */ 169#define CAS_INTRN_RX_BUF_AEMPTY 0x00000010 /* RX desc. ring almost empty */ 170 171/* INTn enable bit for CAS_INTMASK[2-4] */ 172#define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */ 173 174/* TX DMA registers */ 175#define CAS_TX_CONF 0x2004 /* TX configuration */ 176#define CAS_TX_FIFO_WR 0x2014 /* FIFO write pointer */ 177#define CAS_TX_FIFO_SDWR 0x2018 /* FIFO shadow write pointer */ 178#define CAS_TX_FIFO_RD 0x201c /* FIFO read pointer */ 179#define CAS_TX_FIFO_SDRD 0x2020 /* FIFO shadow read pointer */ 180#define CAS_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 181#define CAS_TX_SM1 0x2028 /* TX state machine 1 */ 182#define CAS_TX_SM2 0x202c /* TX state machine 2 */ 183#define CAS_TX_DATA_PTR_LO 0x2030 /* TX data pointer low */ 184#define CAS_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ 185#define CAS_TX_KICK1 0x2038 /* TX kick 1 */ 186#define CAS_TX_KICK2 0x203c /* TX kick 2 */ 187#define CAS_TX_KICK3 0x2040 /* TX kick 3 */ 188#define CAS_TX_KICK4 0x2044 /* TX kick 4 */ 189#define CAS_TX_COMP1 0x2048 /* TX completion 1 */ 190#define CAS_TX_COMP2 0x204c /* TX completion 2 */ 191#define CAS_TX_COMP3 0x2050 /* TX completion 3 */ 192#define CAS_TX_COMP4 0x2054 /* TX completion 4 */ 193#define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */ 194#define CAS_TX_COMPWB_BASE_HI 0x205c /* TX completion writeback base high */ 195#define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */ 196#define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */ 197#define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */ 198#define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */ 199#define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */ 200#define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */ 201#define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */ 202#define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */ 203#define CAS_TX_MAXBURST1 0x2080 /* TX MaxBurst 1 */ 204#define CAS_TX_MAXBURST2 0x2084 /* TX MaxBurst 2 */ 205#define CAS_TX_MAXBURST3 0x2088 /* TX MaxBurst 3 */ 206#define CAS_TX_MAXBURST4 0x208c /* TX MaxBurst 4 */ 207#define CAS_TX_FIFO_ADDR 0x2104 /* TX FIFO address */ 208#define CAS_TX_FIFO_TAG 0x2108 /* TX FIFO tag */ 209#define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */ 210#define CAS_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data highT1 */ 211#define CAS_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data highT0 */ 212#define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size in 64 byte multiples */ 213#define CAS_TX_RAM_BIST 0x211c /* TX RAM BIST control/status */ 214 215#define CAS_TX_CONF_TXDMA_EN 0x00000001 /* TX DMA enable */ 216#define CAS_TX_CONF_FIFO_PIO 0x00000002 /* Allow TX FIFO PIO access. */ 217#define CAS_TX_CONF_DESC1_MASK 0x0000003c /* TX descriptor ring 1 size */ 218#define CAS_TX_CONF_DESC1_SHFT 2 219#define CAS_TX_CONF_DESC2_MASK 0x000003c0 /* TX descriptor ring 2 size */ 220#define CAS_TX_CONF_DESC2_SHFT 6 221#define CAS_TX_CONF_DESC3_MASK 0x00003c00 /* TX descriptor ring 3 size */ 222#define CAS_TX_CONF_DESC3_SHFT 10 223#define CAS_TX_CONF_DESC4_MASK 0x0003c000 /* TX descriptor ring 4 size */ 224#define CAS_TX_CONF_DESC4_SHFT 14 225#define CAS_TX_CONF_PACED 0x00100000 /* ALL intr. on FIFO empty */ 226#define CAS_TX_CONF_RDPP_DIS 0x01000000 /* Should always be set. */ 227#define CAS_TX_CONF_COMPWB_Q1 0x02000000 /* Completion writeback... */ 228#define CAS_TX_CONF_COMPWB_Q2 0x04000000 /* ...happens at the end... */ 229#define CAS_TX_CONF_COMPWB_Q3 0x08000000 /* ...of every packet in... */ 230#define CAS_TX_CONF_COMPWB_Q4 0x10000000 /* ...queue n. */ 231#define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */ 232#define CAS_TX_CONF_CTX_MASK 0xc0000000 /* test port selection */ 233#define CAS_TX_CONF_CTX_SHFT 30 234 235#define CAS_TX_COMPWB_ALIGN 2048 /* TX compl. W/B alignment */ 236 237#define CAS_TX_DESC_ALIGN 2048 /* TX descriptor alignment */ 238 239/* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */ 240#define CAS_DESC_32 0x0 /* 32 descriptors */ 241#define CAS_DESC_64 0x1 /* 64 descriptors */ 242#define CAS_DESC_128 0x2 /* 128 descriptors */ 243#define CAS_DESC_256 0x3 /* 256 descriptors */ 244#define CAS_DESC_512 0x4 /* 512 descriptors */ 245#define CAS_DESC_1K 0x5 /* 1k descriptors */ 246#define CAS_DESC_2K 0x6 /* 2k descriptors */ 247#define CAS_DESC_4K 0x7 /* 4k descriptors */ 248#define CAS_DESC_8K 0x8 /* 8k descriptors */ 249 250#define CAS_TX_SM1_CHAIN 0x000003ff /* chaining state machine */ 251#define CAS_TX_SM1_CKSUM 0x00000c00 /* checksum state machine */ 252#define CAS_TX_SM1_TX_FIFO_LOAD 0x0003f000 /* TX FIFO load state machine */ 253#define CAS_TX_SM1_TX_FIFO_UNLD 0x003c0000 /* TX FIFO unload state mach. */ 254#define CAS_TX_SM1_CACHE_CTRL 0x03c00000 /* cache control state mach. */ 255#define CAS_TX_SM1_CBQARB 0x03c00000 /* CBQ arbiter state machine */ 256 257#define CAS_TX_SM2_COMPWB 0x00000007 /* compl. WB state machine */ 258#define CAS_TX_SM2_SUB_LOAD 0x00000038 /* sub load state machine */ 259#define CAS_TX_SM2_KICK 0x000000c0 /* kick state machine */ 260 261#define CAS_TX_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */ 262#define CAS_TX_RAM_BIST_SUMMARY 0x00000002 /* All RAM okay */ 263#define CAS_TX_RAM_BIST_RAM32B 0x00000004 /* RAM32B okay */ 264#define CAS_TX_RAM_BIST_RAM33B 0x00000008 /* RAM33B okay */ 265#define CAS_TX_RAM_BIST_RAM32A 0x00000010 /* RAM32A okay */ 266#define CAS_TX_RAM_BIST_RAM33A 0x00000020 /* RAM33A okay */ 267#define CAS_TX_RAM_BIST_SM 0x000001c0 /* RAM BIST state machine */ 268 269/* RX DMA registers */ 270#define CAS_RX_CONF 0x4000 /* RX configuration */ 271#define CAS_RX_PSZ 0x4004 /* RX page size */ 272#define CAS_RX_FIFO_WR 0x4008 /* RX FIFO write pointer */ 273#define CAS_RX_FIFO_RD 0x400c /* RX FIFO read pointer */ 274#define CAS_RX_IPP_WR 0x4010 /* RX IPP FIFO write pointer */ 275#define CAS_RX_IPP_SDWR 0x4014 /* RX IPP FIFO shadow write pointer */ 276#define CAS_RX_IPP_RD 0x4018 /* RX IPP FIFO read pointer */ 277#define CAS_RX_DEBUG 0x401c /* RX debug */ 278#define CAS_RX_PTHRS 0x4020 /* RX PAUSE threshold */ 279#define CAS_RX_KICK 0x4024 /* RX kick */ 280#define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */ 281#define CAS_RX_DESC_BASE_HI 0x402c /* RX descriptor ring base high */ 282#define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */ 283#define CAS_RX_COMP_BASE_HI 0x4034 /* RX completion ring base high */ 284#define CAS_RX_COMP 0x4038 /* RX completion */ 285#define CAS_RX_COMP_HEAD 0x403c /* RX completion head */ 286#define CAS_RX_COMP_TAIL 0x4040 /* RX completion tail */ 287#define CAS_RX_BLANK 0x4044 /* RX blanking for ISR read */ 288#define CAS_RX_AEMPTY_THRS 0x4048 /* RX almost empty threshold */ 289#define CAS_RX_RED 0x4048 /* RX random early detection enable */ 290#define CAS_RX_FF 0x4050 /* RX FIFO fullness */ 291#define CAS_RX_IPP_PKT_CNT 0x4054 /* RX IPP packet counter */ 292#define CAS_RX_WORKING_DMA_LO 0x4058 /* RX working DMA pointer low */ 293#define CAS_RX_WORKING_DMA_HI 0x405c /* RX working DMA pointer high */ 294#define CAS_RX_BIST 0x4060 /* RX BIST */ 295#define CAS_RX_CTRL_FIFO_WR 0x4064 /* RX control FIFO write pointer */ 296#define CAS_RX_CTRL_FIFO_RD 0x4068 /* RX control FIFO read pointer */ 297#define CAS_RX_BLANK_ALIAS 0x406c /* RX blanking for ISR read alias */ 298#define CAS_RX_FIFO_ADDR 0x4080 /* RX FIFO address */ 299#define CAS_RX_FIFO_TAG 0x4084 /* RX FIFO tag */ 300#define CAS_RX_FIFO_DATA_LO 0x4088 /* RX FIFO data low */ 301#define CAS_RX_FIFO_DATA_HI_T0 0x408c /* RX FIFO data highT0 */ 302#define CAS_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data highT1 */ 303#define CAS_RX_CTRL_FIFO 0x4094 /* RX control FIFO and batching FIFO */ 304#define CAS_RX_CTRL_FIFO_LO 0x4098 /* RX control FIFO data low */ 305#define CAS_RX_CTRL_FIFO_MD 0x409c /* RX control FIFO data mid */ 306#define CAS_RX_CTRL_FIFO_HI 0x4100 /* RX control FIFO data high, flowID */ 307#define CAS_RX_IPP_ADDR 0x4104 /* RX IPP FIFO address */ 308#define CAS_RX_IPP_TAG 0x4108 /* RX IPP FIFO tag */ 309#define CAS_RX_IPP_DATA_LO 0x410c /* RX IPP FIFO data low */ 310#define CAS_RX_IPP_DATA_HI_T0 0x4110 /* RX IPP FIFO data highT0 */ 311#define CAS_RX_IPP_DATA_HI_T1 0x4114 /* RX IPP FIFO data highT1 */ 312#define CAS_RX_HDR_PAGE_LO 0x4118 /* RX header page pointer low */ 313#define CAS_RX_HDR_PAGE_HIGH 0x411c /* RX header page pointer high */ 314#define CAS_RX_MTU_PAGE_LO 0x4120 /* RX MTU page pointer low */ 315#define CAS_RX_MTU_PAGE_HIGH 0x4124 /* RX MTU page pointer high */ 316#define CAS_RX_REAS_DMA_ADDR 0x4128 /* RX reassembly DMA table address */ 317#define CAS_RX_REAS_DMA_DATA_LO 0x412c /* RX reassembly DMA table data low */ 318#define CAS_RX_REAS_DMA_DATA_MD 0x4130 /* RX reassembly DMA table data mid */ 319#define CAS_RX_REAS_DMA_DATA_HI 0x4134 /* RX reassembly DMA table data high */ 320/* The rest of the RX DMA registers are Cassini+/Saturn only. */ 321#define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */ 322#define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */ 323#define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */ 324#define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */ 325#define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */ 326#define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */ 327#define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */ 328#define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */ 329#define CAS_RX_KICK2 0x4220 /* RX kick 2 */ 330#define CAS_RX_COMP2 0x4224 /* RX completion 2 */ 331#define CAS_RX_COMP_HEAD2 0x4228 /* RX completion head 2 */ 332#define CAS_RX_COMP_TAIL2 0x422c /* RX completion tail 2 */ 333#define CAS_RX_COMP_HEAD3 0x4230 /* RX completion head 3 */ 334#define CAS_RX_COMP_TAIL3 0x4234 /* RX completion tail 3 */ 335#define CAS_RX_COMP_HEAD4 0x4238 /* RX completion head 4 */ 336#define CAS_RX_COMP_TAIL4 0x423c /* RX completion tail 4 */ 337#define CAS_RX_AEMPTY_THRS2 0x4048 /* RX almost empty threshold 2 */ 338 339#define CAS_RX_CONF_RXDMA_EN 0x00000001 /* RX DMA enable */ 340#define CAS_RX_CONF_DESC_MASK 0x0000001e /* RX descriptor ring size */ 341#define CAS_RX_CONF_DESC_SHFT 1 342#define CAS_RX_CONF_COMP_MASK 0x000001e0 /* RX complition ring size */ 343#define CAS_RX_CONF_COMP_SHFT 5 344#define CAS_RX_CONF_BATCH_DIS 0x00000200 /* descriptor batching dis. */ 345#define CAS_RX_CONF_SOFF_MASK 0x00001c00 /* swivel offset */ 346#define CAS_RX_CONF_SOFF_SHFT 10 347/* The RX descriptor ring 2 is Cassini+/Saturn only. */ 348#define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */ 349#define CAS_RX_CONF_DESC2_SHFT 16 350 351#define CAS_RX_CONF_COMP_128 0x0 /* 128 descriptors */ 352#define CAS_RX_CONF_COMP_256 0x1 /* 256 descriptors */ 353#define CAS_RX_CONF_COMP_512 0x2 /* 512 descriptors */ 354#define CAS_RX_CONF_COMP_1K 0x3 /* 1k descriptors */ 355#define CAS_RX_CONF_COMP_2K 0x4 /* 2k descriptors */ 356#define CAS_RX_CONF_COMP_4K 0x5 /* 4k descriptors */ 357#define CAS_RX_CONF_COMP_8K 0x6 /* 8k descriptors */ 358#define CAS_RX_CONF_COMP_16K 0x7 /* 16k descriptors */ 359#define CAS_RX_CONF_COMP_32K 0x8 /* 32k descriptors */ 360 361#define CAS_RX_PSZ_MASK 0x00000003 /* RX page size */ 362#define CAS_RX_PSZ_SHFT 0 363#define CAS_RX_PSZ_MB_CNT_MASK 0x00007800 /* number of MTU buffers */ 364#define CAS_RX_PSZ_MB_CNT_SHFT 11 365#define CAS_RX_PSZ_MB_STRD_MASK 0x18000000 /* MTU buffer stride */ 366#define CAS_RX_PSZ_MB_STRD_SHFT 27 367#define CAS_RX_PSZ_MB_OFF_MASK 0xc0000000 /* MTU buffer offset */ 368#define CAS_RX_PSZ_MB_OFF_SHFT 30 369 370#define CAS_RX_PSZ_2K 0x0 /* page size 2Kbyte */ 371#define CAS_RX_PSZ_4K 0x1 /* page size 4Kbyte */ 372#define CAS_RX_PSZ_8K 0x2 /* page size 8Kbyte */ 373#define CAS_RX_PSZ_16K 0x3 /* page size 16Kbyte*/ 374 375#define CAS_RX_PSZ_MB_STRD_1K 0x0 /* MTU buffer stride 1Kbyte */ 376#define CAS_RX_PSZ_MB_STRD_2K 0x1 /* MTU buffer stride 2Kbyte */ 377#define CAS_RX_PSZ_MB_STRD_4K 0x2 /* MTU buffer stride 4Kbyte */ 378#define CAS_RX_PSZ_MB_STRD_8K 0x3 /* MTU buffer stride 8Kbyte */ 379 380#define CAS_RX_PSZ_MB_OFF_0 0x0 /* MTU buf. offset 0 bytes */ 381#define CAS_RX_PSZ_MB_OFF_64 0x1 /* MTU buf. offset 64 bytes */ 382#define CAS_RX_PSZ_MB_OFF_96 0x2 /* MTU buf. offset 96 bytes */ 383#define CAS_RX_PSZ_MB_OFF_128 0x3 /* MTU buf. offset 128 bytes */ 384 385#define CAS_RX_DESC_ALIGN 8192 /* RX descriptor alignment */ 386 387#define CAS_RX_COMP_ALIGN 8192 /* RX complition alignment */ 388 389/* The RX PAUSE thresholds are specified in multiples of 64 bytes. */ 390#define CAS_RX_PTHRS_XOFF_MASK 0x000001ff /* XOFF PAUSE */ 391#define CAS_RX_PTHRS_XOFF_SHFT 0 392#define CAS_RX_PTHRS_XON_MASK 0x001ff000 /* XON PAUSE */ 393#define CAS_RX_PTHRS_XON_SHFT 12 394 395/* 396 * CAS_RX_BLANK and CAS_RX_BLANK_ALIAS bits 397 * CAS_RX_BLANK is loaded each time CAS_STATUS is read and CAS_RX_BLANK_ALIAS 398 * is read each time CAS_STATUS_ALIAS is read. The blanking time is specified 399 * in multiples of 512 core ticks (which runs at 125MHz). 400 */ 401#define CAS_RX_BLANK_PKTS_MASK 0x000001ff /* RX blanking packets */ 402#define CAS_RX_BLANK_PKTS_SHFT 0 403#define CAS_RX_BLANK_TIME_MASK 0x3ffff000 /* RX blanking time */ 404#define CAS_RX_BLANK_TIME_SHFT 12 405 406/* CAS_RX_AEMPTY_THRS and CAS_RX_AEMPTY_THRS2 bits */ 407#define CAS_RX_AEMPTY_THRS_MASK 0x00001fff /* RX_BUF_AEMPTY threshold */ 408#define CAS_RX_AEMPTY_THRS_SHFT 0 409#define CAS_RX_AEMPTY_COMP_MASK 0x0fffe000 /* RX_COMP_AFULL threshold */ 410#define CAS_RX_AEMPTY_COMP_SHFT 13 411 412/* The RX random early detection probability is in 12.5% granularity. */ 413#define CAS_RX_RED_4K_6K_MASK 0x000000ff /* 4K < FIFO threshold < 6K */ 414#define CAS_RX_RED_4K_6K_SHFT 0 415#define CAS_RX_RED_6K_8K_MASK 0x0000ff00 /* 6K < FIFO threshold < 8K */ 416#define CAS_RX_RED_6K_8K_SHFT 8 417#define CAS_RX_RED_8K_10K_MASK 0x00ff0000 /* 8K < FIFO threshold < 10K */ 418#define CAS_RX_RED_8K_10K_SHFT 16 419#define CAS_RX_RED_10K_12K_MASK 0xff000000 /* 10K < FIFO threshold < 12K */ 420#define CAS_RX_RED_10K_12K_SHFT 24 421 422/* CAS_RX_FF_IPP_MASK and CAS_RX_FF_FIFO_MASK are in 8 bytes granularity. */ 423#define CAS_RX_FF_PKT_MASK 0x000000ff /* # of packets in RX FIFO */ 424#define CAS_RX_FF_PKT_SHFT 0 425#define CAS_RX_FF_IPP_MASK 0x0007ff00 /* IPP FIFO level */ 426#define CAS_RX_FF_IPP_SHFT 8 427#define CAS_RX_FF_FIFO_MASK 0x3ff80000 /* RX FIFO level */ 428#define CAS_RX_FF_FIFO_SHFT 19 429 430#define CAS_RX_BIST_START 0x00000001 /* Start BIST process. */ 431#define CAS_RX_BIST_SUMMARY 0x00000002 /* All okay */ 432#define CAS_RX_BIST_SM 0x00007800 /* BIST state machine */ 433#define CAS_RX_BIST_REAS_27 0x00008000 /* Reas 27 okay */ 434#define CAS_RX_BIST_REAS_26B 0x00010000 /* Reas 26B okay */ 435#define CAS_RX_BIST_REAS_26A 0x00020000 /* Reas 26A okay */ 436#define CAS_RX_BIST_CTRL_33 0x00040000 /* Control FIFO 33 okay */ 437#define CAS_RX_BIST_CTRL_32 0x00080000 /* Control FIFO 32 okay */ 438#define CAS_RX_BIST_IPP_33C 0x00100000 /* IPP 33C okay */ 439#define CAS_RX_BIST_IPP_32C 0x00200000 /* IPP 32C okay */ 440#define CAS_RX_BIST_IPP_33B 0x00400000 /* IPP 33B okay */ 441#define CAS_RX_BIST_IPP_32B 0x00800000 /* IPP 32B okay */ 442#define CAS_RX_BIST_IPP_33A 0x01000000 /* IPP 33A okay */ 443#define CAS_RX_BIST_IPP_32A 0x02000000 /* IPP 32A okay */ 444#define CAS_RX_BIST_33C 0x04000000 /* 33C okay */ 445#define CAS_RX_BIST_32C 0x08000000 /* 32C okay */ 446#define CAS_RX_BIST_33B 0x10000000 /* 33B okay */ 447#define CAS_RX_BIST_32B 0x20000000 /* 32B okay */ 448#define CAS_RX_BIST_33A 0x40000000 /* 33A okay */ 449#define CAS_RX_BIST_32A 0x80000000 /* 32A okay */ 450 451#define CAS_RX_REAS_DMA_ADDR_LC 0x0000003f /* reas. table location sel. */ 452 453/* header parser registers */ 454#define CAS_HP_CONF 0x4140 /* HP configuration */ 455#define CAS_HP_IR_ADDR 0x4144 /* HP instruction RAM address */ 456#define CAS_HP_IR_DATA_LO 0x4148 /* HP instruction RAM data low */ 457#define CAS_HP_IR_DATA_MD 0x414c /* HP instruction RAM data mid */ 458#define CAS_HP_IR_DATA_HI 0x4150 /* HP instruction RAM data high */ 459#define CAS_HP_DR_FDB 0x4154 /* HP data RAM and flow DB address */ 460#define CAS_HP_DR_DATA 0x4158 /* HP data RAM data */ 461#define CAS_HP_FLOW_DB1 0x415c /* HP flow database 1 */ 462#define CAS_HP_FLOW_DB2 0x4160 /* HP flow database 2 */ 463#define CAS_HP_FLOW_DB3 0x4164 /* HP flow database 3 */ 464#define CAS_HP_FLOW_DB4 0x4168 /* HP flow database 4 */ 465#define CAS_HP_FLOW_DB5 0x416c /* HP flow database 5 */ 466#define CAS_HP_FLOW_DB6 0x4170 /* HP flow database 6 */ 467#define CAS_HP_FLOW_DB7 0x4174 /* HP flow database 7 */ 468#define CAS_HP_FLOW_DB8 0x4178 /* HP flow database 8 */ 469#define CAS_HP_FLOW_DB9 0x417c /* HP flow database 9 */ 470#define CAS_HP_FLOW_DB10 0x4180 /* HP flow database 10 */ 471#define CAS_HP_FLOW_DB11 0x4184 /* HP flow database 11 */ 472#define CAS_HP_FLOW_DB12 0x4188 /* HP flow database 12 */ 473#define CAS_HP_SM 0x418c /* HP state machine */ 474#define CAS_HP_STATUS1 0x4190 /* HP status 1 */ 475#define CAS_HP_STATUS2 0x4194 /* HP status 2 */ 476#define CAS_HP_STATUS3 0x4198 /* HP status 3 */ 477#define CAS_HP_RAM_BIST 0x419c /* HP RAM BIST */ 478 479#define CAS_HP_CONF_PARSE_EN 0x00000001 /* header parsing enable */ 480#define CAS_HP_CONF_NCPU_MASK 0x000000fc /* #CPUs (0x0: 64) */ 481#define CAS_HP_CONF_NCPU_SHFT 2 482#define CAS_HP_CONF_SINC_DIS 0x00000100 /* SYN inc. seq. number dis. */ 483#define CAS_HP_CONF_TPT_MASK 0x000ffe00 /* TCP payload threshold */ 484#define CAS_HP_CONF_TPT_SHFT 9 485 486#define CAS_HP_DR_FDB_DR_MASK 0x0000001f /* data RAM location sel. */ 487#define CAS_HP_DR_FDB_DR_SHFT 0 488#define CAS_HP_DR_FDB_FDB_MASK 0x00003f00 /* flow DB location sel. */ 489#define CAS_HP_DR_FDB_FDB_SHFT 8 490 491#define CAS_HP_STATUS1_OP_MASK 0x00000007 /* HRP opcode */ 492#define CAS_HP_STATUS1_OP_SHFT 0 493#define CAS_HP_STATUS1_LB_MASK 0x000001f8 /* load balancing CPU number */ 494#define CAS_HP_STATUS1_LB_SHFT 3 495#define CAS_HP_STATUS1_L3O_MASK 0x0000fe00 /* layer 3 offset */ 496#define CAS_HP_STATUS1_L3O_SHFT 9 497#define CAS_HP_STATUS1_SAP_MASK 0xffff0000 /* ethertype */ 498#define CAS_HP_STATUS1_SAP_SHFT 16 499 500#define CAS_HP_STATUS2_TSZ_MASK 0x0000ffff /* TCP payload size */ 501#define CAS_HP_STATUS2_TSZ_SHFT 0 502#define CAS_HP_STATUS2_TO_MASK 0x007f0000 /* TCP payload offset */ 503#define CAS_HP_STATUS2_TO_SHFT 16 504#define CAS_HP_STATUS2_FID_MASK 0x1f800000 /* flow ID */ 505#define CAS_HP_STATUS2_FID_SHFT 23 506#define CAS_HP_STATUS2_AR2_MASK 0xe0000000 /* accu_R2[6:4] */ 507#define CAS_HP_STATUS2_AR2_SHFT 29 508 509#define CAS_HP_STATUS3_TCP_NCHK 0x00000001 /* TCP no payload check */ 510#define CAS_HP_STATUS3_TCP_CHK 0x00000002 /* TCP payload check */ 511#define CAS_HP_STATUS3_SYN_FLAG 0x00000004 /* SYN flag */ 512#define CAS_HP_STATUS3_TCP_FLAG 0x00000008 /* TCP flag check */ 513#define CAS_HP_STATUS3_CTRL_PF 0x00000010 /* control packet flag */ 514#define CAS_HP_STATUS3_NASSIST 0x00000020 /* no assist */ 515#define CAS_HP_STATUS3_MASK_PT 0x00000040 /* Mask payload threshold. */ 516#define CAS_HP_STATUS3_FRC_TPC 0x00000080 /* Force TCP payload check. */ 517#define CAS_HP_STATUS3_MASK_DLZ 0x00000100 /* Mask data length equal 0. */ 518#define CAS_HP_STATUS3_FRC_TNPC 0x00000200 /* Force TCP no payload chk. */ 519#define CAS_HP_STATUS3_JMBHS_EN 0x00000400 /* jumbo header split enable */ 520#define CAS_HP_STATUS3_BWO_REAS 0x00000800 /* batching w/o reassembly */ 521#define CAS_HP_STATUS3_FRC_DROP 0x00001000 /* force drop */ 522#define CAS_HP_STATUS3_AR1_MASK 0x000fe000 /* accu_R1 */ 523#define CAS_HP_STATUS3_AR1_SHFT 13 524#define CAS_HP_STATUS3_CSO_MASK 0x07f00000 /* checksum start offset */ 525#define CAS_HP_STATUS3_CSO_SHFT 19 526#define CAS_HP_STATUS3_AR2_MASK 0xf0000000 /* accu_R2[3:0] */ 527#define CAS_HP_STATUS3_AR2_SHFT 28 528 529#define CAS_HP_RAM_BIST_START 0x00000001 /* Start RAM BIST process. */ 530#define CAS_HP_RAM_BIST_SUMMARY 0x00000002 /* all RAM okay */ 531#define CAS_HP_RAM_BIST_TCPSEQ 0x00020000 /* TCP seqeunce RAM okay */ 532#define CAS_HP_RAM_BIST_FID31 0x00040000 /* flow ID RAM3 bank 1 okay */ 533#define CAS_HP_RAM_BIST_FID21 0x00080000 /* flow ID RAM2 bank 1 okay */ 534#define CAS_HP_RAM_BIST_FID11 0x00100000 /* flow ID RAM1 bank 1 okay */ 535#define CAS_HP_RAM_BIST_FID01 0x00200000 /* flow ID RAM0 bank 1 okay */ 536#define CAS_HP_RAM_BIST_FID30 0x00400000 /* flow ID RAM3 bank 0 okay */ 537#define CAS_HP_RAM_BIST_FID20 0x00800000 /* flow ID RAM2 bank 0 okay */ 538#define CAS_HP_RAM_BIST_FID10 0x01000000 /* flow ID RAM1 bank 0 okay */ 539#define CAS_HP_RAM_BIST_FID00 0x02000000 /* flow ID RAM0 bank 0 okay */ 540#define CAS_HP_RAM_BIST_AGE1 0x04000000 /* aging RAM1 okay */ 541#define CAS_HP_RAM_BIST_AGE0 0x08000000 /* aging RAM0 okay */ 542#define CAS_HP_RAM_BIST_IR2 0x10000000 /* instruction RAM2 okay */ 543#define CAS_HP_RAM_BIST_IR1 0x20000000 /* instruction RAM1 okay */ 544#define CAS_HP_RAM_BIST_IR0 0x40000000 /* instruction RAM0 okay */ 545#define CAS_HP_RAM_BIST_DR 0x80000000 /* data RAM okay */ 546 547/* MAC registers */ 548#define CAS_MAC_TXRESET 0x6000 /* TX MAC software reset command */ 549#define CAS_MAC_RXRESET 0x6004 /* RX MAC software reset command */ 550#define CAS_MAC_SPC 0x6008 /* send PAUSE command */ 551#define CAS_MAC_TX_STATUS 0x6010 /* TX MAC status */ 552#define CAS_MAC_RX_STATUS 0x6014 /* RX MAC status */ 553#define CAS_MAC_CTRL_STATUS 0x6018 /* MAC control status */ 554#define CAS_MAC_TX_MASK 0x6020 /* TX MAC mask */ 555#define CAS_MAC_RX_MASK 0x6024 /* RX MAC mask */ 556#define CAS_MAC_CTRL_MASK 0x6028 /* MAC control mask */ 557#define CAS_MAC_TX_CONF 0x6030 /* TX MAC configuration */ 558#define CAS_MAC_RX_CONF 0x6034 /* RX MAC configuration */ 559#define CAS_MAC_CTRL_CONF 0x6038 /* MAC control configuration */ 560#define CAS_MAC_XIF_CONF 0x603c /* XIF configuration */ 561#define CAS_MAC_IPG0 0x6040 /* inter packet gap 0 */ 562#define CAS_MAC_IPG1 0x6044 /* inter packet gap 1 */ 563#define CAS_MAC_IPG2 0x6048 /* inter packet gap 2 */ 564#define CAS_MAC_SLOT_TIME 0x604c /* slot time */ 565#define CAS_MAC_MIN_FRAME 0x6050 /* minimum frame size */ 566#define CAS_MAC_MAX_BF 0x6054 /* maximum bust and frame size */ 567#define CAS_MAC_PREAMBLE_LEN 0x6058 /* PA size */ 568#define CAS_MAC_JAM_SIZE 0x605c /* jam size */ 569#define CAS_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit */ 570#define CAS_MAC_CTRL_TYPE 0x6064 /* MAC control type */ 571#define CAS_MAC_ADDR0 0x6080 /* MAC address 0 */ 572#define CAS_MAC_ADDR1 0x6084 /* MAC address 1 */ 573#define CAS_MAC_ADDR2 0x6088 /* MAC address 2 */ 574#define CAS_MAC_ADDR3 0x608c /* MAC address 3 */ 575#define CAS_MAC_ADDR4 0x6090 /* MAC address 4 */ 576#define CAS_MAC_ADDR5 0x6094 /* MAC address 5 */ 577#define CAS_MAC_ADDR6 0x6098 /* MAC address 6 */ 578#define CAS_MAC_ADDR7 0x609c /* MAC address 7 */ 579#define CAS_MAC_ADDR8 0x60a0 /* MAC address 8 */ 580#define CAS_MAC_ADDR9 0x60a4 /* MAC address 9 */ 581#define CAS_MAC_ADDR10 0x60a8 /* MAC address 10 */ 582#define CAS_MAC_ADDR11 0x60ac /* MAC address 11 */ 583#define CAS_MAC_ADDR12 0x60b0 /* MAC address 12 */ 584#define CAS_MAC_ADDR13 0x60b4 /* MAC address 13 */ 585#define CAS_MAC_ADDR14 0x60b8 /* MAC address 14 */ 586#define CAS_MAC_ADDR15 0x60bc /* MAC address 15 */ 587#define CAS_MAC_ADDR16 0x60c0 /* MAC address 16 */ 588#define CAS_MAC_ADDR17 0x60c4 /* MAC address 17 */ 589#define CAS_MAC_ADDR18 0x60c8 /* MAC address 18 */ 590#define CAS_MAC_ADDR19 0x60cc /* MAC address 19 */ 591#define CAS_MAC_ADDR20 0x60d0 /* MAC address 20 */ 592#define CAS_MAC_ADDR21 0x60d4 /* MAC address 21 */ 593#define CAS_MAC_ADDR22 0x60d8 /* MAC address 22 */ 594#define CAS_MAC_ADDR23 0x60dc /* MAC address 23 */ 595#define CAS_MAC_ADDR24 0x60e0 /* MAC address 24 */ 596#define CAS_MAC_ADDR25 0x60e4 /* MAC address 25 */ 597#define CAS_MAC_ADDR26 0x60e8 /* MAC address 26 */ 598#define CAS_MAC_ADDR27 0x60ec /* MAC address 27 */ 599#define CAS_MAC_ADDR28 0x60f0 /* MAC address 28 */ 600#define CAS_MAC_ADDR29 0x60f4 /* MAC address 29 */ 601#define CAS_MAC_ADDR30 0x60f8 /* MAC address 30 */ 602#define CAS_MAC_ADDR31 0x60fc /* MAC address 31 */ 603#define CAS_MAC_ADDR32 0x6100 /* MAC address 32 */ 604#define CAS_MAC_ADDR33 0x6104 /* MAC address 33 */ 605#define CAS_MAC_ADDR34 0x6108 /* MAC address 34 */ 606#define CAS_MAC_ADDR35 0x610c /* MAC address 35 */ 607#define CAS_MAC_ADDR36 0x6110 /* MAC address 36 */ 608#define CAS_MAC_ADDR37 0x6114 /* MAC address 37 */ 609#define CAS_MAC_ADDR38 0x6118 /* MAC address 38 */ 610#define CAS_MAC_ADDR39 0x611c /* MAC address 39 */ 611#define CAS_MAC_ADDR40 0x6120 /* MAC address 40 */ 612#define CAS_MAC_ADDR41 0x6124 /* MAC address 41 */ 613#define CAS_MAC_ADDR42 0x6128 /* MAC address 42 */ 614#define CAS_MAC_ADDR43 0x612c /* MAC address 43 */ 615#define CAS_MAC_ADDR44 0x6130 /* MAC address 44 */ 616#define CAS_MAC_AFILTER0 0x614c /* address filter 0 */ 617#define CAS_MAC_AFILTER1 0x6150 /* address filter 1 */ 618#define CAS_MAC_AFILTER2 0x6154 /* address filter 2 */ 619#define CAS_MAC_AFILTER_MASK1_2 0x6158 /* address filter 2 & 1 mask*/ 620#define CAS_MAC_AFILTER_MASK0 0x615c /* address filter 0 mask */ 621#define CAS_MAC_HASH0 0x6160 /* hash table 0 */ 622#define CAS_MAC_HASH1 0x6164 /* hash table 1 */ 623#define CAS_MAC_HASH2 0x6168 /* hash table 2 */ 624#define CAS_MAC_HASH3 0x616c /* hash table 3 */ 625#define CAS_MAC_HASH4 0x6170 /* hash table 4 */ 626#define CAS_MAC_HASH5 0x6174 /* hash table 5 */ 627#define CAS_MAC_HASH6 0x6178 /* hash table 6 */ 628#define CAS_MAC_HASH7 0x617c /* hash table 7 */ 629#define CAS_MAC_HASH8 0x6180 /* hash table 8 */ 630#define CAS_MAC_HASH9 0x6184 /* hash table 9 */ 631#define CAS_MAC_HASH10 0x6188 /* hash table 10 */ 632#define CAS_MAC_HASH11 0x618c /* hash table 11 */ 633#define CAS_MAC_HASH12 0x6190 /* hash table 12 */ 634#define CAS_MAC_HASH13 0x6194 /* hash table 13 */ 635#define CAS_MAC_HASH14 0x6198 /* hash table 14 */ 636#define CAS_MAC_HASH15 0x619c /* hash table 15 */ 637#define CAS_MAC_NORM_COLL_CNT 0x61a0 /* normal collision counter */ 638#define CAS_MAC_FIRST_COLL_CNT 0x61a4 /* 1st attempt suc. collision counter */ 639#define CAS_MAC_EXCESS_COLL_CNT 0x61a8 /* excess collision counter */ 640#define CAS_MAC_LATE_COLL_CNT 0x61ac /* late collision counter */ 641#define CAS_MAC_DEFER_TMR_CNT 0x61b0 /* defer timer */ 642#define CAS_MAC_PEAK_ATTEMPTS 0x61b4 /* peak attempts */ 643#define CAS_MAC_RX_FRAME_COUNT 0x61b8 /* receive frame counter */ 644#define CAS_MAC_RX_LEN_ERR_CNT 0x61bc /* length error counter */ 645#define CAS_MAC_RX_ALIGN_ERR 0x61c0 /* alignment error counter */ 646#define CAS_MAC_RX_CRC_ERR_CNT 0x61c4 /* FCS error counter */ 647#define CAS_MAC_RX_CODE_VIOL 0x61c8 /* RX code violation error counter */ 648#define CAS_MAC_RANDOM_SEED 0x61cc /* random number seed */ 649#define CAS_MAC_MAC_STATE 0x61d0 /* MAC state machine */ 650 651#define CAS_MAC_SPC_TIME_MASK 0x0000ffff /* PAUSE time value */ 652#define CAS_MAC_SPC_TIME_SHFT 0 653#define CAS_MAC_SPC_SEND 0x00010000 /* Send PAUSE frame. */ 654 655/* CAS_MAC_TX_STATUS and CAS_MAC_TX_MASK register bits */ 656#define CAS_MAC_TX_FRAME_XMTD 0x00000001 /* Frame transmitted. */ 657#define CAS_MAC_TX_UNDERRUN 0x00000002 /* TX data starvation */ 658#define CAS_MAC_TX_MAX_PKT_ERR 0x00000004 /* frame > CAS_MAC_MAX_FRAME */ 659#define CAS_MAC_TX_NCC_EXP 0x00000008 /* normal coll. counter wrap */ 660#define CAS_MAC_TX_ECC_EXP 0x00000010 /* excess coll. counter wrap */ 661#define CAS_MAC_TX_LCC_EXP 0x00000020 /* late coll. counter wrap */ 662#define CAS_MAC_TX_FCC_EXP 0x00000040 /* 1st coll. counter wrap */ 663#define CAS_MAC_TX_DEFER_EXP 0x00000080 /* defer timer wrap */ 664#define CAS_MAC_TX_PEAK_EXP 0x00000100 /* peak attempts counter wrap */ 665 666/* CAS_MAC_RX_STATUS and CAS_MAC_RX_MASK register bits */ 667#define CAS_MAC_RX_FRAME_RCVD 0x00000001 /* Frame received. */ 668#define CAS_MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */ 669#define CAS_MAC_RX_FRAME_EXP 0x00000004 /* RX frame counter wrap */ 670#define CAS_MAC_RX_ALIGN_EXP 0x00000008 /* alignment error cntr. wrap */ 671#define CAS_MAC_RX_CRC_EXP 0x00000010 /* CRC error counter wrap */ 672#define CAS_MAC_RX_LEN_EXP 0x00000020 /* length error counter wrap */ 673#define CAS_MAC_RX_VIOL_EXP 0x00000040 /* code violation cntr. wrap */ 674 675/* CAS_MAC_CTRL_STATUS and CAS_MAC_CTRL_MASK register bits */ 676#define CAS_MAC_CTRL_PAUSE_RCVD 0x00000001 /* PAUSE received. */ 677#define CAS_MAC_CTRL_PAUSE 0x00000002 /* PAUSE state entered. */ 678#define CAS_MAC_CTRL_NON_PAUSE 0x00000004 /* PAUSE state left. */ 679 680#define CAS_MAC_CTRL_STATUS_PT_MASK 0xffff0000 /* PAUSE time */ 681#define CAS_MAC_CTRL_STATUS_PT_SHFT 16 682 683#define CAS_MAC_TX_CONF_EN 0x00000001 /* TX enable */ 684#define CAS_MAC_TX_CONF_ICARR 0x00000002 /* Ignore carrier sense. */ 685#define CAS_MAC_TX_CONF_ICOLLIS 0x00000004 /* Ignore collisions. */ 686#define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */ 687#define CAS_MAC_TX_CONF_NGU 0x00000010 /* Never give up. */ 688#define CAS_MAC_TX_CONF_NGUL 0x00000020 /* never give up limit */ 689#define CAS_MAC_TX_CONF_NBOFF 0x00000040 /* Disable backoff algorithm. */ 690#define CAS_MAC_TX_CONF_SDOWN 0x00000080 /* CSMA/CD slow down */ 691#define CAS_MAC_TX_CONF_NO_FCS 0x00000100 /* Don't generate FCS. */ 692#define CAS_MAC_TX_CONF_CARR 0x00000200 /* carrier extension enable */ 693 694#define CAS_MAC_RX_CONF_EN 0x00000001 /* RX enable */ 695#define CAS_MAC_RX_CONF_STRPPAD 0x00000002 /* Must not be set. */ 696#define CAS_MAC_RX_CONF_STRPFCS 0x00000004 /* Strip FCS bytes. */ 697#define CAS_MAC_RX_CONF_PROMISC 0x00000008 /* promiscuous mode enable */ 698#define CAS_MAC_RX_CONF_PGRP 0x00000010 /* promiscuous group mode en. */ 699#define CAS_MAC_RX_CONF_HFILTER 0x00000020 /* hash filter enable */ 700#define CAS_MAC_RX_CONF_AFILTER 0x00000040 /* address filter enable */ 701#define CAS_MAC_RX_CONF_DIS_DOE 0x00000080 /* disable discard on error */ 702#define CAS_MAC_RX_CONF_CARR 0x00000100 /* carrier extension enable */ 703 704#define CAS_MAC_CTRL_CONF_TXP 0x00000001 /* send PAUSE enable */ 705#define CAS_MAC_CTRL_CONF_RXP 0x00000002 /* receive PAUSE enable */ 706#define CAS_MAC_CTRL_CONF_PASSP 0x00000004 /* Pass PAUSE up to RX DMA. */ 707 708#define CAS_MAC_XIF_CONF_TX_OE 0x00000001 /* MII TX output drivers en. */ 709#define CAS_MAC_XIF_CONF_ILBK 0x00000002 /* MII internal loopback en. */ 710#define CAS_MAC_XIF_CONF_NOECHO 0x00000004 /* Disable echo. */ 711#define CAS_MAC_XIF_CONF_GMII 0x00000008 /* GMII (vs. MII) mode enable */ 712#define CAS_MAC_XIF_CONF_BUF_OE 0x00000010 /* MII_BUF_OE enable */ 713#define CAS_MAC_XIF_CONF_LNKLED 0x00000020 /* Force LINKLED# active. */ 714#define CAS_MAC_XIF_CONF_FDXLED 0x00000040 /* Force FDPLXLED# active. */ 715 716/* 717 * The value of CAS_MAC_SLOT_TIME specifies the PAUSE time unit and depends 718 * on whether carrier extension is enabled. 719 */ 720#define CAS_MAC_SLOT_TIME_CARR 0x200 /* slot time for carr. ext. */ 721#define CAS_MAC_SLOT_TIME_NORM 0x40 /* slot time otherwise */ 722 723#define CAS_MAC_MAX_BF_FRM_MASK 0x00007fff /* maximum frame size */ 724#define CAS_MAC_MAX_BF_FRM_SHFT 0 725#define CAS_MAC_MAX_BF_BST_MASK 0x3fff0000 /* maximum burst size */ 726#define CAS_MAC_MAX_BF_BST_SHFT 16 727 728/* 729 * MIF registers 730 * The bit-bang registers use the low bit only. 731 */ 732#define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */ 733#define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */ 734#define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */ 735#define CAS_MIF_FRAME 0x620c /* MIF frame/output */ 736#define CAS_MIF_CONF 0x6210 /* MIF configuration */ 737#define CAS_MIF_MASK 0x6214 /* MIF mask */ 738#define CAS_MIF_STATUS 0x6218 /* MIF status */ 739#define CAS_MIF_SM 0x621c /* MIF state machine */ 740 741#define CAS_MIF_FRAME_DATA 0x0000ffff /* instruction payload */ 742#define CAS_MIF_FRAME_TA_LSB 0x00010000 /* turn around LSB */ 743#define CAS_MIF_FRAME_TA_MSB 0x00020000 /* turn around MSB */ 744#define CAS_MIF_FRAME_REG_MASK 0x007c0000 /* register address */ 745#define CAS_MIF_FRAME_REG_SHFT 18 746#define CAS_MIF_FRAME_PHY_MASK 0x0f800000 /* PHY address */ 747#define CAS_MIF_FRAME_PHY_SHFT 23 748#define CAS_MIF_FRAME_OP_WRITE 0x10000000 /* write opcode */ 749#define CAS_MIF_FRAME_OP_READ 0x20000000 /* read opcode */ 750#define CAS_MIF_FRAME_OP_MASK \ 751 (CAS_MIF_FRAME_OP_WRITE | CAS_MIF_FRAME_OP_READ) 752#define CAS_MIF_FRAME_ST 0x40000000 /* start of frame */ 753#define CAS_MIF_FRAME_ST_MASK 0xc0000000 /* start of frame */ 754 755#define CAS_MIF_FRAME_READ \ 756 (CAS_MIF_FRAME_TA_MSB | CAS_MIF_FRAME_OP_READ | CAS_MIF_FRAME_ST) 757#define CAS_MIF_FRAME_WRITE \ 758 (CAS_MIF_FRAME_TA_MSB | CAS_MIF_FRAME_OP_WRITE | CAS_MIF_FRAME_ST) 759 760#define CAS_MIF_CONF_PHY_SELECT 0x00000001 /* PHY select, 0: MDIO_0 */ 761#define CAS_MIF_CONF_POLL_EN 0x00000002 /* polling mechanism enable */ 762#define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */ 763#define CAS_MIF_CONF_PREG_MASK 0x000000f8 /* polled register */ 764#define CAS_MIF_CONF_PREG_SHFT 3 765#define CAS_MIF_CONF_MDI0 0x00000100 /* MDIO_0 data/attached */ 766#define CAS_MIF_CONF_MDI1 0x00000200 /* MDIO_1 data/attached */ 767#define CAS_MIF_CONF_PPHY_MASK 0x00007c00 /* polled PHY */ 768#define CAS_MIF_CONF_PPHY_SHFT 10 769 770/* CAS_MIF_MASK and CAS_MIF_STATUS bits */ 771#define CAS_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 772#define CAS_MIF_POLL_STATUS_SHFT 0 773#define CAS_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 774#define CAS_MIF_POLL_DATA_SHFT 8 775 776#define CAS_MIF_SM_CTRL_MASK 0x00000007 /* ctrl. state machine state */ 777#define CAS_MIF_SM_CTRL_SHFT 0 778#define CAS_MIF_SM_EXEC_MASK 0x00000060 /* exec. state machine state */ 779 780/* PCS/Serialink registers */ 781#define CAS_PCS_CTRL 0x9000 /* PCS MII control (PCS "BMCR") */ 782#define CAS_PCS_STATUS 0x9004 /* PCS MII status (PCS "BMSR") */ 783#define CAS_PCS_ANAR 0x9008 /* PCS MII advertisement */ 784#define CAS_PCS_ANLPAR 0x900c /* PCS MII link partner ability */ 785#define CAS_PCS_CONF 0x9010 /* PCS configuration */ 786#define CAS_PCS_SM 0x9014 /* PCS state machine */ 787#define CAS_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */ 788#define CAS_PCS_DATAPATH 0x9050 /* datapath mode */ 789#define CAS_PCS_SERDES_CTRL 0x9054 /* SERDES control */ 790#define CAS_PCS_OUTPUT_SELECT 0x9058 /* shared output select */ 791#define CAS_PCS_SERDES_STATUS 0x905c /* SERDES state */ 792#define CAS_PCS_PKT_CNT 0x9060 /* PCS packet counter */ 793 794#define CAS_PCS_CTRL_1000M 0x00000040 /* 1000Mbps speed select */ 795#define CAS_PCS_CTRL_COLL_TEST 0x00000080 /* collision test */ 796#define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */ 797#define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */ 798#define CAS_PCS_CTRL_ISOLATE 0x00000400 /* isolate PHY from MII */ 799#define CAS_PCS_CTRL_POWERDOWN 0x00000800 /* power down */ 800#define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */ 801#define CAS_PCS_CTRL_10_100M 0x00002000 /* 10/100Mbps speed select */ 802#define CAS_PCS_CTRL_RESET 0x00008000 /* Reset PCS. */ 803 804#define CAS_PCS_STATUS_EXTCAP 0x00000001 /* extended capability */ 805#define CAS_PCS_STATUS_JABBER 0x00000002 /* jabber condition detected */ 806#define CAS_PCS_STATUS_LINK 0x00000004 /* link status */ 807#define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */ 808#define CAS_PCS_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 809#define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 810#define CAS_PCS_STATUS_EXTENDED 0x00000100 /* extended status */ 811 812/* CAS_PCS_ANAR and CAS_PCS_ANLPAR register bits */ 813#define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */ 814#define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */ 815#define CAS_PCS_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 816#define CAS_PCS_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 817#define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 818#define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 819#define CAS_PCS_ANEG_RFLT_MASK \ 820 (CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 821#define CAS_PCS_ANEG_ACK 0x00004000 /* acknowledge */ 822#define CAS_PCS_ANEG_NEXT_PAGE 0x00008000 /* next page */ 823 824#define CAS_PCS_CONF_EN 0x00000001 /* Enable PCS. */ 825#define CAS_PCS_CONF_SDO 0x00000002 /* signal detect override */ 826#define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */ 827#define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */ 828#define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */ 829#define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */ 830#define CAS_PCS_CONF_JS_MASK (CAS_PCS_CONF_JS_HF | CAS_PCS_CONF_JS_LF) 831#define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */ 832 833#define CAS_PCS_SM_TX_CTRL_MASK 0x0000000f /* TX control state */ 834#define CAS_PCS_SM_TX_CTRL_SHFT 0 835#define CAS_PCS_SM_RX_CTRL_MASK 0x000000f0 /* RX control state */ 836#define CAS_PCS_SM_RX_CTRL_SHFT 4 837#define CAS_PCS_SM_WSYNC_MASK 0x00000700 /* word sync. state */ 838#define CAS_PCS_SM_WSYNC_SHFT 8 839#define CAS_PCS_SM_SEQ_MASK 0x00001800 /* sequence detection state */ 840#define CAS_PCS_SM_SEQ_SHFT 11 841#define CAS_PCS_SM_LINK_UP 0x00016000 842#define CAS_PCS_SM_LINK_MASK 0x0001e000 /* link configuration state */ 843#define CAS_PCS_SM_LINK_SHFT 13 844#define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */ 845#define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */ 846#define CAS_PCS_SM_LOS 0x00400000 /* loss of signal */ 847#define CAS_PCS_SM_NLINK_BREAK 0x01000000 /* no link due to breaklink */ 848#define CAS_PCS_SM_NLINK_SERDES 0x02000000 /* no link due to SERDES */ 849#define CAS_PCS_SM_NLINK_C 0x04000000 /* no link due to bad C codes */ 850#define CAS_PCS_SM_NLINK_SYNC 0x08000000 /* no link due to word sync. */ 851#define CAS_PCS_SM_NLINK_WAIT_C 0x10000000 /* no link, waiting for ack. */ 852#define CAS_PCS_SM_NLINK_NIDLE 0x20000000 /* no link due to no idle */ 853 854/* 855 * CAS_PCS_INTR_STATUS has no corresponding mask register. It can only 856 * be masked with CAS_INTR_PCS_INT. 857 */ 858#define CAS_PCS_INTR_LINK 0x00000004 /* link status change */ 859 860#define CAS_PCS_DATAPATH_MII 0x00000001 /* GMII/MII and MAC loopback */ 861#define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 862 863#define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */ 864#define CAS_PCS_SERDES_CTRL_ESD 0x00000002 /* En. sync char. detection. */ 865#define CAS_PCS_SERDES_CTRL_LR 0x00000004 /* Lock to reference clock. */ 866 867#define CAS_PCS_SERDES_STATUS_T 0x00000000 /* Undergoing test. */ 868#define CAS_PCS_SERDES_STATUS_L 0x00000001 /* Waiting 500us w/ lockrefn. */ 869#define CAS_PCS_SERDES_STATUS_C 0x00000002 /* Waiting for comma detect. */ 870#define CAS_PCS_SERDES_STATUS_S 0x00000003 /* Receive data is sync. */ 871 872#define CAS_PCS_PKT_CNT_TX_MASK 0x000007ff /* TX packets */ 873#define CAS_PCS_PKT_CNT_TX_SHFT 0 874#define CAS_PCS_PKT_CNT_RX_MASK 0x07ff0000 /* RX packets */ 875#define CAS_PCS_PKT_CNT_RX_SHFT 16 876 877/* 878 * PCI expansion ROM runtime access 879 * Cassinis and Saturn map a 1MB space for the PCI expansion ROM as the 880 * second half of the first register bank, although they only support up 881 * to 64KB ROMs. 882 */ 883#define CAS_PCI_ROM_OFFSET 0x100000 884#define CAS_PCI_ROM_SIZE 0x10000 885 886/* secondary local bus device */ 887#define CAS_SEC_LBDEV_OFFSET 0x180000 888#define CAS_SEC_LBDE_SIZE 0x7ffff 889 890/* wired PHY addresses */ 891#define CAS_PHYAD_INTERNAL 1 892#define CAS_PHYAD_EXTERNAL 0 893 894/* wired RX FIFO size in bytes */ 895#define CAS_RX_FIFO_SIZE 16 * 1024 896 897/* 898 * descriptor ring structures 899 */ 900struct cas_desc { 901 uint64_t cd_flags; 902 uint64_t cd_buf_ptr; 903}; 904 905/* 906 * transmit flags 907 * CAS_TD_CKSUM_START_MASK, CAS_TD_CKSUM_STUFF_MASK, CAS_TD_CKSUM_EN and 908 * CAS_TD_INT_ME only need to be set in 1st descriptor of a frame. 909 */ 910#define CAS_TD_BUF_LEN_MASK 0x0000000000003fffULL /* buffer length */ 911#define CAS_TD_BUF_LEN_SHFT 0 912#define CAS_TD_CKSUM_START_MASK 0x00000000001f8000ULL /* checksum start... */ 913#define CAS_TD_CKSUM_START_SHFT 15 /* ...offset */ 914#define CAS_TD_CKSUM_STUFF_MASK 0x000000001fe00000ULL /* checksum stuff... */ 915#define CAS_TD_CKSUM_STUFF_SHFT 21 /* ...offset */ 916#define CAS_TD_CKSUM_EN 0x0000000020000000ULL /* checksum enable */ 917#define CAS_TD_END_OF_FRAME 0x0000000040000000ULL /* last desc. of pkt. */ 918#define CAS_TD_START_OF_FRAME 0x0000000080000000ULL /* 1st desc. of pkt. */ 919#define CAS_TD_INT_ME 0x0000000100000000ULL /* intr. when in FIFO */ 920#define CAS_TD_NO_CRC 0x0000000200000000ULL /* Don't insert CRC. */ 921 922/* receive flags */ 923#define CAS_RD_BUF_INDEX_MASK 0x0000000000003fffULL /* data buffer index */ 924#define CAS_RD_BUF_INDEX_SHFT 0 925 926/* 927 * receive completion ring structure 928 */ 929struct cas_rx_comp { 930 uint64_t crc_word1; 931 uint64_t crc_word2; 932 uint64_t crc_word3; 933 uint64_t crc_word4; 934}; 935 936#define CAS_RC1_DATA_SIZE_MASK 0x0000000007ffe000ULL /* pkt. data length */ 937#define CAS_RC1_DATA_SIZE_SHFT 13 938#define CAS_RC1_DATA_OFF_MASK 0x000001fff8000000ULL /* data buffer offset */ 939#define CAS_RC1_DATA_OFF_SHFT 27 940#define CAS_RC1_DATA_INDEX_MASK 0x007ffe0000000000ULL /* data buffer index */ 941#define CAS_RC1_DATA_INDEX_SHFT 41 942#define CAS_RC1_SKIP_MASK 0x0180000000000000ULL /* entries to skip */ 943#define CAS_RC1_SKIP_SHFT 55 944#define CAS_RC1_RELEASE_NEXT 0x0200000000000000ULL /* last in reas. buf. */ 945#define CAS_RC1_SPLIT_PKT 0x0400000000000000ULL /* used 2 reas. buf. */ 946#define CAS_RC1_RELEASE_FLOW 0x0800000000000000ULL /* last pkt. of flow */ 947#define CAS_RC1_RELEASE_DATA 0x1000000000000000ULL /* reas. buf. full */ 948#define CAS_RC1_RELEASE_HDR 0x2000000000000000ULL /* header buf. full */ 949#define CAS_RC1_TYPE_HW 0x0000000000000000ULL /* owned by hardware */ 950#define CAS_RC1_TYPE_RSFB 0x4000000000000000ULL /* stale flow buf... */ 951#define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */ 952#define CAS_RC1_TYPE_RFP 0xc000000000000000ULL /* flow packet... */ 953#define CAS_RC1_TYPE_MASK CAS_RC1_TYPE_RFP /* ...release */ 954#define CAS_RC1_TYPE_SHFT 62 955 956#define CAS_RC2_NEXT_INDEX_MASK 0x00000007ffe00000ULL /* next buf. of pkt. */ 957#define CAS_RC2_NEXT_INDEX_SHFT 21 958#define CAS_RC2_HDR_SIZE_MASK 0x00000ff800000000ULL /* header length */ 959#define CAS_RC2_HDR_SIZE_SHFT 35 960#define CAS_RC2_HDR_OFF_MASK 0x0003f00000000000ULL /* header buf. offset */ 961#define CAS_RC2_HDR_OFF_SHFT 44 962#define CAS_RC2_HDR_INDEX_MASK 0xfffc000000000000ULL /* header buf. index */ 963#define CAS_RC2_HDR_INDEX_SHFT 50 964 965#define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */ 966#define CAS_RC3_JUMBO_PKT 0x0000000000000002ULL /* pkt. > 1522 bytes */ 967#define CAS_RC3_JMBHS_EN 0x0000000000000004ULL /* jmb. hdr. spl. en. */ 968#define CAS_RC3_CSO_MASK 0x000000000007f000ULL /* checksum start... */ 969#define CAS_RC3_CSO_SHFT 12 /* ...offset */ 970#define CAS_RC3_FLOWID_MASK 0x0000000001f80000ULL /* flow ID of pkt. */ 971#define CAS_RC3_FLOWID_SHFT 19 972#define CAS_RC3_OP_MASK 0x000000000e000000ULL /* opcode */ 973#define CAS_RC3_OP_SHFT 25 974#define CAS_RC3_FRC_FLAG 0x0000000010000000ULL /* op. 2 batch. lkhd. */ 975#define CAS_RC3_NASSIST 0x0000000020000000ULL /* no assist */ 976#define CAS_RC3_LB_MASK 0x000001f800000000ULL /* load balancing key */ 977#define CAS_RC3_LB_SHFT 35 978#define CAS_RC3_L3HO_MASK 0x0000fe0000000000ULL /* layer 3 hdr. off. */ 979#define CAS_RC3_L3HO_SHFT 41 980#define CAS_RC3_PLUS_ENC_PKT 0x0000020000000000ULL /* IPsec AH/ESP pkt. */ 981#define CAS_RC3_PLUS_L3HO_MASK 0x0000fc0000000000ULL /* layer 3 hdr. off. */ 982#define CAS_RC3_PLUS_L3HO_SHFT 42 983#define CAS_RC3_SAP_MASK 0xffff000000000000ULL /* ethertype */ 984#define CAS_RC3_SAP_SHFT 48 985 986#define CAS_RC4_TCP_CSUM_MASK 0x000000000000ffffULL /* TCP checksum */ 987#define CAS_RC4_TCP_CSUM_SHFT 0 988#define CAS_RC4_PKT_LEN_MASK 0x000000003fff0000ULL /* entire pkt. length */ 989#define CAS_RC4_PKT_LEN_SHFT 16 990#define CAS_RC4_PAM_MASK 0x00000003c0000000ULL /* mcast. addr. match */ 991#define CAS_RC4_PAM_SHFT 30 992#define CAS_RC4_ZERO 0x0000080000000000ULL /* owned by software */ 993#define CAS_RC4_HASH_VAL_MASK 0x0ffff00000000000ULL /* mcast. addr. hash */ 994#define CAS_RC4_HASH_VAL_SHFT 44 995#define CAS_RC4_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 996#define CAS_RC4_BAD 0x4000000000000000ULL /* CRC error */ 997#define CAS_RC4_LEN_MMATCH 0x8000000000000000ULL /* length field mism. */ 998 999#define CAS_GET(reg, bits) (((reg) & (bits ## _MASK)) >> (bits ## _SHFT)) 1000#define CAS_SET(val, bits) (((val) << (bits ## _SHFT)) & (bits ## _MASK)) 1001 1002#endif 1003