1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: releng/10.3/sys/dev/bxe/ecore_sp.h 272004 2014-09-22 21:12:30Z davidcs $"); 29 30#ifndef ECORE_SP_H 31#define ECORE_SP_H 32 33 34#include <sys/types.h> 35#include <sys/endian.h> 36#include <sys/param.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <machine/bus.h> 42#include <net/ethernet.h> 43 44#if _BYTE_ORDER == _LITTLE_ENDIAN 45#ifndef LITTLE_ENDIAN 46#define LITTLE_ENDIAN 47#endif 48#ifndef __LITTLE_ENDIAN 49#define __LITTLE_ENDIAN 50#endif 51#undef BIG_ENDIAN 52#undef __BIG_ENDIAN 53#else /* _BIG_ENDIAN */ 54#ifndef BIG_ENDIAN 55#define BIG_ENDIAN 56#endif 57#ifndef __BIG_ENDIAN 58#define __BIG_ENDIAN 59#endif 60#undef LITTLE_ENDIAN 61#undef __LITTLE_ENDIAN 62#endif 63 64#include "ecore_mfw_req.h" 65#include "ecore_fw_defs.h" 66#include "ecore_hsi.h" 67#include "ecore_reg.h" 68 69struct bxe_softc; 70typedef bus_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 71typedef volatile int ecore_atomic_t; 72 73#ifndef __bool_true_false_are_defined 74#ifndef __cplusplus 75#define bool _Bool 76#if __STDC_VERSION__ < 199901L && __GNUC__ < 3 && !defined(__INTEL_COMPILER) 77typedef _Bool bool; 78#endif 79#endif /* !__cplusplus */ 80#endif /* !__bool_true_false_are_defined$ */ 81 82#define ETH_ALEN ETHER_ADDR_LEN /* 6 */ 83 84#define ECORE_SWCID_SHIFT 17 85#define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 86 87#define ECORE_MC_HASH_SIZE 8 88#define ECORE_MC_HASH_OFFSET(sc, i) \ 89 (BAR_TSTRORM_INTMEM + \ 90 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 91 92#define ECORE_MAX_MULTICAST 64 93#define ECORE_MAX_EMUL_MULTI 1 94 95#define IRO sc->iro_array 96 97typedef struct mtx ECORE_MUTEX; 98#define ECORE_MUTEX_INIT(_mutex) \ 99 mtx_init(_mutex, "ecore_lock", "ECORE Lock", MTX_DEF) 100#define ECORE_MUTEX_LOCK(_mutex) mtx_lock(_mutex) 101#define ECORE_MUTEX_UNLOCK(_mutex) mtx_unlock(_mutex) 102 103typedef struct mtx ECORE_MUTEX_SPIN; 104#define ECORE_SPIN_LOCK_INIT(_spin, _sc) \ 105 mtx_init(_spin, "ecore_lock", "ECORE Lock", MTX_DEF) 106#define ECORE_SPIN_LOCK_BH(_spin) mtx_lock(_spin) /* bh = bottom-half */ 107#define ECORE_SPIN_UNLOCK_BH(_spin) mtx_unlock(_spin) /* bh = bottom-half */ 108 109#define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 110#define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 111#define ECORE_SMP_MB() mb() 112#define ECORE_SMP_RMB() rmb() 113#define ECORE_SMP_WMB() wmb() 114#define ECORE_MMIOWB() wmb() 115 116#define ECORE_SET_BIT_NA(bit, var) bit_set(var, bit) /* non-atomic */ 117#define ECORE_CLEAR_BIT_NA(bit, var) bit_clear(var, bit) /* non-atomic */ 118#define ECORE_TEST_BIT(bit, var) bxe_test_bit(bit, var) 119#define ECORE_SET_BIT(bit, var) bxe_set_bit(bit, var) 120#define ECORE_CLEAR_BIT(bit, var) bxe_clear_bit(bit, var) 121#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bxe_test_and_clear_bit(bit, var) 122 123#define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 124#define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 125#define ECORE_ATOMIC_CMPXCHG(a, o, n) bxe_cmpxchg((volatile int *)a, o, n) 126 127#define ECORE_RET_PENDING(pending_bit, pending) \ 128 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 129 130#define ECORE_SET_FLAG(value, mask, flag) \ 131 do { \ 132 (value) &= ~(mask); \ 133 (value) |= ((flag) << (mask##_SHIFT)); \ 134 } while (0) 135 136#define ECORE_GET_FLAG(value, mask) \ 137 (((value) &= (mask)) >> (mask##_SHIFT)) 138 139#define ECORE_MIGHT_SLEEP() 140 141#define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 142 143#define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 144#define ECORE_MEMCPY(_a, _b, _s) memcpy(_a, _b, _s) 145#define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 146 147#define ECORE_CPU_TO_LE16(x) htole16(x) 148#define ECORE_CPU_TO_LE32(x) htole32(x) 149 150#define ECORE_WAIT(_s, _t) DELAY(1000) 151#define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 152 153#define ECORE_LIKELY(x) __predict_true(x) 154#define ECORE_UNLIKELY(x) __predict_false(x) 155 156#define ECORE_ZALLOC(_size, _flags, _sc) \ 157 malloc(_size, M_TEMP, (M_NOWAIT | M_ZERO)) 158 159#define ECORE_CALLOC(_len, _size, _flags, _sc) \ 160 malloc(_len * _size, M_TEMP, (M_NOWAIT | M_ZERO)) 161 162#define ECORE_FREE(_s, _buf, _size) free(_buf, M_TEMP) 163 164#define SC_ILT(sc) ((sc)->ilt) 165#define ILOG2(x) bxe_ilog2(x) 166 167#define ECORE_ILT_ZALLOC(x, y, size) \ 168 do { \ 169 x = malloc(sizeof(struct bxe_dma), M_DEVBUF, (M_NOWAIT | M_ZERO)); \ 170 if (x) { \ 171 if (bxe_dma_alloc((struct bxe_softc *)sc, \ 172 size, (struct bxe_dma *)x, \ 173 "ECORE_ILT") != 0) { \ 174 free(x, M_DEVBUF); \ 175 x = NULL; \ 176 *y = 0; \ 177 } else { \ 178 *y = ((struct bxe_dma *)x)->paddr; \ 179 } \ 180 } \ 181 } while (0) 182 183#define ECORE_ILT_FREE(x, y, size) \ 184 do { \ 185 if (x) { \ 186 bxe_dma_free((struct bxe_softc *)sc, x); \ 187 free(x, M_DEVBUF); \ 188 x = NULL; \ 189 y = 0; \ 190 } \ 191 } while (0) 192 193#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE 194 195#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 196#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 197#define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 198 199#define ECORE_SET_CTX_VALIDATION bxe_set_ctx_validation 200 201#define ECORE_UPDATE_COALESCE_SB_INDEX bxe_update_coalesce_sb_index 202 203#define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 204 205#define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 206 207#define ECORE_PATH_ID SC_PATH 208#define ECORE_PORT_ID SC_PORT 209#define ECORE_FUNC_ID SC_FUNC 210#define ECORE_ABS_FUNC_ID SC_ABS_FUNC 211 212uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length, 213 uint32_t crc32_seed, uint8_t complement); 214static inline uint32_t 215ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 216{ 217 uint32_t packet_buf[2] = {0}; 218 memcpy(((uint8_t *)(&packet_buf[0]))+2, &mac[0], 2); 219 memcpy(&packet_buf[1], &mac[2], 4); 220 return bswap32(calc_crc32((uint8_t *)packet_buf, 8, seed, 0)); 221} 222 223#define ecore_sp_post(_sc, _a, _b, _c, _d) \ 224 bxe_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 225 226#ifdef ECORE_STOP_ON_ERROR 227 228#define ECORE_DBG_BREAK_IF(exp) \ 229 do { \ 230 if (__predict_false(exp)) { \ 231 panic("ECORE"); \ 232 } \ 233 } while (0) 234 235#define ECORE_BUG() \ 236 do { \ 237 panic("BUG (%s:%d)", __FILE__, __LINE__); \ 238 } while(0); 239 240#define ECORE_BUG_ON(exp) \ 241 do { \ 242 if (__predict_true(exp)) { \ 243 panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 244 } \ 245 } while (0) 246 247#else 248 249extern unsigned long bxe_debug; 250 251#define BXE_DEBUG_ECORE_DBG_BREAK_IF 0x01 252#define BXE_DEBUG_ECORE_BUG 0x02 253#define BXE_DEBUG_ECORE_BUG_ON 0x04 254 255#define ECORE_DBG_BREAK_IF(exp) \ 256 if (bxe_debug & BXE_DEBUG_ECORE_DBG_BREAK_IF) \ 257 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 258 259#define ECORE_BUG(exp) \ 260 if (bxe_debug & BXE_DEBUG_ECORE_BUG) \ 261 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 262 263#define ECORE_BUG_ON(exp) \ 264 if (bxe_debug & BXE_DEBUG_ECORE_BUG_ON) \ 265 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 266 267 268#endif /* #ifdef ECORE_STOP_ON_ERROR */ 269 270#define ECORE_ERR(str, ...) \ 271 BLOGE(sc, "ECORE: " str, ##__VA_ARGS__) 272 273#define DBG_SP 0x00000004 /* defined in bxe.h */ 274 275#define ECORE_MSG(sc, m, ...) \ 276 BLOGD(sc, DBG_SP, "ECORE: " m, ##__VA_ARGS__) 277 278typedef struct _ecore_list_entry_t 279{ 280 struct _ecore_list_entry_t *next, *prev; 281} ecore_list_entry_t; 282 283typedef struct ecore_list_t 284{ 285 ecore_list_entry_t *head, *tail; 286 unsigned long cnt; 287} ecore_list_t; 288 289/* initialize the list */ 290#define ECORE_LIST_INIT(_list) \ 291 do { \ 292 (_list)->head = NULL; \ 293 (_list)->tail = NULL; \ 294 (_list)->cnt = 0; \ 295 } while (0) 296 297/* return TRUE if the element is the last on the list */ 298#define ECORE_LIST_IS_LAST(_elem, _list) \ 299 (_elem == (_list)->tail) 300 301/* return TRUE if the list is empty */ 302#define ECORE_LIST_IS_EMPTY(_list) \ 303 ((_list)->cnt == 0) 304 305/* return the first element */ 306#define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 307 (cast *)((_list)->head) 308 309/* return the next element */ 310#define ECORE_LIST_NEXT(_elem, _link, cast) \ 311 (cast *)((&((_elem)->_link))->next) 312 313/* push an element on the head of the list */ 314#define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 315 do { \ 316 (_elem)->prev = (ecore_list_entry_t *)0; \ 317 (_elem)->next = (_list)->head; \ 318 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 319 (_list)->tail = (_elem); \ 320 } else { \ 321 (_list)->head->prev = (_elem); \ 322 } \ 323 (_list)->head = (_elem); \ 324 (_list)->cnt++; \ 325 } while (0) 326 327/* push an element on the tail of the list */ 328#define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 329 do { \ 330 (_elem)->next = (ecore_list_entry_t *)0; \ 331 (_elem)->prev = (_list)->tail; \ 332 if ((_list)->tail) { \ 333 (_list)->tail->next = (_elem); \ 334 } else { \ 335 (_list)->head = (_elem); \ 336 } \ 337 (_list)->tail = (_elem); \ 338 (_list)->cnt++; \ 339 } while (0) 340 341/* push list1 on the head of list2 and return with list1 as empty */ 342#define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 343 do { \ 344 (_list1)->tail->next = (_list2)->head; \ 345 if ((_list2)->head) { \ 346 (_list2)->head->prev = (_list1)->tail; \ 347 } else { \ 348 (_list2)->tail = (_list1)->tail; \ 349 } \ 350 (_list2)->head = (_list1)->head; \ 351 (_list2)->cnt += (_list1)->cnt; \ 352 (_list1)->head = NULL; \ 353 (_list1)->tail = NULL; \ 354 (_list1)->cnt = 0; \ 355 } while (0) 356 357/* remove an element from the list */ 358#define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 359 do { \ 360 if ((_list)->head == (_elem)) { \ 361 if ((_list)->head) { \ 362 (_list)->head = (_list)->head->next; \ 363 if ((_list)->head) { \ 364 (_list)->head->prev = (ecore_list_entry_t *)0; \ 365 } else { \ 366 (_list)->tail = (ecore_list_entry_t *)0; \ 367 } \ 368 (_list)->cnt--; \ 369 } \ 370 } else if ((_list)->tail == (_elem)) { \ 371 if ((_list)->tail) { \ 372 (_list)->tail = (_list)->tail->prev; \ 373 if ((_list)->tail) { \ 374 (_list)->tail->next = (ecore_list_entry_t *)0; \ 375 } else { \ 376 (_list)->head = (ecore_list_entry_t *)0; \ 377 } \ 378 (_list)->cnt--; \ 379 } \ 380 } else { \ 381 (_elem)->prev->next = (_elem)->next; \ 382 (_elem)->next->prev = (_elem)->prev; \ 383 (_list)->cnt--; \ 384 } \ 385 } while (0) 386 387/* walk the list */ 388#define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 389 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 390 pos; \ 391 pos = ECORE_LIST_NEXT(pos, _link, cast)) 392 393/* walk the list (safely) */ 394#define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 395 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 396 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 397 pos != NULL; \ 398 pos = (cast *)n, \ 399 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 400 401 402/* Manipulate a bit vector defined as an array of uint64_t */ 403 404/* Number of bits in one sge_mask array element */ 405#define BIT_VEC64_ELEM_SZ 64 406#define BIT_VEC64_ELEM_SHIFT 6 407#define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 408 409#define __BIT_VEC64_SET_BIT(el, bit) \ 410 do { \ 411 el = ((el) | ((uint64_t)0x1 << (bit))); \ 412 } while (0) 413 414#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 415 do { \ 416 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 417 } while (0) 418 419#define BIT_VEC64_SET_BIT(vec64, idx) \ 420 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 421 (idx) & BIT_VEC64_ELEM_MASK) 422 423#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 424 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 425 (idx) & BIT_VEC64_ELEM_MASK) 426 427#define BIT_VEC64_TEST_BIT(vec64, idx) \ 428 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 429 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 430 431/* 432 * Creates a bitmask of all ones in less significant bits. 433 * idx - index of the most significant bit in the created mask 434 */ 435#define BIT_VEC64_ONES_MASK(idx) \ 436 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 437#define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 438 439/* fill in a MAC address the way the FW likes it */ 440static inline void 441ecore_set_fw_mac_addr(uint16_t *fw_hi, 442 uint16_t *fw_mid, 443 uint16_t *fw_lo, 444 uint8_t *mac) 445{ 446 ((uint8_t *)fw_hi)[0] = mac[1]; 447 ((uint8_t *)fw_hi)[1] = mac[0]; 448 ((uint8_t *)fw_mid)[0] = mac[3]; 449 ((uint8_t *)fw_mid)[1] = mac[2]; 450 ((uint8_t *)fw_lo)[0] = mac[5]; 451 ((uint8_t *)fw_lo)[1] = mac[4]; 452} 453 454 455enum ecore_status_t { 456 ECORE_EXISTS = -6, 457 ECORE_IO = -5, 458 ECORE_TIMEOUT = -4, 459 ECORE_INVAL = -3, 460 ECORE_BUSY = -2, 461 ECORE_NOMEM = -1, 462 ECORE_SUCCESS = 0, 463 /* PENDING is not an error and should be positive */ 464 ECORE_PENDING = 1, 465}; 466 467enum { 468 SWITCH_UPDATE, 469 AFEX_UPDATE, 470}; 471 472 473 474 475struct bxe_softc; 476struct eth_context; 477 478/* Bits representing general command's configuration */ 479enum { 480 RAMROD_TX, 481 RAMROD_RX, 482 /* Wait until all pending commands complete */ 483 RAMROD_COMP_WAIT, 484 /* Don't send a ramrod, only update a registry */ 485 RAMROD_DRV_CLR_ONLY, 486 /* Configure HW according to the current object state */ 487 RAMROD_RESTORE, 488 /* Execute the next command now */ 489 RAMROD_EXEC, 490 /* Don't add a new command and continue execution of posponed 491 * commands. If not set a new command will be added to the 492 * pending commands list. 493 */ 494 RAMROD_CONT, 495 /* If there is another pending ramrod, wait until it finishes and 496 * re-try to submit this one. This flag can be set only in sleepable 497 * context, and should not be set from the context that completes the 498 * ramrods as deadlock will occur. 499 */ 500 RAMROD_RETRY, 501}; 502 503typedef enum { 504 ECORE_OBJ_TYPE_RX, 505 ECORE_OBJ_TYPE_TX, 506 ECORE_OBJ_TYPE_RX_TX, 507} ecore_obj_type; 508 509/* Public slow path states */ 510enum { 511 ECORE_FILTER_MAC_PENDING, 512 ECORE_FILTER_VLAN_PENDING, 513 ECORE_FILTER_VLAN_MAC_PENDING, 514 ECORE_FILTER_RX_MODE_PENDING, 515 ECORE_FILTER_RX_MODE_SCHED, 516 ECORE_FILTER_ISCSI_ETH_START_SCHED, 517 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 518 ECORE_FILTER_FCOE_ETH_START_SCHED, 519 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 520 ECORE_FILTER_BYPASS_RX_MODE_PENDING, 521 ECORE_FILTER_BYPASS_MAC_PENDING, 522 ECORE_FILTER_BYPASS_RSS_CONF_PENDING, 523 ECORE_FILTER_MCAST_PENDING, 524 ECORE_FILTER_MCAST_SCHED, 525 ECORE_FILTER_RSS_CONF_PENDING, 526 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 527 ECORE_AFEX_PENDING_VIFSET_MCP_ACK 528}; 529 530struct ecore_raw_obj { 531 uint8_t func_id; 532 533 /* Queue params */ 534 uint8_t cl_id; 535 uint32_t cid; 536 537 /* Ramrod data buffer params */ 538 void *rdata; 539 ecore_dma_addr_t rdata_mapping; 540 541 /* Ramrod state params */ 542 int state; /* "ramrod is pending" state bit */ 543 unsigned long *pstate; /* pointer to state buffer */ 544 545 ecore_obj_type obj_type; 546 547 int (*wait_comp)(struct bxe_softc *sc, 548 struct ecore_raw_obj *o); 549 550 bool (*check_pending)(struct ecore_raw_obj *o); 551 void (*clear_pending)(struct ecore_raw_obj *o); 552 void (*set_pending)(struct ecore_raw_obj *o); 553}; 554 555/************************* VLAN-MAC commands related parameters ***************/ 556struct ecore_mac_ramrod_data { 557 uint8_t mac[ETH_ALEN]; 558 uint8_t is_inner_mac; 559}; 560 561struct ecore_vlan_ramrod_data { 562 uint16_t vlan; 563}; 564 565struct ecore_vlan_mac_ramrod_data { 566 uint8_t mac[ETH_ALEN]; 567 uint8_t is_inner_mac; 568 uint16_t vlan; 569}; 570 571union ecore_classification_ramrod_data { 572 struct ecore_mac_ramrod_data mac; 573 struct ecore_vlan_ramrod_data vlan; 574 struct ecore_vlan_mac_ramrod_data vlan_mac; 575}; 576 577/* VLAN_MAC commands */ 578enum ecore_vlan_mac_cmd { 579 ECORE_VLAN_MAC_ADD, 580 ECORE_VLAN_MAC_DEL, 581 ECORE_VLAN_MAC_MOVE, 582}; 583 584struct ecore_vlan_mac_data { 585 /* Requested command: ECORE_VLAN_MAC_XX */ 586 enum ecore_vlan_mac_cmd cmd; 587 /* used to contain the data related vlan_mac_flags bits from 588 * ramrod parameters. 589 */ 590 unsigned long vlan_mac_flags; 591 592 /* Needed for MOVE command */ 593 struct ecore_vlan_mac_obj *target_obj; 594 595 union ecore_classification_ramrod_data u; 596}; 597 598/*************************** Exe Queue obj ************************************/ 599union ecore_exe_queue_cmd_data { 600 struct ecore_vlan_mac_data vlan_mac; 601 602 struct { 603 /* TODO */ 604 } mcast; 605}; 606 607struct ecore_exeq_elem { 608 ecore_list_entry_t link; 609 610 /* Length of this element in the exe_chunk. */ 611 int cmd_len; 612 613 union ecore_exe_queue_cmd_data cmd_data; 614}; 615 616union ecore_qable_obj; 617 618union ecore_exeq_comp_elem { 619 union event_ring_elem *elem; 620}; 621 622struct ecore_exe_queue_obj; 623 624typedef int (*exe_q_validate)(struct bxe_softc *sc, 625 union ecore_qable_obj *o, 626 struct ecore_exeq_elem *elem); 627 628typedef int (*exe_q_remove)(struct bxe_softc *sc, 629 union ecore_qable_obj *o, 630 struct ecore_exeq_elem *elem); 631 632/* Return positive if entry was optimized, 0 - if not, negative 633 * in case of an error. 634 */ 635typedef int (*exe_q_optimize)(struct bxe_softc *sc, 636 union ecore_qable_obj *o, 637 struct ecore_exeq_elem *elem); 638typedef int (*exe_q_execute)(struct bxe_softc *sc, 639 union ecore_qable_obj *o, 640 ecore_list_t *exe_chunk, 641 unsigned long *ramrod_flags); 642typedef struct ecore_exeq_elem * 643 (*exe_q_get)(struct ecore_exe_queue_obj *o, 644 struct ecore_exeq_elem *elem); 645 646struct ecore_exe_queue_obj { 647 /* Commands pending for an execution. */ 648 ecore_list_t exe_queue; 649 650 /* Commands pending for an completion. */ 651 ecore_list_t pending_comp; 652 653 ECORE_MUTEX_SPIN lock; 654 655 /* Maximum length of commands' list for one execution */ 656 int exe_chunk_len; 657 658 union ecore_qable_obj *owner; 659 660 /****** Virtual functions ******/ 661 /** 662 * Called before commands execution for commands that are really 663 * going to be executed (after 'optimize'). 664 * 665 * Must run under exe_queue->lock 666 */ 667 exe_q_validate validate; 668 669 /** 670 * Called before removing pending commands, cleaning allocated 671 * resources (e.g., credits from validate) 672 */ 673 exe_q_remove remove; 674 675 /** 676 * This will try to cancel the current pending commands list 677 * considering the new command. 678 * 679 * Returns the number of optimized commands or a negative error code 680 * 681 * Must run under exe_queue->lock 682 */ 683 exe_q_optimize optimize; 684 685 /** 686 * Run the next commands chunk (owner specific). 687 */ 688 exe_q_execute execute; 689 690 /** 691 * Return the exe_queue element containing the specific command 692 * if any. Otherwise return NULL. 693 */ 694 exe_q_get get; 695}; 696/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 697/* 698 * Element in the VLAN_MAC registry list having all current configured 699 * rules. 700 */ 701struct ecore_vlan_mac_registry_elem { 702 ecore_list_entry_t link; 703 704 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 705 * Relevant for 57710 and 57711 only. VLANs and MACs share the 706 * same CAM for these chips. 707 */ 708 int cam_offset; 709 710 /* Needed for DEL and RESTORE flows */ 711 unsigned long vlan_mac_flags; 712 713 union ecore_classification_ramrod_data u; 714}; 715 716/* Bits representing VLAN_MAC commands specific flags */ 717enum { 718 ECORE_UC_LIST_MAC, 719 ECORE_ETH_MAC, 720 ECORE_ISCSI_ETH_MAC, 721 ECORE_NETQ_ETH_MAC, 722 ECORE_DONT_CONSUME_CAM_CREDIT, 723 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 724}; 725 726struct ecore_vlan_mac_ramrod_params { 727 /* Object to run the command from */ 728 struct ecore_vlan_mac_obj *vlan_mac_obj; 729 730 /* General command flags: COMP_WAIT, etc. */ 731 unsigned long ramrod_flags; 732 733 /* Command specific configuration request */ 734 struct ecore_vlan_mac_data user_req; 735}; 736 737struct ecore_vlan_mac_obj { 738 struct ecore_raw_obj raw; 739 740 /* Bookkeeping list: will prevent the addition of already existing 741 * entries. 742 */ 743 ecore_list_t head; 744 /* Implement a simple reader/writer lock on the head list. 745 * all these fields should only be accessed under the exe_queue lock 746 */ 747 uint8_t head_reader; /* Num. of readers accessing head list */ 748 bool head_exe_request; /* Pending execution request. */ 749 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 750 751 /* Execution queue interface instance */ 752 struct ecore_exe_queue_obj exe_queue; 753 754 /* MACs credit pool */ 755 struct ecore_credit_pool_obj *macs_pool; 756 757 /* VLANs credit pool */ 758 struct ecore_credit_pool_obj *vlans_pool; 759 760 /* RAMROD command to be used */ 761 int ramrod_cmd; 762 763 /* copy first n elements onto preallocated buffer 764 * 765 * @param n number of elements to get 766 * @param buf buffer preallocated by caller into which elements 767 * will be copied. Note elements are 4-byte aligned 768 * so buffer size must be able to accommodate the 769 * aligned elements. 770 * 771 * @return number of copied bytes 772 */ 773 774 int (*get_n_elements)(struct bxe_softc *sc, 775 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 776 uint8_t stride, uint8_t size); 777 778 /** 779 * Checks if ADD-ramrod with the given params may be performed. 780 * 781 * @return zero if the element may be added 782 */ 783 784 int (*check_add)(struct bxe_softc *sc, 785 struct ecore_vlan_mac_obj *o, 786 union ecore_classification_ramrod_data *data); 787 788 /** 789 * Checks if DEL-ramrod with the given params may be performed. 790 * 791 * @return TRUE if the element may be deleted 792 */ 793 struct ecore_vlan_mac_registry_elem * 794 (*check_del)(struct bxe_softc *sc, 795 struct ecore_vlan_mac_obj *o, 796 union ecore_classification_ramrod_data *data); 797 798 /** 799 * Checks if DEL-ramrod with the given params may be performed. 800 * 801 * @return TRUE if the element may be deleted 802 */ 803 bool (*check_move)(struct bxe_softc *sc, 804 struct ecore_vlan_mac_obj *src_o, 805 struct ecore_vlan_mac_obj *dst_o, 806 union ecore_classification_ramrod_data *data); 807 808 /** 809 * Update the relevant credit object(s) (consume/return 810 * correspondingly). 811 */ 812 bool (*get_credit)(struct ecore_vlan_mac_obj *o); 813 bool (*put_credit)(struct ecore_vlan_mac_obj *o); 814 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 815 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 816 817 /** 818 * Configures one rule in the ramrod data buffer. 819 */ 820 void (*set_one_rule)(struct bxe_softc *sc, 821 struct ecore_vlan_mac_obj *o, 822 struct ecore_exeq_elem *elem, int rule_idx, 823 int cam_offset); 824 825 /** 826 * Delete all configured elements having the given 827 * vlan_mac_flags specification. Assumes no pending for 828 * execution commands. Will schedule all all currently 829 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 830 * specification for deletion and will use the given 831 * ramrod_flags for the last DEL operation. 832 * 833 * @param sc 834 * @param o 835 * @param ramrod_flags RAMROD_XX flags 836 * 837 * @return 0 if the last operation has completed successfully 838 * and there are no more elements left, positive value 839 * if there are pending for completion commands, 840 * negative value in case of failure. 841 */ 842 int (*delete_all)(struct bxe_softc *sc, 843 struct ecore_vlan_mac_obj *o, 844 unsigned long *vlan_mac_flags, 845 unsigned long *ramrod_flags); 846 847 /** 848 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 849 * configured elements list. 850 * 851 * @param sc 852 * @param p Command parameters (RAMROD_COMP_WAIT bit in 853 * ramrod_flags is only taken into an account) 854 * @param ppos a pointer to the cookie that should be given back in the 855 * next call to make function handle the next element. If 856 * *ppos is set to NULL it will restart the iterator. 857 * If returned *ppos == NULL this means that the last 858 * element has been handled. 859 * 860 * @return int 861 */ 862 int (*restore)(struct bxe_softc *sc, 863 struct ecore_vlan_mac_ramrod_params *p, 864 struct ecore_vlan_mac_registry_elem **ppos); 865 866 /** 867 * Should be called on a completion arrival. 868 * 869 * @param sc 870 * @param o 871 * @param cqe Completion element we are handling 872 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 873 * pending commands will be executed. 874 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 875 * may also be set if needed. 876 * 877 * @return 0 if there are neither pending nor waiting for 878 * completion commands. Positive value if there are 879 * pending for execution or for completion commands. 880 * Negative value in case of an error (including an 881 * error in the cqe). 882 */ 883 int (*complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, 884 union event_ring_elem *cqe, 885 unsigned long *ramrod_flags); 886 887 /** 888 * Wait for completion of all commands. Don't schedule new ones, 889 * just wait. It assumes that the completion code will schedule 890 * for new commands. 891 */ 892 int (*wait)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o); 893}; 894 895enum { 896 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 897 ECORE_LLH_CAM_ETH_LINE, 898 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 899}; 900 901void ecore_set_mac_in_nig(struct bxe_softc *sc, 902 bool add, unsigned char *dev_addr, int index); 903 904/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 905 906/* RX_MODE ramrod special flags: set in rx_mode_flags field in 907 * a ecore_rx_mode_ramrod_params. 908 */ 909enum { 910 ECORE_RX_MODE_FCOE_ETH, 911 ECORE_RX_MODE_ISCSI_ETH, 912}; 913 914enum { 915 ECORE_ACCEPT_UNICAST, 916 ECORE_ACCEPT_MULTICAST, 917 ECORE_ACCEPT_ALL_UNICAST, 918 ECORE_ACCEPT_ALL_MULTICAST, 919 ECORE_ACCEPT_BROADCAST, 920 ECORE_ACCEPT_UNMATCHED, 921 ECORE_ACCEPT_ANY_VLAN 922}; 923 924struct ecore_rx_mode_ramrod_params { 925 struct ecore_rx_mode_obj *rx_mode_obj; 926 unsigned long *pstate; 927 int state; 928 uint8_t cl_id; 929 uint32_t cid; 930 uint8_t func_id; 931 unsigned long ramrod_flags; 932 unsigned long rx_mode_flags; 933 934 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 935 * a tstorm_eth_mac_filter_config (e1x). 936 */ 937 void *rdata; 938 ecore_dma_addr_t rdata_mapping; 939 940 /* Rx mode settings */ 941 unsigned long rx_accept_flags; 942 943 /* internal switching settings */ 944 unsigned long tx_accept_flags; 945}; 946 947struct ecore_rx_mode_obj { 948 int (*config_rx_mode)(struct bxe_softc *sc, 949 struct ecore_rx_mode_ramrod_params *p); 950 951 int (*wait_comp)(struct bxe_softc *sc, 952 struct ecore_rx_mode_ramrod_params *p); 953}; 954 955/********************** Set multicast group ***********************************/ 956 957struct ecore_mcast_list_elem { 958 ecore_list_entry_t link; 959 uint8_t *mac; 960}; 961 962union ecore_mcast_config_data { 963 uint8_t *mac; 964 uint8_t bin; /* used in a RESTORE flow */ 965}; 966 967struct ecore_mcast_ramrod_params { 968 struct ecore_mcast_obj *mcast_obj; 969 970 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 971 unsigned long ramrod_flags; 972 973 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 974 /** TODO: 975 * - rename it to macs_num. 976 * - Add a new command type for handling pending commands 977 * (remove "zero semantics"). 978 * 979 * Length of mcast_list. If zero and ADD_CONT command - post 980 * pending commands. 981 */ 982 int mcast_list_len; 983}; 984 985enum ecore_mcast_cmd { 986 ECORE_MCAST_CMD_ADD, 987 ECORE_MCAST_CMD_CONT, 988 ECORE_MCAST_CMD_DEL, 989 ECORE_MCAST_CMD_RESTORE, 990}; 991 992struct ecore_mcast_obj { 993 struct ecore_raw_obj raw; 994 995 union { 996 struct { 997 #define ECORE_MCAST_BINS_NUM 256 998 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 999 uint64_t vec[ECORE_MCAST_VEC_SZ]; 1000 1001 /** Number of BINs to clear. Should be updated 1002 * immediately when a command arrives in order to 1003 * properly create DEL commands. 1004 */ 1005 int num_bins_set; 1006 } aprox_match; 1007 1008 struct { 1009 ecore_list_t macs; 1010 int num_macs_set; 1011 } exact_match; 1012 } registry; 1013 1014 /* Pending commands */ 1015 ecore_list_t pending_cmds_head; 1016 1017 /* A state that is set in raw.pstate, when there are pending commands */ 1018 int sched_state; 1019 1020 /* Maximal number of mcast MACs configured in one command */ 1021 int max_cmd_len; 1022 1023 /* Total number of currently pending MACs to configure: both 1024 * in the pending commands list and in the current command. 1025 */ 1026 int total_pending_num; 1027 1028 uint8_t engine_id; 1029 1030 /** 1031 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 1032 */ 1033 int (*config_mcast)(struct bxe_softc *sc, 1034 struct ecore_mcast_ramrod_params *p, 1035 enum ecore_mcast_cmd cmd); 1036 1037 /** 1038 * Fills the ramrod data during the RESTORE flow. 1039 * 1040 * @param sc 1041 * @param o 1042 * @param start_idx Registry index to start from 1043 * @param rdata_idx Index in the ramrod data to start from 1044 * 1045 * @return -1 if we handled the whole registry or index of the last 1046 * handled registry element. 1047 */ 1048 int (*hdl_restore)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1049 int start_bin, int *rdata_idx); 1050 1051 int (*enqueue_cmd)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1052 struct ecore_mcast_ramrod_params *p, 1053 enum ecore_mcast_cmd cmd); 1054 1055 void (*set_one_rule)(struct bxe_softc *sc, 1056 struct ecore_mcast_obj *o, int idx, 1057 union ecore_mcast_config_data *cfg_data, 1058 enum ecore_mcast_cmd cmd); 1059 1060 /** Checks if there are more mcast MACs to be set or a previous 1061 * command is still pending. 1062 */ 1063 bool (*check_pending)(struct ecore_mcast_obj *o); 1064 1065 /** 1066 * Set/Clear/Check SCHEDULED state of the object 1067 */ 1068 void (*set_sched)(struct ecore_mcast_obj *o); 1069 void (*clear_sched)(struct ecore_mcast_obj *o); 1070 bool (*check_sched)(struct ecore_mcast_obj *o); 1071 1072 /* Wait until all pending commands complete */ 1073 int (*wait_comp)(struct bxe_softc *sc, struct ecore_mcast_obj *o); 1074 1075 /** 1076 * Handle the internal object counters needed for proper 1077 * commands handling. Checks that the provided parameters are 1078 * feasible. 1079 */ 1080 int (*validate)(struct bxe_softc *sc, 1081 struct ecore_mcast_ramrod_params *p, 1082 enum ecore_mcast_cmd cmd); 1083 1084 /** 1085 * Restore the values of internal counters in case of a failure. 1086 */ 1087 void (*revert)(struct bxe_softc *sc, 1088 struct ecore_mcast_ramrod_params *p, 1089 int old_num_bins); 1090 1091 int (*get_registry_size)(struct ecore_mcast_obj *o); 1092 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1093}; 1094 1095/*************************** Credit handling **********************************/ 1096struct ecore_credit_pool_obj { 1097 1098 /* Current amount of credit in the pool */ 1099 ecore_atomic_t credit; 1100 1101 /* Maximum allowed credit. put() will check against it. */ 1102 int pool_sz; 1103 1104 /* Allocate a pool table statically. 1105 * 1106 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1107 * 1108 * The set bit in the table will mean that the entry is available. 1109 */ 1110#define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1111 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1112 1113 /* Base pool offset (initialized differently */ 1114 int base_pool_offset; 1115 1116 /** 1117 * Get the next free pool entry. 1118 * 1119 * @return TRUE if there was a free entry in the pool 1120 */ 1121 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1122 1123 /** 1124 * Return the entry back to the pool. 1125 * 1126 * @return TRUE if entry is legal and has been successfully 1127 * returned to the pool. 1128 */ 1129 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1130 1131 /** 1132 * Get the requested amount of credit from the pool. 1133 * 1134 * @param cnt Amount of requested credit 1135 * @return TRUE if the operation is successful 1136 */ 1137 bool (*get)(struct ecore_credit_pool_obj *o, int cnt); 1138 1139 /** 1140 * Returns the credit to the pool. 1141 * 1142 * @param cnt Amount of credit to return 1143 * @return TRUE if the operation is successful 1144 */ 1145 bool (*put)(struct ecore_credit_pool_obj *o, int cnt); 1146 1147 /** 1148 * Reads the current amount of credit. 1149 */ 1150 int (*check)(struct ecore_credit_pool_obj *o); 1151}; 1152 1153/*************************** RSS configuration ********************************/ 1154enum { 1155 /* RSS_MODE bits are mutually exclusive */ 1156 ECORE_RSS_MODE_DISABLED, 1157 ECORE_RSS_MODE_REGULAR, 1158 1159 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1160 1161 ECORE_RSS_IPV4, 1162 ECORE_RSS_IPV4_TCP, 1163 ECORE_RSS_IPV4_UDP, 1164 ECORE_RSS_IPV6, 1165 ECORE_RSS_IPV6_TCP, 1166 ECORE_RSS_IPV6_UDP, 1167 1168 ECORE_RSS_TUNNELING, 1169#if defined(__VMKLNX__) && (VMWARE_ESX_DDK_VERSION < 55000) /* ! BNX2X_UPSTREAM */ 1170 ECORE_RSS_MODE_ESX51, 1171#endif 1172}; 1173 1174struct ecore_config_rss_params { 1175 struct ecore_rss_config_obj *rss_obj; 1176 1177 /* may have RAMROD_COMP_WAIT set only */ 1178 unsigned long ramrod_flags; 1179 1180 /* ECORE_RSS_X bits */ 1181 unsigned long rss_flags; 1182 1183 /* Number hash bits to take into an account */ 1184 uint8_t rss_result_mask; 1185 1186 /* Indirection table */ 1187 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1188 1189 /* RSS hash values */ 1190 uint32_t rss_key[10]; 1191 1192 /* valid only iff ECORE_RSS_UPDATE_TOE is set */ 1193 uint16_t toe_rss_bitmap; 1194 1195 /* valid iff ECORE_RSS_TUNNELING is set */ 1196 uint16_t tunnel_value; 1197 uint16_t tunnel_mask; 1198}; 1199 1200struct ecore_rss_config_obj { 1201 struct ecore_raw_obj raw; 1202 1203 /* RSS engine to use */ 1204 uint8_t engine_id; 1205 1206 /* Last configured indirection table */ 1207 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1208 1209 /* flags for enabling 4-tupple hash on UDP */ 1210 uint8_t udp_rss_v4; 1211 uint8_t udp_rss_v6; 1212 1213 int (*config_rss)(struct bxe_softc *sc, 1214 struct ecore_config_rss_params *p); 1215}; 1216 1217/*********************** Queue state update ***********************************/ 1218 1219/* UPDATE command options */ 1220enum { 1221 ECORE_Q_UPDATE_IN_VLAN_REM, 1222 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1223 ECORE_Q_UPDATE_OUT_VLAN_REM, 1224 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1225 ECORE_Q_UPDATE_ANTI_SPOOF, 1226 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1227 ECORE_Q_UPDATE_ACTIVATE, 1228 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1229 ECORE_Q_UPDATE_DEF_VLAN_EN, 1230 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1231 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1232 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1233 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1234 ECORE_Q_UPDATE_TX_SWITCHING, 1235}; 1236 1237/* Allowed Queue states */ 1238enum ecore_q_state { 1239 ECORE_Q_STATE_RESET, 1240 ECORE_Q_STATE_INITIALIZED, 1241 ECORE_Q_STATE_ACTIVE, 1242 ECORE_Q_STATE_MULTI_COS, 1243 ECORE_Q_STATE_MCOS_TERMINATED, 1244 ECORE_Q_STATE_INACTIVE, 1245 ECORE_Q_STATE_STOPPED, 1246 ECORE_Q_STATE_TERMINATED, 1247 ECORE_Q_STATE_FLRED, 1248 ECORE_Q_STATE_MAX, 1249}; 1250 1251/* Allowed Queue states */ 1252enum ecore_q_logical_state { 1253 ECORE_Q_LOGICAL_STATE_ACTIVE, 1254 ECORE_Q_LOGICAL_STATE_STOPPED, 1255}; 1256 1257/* Allowed commands */ 1258enum ecore_queue_cmd { 1259 ECORE_Q_CMD_INIT, 1260 ECORE_Q_CMD_SETUP, 1261 ECORE_Q_CMD_SETUP_TX_ONLY, 1262 ECORE_Q_CMD_DEACTIVATE, 1263 ECORE_Q_CMD_ACTIVATE, 1264 ECORE_Q_CMD_UPDATE, 1265 ECORE_Q_CMD_UPDATE_TPA, 1266 ECORE_Q_CMD_HALT, 1267 ECORE_Q_CMD_CFC_DEL, 1268 ECORE_Q_CMD_TERMINATE, 1269 ECORE_Q_CMD_EMPTY, 1270 ECORE_Q_CMD_MAX, 1271}; 1272 1273/* queue SETUP + INIT flags */ 1274enum { 1275 ECORE_Q_FLG_TPA, 1276 ECORE_Q_FLG_TPA_IPV6, 1277 ECORE_Q_FLG_TPA_GRO, 1278 ECORE_Q_FLG_STATS, 1279 ECORE_Q_FLG_ZERO_STATS, 1280 ECORE_Q_FLG_ACTIVE, 1281 ECORE_Q_FLG_OV, 1282 ECORE_Q_FLG_VLAN, 1283 ECORE_Q_FLG_COS, 1284 ECORE_Q_FLG_HC, 1285 ECORE_Q_FLG_HC_EN, 1286 ECORE_Q_FLG_DHC, 1287 ECORE_Q_FLG_OOO, 1288 ECORE_Q_FLG_FCOE, 1289 ECORE_Q_FLG_LEADING_RSS, 1290 ECORE_Q_FLG_MCAST, 1291 ECORE_Q_FLG_DEF_VLAN, 1292 ECORE_Q_FLG_TX_SWITCH, 1293 ECORE_Q_FLG_TX_SEC, 1294 ECORE_Q_FLG_ANTI_SPOOF, 1295 ECORE_Q_FLG_SILENT_VLAN_REM, 1296 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1297 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1298 ECORE_Q_FLG_PCSUM_ON_PKT, 1299 ECORE_Q_FLG_TUN_INC_INNER_IP_ID 1300}; 1301 1302/* Queue type options: queue type may be a combination of below. */ 1303enum ecore_q_type { 1304 ECORE_Q_TYPE_FWD, 1305 /** TODO: Consider moving both these flags into the init() 1306 * ramrod params. 1307 */ 1308 ECORE_Q_TYPE_HAS_RX, 1309 ECORE_Q_TYPE_HAS_TX, 1310}; 1311 1312#define ECORE_PRIMARY_CID_INDEX 0 1313#define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1314#define ECORE_MULTI_TX_COS_E2_E3A0 2 1315#define ECORE_MULTI_TX_COS_E3B0 3 1316#define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1317#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1318 1319struct ecore_queue_init_params { 1320 struct { 1321 unsigned long flags; 1322 uint16_t hc_rate; 1323 uint8_t fw_sb_id; 1324 uint8_t sb_cq_index; 1325 } tx; 1326 1327 struct { 1328 unsigned long flags; 1329 uint16_t hc_rate; 1330 uint8_t fw_sb_id; 1331 uint8_t sb_cq_index; 1332 } rx; 1333 1334 /* CID context in the host memory */ 1335 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1336 1337 /* maximum number of cos supported by hardware */ 1338 uint8_t max_cos; 1339}; 1340 1341struct ecore_queue_terminate_params { 1342 /* index within the tx_only cids of this queue object */ 1343 uint8_t cid_index; 1344}; 1345 1346struct ecore_queue_cfc_del_params { 1347 /* index within the tx_only cids of this queue object */ 1348 uint8_t cid_index; 1349}; 1350 1351struct ecore_queue_update_params { 1352 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ 1353 uint16_t def_vlan; 1354 uint16_t silent_removal_value; 1355 uint16_t silent_removal_mask; 1356/* index within the tx_only cids of this queue object */ 1357 uint8_t cid_index; 1358}; 1359 1360struct rxq_pause_params { 1361 uint16_t bd_th_lo; 1362 uint16_t bd_th_hi; 1363 uint16_t rcq_th_lo; 1364 uint16_t rcq_th_hi; 1365 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */ 1366 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */ 1367 uint16_t pri_map; 1368}; 1369 1370/* general */ 1371struct ecore_general_setup_params { 1372 /* valid iff ECORE_Q_FLG_STATS */ 1373 uint8_t stat_id; 1374 1375 uint8_t spcl_id; 1376 uint16_t mtu; 1377 uint8_t cos; 1378}; 1379 1380struct ecore_rxq_setup_params { 1381 /* dma */ 1382 ecore_dma_addr_t dscr_map; 1383 ecore_dma_addr_t sge_map; 1384 ecore_dma_addr_t rcq_map; 1385 ecore_dma_addr_t rcq_np_map; 1386 1387 uint16_t drop_flags; 1388 uint16_t buf_sz; 1389 uint8_t fw_sb_id; 1390 uint8_t cl_qzone_id; 1391 1392 /* valid iff ECORE_Q_FLG_TPA */ 1393 uint16_t tpa_agg_sz; 1394 uint16_t sge_buf_sz; 1395 uint8_t max_sges_pkt; 1396 uint8_t max_tpa_queues; 1397 uint8_t rss_engine_id; 1398 1399 /* valid iff ECORE_Q_FLG_MCAST */ 1400 uint8_t mcast_engine_id; 1401 1402 uint8_t cache_line_log; 1403 1404 uint8_t sb_cq_index; 1405 1406 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 1407 uint16_t silent_removal_value; 1408 uint16_t silent_removal_mask; 1409}; 1410 1411struct ecore_txq_setup_params { 1412 /* dma */ 1413 ecore_dma_addr_t dscr_map; 1414 1415 uint8_t fw_sb_id; 1416 uint8_t sb_cq_index; 1417 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */ 1418 uint16_t traffic_type; 1419 /* equals to the leading rss client id, used for TX classification*/ 1420 uint8_t tss_leading_cl_id; 1421 1422 /* valid iff ECORE_Q_FLG_DEF_VLAN */ 1423 uint16_t default_vlan; 1424}; 1425 1426struct ecore_queue_setup_params { 1427 struct ecore_general_setup_params gen_params; 1428 struct ecore_txq_setup_params txq_params; 1429 struct ecore_rxq_setup_params rxq_params; 1430 struct rxq_pause_params pause_params; 1431 unsigned long flags; 1432}; 1433 1434struct ecore_queue_setup_tx_only_params { 1435 struct ecore_general_setup_params gen_params; 1436 struct ecore_txq_setup_params txq_params; 1437 unsigned long flags; 1438 /* index within the tx_only cids of this queue object */ 1439 uint8_t cid_index; 1440}; 1441 1442struct ecore_queue_state_params { 1443 struct ecore_queue_sp_obj *q_obj; 1444 1445 /* Current command */ 1446 enum ecore_queue_cmd cmd; 1447 1448 /* may have RAMROD_COMP_WAIT set only */ 1449 unsigned long ramrod_flags; 1450 1451 /* Params according to the current command */ 1452 union { 1453 struct ecore_queue_update_params update; 1454 struct ecore_queue_setup_params setup; 1455 struct ecore_queue_init_params init; 1456 struct ecore_queue_setup_tx_only_params tx_only; 1457 struct ecore_queue_terminate_params terminate; 1458 struct ecore_queue_cfc_del_params cfc_del; 1459 } params; 1460}; 1461 1462struct ecore_viflist_params { 1463 uint8_t echo_res; 1464 uint8_t func_bit_map_res; 1465}; 1466 1467struct ecore_queue_sp_obj { 1468 uint32_t cids[ECORE_MULTI_TX_COS]; 1469 uint8_t cl_id; 1470 uint8_t func_id; 1471 1472 /* number of traffic classes supported by queue. 1473 * The primary connection of the queue supports the first traffic 1474 * class. Any further traffic class is supported by a tx-only 1475 * connection. 1476 * 1477 * Therefore max_cos is also a number of valid entries in the cids 1478 * array. 1479 */ 1480 uint8_t max_cos; 1481 uint8_t num_tx_only, next_tx_only; 1482 1483 enum ecore_q_state state, next_state; 1484 1485 /* bits from enum ecore_q_type */ 1486 unsigned long type; 1487 1488 /* ECORE_Q_CMD_XX bits. This object implements "one 1489 * pending" paradigm but for debug and tracing purposes it's 1490 * more convenient to have different bits for different 1491 * commands. 1492 */ 1493 unsigned long pending; 1494 1495 /* Buffer to use as a ramrod data and its mapping */ 1496 void *rdata; 1497 ecore_dma_addr_t rdata_mapping; 1498 1499 /** 1500 * Performs one state change according to the given parameters. 1501 * 1502 * @return 0 in case of success and negative value otherwise. 1503 */ 1504 int (*send_cmd)(struct bxe_softc *sc, 1505 struct ecore_queue_state_params *params); 1506 1507 /** 1508 * Sets the pending bit according to the requested transition. 1509 */ 1510 int (*set_pending)(struct ecore_queue_sp_obj *o, 1511 struct ecore_queue_state_params *params); 1512 1513 /** 1514 * Checks that the requested state transition is legal. 1515 */ 1516 int (*check_transition)(struct bxe_softc *sc, 1517 struct ecore_queue_sp_obj *o, 1518 struct ecore_queue_state_params *params); 1519 1520 /** 1521 * Completes the pending command. 1522 */ 1523 int (*complete_cmd)(struct bxe_softc *sc, 1524 struct ecore_queue_sp_obj *o, 1525 enum ecore_queue_cmd); 1526 1527 int (*wait_comp)(struct bxe_softc *sc, 1528 struct ecore_queue_sp_obj *o, 1529 enum ecore_queue_cmd cmd); 1530}; 1531 1532/********************** Function state update *********************************/ 1533/* Allowed Function states */ 1534enum ecore_func_state { 1535 ECORE_F_STATE_RESET, 1536 ECORE_F_STATE_INITIALIZED, 1537 ECORE_F_STATE_STARTED, 1538 ECORE_F_STATE_TX_STOPPED, 1539 ECORE_F_STATE_MAX, 1540}; 1541 1542/* Allowed Function commands */ 1543enum ecore_func_cmd { 1544 ECORE_F_CMD_HW_INIT, 1545 ECORE_F_CMD_START, 1546 ECORE_F_CMD_STOP, 1547 ECORE_F_CMD_HW_RESET, 1548 ECORE_F_CMD_AFEX_UPDATE, 1549 ECORE_F_CMD_AFEX_VIFLISTS, 1550 ECORE_F_CMD_TX_STOP, 1551 ECORE_F_CMD_TX_START, 1552 ECORE_F_CMD_SWITCH_UPDATE, 1553 ECORE_F_CMD_MAX, 1554}; 1555 1556struct ecore_func_hw_init_params { 1557 /* A load phase returned by MCP. 1558 * 1559 * May be: 1560 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1561 * FW_MSG_CODE_DRV_LOAD_COMMON 1562 * FW_MSG_CODE_DRV_LOAD_PORT 1563 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1564 */ 1565 uint32_t load_phase; 1566}; 1567 1568struct ecore_func_hw_reset_params { 1569 /* A load phase returned by MCP. 1570 * 1571 * May be: 1572 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1573 * FW_MSG_CODE_DRV_LOAD_COMMON 1574 * FW_MSG_CODE_DRV_LOAD_PORT 1575 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1576 */ 1577 uint32_t reset_phase; 1578}; 1579 1580struct ecore_func_start_params { 1581 /* Multi Function mode: 1582 * - Single Function 1583 * - Switch Dependent 1584 * - Switch Independent 1585 */ 1586 uint16_t mf_mode; 1587 1588 /* Switch Dependent mode outer VLAN tag */ 1589 uint16_t sd_vlan_tag; 1590 1591 /* Function cos mode */ 1592 uint8_t network_cos_mode; 1593 1594 /* NVGRE classification enablement */ 1595 uint8_t nvgre_clss_en; 1596 1597 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1598 uint8_t gre_tunnel_mode; 1599 1600 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1601 uint8_t gre_tunnel_rss; 1602 1603}; 1604 1605struct ecore_func_switch_update_params { 1606 uint8_t suspend; 1607}; 1608 1609struct ecore_func_afex_update_params { 1610 uint16_t vif_id; 1611 uint16_t afex_default_vlan; 1612 uint8_t allowed_priorities; 1613}; 1614 1615struct ecore_func_afex_viflists_params { 1616 uint16_t vif_list_index; 1617 uint8_t func_bit_map; 1618 uint8_t afex_vif_list_command; 1619 uint8_t func_to_clear; 1620}; 1621struct ecore_func_tx_start_params { 1622 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1623 uint8_t dcb_enabled; 1624 uint8_t dcb_version; 1625 uint8_t dont_add_pri_0; 1626}; 1627 1628struct ecore_func_state_params { 1629 struct ecore_func_sp_obj *f_obj; 1630 1631 /* Current command */ 1632 enum ecore_func_cmd cmd; 1633 1634 /* may have RAMROD_COMP_WAIT set only */ 1635 unsigned long ramrod_flags; 1636 1637 /* Params according to the current command */ 1638 union { 1639 struct ecore_func_hw_init_params hw_init; 1640 struct ecore_func_hw_reset_params hw_reset; 1641 struct ecore_func_start_params start; 1642 struct ecore_func_switch_update_params switch_update; 1643 struct ecore_func_afex_update_params afex_update; 1644 struct ecore_func_afex_viflists_params afex_viflists; 1645 struct ecore_func_tx_start_params tx_start; 1646 } params; 1647}; 1648 1649struct ecore_func_sp_drv_ops { 1650 /* Init tool + runtime initialization: 1651 * - Common Chip 1652 * - Common (per Path) 1653 * - Port 1654 * - Function phases 1655 */ 1656 int (*init_hw_cmn_chip)(struct bxe_softc *sc); 1657 int (*init_hw_cmn)(struct bxe_softc *sc); 1658 int (*init_hw_port)(struct bxe_softc *sc); 1659 int (*init_hw_func)(struct bxe_softc *sc); 1660 1661 /* Reset Function HW: Common, Port, Function phases. */ 1662 void (*reset_hw_cmn)(struct bxe_softc *sc); 1663 void (*reset_hw_port)(struct bxe_softc *sc); 1664 void (*reset_hw_func)(struct bxe_softc *sc); 1665 1666 /* Init/Free GUNZIP resources */ 1667 int (*gunzip_init)(struct bxe_softc *sc); 1668 void (*gunzip_end)(struct bxe_softc *sc); 1669 1670 /* Prepare/Release FW resources */ 1671 int (*init_fw)(struct bxe_softc *sc); 1672 void (*release_fw)(struct bxe_softc *sc); 1673}; 1674 1675struct ecore_func_sp_obj { 1676 enum ecore_func_state state, next_state; 1677 1678 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1679 * pending" paradigm but for debug and tracing purposes it's 1680 * more convenient to have different bits for different 1681 * commands. 1682 */ 1683 unsigned long pending; 1684 1685 /* Buffer to use as a ramrod data and its mapping */ 1686 void *rdata; 1687 ecore_dma_addr_t rdata_mapping; 1688 1689 /* Buffer to use as a afex ramrod data and its mapping. 1690 * This can't be same rdata as above because afex ramrod requests 1691 * can arrive to the object in parallel to other ramrod requests. 1692 */ 1693 void *afex_rdata; 1694 ecore_dma_addr_t afex_rdata_mapping; 1695 1696 /* this mutex validates that when pending flag is taken, the next 1697 * ramrod to be sent will be the one set the pending bit 1698 */ 1699 ECORE_MUTEX one_pending_mutex; 1700 1701 /* Driver interface */ 1702 struct ecore_func_sp_drv_ops *drv; 1703 1704 /** 1705 * Performs one state change according to the given parameters. 1706 * 1707 * @return 0 in case of success and negative value otherwise. 1708 */ 1709 int (*send_cmd)(struct bxe_softc *sc, 1710 struct ecore_func_state_params *params); 1711 1712 /** 1713 * Checks that the requested state transition is legal. 1714 */ 1715 int (*check_transition)(struct bxe_softc *sc, 1716 struct ecore_func_sp_obj *o, 1717 struct ecore_func_state_params *params); 1718 1719 /** 1720 * Completes the pending command. 1721 */ 1722 int (*complete_cmd)(struct bxe_softc *sc, 1723 struct ecore_func_sp_obj *o, 1724 enum ecore_func_cmd cmd); 1725 1726 int (*wait_comp)(struct bxe_softc *sc, struct ecore_func_sp_obj *o, 1727 enum ecore_func_cmd cmd); 1728}; 1729 1730/********************** Interfaces ********************************************/ 1731/* Queueable objects set */ 1732union ecore_qable_obj { 1733 struct ecore_vlan_mac_obj vlan_mac; 1734}; 1735/************** Function state update *********/ 1736void ecore_init_func_obj(struct bxe_softc *sc, 1737 struct ecore_func_sp_obj *obj, 1738 void *rdata, ecore_dma_addr_t rdata_mapping, 1739 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1740 struct ecore_func_sp_drv_ops *drv_iface); 1741 1742int ecore_func_state_change(struct bxe_softc *sc, 1743 struct ecore_func_state_params *params); 1744 1745enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc, 1746 struct ecore_func_sp_obj *o); 1747/******************* Queue State **************/ 1748void ecore_init_queue_obj(struct bxe_softc *sc, 1749 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1750 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1751 ecore_dma_addr_t rdata_mapping, unsigned long type); 1752 1753int ecore_queue_state_change(struct bxe_softc *sc, 1754 struct ecore_queue_state_params *params); 1755 1756int ecore_get_q_logical_state(struct bxe_softc *sc, 1757 struct ecore_queue_sp_obj *obj); 1758 1759/********************* VLAN-MAC ****************/ 1760void ecore_init_mac_obj(struct bxe_softc *sc, 1761 struct ecore_vlan_mac_obj *mac_obj, 1762 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1763 ecore_dma_addr_t rdata_mapping, int state, 1764 unsigned long *pstate, ecore_obj_type type, 1765 struct ecore_credit_pool_obj *macs_pool); 1766 1767void ecore_init_vlan_obj(struct bxe_softc *sc, 1768 struct ecore_vlan_mac_obj *vlan_obj, 1769 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1770 ecore_dma_addr_t rdata_mapping, int state, 1771 unsigned long *pstate, ecore_obj_type type, 1772 struct ecore_credit_pool_obj *vlans_pool); 1773 1774void ecore_init_vlan_mac_obj(struct bxe_softc *sc, 1775 struct ecore_vlan_mac_obj *vlan_mac_obj, 1776 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1777 ecore_dma_addr_t rdata_mapping, int state, 1778 unsigned long *pstate, ecore_obj_type type, 1779 struct ecore_credit_pool_obj *macs_pool, 1780 struct ecore_credit_pool_obj *vlans_pool); 1781 1782int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc, 1783 struct ecore_vlan_mac_obj *o); 1784void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc, 1785 struct ecore_vlan_mac_obj *o); 1786int ecore_vlan_mac_h_write_lock(struct bxe_softc *sc, 1787 struct ecore_vlan_mac_obj *o); 1788void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc, 1789 struct ecore_vlan_mac_obj *o); 1790int ecore_config_vlan_mac(struct bxe_softc *sc, 1791 struct ecore_vlan_mac_ramrod_params *p); 1792 1793int ecore_vlan_mac_move(struct bxe_softc *sc, 1794 struct ecore_vlan_mac_ramrod_params *p, 1795 struct ecore_vlan_mac_obj *dest_o); 1796 1797/********************* RX MODE ****************/ 1798 1799void ecore_init_rx_mode_obj(struct bxe_softc *sc, 1800 struct ecore_rx_mode_obj *o); 1801 1802/** 1803 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1804 * 1805 * @p: Command parameters 1806 * 1807 * Return: 0 - if operation was successful and there is no pending completions, 1808 * positive number - if there are pending completions, 1809 * negative - if there were errors 1810 */ 1811int ecore_config_rx_mode(struct bxe_softc *sc, 1812 struct ecore_rx_mode_ramrod_params *p); 1813 1814/****************** MULTICASTS ****************/ 1815 1816void ecore_init_mcast_obj(struct bxe_softc *sc, 1817 struct ecore_mcast_obj *mcast_obj, 1818 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1819 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1820 int state, unsigned long *pstate, 1821 ecore_obj_type type); 1822 1823/** 1824 * ecore_config_mcast - Configure multicast MACs list. 1825 * 1826 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1827 * 1828 * May configure a new list 1829 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1830 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1831 * configuration, continue to execute the pending commands 1832 * (ECORE_MCAST_CMD_CONT). 1833 * 1834 * If previous command is still pending or if number of MACs to 1835 * configure is more that maximum number of MACs in one command, 1836 * the current command will be enqueued to the tail of the 1837 * pending commands list. 1838 * 1839 * Return: 0 is operation was successfull and there are no pending completions, 1840 * negative if there were errors, positive if there are pending 1841 * completions. 1842 */ 1843int ecore_config_mcast(struct bxe_softc *sc, 1844 struct ecore_mcast_ramrod_params *p, 1845 enum ecore_mcast_cmd cmd); 1846 1847/****************** CREDIT POOL ****************/ 1848void ecore_init_mac_credit_pool(struct bxe_softc *sc, 1849 struct ecore_credit_pool_obj *p, uint8_t func_id, 1850 uint8_t func_num); 1851void ecore_init_vlan_credit_pool(struct bxe_softc *sc, 1852 struct ecore_credit_pool_obj *p, uint8_t func_id, 1853 uint8_t func_num); 1854 1855/****************** RSS CONFIGURATION ****************/ 1856void ecore_init_rss_config_obj(struct bxe_softc *sc, 1857 struct ecore_rss_config_obj *rss_obj, 1858 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1859 void *rdata, ecore_dma_addr_t rdata_mapping, 1860 int state, unsigned long *pstate, 1861 ecore_obj_type type); 1862 1863/** 1864 * ecore_config_rss - Updates RSS configuration according to provided parameters 1865 * 1866 * Return: 0 in case of success 1867 */ 1868int ecore_config_rss(struct bxe_softc *sc, 1869 struct ecore_config_rss_params *p); 1870 1871/** 1872 * ecore_get_rss_ind_table - Return the current ind_table configuration. 1873 * 1874 * @ind_table: buffer to fill with the current indirection 1875 * table content. Should be at least 1876 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1877 */ 1878void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj, 1879 uint8_t *ind_table); 1880 1881/* set as inline so printout will show the offending function */ 1882int validate_vlan_mac(struct bxe_softc *sc, 1883 struct ecore_vlan_mac_obj *vlan_mac); 1884 1885#endif /* ECORE_SP_H */ 1886 1887