1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#ifndef __BXE_H__ 28#define __BXE_H__ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: releng/10.3/sys/dev/bxe/bxe.h 296069 2016-02-25 22:07:32Z davidcs $"); 32 33#include <sys/param.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/sx.h> 39#include <sys/module.h> 40#include <sys/endian.h> 41#include <sys/types.h> 42#include <sys/malloc.h> 43#include <sys/kobj.h> 44#include <sys/bus.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49#include <sys/smp.h> 50#include <sys/bitstring.h> 51#include <sys/limits.h> 52#include <sys/queue.h> 53#include <sys/taskqueue.h> 54 55#include <net/if.h> 56#include <net/if_types.h> 57#include <net/if_arp.h> 58#include <net/ethernet.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_var.h> 62#include <net/if_vlan_var.h> 63#include <net/zlib.h> 64#include <net/bpf.h> 65 66#include <netinet/in.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/udp.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/atomic.h> 76#include <machine/resource.h> 77#include <machine/endian.h> 78#include <machine/bus.h> 79#include <machine/in_cksum.h> 80 81#include "device_if.h" 82#include "bus_if.h" 83#include "pci_if.h" 84 85#if _BYTE_ORDER == _LITTLE_ENDIAN 86#ifndef LITTLE_ENDIAN 87#define LITTLE_ENDIAN 88#endif 89#ifndef __LITTLE_ENDIAN 90#define __LITTLE_ENDIAN 91#endif 92#undef BIG_ENDIAN 93#undef __BIG_ENDIAN 94#else /* _BIG_ENDIAN */ 95#ifndef BIG_ENDIAN 96#define BIG_ENDIAN 97#endif 98#ifndef __BIG_ENDIAN 99#define __BIG_ENDIAN 100#endif 101#undef LITTLE_ENDIAN 102#undef __LITTLE_ENDIAN 103#endif 104 105#include "ecore_mfw_req.h" 106#include "ecore_fw_defs.h" 107#include "ecore_hsi.h" 108#include "ecore_reg.h" 109#include "bxe_dcb.h" 110#include "bxe_stats.h" 111 112#include "bxe_elink.h" 113 114#if __FreeBSD_version < 800054 115#if defined(__i386__) || defined(__amd64__) 116#define mb() __asm volatile("mfence;" : : : "memory") 117#define wmb() __asm volatile("sfence;" : : : "memory") 118#define rmb() __asm volatile("lfence;" : : : "memory") 119static __inline void prefetch(void *x) 120{ 121 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 122} 123#else 124#define mb() 125#define rmb() 126#define wmb() 127#define prefetch(x) 128#endif 129#endif 130 131#if __FreeBSD_version >= 1000000 132#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 133#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 134#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 135#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 136#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 137#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 138#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 139#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 140#endif 141 142#ifndef ARRAY_SIZE 143#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 144#endif 145#ifndef ARRSIZE 146#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147#endif 148#ifndef DIV_ROUND_UP 149#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 150#endif 151#ifndef roundup 152#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 153#endif 154#ifndef ilog2 155static inline 156int bxe_ilog2(int x) 157{ 158 int log = 0; 159 while (x >>= 1) log++; 160 return (log); 161} 162#define ilog2(x) bxe_ilog2(x) 163#endif 164 165#include "ecore_sp.h" 166 167#define BRCM_VENDORID 0x14e4 168#define PCI_ANY_ID (uint16_t)(~0U) 169 170struct bxe_device_type 171{ 172 uint16_t bxe_vid; 173 uint16_t bxe_did; 174 uint16_t bxe_svid; 175 uint16_t bxe_sdid; 176 char *bxe_name; 177}; 178 179#define BCM_PAGE_SHIFT 12 180#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 181#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 182#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 183 184#if BCM_PAGE_SIZE != 4096 185#error Page sizes other than 4KB are unsupported! 186#endif 187 188#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 189#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 190#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 191#else 192#define U64_LO(addr) ((uint32_t)(addr)) 193#define U64_HI(addr) (0) 194#endif 195#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 196 197#define SET_FLAG(value, mask, flag) \ 198 do { \ 199 (value) &= ~(mask); \ 200 (value) |= ((flag) << (mask##_SHIFT)); \ 201 } while (0) 202 203#define GET_FLAG(value, mask) \ 204 (((value) & (mask)) >> (mask##_SHIFT)) 205 206#define GET_FIELD(value, fname) \ 207 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 208 209#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 210#define BXE_TSO_MAX_SEGMENTS 32 211#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 212#define BXE_TSO_MAX_SEG_SIZE 4096 213 214/* dropless fc FW/HW related params */ 215#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 216#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 217 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 218 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 219#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 220#define FW_PREFETCH_CNT 16 221#define DROPLESS_FC_HEADROOM 100 222 223/******************/ 224/* RX SGE defines */ 225/******************/ 226 227#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 228#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 229#define RX_SGE_NEXT_PAGE_DESC_CNT 2 230#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 231#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 232#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 233#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 234#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 235#define RX_SGE(x) ((x) & RX_SGE_MAX) 236 237#define RX_SGE_NEXT(x) \ 238 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 239 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 240 241#define RX_SGE_MASK_ELEM_SZ 64 242#define RX_SGE_MASK_ELEM_SHIFT 6 243#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 244 245/* 246 * Creates a bitmask of all ones in less significant bits. 247 * idx - index of the most significant bit in the created mask. 248 */ 249#define RX_SGE_ONES_MASK(idx) \ 250 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 251#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 252 253/* Number of uint64_t elements in SGE mask array. */ 254#define RX_SGE_MASK_LEN \ 255 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 256#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 257#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 258 259/* 260 * dropless fc calculations for SGEs 261 * Number of required SGEs is the sum of two: 262 * 1. Number of possible opened aggregations (next packet for 263 * these aggregations will probably consume SGE immidiatelly) 264 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 265 * after placement on BD for new TPA aggregation) 266 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 267 */ 268#define NUM_SGE_REQ(sc) \ 269 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 270#define NUM_SGE_PG_REQ(sc) \ 271 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 272#define SGE_TH_LO(sc) \ 273 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 274#define SGE_TH_HI(sc) \ 275 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 276 277#define PAGES_PER_SGE_SHIFT 0 278#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 279#define SGE_PAGE_SIZE BCM_PAGE_SIZE 280#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 281#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 282#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 283#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 284 285/*****************/ 286/* TX BD defines */ 287/*****************/ 288 289#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 290#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 291#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 292#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 293#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 294#define TX_BD_MAX (TX_BD_TOTAL - 1) 295 296#define TX_BD_NEXT(x) \ 297 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 298 ((x) + 2) : ((x) + 1)) 299#define TX_BD(x) ((x) & TX_BD_MAX) 300#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 301#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 302 303/* 304 * Trigger pending transmits when the number of available BDs is greater 305 * than 1/8 of the total number of usable BDs. 306 */ 307#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 308#define BXE_TX_TIMEOUT 5 309 310/*****************/ 311/* RX BD defines */ 312/*****************/ 313 314#define RX_BD_NUM_PAGES 8 /* power of 2 */ 315#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 316#define RX_BD_NEXT_PAGE_DESC_CNT 2 317#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 318#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 319#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 320#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 321#define RX_BD_MAX (RX_BD_TOTAL - 1) 322 323#define RX_BD_NEXT(x) \ 324 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 325 ((x) + 3) : ((x) + 1)) 326#define RX_BD(x) ((x) & RX_BD_MAX) 327#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 328#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 329 330/* 331 * dropless fc calculations for BDs 332 * Number of BDs should be as number of buffers in BRB: 333 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 334 * "next" elements on each page 335 */ 336#define NUM_BD_REQ(sc) \ 337 BRB_SIZE(sc) 338#define NUM_BD_PG_REQ(sc) \ 339 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 340#define BD_TH_LO(sc) \ 341 (NUM_BD_REQ(sc) + \ 342 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 343 FW_DROP_LEVEL(sc)) 344#define BD_TH_HI(sc) \ 345 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 346#define MIN_RX_AVAIL(sc) \ 347 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 348#define MIN_RX_SIZE_TPA_HW(sc) \ 349 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 350 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 351#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 352#define MIN_RX_SIZE_TPA(sc) \ 353 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 354#define MIN_RX_SIZE_NONTPA(sc) \ 355 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 356 357/***************/ 358/* RCQ defines */ 359/***************/ 360 361/* 362 * As long as CQE is X times bigger than BD entry we have to allocate X times 363 * more pages for CQ ring in order to keep it balanced with BD ring 364 */ 365#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 366 sizeof(struct eth_rx_bd)) 367#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 368#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 369#define RCQ_NEXT_PAGE_DESC_CNT 1 370#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 371#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 372#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 373#define RCQ_MAX (RCQ_TOTAL - 1) 374 375#define RCQ_NEXT(x) \ 376 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 377 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 378#define RCQ(x) ((x) & RCQ_MAX) 379#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 380#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 381 382/* 383 * dropless fc calculations for RCQs 384 * Number of RCQs should be as number of buffers in BRB: 385 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 386 * "next" elements on each page 387 */ 388#define NUM_RCQ_REQ(sc) \ 389 BRB_SIZE(sc) 390#define NUM_RCQ_PG_REQ(sc) \ 391 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 392#define RCQ_TH_LO(sc) \ 393 (NUM_RCQ_REQ(sc) + \ 394 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 395 FW_DROP_LEVEL(sc)) 396#define RCQ_TH_HI(sc) \ 397 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 398 399/* This is needed for determening of last_max */ 400#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 401 402#define __SGE_MASK_SET_BIT(el, bit) \ 403 do { \ 404 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 405 } while (0) 406 407#define __SGE_MASK_CLEAR_BIT(el, bit) \ 408 do { \ 409 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 410 } while (0) 411 412#define SGE_MASK_SET_BIT(fp, idx) \ 413 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 414 ((idx) & RX_SGE_MASK_ELEM_MASK)) 415 416#define SGE_MASK_CLEAR_BIT(fp, idx) \ 417 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 418 ((idx) & RX_SGE_MASK_ELEM_MASK)) 419 420/* Load / Unload modes */ 421#define LOAD_NORMAL 0 422#define LOAD_OPEN 1 423#define LOAD_DIAG 2 424#define LOAD_LOOPBACK_EXT 3 425#define UNLOAD_NORMAL 0 426#define UNLOAD_CLOSE 1 427#define UNLOAD_RECOVERY 2 428 429/* Some constants... */ 430//#define MAX_PATH_NUM 2 431//#define E2_MAX_NUM_OF_VFS 64 432//#define E1H_FUNC_MAX 8 433//#define E2_FUNC_MAX 4 /* per path */ 434#define MAX_VNIC_NUM 4 435#define MAX_FUNC_NUM 8 /* common to all chips */ 436//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 437#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 438#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 439 440#define ILT_NUM_PAGE_ENTRIES 3072 441/* 442 * 57710/11 we use whole table since we have 8 functions. 443 * 57712 we have only 4 functions, but use same size per func, so only half 444 * of the table is used. 445 */ 446#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 447#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 448/* 449 * the phys address is shifted right 12 bits and has an added 450 * 1=valid bit added to the 53rd bit 451 * then since this is a wide register(TM) 452 * we split it into two 32 bit writes 453 */ 454#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 455#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 456 457/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 458#define ETH_HLEN 14 459#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 460#define ETH_MIN_PACKET_SIZE 60 461#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 462#define ETH_MAX_JUMBO_PACKET_SIZE 9600 463/* TCP with Timestamp Option (32) + IPv6 (40) */ 464#define ETH_MAX_TPA_HEADER_SIZE 72 465 466/* max supported alignment is 256 (8 shift) */ 467//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 468#define BXE_RX_ALIGN_SHIFT 8 469/* FW uses 2 cache lines alignment for start packet and size */ 470#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 471#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 472 473#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 474 475struct bxe_bar { 476 struct resource *resource; 477 int rid; 478 bus_space_tag_t tag; 479 bus_space_handle_t handle; 480 vm_offset_t kva; 481}; 482 483struct bxe_intr { 484 struct resource *resource; 485 int rid; 486 void *tag; 487}; 488 489/* Used to manage DMA allocations. */ 490struct bxe_dma { 491 struct bxe_softc *sc; 492 bus_addr_t paddr; 493 void *vaddr; 494 bus_dma_tag_t tag; 495 bus_dmamap_t map; 496 bus_dma_segment_t seg; 497 bus_size_t size; 498 int nseg; 499 char msg[32]; 500}; 501 502/* attn group wiring */ 503#define MAX_DYNAMIC_ATTN_GRPS 8 504 505struct attn_route { 506 uint32_t sig[5]; 507}; 508 509struct iro { 510 uint32_t base; 511 uint16_t m1; 512 uint16_t m2; 513 uint16_t m3; 514 uint16_t size; 515}; 516 517union bxe_host_hc_status_block { 518 /* pointer to fp status block e2 */ 519 struct host_hc_status_block_e2 *e2_sb; 520 /* pointer to fp status block e1x */ 521 struct host_hc_status_block_e1x *e1x_sb; 522}; 523 524union bxe_db_prod { 525 struct doorbell_set_prod data; 526 uint32_t raw; 527}; 528 529struct bxe_sw_tx_bd { 530 struct mbuf *m; 531 bus_dmamap_t m_map; 532 uint16_t first_bd; 533 uint8_t flags; 534/* set on the first BD descriptor when there is a split BD */ 535#define BXE_TSO_SPLIT_BD (1 << 0) 536}; 537 538struct bxe_sw_rx_bd { 539 struct mbuf *m; 540 bus_dmamap_t m_map; 541}; 542 543struct bxe_sw_tpa_info { 544 struct bxe_sw_rx_bd bd; 545 bus_dma_segment_t seg; 546 uint8_t state; 547#define BXE_TPA_STATE_START 1 548#define BXE_TPA_STATE_STOP 2 549 uint8_t placement_offset; 550 uint16_t parsing_flags; 551 uint16_t vlan_tag; 552 uint16_t len_on_bd; 553}; 554 555/* 556 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 557 * instances of the fastpath structure when using multiple queues. 558 */ 559struct bxe_fastpath { 560 /* pointer back to parent structure */ 561 struct bxe_softc *sc; 562 563 struct mtx tx_mtx; 564 char tx_mtx_name[32]; 565 struct mtx rx_mtx; 566 char rx_mtx_name[32]; 567 568#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 569#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 570#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 571#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 572 573#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 574#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 575#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 576 577 /* status block */ 578 struct bxe_dma sb_dma; 579 union bxe_host_hc_status_block status_block; 580 581 /* transmit chain (tx bds) */ 582 struct bxe_dma tx_dma; 583 union eth_tx_bd_types *tx_chain; 584 585 /* receive chain (rx bds) */ 586 struct bxe_dma rx_dma; 587 struct eth_rx_bd *rx_chain; 588 589 /* receive completion queue chain (rcq bds) */ 590 struct bxe_dma rcq_dma; 591 union eth_rx_cqe *rcq_chain; 592 593 /* receive scatter/gather entry chain (for TPA) */ 594 struct bxe_dma rx_sge_dma; 595 struct eth_rx_sge *rx_sge_chain; 596 597 /* tx mbufs */ 598 bus_dma_tag_t tx_mbuf_tag; 599 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 600 601 /* rx mbufs */ 602 bus_dma_tag_t rx_mbuf_tag; 603 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 604 bus_dmamap_t rx_mbuf_spare_map; 605 606 /* rx sge mbufs */ 607 bus_dma_tag_t rx_sge_mbuf_tag; 608 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 609 bus_dmamap_t rx_sge_mbuf_spare_map; 610 611 /* rx tpa mbufs (use the larger size for TPA queue length) */ 612 int tpa_enable; /* disabled per fastpath upon error */ 613 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 614 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 615 uint64_t rx_tpa_queue_used; 616 617 uint16_t *sb_index_values; 618 uint16_t *sb_running_index; 619 uint32_t ustorm_rx_prods_offset; 620 621 uint8_t igu_sb_id; /* status block number in HW */ 622 uint8_t fw_sb_id; /* status block number in FW */ 623 624 uint32_t rx_buf_size; 625 int mbuf_alloc_size; 626 627 int state; 628#define BXE_FP_STATE_CLOSED 0x01 629#define BXE_FP_STATE_IRQ 0x02 630#define BXE_FP_STATE_OPENING 0x04 631#define BXE_FP_STATE_OPEN 0x08 632#define BXE_FP_STATE_HALTING 0x10 633#define BXE_FP_STATE_HALTED 0x20 634 635 /* reference back to this fastpath queue number */ 636 uint8_t index; /* this is also the 'cid' */ 637#define FP_IDX(fp) (fp->index) 638 639 /* interrupt taskqueue (fast) */ 640 struct task tq_task; 641 struct taskqueue *tq; 642 char tq_name[32]; 643 644 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 645 uint8_t cl_id; 646#define FP_CL_ID(fp) (fp->cl_id) 647 uint8_t cl_qzone_id; 648 649 uint16_t fp_hc_idx; 650 651 /* driver copy of the receive buffer descriptor prod/cons indices */ 652 uint16_t rx_bd_prod; 653 uint16_t rx_bd_cons; 654 655 /* driver copy of the receive completion queue prod/cons indices */ 656 uint16_t rx_cq_prod; 657 uint16_t rx_cq_cons; 658 659 union bxe_db_prod tx_db; 660 661 /* Transmit packet producer index (used in eth_tx_bd). */ 662 uint16_t tx_pkt_prod; 663 uint16_t tx_pkt_cons; 664 665 /* Transmit buffer descriptor producer index. */ 666 uint16_t tx_bd_prod; 667 uint16_t tx_bd_cons; 668 669 uint64_t sge_mask[RX_SGE_MASK_LEN]; 670 uint16_t rx_sge_prod; 671 672 struct tstorm_per_queue_stats old_tclient; 673 struct ustorm_per_queue_stats old_uclient; 674 struct xstorm_per_queue_stats old_xclient; 675 struct bxe_eth_q_stats eth_q_stats; 676 struct bxe_eth_q_stats_old eth_q_stats_old; 677 678 /* Pointer to the receive consumer in the status block */ 679 uint16_t *rx_cq_cons_sb; 680 681 /* Pointer to the transmit consumer in the status block */ 682 uint16_t *tx_cons_sb; 683 684 /* transmit timeout until chip reset */ 685 int watchdog_timer; 686 687 /* Free/used buffer descriptor counters. */ 688 //uint16_t used_tx_bd; 689 690 /* Last maximal completed SGE */ 691 uint16_t last_max_sge; 692 693 //uint16_t rx_sge_free_idx; 694 695 //uint8_t segs; 696 697#if __FreeBSD_version >= 800000 698#define BXE_BR_SIZE 4096 699 struct buf_ring *tx_br; 700#endif 701}; /* struct bxe_fastpath */ 702 703/* sriov XXX */ 704#define BXE_MAX_NUM_OF_VFS 64 705#define BXE_VF_CID_WND 0 706#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 707#define BXE_CLIENTS_PER_VF 1 708#define BXE_FIRST_VF_CID 256 709#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 710#define BXE_VF_ID_INVALID 0xFF 711#define IS_SRIOV(sc) 0 712 713#define GET_NUM_VFS_PER_PATH(sc) 0 714#define GET_NUM_VFS_PER_PF(sc) 0 715 716/* maximum number of fast-path interrupt contexts */ 717#define FP_SB_MAX_E1x 16 718#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 719 720union cdu_context { 721 struct eth_context eth; 722 char pad[1024]; 723}; 724 725/* CDU host DB constants */ 726#define CDU_ILT_PAGE_SZ_HW 2 727#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 728#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 729 730#define CNIC_ISCSI_CID_MAX 256 731#define CNIC_FCOE_CID_MAX 2048 732#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 733#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 734 735#define QM_ILT_PAGE_SZ_HW 0 736#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 737#define QM_CID_ROUND 1024 738 739/* TM (timers) host DB constants */ 740#define TM_ILT_PAGE_SZ_HW 0 741#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 742/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 743#define TM_CONN_NUM 1024 744#define TM_ILT_SZ (8 * TM_CONN_NUM) 745#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 746 747/* SRC (Searcher) host DB constants */ 748#define SRC_ILT_PAGE_SZ_HW 0 749#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 750#define SRC_HASH_BITS 10 751#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 752#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 753#define SRC_T2_SZ SRC_ILT_SZ 754#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 755 756struct hw_context { 757 struct bxe_dma vcxt_dma; 758 union cdu_context *vcxt; 759 //bus_addr_t cxt_mapping; 760 size_t size; 761}; 762 763#define SM_RX_ID 0 764#define SM_TX_ID 1 765 766/* defines for multiple tx priority indices */ 767#define FIRST_TX_ONLY_COS_INDEX 1 768#define FIRST_TX_COS_INDEX 0 769 770#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 771 772#define HC_INDEX_ETH_RX_CQ_CONS 1 773#define HC_INDEX_OOO_TX_CQ_CONS 4 774#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 775#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 776#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 777#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 778 779/* congestion management fairness mode */ 780#define CMNG_FNS_NONE 0 781#define CMNG_FNS_MINMAX 1 782 783/* CMNG constants, as derived from system spec calculations */ 784/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 785#define DEF_MIN_RATE 100 786/* resolution of the rate shaping timer - 400 usec */ 787#define RS_PERIODIC_TIMEOUT_USEC 400 788/* number of bytes in single QM arbitration cycle - 789 * coefficient for calculating the fairness timer */ 790#define QM_ARB_BYTES 160000 791/* resolution of Min algorithm 1:100 */ 792#define MIN_RES 100 793/* how many bytes above threshold for the minimal credit of Min algorithm*/ 794#define MIN_ABOVE_THRESH 32768 795/* fairness algorithm integration time coefficient - 796 * for calculating the actual Tfair */ 797#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 798/* memory of fairness algorithm - 2 cycles */ 799#define FAIR_MEM 2 800 801#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 802#define HC_SEG_ACCESS_ATTN 4 803#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 804 805/* 806 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 807 * control by the number of fast-path status blocks supported by the 808 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 809 * status block represents an independent interrupts context that can 810 * serve a regular L2 networking queue. However special L2 queues such 811 * as the FCoE queue do not require a FP-SB and other components like 812 * the CNIC may consume FP-SB reducing the number of possible L2 queues 813 * 814 * If the maximum number of FP-SB available is X then: 815 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 816 * regular L2 queues is Y=X-1 817 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 818 * c. If the FCoE L2 queue is supported the actual number of L2 queues 819 * is Y+1 820 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 821 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 822 * FP interrupt context for the CNIC). 823 * e. The number of HW context (CID count) is always X or X+1 if FCoE 824 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 825 * 826 * So this is quite simple for now as no ULPs are supported yet. :-) 827 */ 828#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 829#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 830#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 831#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 832 833#define FOR_EACH_QUEUE(sc, var) \ 834 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 835 836#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 837 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 838 839#define FOR_EACH_ETH_QUEUE(sc, var) \ 840 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 841 842#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 843 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 844 845#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 846 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 847 848#define FOR_EACH_CNIC_QUEUE(sc, var) \ 849 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 850 (var) < BXE_NUM_QUEUES(sc); \ 851 (var)++) 852 853enum { 854 OOO_IDX_OFFSET, 855 FCOE_IDX_OFFSET, 856 FWD_IDX_OFFSET, 857}; 858 859#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 860#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 861#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 862#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 863#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 864#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 865 866#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 867#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 868#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 869#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 870#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 871 872#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 873#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 874#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 875#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 876#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 877#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 878 879#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 880#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 881#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 882#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 883#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 884#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 885#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 886 887enum { 888 BXE_PORT_QUERY_IDX, 889 BXE_PF_QUERY_IDX, 890 BXE_FCOE_QUERY_IDX, 891 BXE_FIRST_QUEUE_QUERY_IDX, 892}; 893 894struct bxe_fw_stats_req { 895 struct stats_query_header hdr; 896 struct stats_query_entry query[FP_SB_MAX_E1x + 897 BXE_FIRST_QUEUE_QUERY_IDX]; 898}; 899 900struct bxe_fw_stats_data { 901 struct stats_counter storm_counters; 902 struct per_port_stats port; 903 struct per_pf_stats pf; 904 //struct fcoe_statistics_params fcoe; 905 struct per_queue_stats queue_stats[1]; 906}; 907 908/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 909#define BXE_IGU_STAS_MSG_VF_CNT 64 910#define BXE_IGU_STAS_MSG_PF_CNT 4 911 912#define MAX_DMAE_C 8 913 914/* 915 * For the main interface up/down code paths, a not-so-fine-grained CORE 916 * mutex lock is used. Inside this code are various calls to kernel routines 917 * that can cause a sleep to occur. Namely memory allocations and taskqueue 918 * handling. If using an MTX lock we are *not* allowed to sleep but we can 919 * with an SX lock. This define forces the CORE lock to use and SX lock. 920 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 921 * path can cause problems since it's called by a non-sleepable thread. To 922 * alleviate a potential sleep, any IOCTL processing that results in the 923 * chip/interface being started/stopped/reinitialized, the actual work is 924 * offloaded to a taskqueue. 925 */ 926#define BXE_CORE_LOCK_SX 927 928/* 929 * This is the slowpath data structure. It is mapped into non-paged memory 930 * so that the hardware can access it's contents directly and must be page 931 * aligned. 932 */ 933struct bxe_slowpath { 934 935 /* used by the DMAE command executer */ 936 struct dmae_command dmae[MAX_DMAE_C]; 937 938 /* statistics completion */ 939 uint32_t stats_comp; 940 941 /* firmware defined statistics blocks */ 942 union mac_stats mac_stats; 943 struct nig_stats nig_stats; 944 struct host_port_stats port_stats; 945 struct host_func_stats func_stats; 946 //struct host_func_stats func_stats_base; 947 948 /* DMAE completion value and data source/sink */ 949 uint32_t wb_comp; 950 uint32_t wb_data[4]; 951 952 union { 953 struct mac_configuration_cmd e1x; 954 struct eth_classify_rules_ramrod_data e2; 955 } mac_rdata; 956 957 union { 958 struct tstorm_eth_mac_filter_config e1x; 959 struct eth_filter_rules_ramrod_data e2; 960 } rx_mode_rdata; 961 962 struct eth_rss_update_ramrod_data rss_rdata; 963 964 union { 965 struct mac_configuration_cmd e1; 966 struct eth_multicast_rules_ramrod_data e2; 967 } mcast_rdata; 968 969 union { 970 struct function_start_data func_start; 971 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 972 } func_rdata; 973 974 /* Queue State related ramrods */ 975 union { 976 struct client_init_ramrod_data init_data; 977 struct client_update_ramrod_data update_data; 978 } q_rdata; 979 980 /* 981 * AFEX ramrod can not be a part of func_rdata union because these 982 * events might arrive in parallel to other events from func_rdata. 983 * If they were defined in the same union the data can get corrupted. 984 */ 985 struct afex_vif_list_ramrod_data func_afex_rdata; 986 987 union drv_info_to_mcp drv_info_to_mcp; 988}; /* struct bxe_slowpath */ 989 990/* 991 * Port specifc data structure. 992 */ 993struct bxe_port { 994 /* 995 * Port Management Function (for 57711E only). 996 * When this field is set the driver instance is 997 * responsible for managing port specifc 998 * configurations such as handling link attentions. 999 */ 1000 uint32_t pmf; 1001 1002 /* Ethernet maximum transmission unit. */ 1003 uint16_t ether_mtu; 1004 1005 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1006 1007 uint32_t ext_phy_config; 1008 1009 /* Port feature config.*/ 1010 uint32_t config; 1011 1012 /* Defines the features supported by the PHY. */ 1013 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1014 1015 /* Defines the features advertised by the PHY. */ 1016 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1017#define ADVERTISED_10baseT_Half (1 << 1) 1018#define ADVERTISED_10baseT_Full (1 << 2) 1019#define ADVERTISED_100baseT_Half (1 << 3) 1020#define ADVERTISED_100baseT_Full (1 << 4) 1021#define ADVERTISED_1000baseT_Half (1 << 5) 1022#define ADVERTISED_1000baseT_Full (1 << 6) 1023#define ADVERTISED_TP (1 << 7) 1024#define ADVERTISED_FIBRE (1 << 8) 1025#define ADVERTISED_Autoneg (1 << 9) 1026#define ADVERTISED_Asym_Pause (1 << 10) 1027#define ADVERTISED_Pause (1 << 11) 1028#define ADVERTISED_2500baseX_Full (1 << 15) 1029#define ADVERTISED_10000baseT_Full (1 << 16) 1030 1031 uint32_t phy_addr; 1032 1033 /* Used to synchronize phy accesses. */ 1034 struct mtx phy_mtx; 1035 char phy_mtx_name[32]; 1036 1037#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1038#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1039#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1040 1041 /* 1042 * MCP scratchpad address for port specific statistics. 1043 * The device is responsible for writing statistcss 1044 * back to the MCP for use with management firmware such 1045 * as UMP/NC-SI. 1046 */ 1047 uint32_t port_stx; 1048 1049 struct nig_stats old_nig_stats; 1050}; /* struct bxe_port */ 1051 1052struct bxe_mf_info { 1053 uint32_t mf_config[E1HVN_MAX]; 1054 1055 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1056 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1057 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1058 1059#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1060#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1061#define VNICS_PER_PATH(sc) \ 1062 ((sc)->devinfo.mf_info.vnics_per_port * \ 1063 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1064 1065 uint8_t min_bw[MAX_VNIC_NUM]; 1066 uint8_t max_bw[MAX_VNIC_NUM]; 1067 1068 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1069#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1070#define INVALID_VIF_ID 0xFFFF 1071#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1072#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1073 1074 uint16_t default_vlan; 1075#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1076 1077 uint8_t niv_allowed_priorities; 1078#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1079 1080 uint8_t niv_default_cos; 1081#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1082 1083 uint8_t niv_mba_enabled; 1084 1085 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1086#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1087 int afex_def_vlan_tag; 1088 uint32_t pending_max; 1089 1090 uint16_t flags; 1091#define MF_INFO_VALID_MAC 0x0001 1092 1093 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1094#define IS_MF(sc) \ 1095 (IS_MULTI_VNIC(sc) && \ 1096 ((sc)->devinfo.mf_info.mf_mode != 0)) 1097#define IS_MF_SD(sc) \ 1098 (IS_MULTI_VNIC(sc) && \ 1099 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1100#define IS_MF_SI(sc) \ 1101 (IS_MULTI_VNIC(sc) && \ 1102 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1103#define IS_MF_AFEX(sc) \ 1104 (IS_MULTI_VNIC(sc) && \ 1105 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1106#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1107#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1108#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1109 1110 uint32_t mf_protos_supported; 1111 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1112 #define MF_PROTO_SUPPORT_ISCSI 0x2 1113 #define MF_PROTO_SUPPORT_FCOE 0x4 1114}; /* struct bxe_mf_info */ 1115 1116/* Device information data structure. */ 1117struct bxe_devinfo { 1118 /* PCIe info */ 1119 uint16_t vendor_id; 1120 uint16_t device_id; 1121 uint16_t subvendor_id; 1122 uint16_t subdevice_id; 1123 1124 /* 1125 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1126 * C = Chip Number (bits 16-31) 1127 * R = Chip Revision (bits 12-15) 1128 * M = Chip Metal (bits 4-11) 1129 * B = Chip Bond ID (bits 0-3) 1130 */ 1131 uint32_t chip_id; 1132#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1133#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1134/* device ids */ 1135#define CHIP_NUM_57710 0x164e 1136#define CHIP_NUM_57711 0x164f 1137#define CHIP_NUM_57711E 0x1650 1138#define CHIP_NUM_57712 0x1662 1139#define CHIP_NUM_57712_MF 0x1663 1140#define CHIP_NUM_57712_VF 0x166f 1141#define CHIP_NUM_57800 0x168a 1142#define CHIP_NUM_57800_MF 0x16a5 1143#define CHIP_NUM_57800_VF 0x16a9 1144#define CHIP_NUM_57810 0x168e 1145#define CHIP_NUM_57810_MF 0x16ae 1146#define CHIP_NUM_57810_VF 0x16af 1147#define CHIP_NUM_57811 0x163d 1148#define CHIP_NUM_57811_MF 0x163e 1149#define CHIP_NUM_57811_VF 0x163f 1150#define CHIP_NUM_57840_OBS 0x168d 1151#define CHIP_NUM_57840_OBS_MF 0x16ab 1152#define CHIP_NUM_57840_4_10 0x16a1 1153#define CHIP_NUM_57840_2_20 0x16a2 1154#define CHIP_NUM_57840_MF 0x16a4 1155#define CHIP_NUM_57840_VF 0x16ad 1156 1157#define CHIP_REV_SHIFT 12 1158#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1159#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1160 1161#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1162#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1163#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1164 1165#define CHIP_REV_IS_SLOW(sc) \ 1166 (CHIP_REV(sc) > 0x00005000) 1167#define CHIP_REV_IS_FPGA(sc) \ 1168 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1169#define CHIP_REV_IS_EMUL(sc) \ 1170 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1171#define CHIP_REV_IS_ASIC(sc) \ 1172 (!CHIP_REV_IS_SLOW(sc)) 1173 1174#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1175#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1176 1177#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1178#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1179#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1180#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1181#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1182 (CHIP_IS_57711E(sc))) 1183#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1184 CHIP_IS_E1H((sc))) 1185 1186#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1187#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1188#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1189#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1190 CHIP_IS_57712_MF(sc)) 1191 1192#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1193#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1194#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1195#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1196#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1197#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1198#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1199#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1200#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1201#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1202 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1203 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1204#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1205 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1206#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1207 1208#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1209 CHIP_IS_57800_MF(sc) || \ 1210 CHIP_IS_57800_VF(sc) || \ 1211 CHIP_IS_57810(sc) || \ 1212 CHIP_IS_57810_MF(sc) || \ 1213 CHIP_IS_57810_VF(sc) || \ 1214 CHIP_IS_57811(sc) || \ 1215 CHIP_IS_57811_MF(sc) || \ 1216 CHIP_IS_57811_VF(sc) || \ 1217 CHIP_IS_57840(sc) || \ 1218 CHIP_IS_57840_MF(sc) || \ 1219 CHIP_IS_57840_VF(sc)) 1220#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1221 (CHIP_REV(sc) == CHIP_REV_Ax)) 1222#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1223 (CHIP_REV(sc) == CHIP_REV_Bx)) 1224 1225#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1226#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1227 CHIP_IS_E3(sc)) 1228 1229#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1230 CHIP_IS_57712_MF(sc) || \ 1231 CHIP_IS_E3(sc)) 1232 1233#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1234 CHIP_IS_57800_VF(sc) || \ 1235 CHIP_IS_57810_VF(sc) || \ 1236 CHIP_IS_57840_VF(sc)) 1237#define IS_PF(sc) (!IS_VF(sc)) 1238 1239/* 1240 * This define is used in two main places: 1241 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1242 * to nic-only mode or to offload mode. Offload mode is configured if either 1243 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1244 * already registered for this port (which means that the user wants storage 1245 * services). 1246 * 2. During cnic-related load, to know if offload mode is already configured 1247 * in the HW or needs to be configrued. Since the transition from nic-mode to 1248 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1249 * in ports on which storage services where never requested. 1250 */ 1251#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1252 1253 uint8_t chip_port_mode; 1254#define CHIP_4_PORT_MODE 0x0 1255#define CHIP_2_PORT_MODE 0x1 1256#define CHIP_PORT_MODE_NONE 0x2 1257#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1258#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1259 1260 uint8_t int_block; 1261#define INT_BLOCK_HC 0 1262#define INT_BLOCK_IGU 1 1263#define INT_BLOCK_MODE_NORMAL 0 1264#define INT_BLOCK_MODE_BW_COMP 2 1265#define CHIP_INT_MODE_IS_NBC(sc) \ 1266 (!CHIP_IS_E1x(sc) && \ 1267 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1268#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1269 1270 uint32_t shmem_base; 1271 uint32_t shmem2_base; 1272 uint32_t bc_ver; 1273 char bc_ver_str[32]; 1274 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1275 struct bxe_mf_info mf_info; 1276 1277 int flash_size; 1278#define NVRAM_1MB_SIZE 0x20000 1279#define NVRAM_TIMEOUT_COUNT 30000 1280#define NVRAM_PAGE_SIZE 256 1281 1282 /* PCIe capability information */ 1283 uint32_t pcie_cap_flags; 1284#define BXE_PM_CAPABLE_FLAG 0x00000001 1285#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1286#define BXE_MSI_CAPABLE_FLAG 0x00000004 1287#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1288 uint16_t pcie_pm_cap_reg; 1289 uint16_t pcie_pcie_cap_reg; 1290 //uint16_t pcie_devctl; 1291 uint16_t pcie_link_width; 1292 uint16_t pcie_link_speed; 1293 uint16_t pcie_msi_cap_reg; 1294 uint16_t pcie_msix_cap_reg; 1295 1296 /* device configuration read from bootcode shared memory */ 1297 uint32_t hw_config; 1298 uint32_t hw_config2; 1299}; /* struct bxe_devinfo */ 1300 1301struct bxe_sp_objs { 1302 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1303 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1304}; /* struct bxe_sp_objs */ 1305 1306/* 1307 * Data that will be used to create a link report message. We will keep the 1308 * data used for the last link report in order to prevent reporting the same 1309 * link parameters twice. 1310 */ 1311struct bxe_link_report_data { 1312 uint16_t line_speed; /* Effective line speed */ 1313 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1314}; 1315enum { 1316 BXE_LINK_REPORT_FULL_DUPLEX, 1317 BXE_LINK_REPORT_LINK_DOWN, 1318 BXE_LINK_REPORT_RX_FC_ON, 1319 BXE_LINK_REPORT_TX_FC_ON 1320}; 1321 1322/* Top level device private data structure. */ 1323struct bxe_softc { 1324 /* 1325 * First entry must be a pointer to the BSD ifnet struct which 1326 * has a first element of 'void *if_softc' (which is us). 1327 */ 1328 struct ifnet *ifnet; 1329 struct ifmedia ifmedia; /* network interface media structure */ 1330 int media; 1331 1332 int state; /* device state */ 1333#define BXE_STATE_CLOSED 0x0000 1334#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1335#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1336#define BXE_STATE_OPEN 0x3000 1337#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1338#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1339#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1340#define BXE_STATE_DISABLED 0xD000 1341#define BXE_STATE_DIAG 0xE000 1342#define BXE_STATE_ERROR 0xF000 1343 1344 int flags; 1345#define BXE_ONE_PORT_FLAG 0x00000001 1346#define BXE_NO_ISCSI 0x00000002 1347#define BXE_NO_FCOE 0x00000004 1348#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1349//#define BXE_NO_WOL_FLAG 0x00000008 1350//#define BXE_USING_DAC_FLAG 0x00000010 1351//#define BXE_USING_MSIX_FLAG 0x00000020 1352//#define BXE_USING_MSI_FLAG 0x00000040 1353//#define BXE_DISABLE_MSI_FLAG 0x00000080 1354#define BXE_NO_MCP_FLAG 0x00000200 1355#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1356//#define BXE_SAFC_TX_FLAG 0x00000400 1357#define BXE_MF_FUNC_DIS 0x00000800 1358#define BXE_TX_SWITCHING 0x00001000 1359#define BXE_NO_PULSE 0x00002000 1360 1361 unsigned long debug; /* per-instance debug logging config */ 1362 1363#define MAX_BARS 5 1364 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1365 1366 uint16_t doorbell_size; 1367 1368 /* periodic timer callout */ 1369#define PERIODIC_STOP 0 1370#define PERIODIC_GO 1 1371 volatile unsigned long periodic_flags; 1372 struct callout periodic_callout; 1373 1374 /* chip start/stop/reset taskqueue */ 1375#define CHIP_TQ_NONE 0 1376#define CHIP_TQ_START 1 1377#define CHIP_TQ_STOP 2 1378#define CHIP_TQ_REINIT 3 1379 volatile unsigned long chip_tq_flags; 1380 struct task chip_tq_task; 1381 struct taskqueue *chip_tq; 1382 char chip_tq_name[32]; 1383 1384 /* slowpath interrupt taskqueue */ 1385 struct task sp_tq_task; 1386 struct taskqueue *sp_tq; 1387 char sp_tq_name[32]; 1388 1389 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1390 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1391 1392 device_t dev; /* parent device handle */ 1393 uint8_t unit; /* driver instance number */ 1394 1395 int pcie_bus; /* PCIe bus number */ 1396 int pcie_device; /* PCIe device/slot number */ 1397 int pcie_func; /* PCIe function number */ 1398 1399 uint8_t pfunc_rel; /* function relative */ 1400 uint8_t pfunc_abs; /* function absolute */ 1401 uint8_t path_id; /* function absolute */ 1402#define SC_PATH(sc) (sc->path_id) 1403#define SC_PORT(sc) (sc->pfunc_rel & 1) 1404#define SC_FUNC(sc) (sc->pfunc_rel) 1405#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1406#define SC_VN(sc) (sc->pfunc_rel >> 1) 1407#define SC_L_ID(sc) (SC_VN(sc) << 2) 1408#define PORT_ID(sc) SC_PORT(sc) 1409#define PATH_ID(sc) SC_PATH(sc) 1410#define VNIC_ID(sc) SC_VN(sc) 1411#define FUNC_ID(sc) SC_FUNC(sc) 1412#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1413#define SC_FW_MB_IDX_VN(sc, vn) \ 1414 (SC_PORT(sc) + (vn) * \ 1415 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1416#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1417 1418 int if_capen; /* enabled interface capabilities */ 1419 1420 struct bxe_devinfo devinfo; 1421 char fw_ver_str[32]; 1422 char mf_mode_str[32]; 1423 char pci_link_str[32]; 1424 1425 const struct iro *iro_array; 1426 1427#ifdef BXE_CORE_LOCK_SX 1428 struct sx core_sx; 1429 char core_sx_name[32]; 1430#else 1431 struct mtx core_mtx; 1432 char core_mtx_name[32]; 1433#endif 1434 struct mtx sp_mtx; 1435 char sp_mtx_name[32]; 1436 struct mtx dmae_mtx; 1437 char dmae_mtx_name[32]; 1438 struct mtx fwmb_mtx; 1439 char fwmb_mtx_name[32]; 1440 struct mtx print_mtx; 1441 char print_mtx_name[32]; 1442 struct mtx stats_mtx; 1443 char stats_mtx_name[32]; 1444 struct mtx mcast_mtx; 1445 char mcast_mtx_name[32]; 1446 1447#ifdef BXE_CORE_LOCK_SX 1448#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1449#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1450#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1451#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1452#else 1453#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1454#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1455#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1456#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1457#endif 1458 1459#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1460#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1461#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1462 1463#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1464#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1465#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1466 1467#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1468#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1469#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1470 1471#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1472#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1473#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1474 1475#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1476#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1477#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1478 1479#if __FreeBSD_version < 800000 1480#define BXE_MCAST_LOCK(sc) \ 1481 do { \ 1482 mtx_lock(&sc->mcast_mtx); \ 1483 IF_ADDR_LOCK(sc->ifnet); \ 1484 } while (0) 1485#define BXE_MCAST_UNLOCK(sc) \ 1486 do { \ 1487 IF_ADDR_UNLOCK(sc->ifnet); \ 1488 mtx_unlock(&sc->mcast_mtx); \ 1489 } while (0) 1490#else 1491#define BXE_MCAST_LOCK(sc) \ 1492 do { \ 1493 mtx_lock(&sc->mcast_mtx); \ 1494 if_maddr_rlock(sc->ifnet); \ 1495 } while (0) 1496#define BXE_MCAST_UNLOCK(sc) \ 1497 do { \ 1498 if_maddr_runlock(sc->ifnet); \ 1499 mtx_unlock(&sc->mcast_mtx); \ 1500 } while (0) 1501#endif 1502#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1503 1504 int dmae_ready; 1505#define DMAE_READY(sc) (sc->dmae_ready) 1506 1507 struct ecore_credit_pool_obj vlans_pool; 1508 struct ecore_credit_pool_obj macs_pool; 1509 struct ecore_rx_mode_obj rx_mode_obj; 1510 struct ecore_mcast_obj mcast_obj; 1511 struct ecore_rss_config_obj rss_conf_obj; 1512 struct ecore_func_sp_obj func_obj; 1513 1514 uint16_t fw_seq; 1515 uint16_t fw_drv_pulse_wr_seq; 1516 uint32_t func_stx; 1517 1518 struct elink_params link_params; 1519 struct elink_vars link_vars; 1520 uint32_t link_cnt; 1521 struct bxe_link_report_data last_reported_link; 1522 char mac_addr_str[32]; 1523 1524 int last_reported_link_state; 1525 1526 int tx_ring_size; 1527 int rx_ring_size; 1528 int wol; 1529 1530 int is_leader; 1531 int recovery_state; 1532#define BXE_RECOVERY_DONE 1 1533#define BXE_RECOVERY_INIT 2 1534#define BXE_RECOVERY_WAIT 3 1535#define BXE_RECOVERY_FAILED 4 1536#define BXE_RECOVERY_NIC_LOADING 5 1537 1538 uint32_t rx_mode; 1539#define BXE_RX_MODE_NONE 0 1540#define BXE_RX_MODE_NORMAL 1 1541#define BXE_RX_MODE_ALLMULTI 2 1542#define BXE_RX_MODE_PROMISC 3 1543#define BXE_MAX_MULTICAST 64 1544 1545 struct bxe_port port; 1546 1547 struct cmng_init cmng; 1548 1549 /* user configs */ 1550 int num_queues; 1551 int max_rx_bufs; 1552 int hc_rx_ticks; 1553 int hc_tx_ticks; 1554 int rx_budget; 1555 int max_aggregation_size; 1556 int mrrs; 1557 int autogreeen; 1558#define AUTO_GREEN_HW_DEFAULT 0 1559#define AUTO_GREEN_FORCE_ON 1 1560#define AUTO_GREEN_FORCE_OFF 2 1561 int interrupt_mode; 1562#define INTR_MODE_INTX 0 1563#define INTR_MODE_MSI 1 1564#define INTR_MODE_MSIX 2 1565 int udp_rss; 1566 1567 /* interrupt allocations */ 1568 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1569 int intr_count; 1570 uint8_t igu_dsb_id; 1571 uint8_t igu_base_sb; 1572 uint8_t igu_sb_cnt; 1573 //uint8_t min_msix_vec_cnt; 1574 uint32_t igu_base_addr; 1575 //bus_addr_t def_status_blk_mapping; 1576 uint8_t base_fw_ndsb; 1577#define DEF_SB_IGU_ID 16 1578#define DEF_SB_ID HC_SP_SB_ID 1579 1580 /* parent bus DMA tag */ 1581 bus_dma_tag_t parent_dma_tag; 1582 1583 /* default status block */ 1584 struct bxe_dma def_sb_dma; 1585 struct host_sp_status_block *def_sb; 1586 uint16_t def_idx; 1587 uint16_t def_att_idx; 1588 uint32_t attn_state; 1589 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1590 1591/* general SP events - stats query, cfc delete, etc */ 1592#define HC_SP_INDEX_ETH_DEF_CONS 3 1593/* EQ completions */ 1594#define HC_SP_INDEX_EQ_CONS 7 1595/* FCoE L2 connection completions */ 1596#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1597#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1598/* iSCSI L2 */ 1599#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1600#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1601 1602 /* event queue */ 1603 struct bxe_dma eq_dma; 1604 union event_ring_elem *eq; 1605 uint16_t eq_prod; 1606 uint16_t eq_cons; 1607 uint16_t *eq_cons_sb; 1608#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1609#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1610#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1611#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1612#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1613#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1614/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1615#define NEXT_EQ_IDX(x) \ 1616 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1617 ((x) + 2) : ((x) + 1)) 1618/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1619#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1620 1621 /* slow path */ 1622 struct bxe_dma sp_dma; 1623 struct bxe_slowpath *sp; 1624 unsigned long sp_state; 1625 1626 /* slow path queue */ 1627 struct bxe_dma spq_dma; 1628 struct eth_spe *spq; 1629#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1630#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1631#define MAX_SPQ_PENDING 8 1632 1633 uint16_t spq_prod_idx; 1634 struct eth_spe *spq_prod_bd; 1635 struct eth_spe *spq_last_bd; 1636 uint16_t *dsb_sp_prod; 1637 //uint16_t *spq_hw_con; 1638 //uint16_t spq_left; 1639 1640 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1641 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1642 1643 /* fw decompression buffer */ 1644 struct bxe_dma gz_buf_dma; 1645 void *gz_buf; 1646 z_streamp gz_strm; 1647 uint32_t gz_outlen; 1648#define GUNZIP_BUF(sc) (sc->gz_buf) 1649#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1650#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1651#define FW_BUF_SIZE 0x40000 1652 1653 const struct raw_op *init_ops; 1654 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1655 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1656 uint32_t init_mode_flags; 1657#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1658 /* PRAM blobs - raw data */ 1659 const uint8_t *tsem_int_table_data; 1660 const uint8_t *tsem_pram_data; 1661 const uint8_t *usem_int_table_data; 1662 const uint8_t *usem_pram_data; 1663 const uint8_t *xsem_int_table_data; 1664 const uint8_t *xsem_pram_data; 1665 const uint8_t *csem_int_table_data; 1666 const uint8_t *csem_pram_data; 1667#define INIT_OPS(sc) (sc->init_ops) 1668#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1669#define INIT_DATA(sc) (sc->init_data) 1670#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1671#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1672#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1673#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1674#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1675#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1676#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1677#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1678 1679 /* ILT 1680 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1681 * context size we need 8 ILT entries. 1682 */ 1683#define ILT_MAX_L2_LINES 8 1684 struct hw_context context[ILT_MAX_L2_LINES]; 1685 struct ecore_ilt *ilt; 1686#define ILT_MAX_LINES 256 1687 1688/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1689#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1690/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1691#if 1 1692#define BXE_L2_MAX_CID(sc) \ 1693 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1694#else 1695#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1696 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1697#endif 1698#if 1 1699#define BXE_L2_CID_COUNT(sc) \ 1700 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1701#else 1702#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1703 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1704#endif 1705#define L2_ILT_LINES(sc) \ 1706 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1707 1708 int qm_cid_count; 1709 1710 uint8_t dropless_fc; 1711 1712 /* total number of FW statistics requests */ 1713 uint8_t fw_stats_num; 1714 /* 1715 * This is a memory buffer that will contain both statistics ramrod 1716 * request and data. 1717 */ 1718 struct bxe_dma fw_stats_dma; 1719 /* 1720 * FW statistics request shortcut (points at the beginning of fw_stats 1721 * buffer). 1722 */ 1723 int fw_stats_req_size; 1724 struct bxe_fw_stats_req *fw_stats_req; 1725 bus_addr_t fw_stats_req_mapping; 1726 /* 1727 * FW statistics data shortcut (points at the beginning of fw_stats 1728 * buffer + fw_stats_req_size). 1729 */ 1730 int fw_stats_data_size; 1731 struct bxe_fw_stats_data *fw_stats_data; 1732 bus_addr_t fw_stats_data_mapping; 1733 1734 /* tracking a pending STAT_QUERY ramrod */ 1735 uint16_t stats_pending; 1736 /* number of completed statistics ramrods */ 1737 uint16_t stats_comp; 1738 uint16_t stats_counter; 1739 uint8_t stats_init; 1740 int stats_state; 1741 1742 struct bxe_eth_stats eth_stats; 1743 struct host_func_stats func_stats; 1744 struct bxe_eth_stats_old eth_stats_old; 1745 struct bxe_net_stats_old net_stats_old; 1746 struct bxe_fw_port_stats_old fw_stats_old; 1747 1748 struct dmae_command stats_dmae; /* used by dmae command loader */ 1749 int executer_idx; 1750 1751 int mtu; 1752 1753 /* LLDP params */ 1754 struct bxe_config_lldp_params lldp_config_params; 1755 /* DCB support on/off */ 1756 int dcb_state; 1757#define BXE_DCB_STATE_OFF 0 1758#define BXE_DCB_STATE_ON 1 1759 /* DCBX engine mode */ 1760 int dcbx_enabled; 1761#define BXE_DCBX_ENABLED_OFF 0 1762#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1763#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1764#define BXE_DCBX_ENABLED_INVALID -1 1765 uint8_t dcbx_mode_uset; 1766 struct bxe_config_dcbx_params dcbx_config_params; 1767 struct bxe_dcbx_port_params dcbx_port_params; 1768 int dcb_version; 1769 1770 uint8_t cnic_support; 1771 uint8_t cnic_enabled; 1772 uint8_t cnic_loaded; 1773#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1774#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1775#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1776 1777 /* multiple tx classes of service */ 1778 uint8_t max_cos; 1779#define BXE_MAX_PRIORITY 8 1780 /* priority to cos mapping */ 1781 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1782 1783 int panic; 1784 1785 struct cdev *ioctl_dev; 1786 void *grc_dump; 1787 int grcdump_done; 1788}; /* struct bxe_softc */ 1789 1790/* IOCTL sub-commands for edebug and firmware upgrade */ 1791#define BXE_IOC_RD_NVRAM 1 1792#define BXE_IOC_WR_NVRAM 2 1793#define BXE_IOC_STATS_SHOW_NUM 3 1794#define BXE_IOC_STATS_SHOW_STR 4 1795#define BXE_IOC_STATS_SHOW_CNT 5 1796 1797struct bxe_nvram_data { 1798 uint32_t op; /* ioctl sub-command */ 1799 uint32_t offset; 1800 uint32_t len; 1801 uint32_t value[1]; /* variable */ 1802}; 1803 1804union bxe_stats_show_data { 1805 uint32_t op; /* ioctl sub-command */ 1806 1807 struct { 1808 uint32_t num; /* return number of stats */ 1809 uint32_t len; /* length of each string item */ 1810 } desc; 1811 1812 /* variable length... */ 1813 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1814 1815 /* variable length... */ 1816 uint64_t stats[1]; /* holds all stats */ 1817}; 1818 1819/* function init flags */ 1820#define FUNC_FLG_RSS 0x0001 1821#define FUNC_FLG_STATS 0x0002 1822/* FUNC_FLG_UNMATCHED 0x0004 */ 1823#define FUNC_FLG_TPA 0x0008 1824#define FUNC_FLG_SPQ 0x0010 1825#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1826 1827struct bxe_func_init_params { 1828 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1829 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1830 uint16_t func_flgs; 1831 uint16_t func_id; /* abs function id */ 1832 uint16_t pf_id; 1833 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1834}; 1835 1836/* memory resources reside at BARs 0, 2, 4 */ 1837/* Run `pciconf -lb` to see mappings */ 1838#define BAR0 0 1839#define BAR1 2 1840#define BAR2 4 1841 1842#ifdef BXE_REG_NO_INLINE 1843 1844uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1845uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1846uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1847 1848void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1849void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1850void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1851 1852#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1853#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1854#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1855 1856#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1857#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1858#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1859 1860#else /* not BXE_REG_NO_INLINE */ 1861 1862#define REG_WR8(sc, offset, val) \ 1863 bus_space_write_1(sc->bar[BAR0].tag, \ 1864 sc->bar[BAR0].handle, \ 1865 offset, val) 1866 1867#define REG_WR16(sc, offset, val) \ 1868 bus_space_write_2(sc->bar[BAR0].tag, \ 1869 sc->bar[BAR0].handle, \ 1870 offset, val) 1871 1872#define REG_WR32(sc, offset, val) \ 1873 bus_space_write_4(sc->bar[BAR0].tag, \ 1874 sc->bar[BAR0].handle, \ 1875 offset, val) 1876 1877#define REG_RD8(sc, offset) \ 1878 bus_space_read_1(sc->bar[BAR0].tag, \ 1879 sc->bar[BAR0].handle, \ 1880 offset) 1881 1882#define REG_RD16(sc, offset) \ 1883 bus_space_read_2(sc->bar[BAR0].tag, \ 1884 sc->bar[BAR0].handle, \ 1885 offset) 1886 1887#define REG_RD32(sc, offset) \ 1888 bus_space_read_4(sc->bar[BAR0].tag, \ 1889 sc->bar[BAR0].handle, \ 1890 offset) 1891 1892#endif /* BXE_REG_NO_INLINE */ 1893 1894#define REG_RD(sc, offset) REG_RD32(sc, offset) 1895#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1896 1897#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1898#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1899 1900#define BXE_SP(sc, var) (&(sc)->sp->var) 1901#define BXE_SP_MAPPING(sc, var) \ 1902 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1903 1904#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1905#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1906 1907#define REG_RD_DMAE(sc, offset, valp, len32) \ 1908 do { \ 1909 bxe_read_dmae(sc, offset, len32); \ 1910 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1911 } while (0) 1912 1913#define REG_WR_DMAE(sc, offset, valp, len32) \ 1914 do { \ 1915 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1916 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1917 } while (0) 1918 1919#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1920 REG_WR_DMAE(sc, offset, valp, len32) 1921 1922#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1923 REG_RD_DMAE(sc, offset, valp, len32) 1924 1925#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1926 do { \ 1927 /* if (le32_swap) { */ \ 1928 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1929 /* } */ \ 1930 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1931 ecore_write_big_buf_wb(sc, addr, len32); \ 1932 } while (0) 1933 1934#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1935#define BXE_DB_SHIFT 7 /* 128 bytes */ 1936#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1937#error "Minimum DB doorbell stride is 8" 1938#endif 1939#define DPM_TRIGGER_TYPE 0x40 1940#define DOORBELL(sc, cid, val) \ 1941 do { \ 1942 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1943 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1944 (uint32_t)val); \ 1945 } while(0) 1946 1947#define SHMEM_ADDR(sc, field) \ 1948 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1949#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1950#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1951#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1952 1953#define SHMEM2_ADDR(sc, field) \ 1954 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1955#define SHMEM2_HAS(sc, field) \ 1956 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1957 offsetof(struct shmem2_region, field))) 1958#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1959#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1960 1961#define MFCFG_ADDR(sc, field) \ 1962 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1963#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1964#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1965#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1966 1967/* DMAE command defines */ 1968 1969#define DMAE_TIMEOUT -1 1970#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1971#define DMAE_NOT_RDY -3 1972#define DMAE_PCI_ERR_FLAG 0x80000000 1973 1974#define DMAE_SRC_PCI 0 1975#define DMAE_SRC_GRC 1 1976 1977#define DMAE_DST_NONE 0 1978#define DMAE_DST_PCI 1 1979#define DMAE_DST_GRC 2 1980 1981#define DMAE_COMP_PCI 0 1982#define DMAE_COMP_GRC 1 1983 1984#define DMAE_COMP_REGULAR 0 1985#define DMAE_COM_SET_ERR 1 1986 1987#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT) 1988#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT) 1989#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT) 1990#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT) 1991 1992#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT) 1993#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT) 1994 1995#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1996#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1997#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1998#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1999 2000#define DMAE_CMD_PORT_0 0 2001#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2002 2003#define DMAE_SRC_PF 0 2004#define DMAE_SRC_VF 1 2005 2006#define DMAE_DST_PF 0 2007#define DMAE_DST_VF 1 2008 2009#define DMAE_C_SRC 0 2010#define DMAE_C_DST 1 2011 2012#define DMAE_LEN32_RD_MAX 0x80 2013#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2014 2015#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2016 2017#define MAX_DMAE_C_PER_PORT 8 2018#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2019#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2020 2021static const uint32_t dmae_reg_go_c[] = { 2022 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2023 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2024 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2025 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2026}; 2027 2028#define ATTN_NIG_FOR_FUNC (1L << 8) 2029#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2030#define GPIO_2_FUNC (1L << 10) 2031#define GPIO_3_FUNC (1L << 11) 2032#define GPIO_4_FUNC (1L << 12) 2033#define ATTN_GENERAL_ATTN_1 (1L << 13) 2034#define ATTN_GENERAL_ATTN_2 (1L << 14) 2035#define ATTN_GENERAL_ATTN_3 (1L << 15) 2036#define ATTN_GENERAL_ATTN_4 (1L << 13) 2037#define ATTN_GENERAL_ATTN_5 (1L << 14) 2038#define ATTN_GENERAL_ATTN_6 (1L << 15) 2039#define ATTN_HARD_WIRED_MASK 0xff00 2040#define ATTENTION_ID 4 2041 2042#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2043 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2044 2045#define MAX_IGU_ATTN_ACK_TO 100 2046 2047#define STORM_ASSERT_ARRAY_SIZE 50 2048 2049#define BXE_PMF_LINK_ASSERT(sc) \ 2050 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2051 2052#define BXE_MC_ASSERT_BITS \ 2053 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2054 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2055 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2056 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2057 2058#define BXE_MCP_ASSERT \ 2059 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2060 2061#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2062#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2063 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2064 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2065 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2066 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2067 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2068 2069#define MULTI_MASK 0x7f 2070 2071#define PFS_PER_PORT(sc) \ 2072 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2073#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2074 2075#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2076 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2077 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2078 2079#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2080 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2081 (i) < MAX_FUNC_NUM; \ 2082 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2083 2084#define BXE_SWCID_SHIFT 17 2085#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2086 2087#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2088#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2089 2090#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2091#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2092#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2093#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2094#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2095 2096/* must be used on a CID before placing it on a HW ring */ 2097#define HW_CID(sc, x) \ 2098 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2099 2100#define SPEED_10 10 2101#define SPEED_100 100 2102#define SPEED_1000 1000 2103#define SPEED_2500 2500 2104#define SPEED_10000 10000 2105 2106#define PCI_PM_D0 1 2107#define PCI_PM_D3hot 2 2108 2109int bxe_test_bit(int nr, volatile unsigned long * addr); 2110void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2111void bxe_clear_bit(int nr, volatile unsigned long * addr); 2112int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2113int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2114int bxe_cmpxchg(volatile int *addr, int old, int new); 2115 2116void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2117 uint32_t val); 2118uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2119 2120 2121int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2122 struct bxe_dma *dma, const char *msg); 2123void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2124 2125uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2126uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2127uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2128 uint8_t dst_type, uint8_t with_comp, 2129 uint8_t comp_type); 2130void bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx); 2131void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2132void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2133 uint32_t dst_addr, uint32_t len32); 2134void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2135 uint32_t addr, uint32_t len); 2136 2137void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2138 uint32_t cid); 2139void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2140 uint8_t sb_index, uint8_t disable, 2141 uint16_t usec); 2142 2143int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2144 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2145 2146void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2147 uint8_t segment, uint16_t index, uint8_t op, 2148 uint8_t update); 2149 2150void ecore_init_e1_firmware(struct bxe_softc *sc); 2151void ecore_init_e1h_firmware(struct bxe_softc *sc); 2152void ecore_init_e2_firmware(struct bxe_softc *sc); 2153 2154void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2155 size_t size, uint32_t *data); 2156 2157/*********************/ 2158/* LOGGING AND DEBUG */ 2159/*********************/ 2160 2161/* debug logging codepaths */ 2162#define DBG_LOAD 0x00000001 /* load and unload */ 2163#define DBG_INTR 0x00000002 /* interrupt handling */ 2164#define DBG_SP 0x00000004 /* slowpath handling */ 2165#define DBG_STATS 0x00000008 /* stats updates */ 2166#define DBG_TX 0x00000010 /* packet transmit */ 2167#define DBG_RX 0x00000020 /* packet receive */ 2168#define DBG_PHY 0x00000040 /* phy/link handling */ 2169#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2170#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2171#define DBG_REGS 0x00000200 /* register access */ 2172#define DBG_LRO 0x00000400 /* lro processing */ 2173#define DBG_ASSERT 0x80000000 /* debug assert */ 2174#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2175 2176#define DBASSERT(sc, exp, msg) \ 2177 do { \ 2178 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2179 if (__predict_false(!(exp))) { \ 2180 panic msg; \ 2181 } \ 2182 } \ 2183 } while (0) 2184 2185/* log a debug message */ 2186#define BLOGD(sc, codepath, format, args...) \ 2187 do { \ 2188 if (__predict_false(sc->debug & (codepath))) { \ 2189 device_printf((sc)->dev, \ 2190 "%s(%s:%d) " format, \ 2191 __FUNCTION__, \ 2192 __FILE__, \ 2193 __LINE__, \ 2194 ## args); \ 2195 } \ 2196 } while(0) 2197 2198/* log a info message */ 2199#define BLOGI(sc, format, args...) \ 2200 do { \ 2201 if (__predict_false(sc->debug)) { \ 2202 device_printf((sc)->dev, \ 2203 "%s(%s:%d) " format, \ 2204 __FUNCTION__, \ 2205 __FILE__, \ 2206 __LINE__, \ 2207 ## args); \ 2208 } else { \ 2209 device_printf((sc)->dev, \ 2210 format, \ 2211 ## args); \ 2212 } \ 2213 } while(0) 2214 2215/* log a warning message */ 2216#define BLOGW(sc, format, args...) \ 2217 do { \ 2218 if (__predict_false(sc->debug)) { \ 2219 device_printf((sc)->dev, \ 2220 "%s(%s:%d) WARNING: " format, \ 2221 __FUNCTION__, \ 2222 __FILE__, \ 2223 __LINE__, \ 2224 ## args); \ 2225 } else { \ 2226 device_printf((sc)->dev, \ 2227 "WARNING: " format, \ 2228 ## args); \ 2229 } \ 2230 } while(0) 2231 2232/* log a error message */ 2233#define BLOGE(sc, format, args...) \ 2234 do { \ 2235 if (__predict_false(sc->debug)) { \ 2236 device_printf((sc)->dev, \ 2237 "%s(%s:%d) ERROR: " format, \ 2238 __FUNCTION__, \ 2239 __FILE__, \ 2240 __LINE__, \ 2241 ## args); \ 2242 } else { \ 2243 device_printf((sc)->dev, \ 2244 "ERROR: " format, \ 2245 ## args); \ 2246 } \ 2247 } while(0) 2248 2249#ifdef ECORE_STOP_ON_ERROR 2250 2251#define bxe_panic(sc, msg) \ 2252 do { \ 2253 panic msg; \ 2254 } while (0) 2255 2256#else 2257 2258#define bxe_panic(sc, msg) \ 2259 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2260 2261#endif 2262 2263#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2264#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2265 2266void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2267 uint8_t *mem, uint32_t len); 2268void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2269 struct mbuf *m, uint8_t contents); 2270 2271/***********/ 2272/* INLINES */ 2273/***********/ 2274 2275static inline uint32_t 2276reg_poll(struct bxe_softc *sc, 2277 uint32_t reg, 2278 uint32_t expected, 2279 int ms, 2280 int wait) 2281{ 2282 uint32_t val; 2283 2284 do { 2285 val = REG_RD(sc, reg); 2286 if (val == expected) { 2287 break; 2288 } 2289 ms -= wait; 2290 DELAY(wait * 1000); 2291 } while (ms > 0); 2292 2293 return (val); 2294} 2295 2296static inline void 2297bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2298{ 2299 mb(); /* status block is written to by the chip */ 2300 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2301} 2302 2303static inline void 2304bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2305 uint8_t igu_sb_id, 2306 uint8_t segment, 2307 uint16_t index, 2308 uint8_t op, 2309 uint8_t update, 2310 uint32_t igu_addr) 2311{ 2312 struct igu_regular cmd_data = {0}; 2313 2314 cmd_data.sb_id_and_flags = 2315 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2316 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2317 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2318 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2319 2320 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2321 cmd_data.sb_id_and_flags, igu_addr); 2322 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2323 2324 /* Make sure that ACK is written */ 2325 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2326 BUS_SPACE_BARRIER_WRITE); 2327 mb(); 2328} 2329 2330static inline void 2331bxe_hc_ack_sb(struct bxe_softc *sc, 2332 uint8_t sb_id, 2333 uint8_t storm, 2334 uint16_t index, 2335 uint8_t op, 2336 uint8_t update) 2337{ 2338 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2339 COMMAND_REG_INT_ACK); 2340 struct igu_ack_register igu_ack; 2341 2342 igu_ack.status_block_index = index; 2343 igu_ack.sb_id_and_flags = 2344 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2345 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2346 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2347 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2348 2349 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2350 2351 /* Make sure that ACK is written */ 2352 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2353 BUS_SPACE_BARRIER_WRITE); 2354 mb(); 2355} 2356 2357static inline void 2358bxe_ack_sb(struct bxe_softc *sc, 2359 uint8_t igu_sb_id, 2360 uint8_t storm, 2361 uint16_t index, 2362 uint8_t op, 2363 uint8_t update) 2364{ 2365 if (sc->devinfo.int_block == INT_BLOCK_HC) 2366 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2367 else { 2368 uint8_t segment; 2369 if (CHIP_INT_MODE_IS_BC(sc)) { 2370 segment = storm; 2371 } else if (igu_sb_id != sc->igu_dsb_id) { 2372 segment = IGU_SEG_ACCESS_DEF; 2373 } else if (storm == ATTENTION_ID) { 2374 segment = IGU_SEG_ACCESS_ATTN; 2375 } else { 2376 segment = IGU_SEG_ACCESS_DEF; 2377 } 2378 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2379 } 2380} 2381 2382static inline uint16_t 2383bxe_hc_ack_int(struct bxe_softc *sc) 2384{ 2385 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2386 COMMAND_REG_SIMD_MASK); 2387 uint32_t result = REG_RD(sc, hc_addr); 2388 2389 mb(); 2390 return (result); 2391} 2392 2393static inline uint16_t 2394bxe_igu_ack_int(struct bxe_softc *sc) 2395{ 2396 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2397 uint32_t result = REG_RD(sc, igu_addr); 2398 2399 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2400 result, igu_addr); 2401 2402 mb(); 2403 return (result); 2404} 2405 2406static inline uint16_t 2407bxe_ack_int(struct bxe_softc *sc) 2408{ 2409 mb(); 2410 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2411 return (bxe_hc_ack_int(sc)); 2412 } else { 2413 return (bxe_igu_ack_int(sc)); 2414 } 2415} 2416 2417static inline int 2418func_by_vn(struct bxe_softc *sc, 2419 int vn) 2420{ 2421 return (2 * vn + SC_PORT(sc)); 2422} 2423 2424/* 2425 * Statistics ID are global per chip/path, while Client IDs for E1x 2426 * are per port. 2427 */ 2428static inline uint8_t 2429bxe_stats_id(struct bxe_fastpath *fp) 2430{ 2431 struct bxe_softc *sc = fp->sc; 2432 2433 if (!CHIP_IS_E1x(sc)) { 2434 return (fp->cl_id); 2435 } 2436 2437 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2438} 2439 2440#endif /* __BXE_H__ */ 2441 2442