if_bge.c revision 199761
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 199761 2009-11-24 17:46:58Z yongari $"); 36 37/* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69#ifdef HAVE_KERNEL_OPTION_HEADERS 70#include "opt_device_polling.h" 71#endif 72 73#include <sys/param.h> 74#include <sys/endian.h> 75#include <sys/systm.h> 76#include <sys/sockio.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/socket.h> 82#include <sys/sysctl.h> 83#include <sys/taskqueue.h> 84 85#include <net/if.h> 86#include <net/if_arp.h> 87#include <net/ethernet.h> 88#include <net/if_dl.h> 89#include <net/if_media.h> 90 91#include <net/bpf.h> 92 93#include <net/if_types.h> 94#include <net/if_vlan_var.h> 95 96#include <netinet/in_systm.h> 97#include <netinet/in.h> 98#include <netinet/ip.h> 99#include <netinet/tcp.h> 100 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include "miidevs.h" 109#include <dev/mii/brgphyreg.h> 110 111#ifdef __sparc64__ 112#include <dev/ofw/ofw_bus.h> 113#include <dev/ofw/openfirm.h> 114#include <machine/ofw_machdep.h> 115#include <machine/ver.h> 116#endif 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121#include <dev/bge/if_bgereg.h> 122 123#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 124#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126MODULE_DEPEND(bge, pci, 1, 1, 1); 127MODULE_DEPEND(bge, ether, 1, 1, 1); 128MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130/* "device miibus" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133/* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142} bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 217 218 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 219 220 { TC_VENDORID, TC_DEVICEID_3C996 }, 221 222 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 224 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 225 226 { 0, 0 } 227}; 228 229static const struct bge_vendor { 230 uint16_t v_id; 231 const char *v_name; 232} bge_vendors[] = { 233 { ALTEON_VENDORID, "Alteon" }, 234 { ALTIMA_VENDORID, "Altima" }, 235 { APPLE_VENDORID, "Apple" }, 236 { BCOM_VENDORID, "Broadcom" }, 237 { SK_VENDORID, "SysKonnect" }, 238 { TC_VENDORID, "3Com" }, 239 { FJTSU_VENDORID, "Fujitsu" }, 240 241 { 0, NULL } 242}; 243 244static const struct bge_revision { 245 uint32_t br_chipid; 246 const char *br_name; 247} bge_revisions[] = { 248 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 249 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 250 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 251 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 252 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 253 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 254 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 255 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 256 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 257 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 258 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 259 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 260 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 261 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 262 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 263 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 264 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 265 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 266 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 267 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 268 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 269 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 270 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 271 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 272 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 273 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 274 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 275 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 276 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 277 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 278 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 279 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 280 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 281 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 282 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 283 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 284 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 285 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 286 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 287 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 288 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 289 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 290 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 291 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 292 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 293 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 294 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 295 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 296 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 297 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 298 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 299 /* 5754 and 5787 share the same ASIC ID */ 300 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 301 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 302 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 303 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 304 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 305 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 306 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 307 308 { 0, NULL } 309}; 310 311/* 312 * Some defaults for major revisions, so that newer steppings 313 * that we don't know about have a shot at working. 314 */ 315static const struct bge_revision bge_majorrevs[] = { 316 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 317 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 318 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 319 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 320 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 321 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 322 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 323 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 324 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 325 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 326 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 327 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 328 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 329 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 330 /* 5754 and 5787 share the same ASIC ID */ 331 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 332 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 333 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 334 335 { 0, NULL } 336}; 337 338#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 339#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 340#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 341#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 342#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 343#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 344 345const struct bge_revision * bge_lookup_rev(uint32_t); 346const struct bge_vendor * bge_lookup_vendor(uint16_t); 347 348typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 349 350static int bge_probe(device_t); 351static int bge_attach(device_t); 352static int bge_detach(device_t); 353static int bge_suspend(device_t); 354static int bge_resume(device_t); 355static void bge_release_resources(struct bge_softc *); 356static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 357static int bge_dma_alloc(device_t); 358static void bge_dma_free(struct bge_softc *); 359 360static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 361static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 362static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 363static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 364static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 365 366static void bge_txeof(struct bge_softc *, uint16_t); 367static int bge_rxeof(struct bge_softc *, uint16_t, int); 368 369static void bge_asf_driver_up (struct bge_softc *); 370static void bge_tick(void *); 371static void bge_stats_update(struct bge_softc *); 372static void bge_stats_update_regs(struct bge_softc *); 373static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 374 uint16_t *); 375static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 376 377static void bge_intr(void *); 378static int bge_msi_intr(void *); 379static void bge_intr_task(void *, int); 380static void bge_start_locked(struct ifnet *); 381static void bge_start(struct ifnet *); 382static int bge_ioctl(struct ifnet *, u_long, caddr_t); 383static void bge_init_locked(struct bge_softc *); 384static void bge_init(void *); 385static void bge_stop(struct bge_softc *); 386static void bge_watchdog(struct bge_softc *); 387static int bge_shutdown(device_t); 388static int bge_ifmedia_upd_locked(struct ifnet *); 389static int bge_ifmedia_upd(struct ifnet *); 390static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 391 392static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 393static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 394 395static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 396static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 397 398static void bge_setpromisc(struct bge_softc *); 399static void bge_setmulti(struct bge_softc *); 400static void bge_setvlan(struct bge_softc *); 401 402static int bge_newbuf_std(struct bge_softc *, int); 403static int bge_newbuf_jumbo(struct bge_softc *, int); 404static int bge_init_rx_ring_std(struct bge_softc *); 405static void bge_free_rx_ring_std(struct bge_softc *); 406static int bge_init_rx_ring_jumbo(struct bge_softc *); 407static void bge_free_rx_ring_jumbo(struct bge_softc *); 408static void bge_free_tx_ring(struct bge_softc *); 409static int bge_init_tx_ring(struct bge_softc *); 410 411static int bge_chipinit(struct bge_softc *); 412static int bge_blockinit(struct bge_softc *); 413 414static int bge_has_eaddr(struct bge_softc *); 415static uint32_t bge_readmem_ind(struct bge_softc *, int); 416static void bge_writemem_ind(struct bge_softc *, int, int); 417static void bge_writembx(struct bge_softc *, int, int); 418#ifdef notdef 419static uint32_t bge_readreg_ind(struct bge_softc *, int); 420#endif 421static void bge_writemem_direct(struct bge_softc *, int, int); 422static void bge_writereg_ind(struct bge_softc *, int, int); 423static void bge_set_max_readrq(struct bge_softc *); 424 425static int bge_miibus_readreg(device_t, int, int); 426static int bge_miibus_writereg(device_t, int, int, int); 427static void bge_miibus_statchg(device_t); 428#ifdef DEVICE_POLLING 429static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 430#endif 431 432#define BGE_RESET_START 1 433#define BGE_RESET_STOP 2 434static void bge_sig_post_reset(struct bge_softc *, int); 435static void bge_sig_legacy(struct bge_softc *, int); 436static void bge_sig_pre_reset(struct bge_softc *, int); 437static int bge_reset(struct bge_softc *); 438static void bge_link_upd(struct bge_softc *); 439 440/* 441 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 442 * leak information to untrusted users. It is also known to cause alignment 443 * traps on certain architectures. 444 */ 445#ifdef BGE_REGISTER_DEBUG 446static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 447static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 448static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 449#endif 450static void bge_add_sysctls(struct bge_softc *); 451static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 452 453static device_method_t bge_methods[] = { 454 /* Device interface */ 455 DEVMETHOD(device_probe, bge_probe), 456 DEVMETHOD(device_attach, bge_attach), 457 DEVMETHOD(device_detach, bge_detach), 458 DEVMETHOD(device_shutdown, bge_shutdown), 459 DEVMETHOD(device_suspend, bge_suspend), 460 DEVMETHOD(device_resume, bge_resume), 461 462 /* bus interface */ 463 DEVMETHOD(bus_print_child, bus_generic_print_child), 464 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 465 466 /* MII interface */ 467 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 468 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 469 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 470 471 { 0, 0 } 472}; 473 474static driver_t bge_driver = { 475 "bge", 476 bge_methods, 477 sizeof(struct bge_softc) 478}; 479 480static devclass_t bge_devclass; 481 482DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 483DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 484 485static int bge_allow_asf = 1; 486 487TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 488 489SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 490SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 491 "Allow ASF mode if available"); 492 493#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 494#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 495#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 496#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 497#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 498 499static int 500bge_has_eaddr(struct bge_softc *sc) 501{ 502#ifdef __sparc64__ 503 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 504 device_t dev; 505 uint32_t subvendor; 506 507 dev = sc->bge_dev; 508 509 /* 510 * The on-board BGEs found in sun4u machines aren't fitted with 511 * an EEPROM which means that we have to obtain the MAC address 512 * via OFW and that some tests will always fail. We distinguish 513 * such BGEs by the subvendor ID, which also has to be obtained 514 * from OFW instead of the PCI configuration space as the latter 515 * indicates Broadcom as the subvendor of the netboot interface. 516 * For early Blade 1500 and 2500 we even have to check the OFW 517 * device path as the subvendor ID always defaults to Broadcom 518 * there. 519 */ 520 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 521 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 522 subvendor == SUN_VENDORID) 523 return (0); 524 memset(buf, 0, sizeof(buf)); 525 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 526 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 527 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 528 return (0); 529 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 530 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 531 return (0); 532 } 533#endif 534 return (1); 535} 536 537static uint32_t 538bge_readmem_ind(struct bge_softc *sc, int off) 539{ 540 device_t dev; 541 uint32_t val; 542 543 dev = sc->bge_dev; 544 545 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 546 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 547 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 548 return (val); 549} 550 551static void 552bge_writemem_ind(struct bge_softc *sc, int off, int val) 553{ 554 device_t dev; 555 556 dev = sc->bge_dev; 557 558 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 559 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 560 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 561} 562 563/* 564 * PCI Express only 565 */ 566static void 567bge_set_max_readrq(struct bge_softc *sc) 568{ 569 device_t dev; 570 uint16_t val; 571 572 dev = sc->bge_dev; 573 574 val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 575 if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) != 576 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 577 if (bootverbose) 578 device_printf(dev, "adjust device control 0x%04x ", 579 val); 580 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 581 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 582 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 583 val, 2); 584 if (bootverbose) 585 printf("-> 0x%04x\n", val); 586 } 587} 588 589#ifdef notdef 590static uint32_t 591bge_readreg_ind(struct bge_softc *sc, int off) 592{ 593 device_t dev; 594 595 dev = sc->bge_dev; 596 597 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 598 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 599} 600#endif 601 602static void 603bge_writereg_ind(struct bge_softc *sc, int off, int val) 604{ 605 device_t dev; 606 607 dev = sc->bge_dev; 608 609 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 610 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 611} 612 613static void 614bge_writemem_direct(struct bge_softc *sc, int off, int val) 615{ 616 CSR_WRITE_4(sc, off, val); 617} 618 619static void 620bge_writembx(struct bge_softc *sc, int off, int val) 621{ 622 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 623 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 624 625 CSR_WRITE_4(sc, off, val); 626} 627 628/* 629 * Map a single buffer address. 630 */ 631 632static void 633bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 634{ 635 struct bge_dmamap_arg *ctx; 636 637 if (error) 638 return; 639 640 ctx = arg; 641 642 if (nseg > ctx->bge_maxsegs) { 643 ctx->bge_maxsegs = 0; 644 return; 645 } 646 647 ctx->bge_busaddr = segs->ds_addr; 648} 649 650static uint8_t 651bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 652{ 653 uint32_t access, byte = 0; 654 int i; 655 656 /* Lock. */ 657 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 658 for (i = 0; i < 8000; i++) { 659 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 660 break; 661 DELAY(20); 662 } 663 if (i == 8000) 664 return (1); 665 666 /* Enable access. */ 667 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 668 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 669 670 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 671 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 672 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 673 DELAY(10); 674 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 675 DELAY(10); 676 break; 677 } 678 } 679 680 if (i == BGE_TIMEOUT * 10) { 681 if_printf(sc->bge_ifp, "nvram read timed out\n"); 682 return (1); 683 } 684 685 /* Get result. */ 686 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 687 688 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 689 690 /* Disable access. */ 691 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 692 693 /* Unlock. */ 694 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 695 CSR_READ_4(sc, BGE_NVRAM_SWARB); 696 697 return (0); 698} 699 700/* 701 * Read a sequence of bytes from NVRAM. 702 */ 703static int 704bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 705{ 706 int err = 0, i; 707 uint8_t byte = 0; 708 709 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 710 return (1); 711 712 for (i = 0; i < cnt; i++) { 713 err = bge_nvram_getbyte(sc, off + i, &byte); 714 if (err) 715 break; 716 *(dest + i) = byte; 717 } 718 719 return (err ? 1 : 0); 720} 721 722/* 723 * Read a byte of data stored in the EEPROM at address 'addr.' The 724 * BCM570x supports both the traditional bitbang interface and an 725 * auto access interface for reading the EEPROM. We use the auto 726 * access method. 727 */ 728static uint8_t 729bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 730{ 731 int i; 732 uint32_t byte = 0; 733 734 /* 735 * Enable use of auto EEPROM access so we can avoid 736 * having to use the bitbang method. 737 */ 738 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 739 740 /* Reset the EEPROM, load the clock period. */ 741 CSR_WRITE_4(sc, BGE_EE_ADDR, 742 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 743 DELAY(20); 744 745 /* Issue the read EEPROM command. */ 746 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 747 748 /* Wait for completion */ 749 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 750 DELAY(10); 751 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 752 break; 753 } 754 755 if (i == BGE_TIMEOUT * 10) { 756 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 757 return (1); 758 } 759 760 /* Get result. */ 761 byte = CSR_READ_4(sc, BGE_EE_DATA); 762 763 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 764 765 return (0); 766} 767 768/* 769 * Read a sequence of bytes from the EEPROM. 770 */ 771static int 772bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 773{ 774 int i, error = 0; 775 uint8_t byte = 0; 776 777 for (i = 0; i < cnt; i++) { 778 error = bge_eeprom_getbyte(sc, off + i, &byte); 779 if (error) 780 break; 781 *(dest + i) = byte; 782 } 783 784 return (error ? 1 : 0); 785} 786 787static int 788bge_miibus_readreg(device_t dev, int phy, int reg) 789{ 790 struct bge_softc *sc; 791 uint32_t val, autopoll; 792 int i; 793 794 sc = device_get_softc(dev); 795 796 /* 797 * Broadcom's own driver always assumes the internal 798 * PHY is at GMII address 1. On some chips, the PHY responds 799 * to accesses at all addresses, which could cause us to 800 * bogusly attach the PHY 32 times at probe type. Always 801 * restricting the lookup to address 1 is simpler than 802 * trying to figure out which chips revisions should be 803 * special-cased. 804 */ 805 if (phy != 1) 806 return (0); 807 808 /* Reading with autopolling on may trigger PCI errors */ 809 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 810 if (autopoll & BGE_MIMODE_AUTOPOLL) { 811 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 812 DELAY(40); 813 } 814 815 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 816 BGE_MIPHY(phy) | BGE_MIREG(reg)); 817 818 for (i = 0; i < BGE_TIMEOUT; i++) { 819 DELAY(10); 820 val = CSR_READ_4(sc, BGE_MI_COMM); 821 if (!(val & BGE_MICOMM_BUSY)) 822 break; 823 } 824 825 if (i == BGE_TIMEOUT) { 826 device_printf(sc->bge_dev, 827 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 828 phy, reg, val); 829 val = 0; 830 goto done; 831 } 832 833 DELAY(5); 834 val = CSR_READ_4(sc, BGE_MI_COMM); 835 836done: 837 if (autopoll & BGE_MIMODE_AUTOPOLL) { 838 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 839 DELAY(40); 840 } 841 842 if (val & BGE_MICOMM_READFAIL) 843 return (0); 844 845 return (val & 0xFFFF); 846} 847 848static int 849bge_miibus_writereg(device_t dev, int phy, int reg, int val) 850{ 851 struct bge_softc *sc; 852 uint32_t autopoll; 853 int i; 854 855 sc = device_get_softc(dev); 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 858 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 859 return(0); 860 861 /* Reading with autopolling on may trigger PCI errors */ 862 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 863 if (autopoll & BGE_MIMODE_AUTOPOLL) { 864 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 865 DELAY(40); 866 } 867 868 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 869 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 870 871 for (i = 0; i < BGE_TIMEOUT; i++) { 872 DELAY(10); 873 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 874 DELAY(5); 875 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 876 break; 877 } 878 } 879 880 if (i == BGE_TIMEOUT) { 881 device_printf(sc->bge_dev, 882 "PHY write timed out (phy %d, reg %d, val %d)\n", 883 phy, reg, val); 884 return (0); 885 } 886 887 if (autopoll & BGE_MIMODE_AUTOPOLL) { 888 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 889 DELAY(40); 890 } 891 892 return (0); 893} 894 895static void 896bge_miibus_statchg(device_t dev) 897{ 898 struct bge_softc *sc; 899 struct mii_data *mii; 900 sc = device_get_softc(dev); 901 mii = device_get_softc(sc->bge_miibus); 902 903 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 904 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 905 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 906 else 907 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 908 909 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 910 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 911 else 912 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 913} 914 915/* 916 * Intialize a standard receive ring descriptor. 917 */ 918static int 919bge_newbuf_std(struct bge_softc *sc, int i) 920{ 921 struct mbuf *m; 922 struct bge_rx_bd *r; 923 bus_dma_segment_t segs[1]; 924 bus_dmamap_t map; 925 int error, nsegs; 926 927 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 928 if (m == NULL) 929 return (ENOBUFS); 930 m->m_len = m->m_pkthdr.len = MCLBYTES; 931 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 932 m_adj(m, ETHER_ALIGN); 933 934 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 935 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 936 if (error != 0) { 937 m_freem(m); 938 return (error); 939 } 940 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 941 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 942 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 943 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 944 sc->bge_cdata.bge_rx_std_dmamap[i]); 945 } 946 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 947 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 948 sc->bge_cdata.bge_rx_std_sparemap = map; 949 sc->bge_cdata.bge_rx_std_chain[i] = m; 950 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 951 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 952 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 953 r->bge_flags = BGE_RXBDFLAG_END; 954 r->bge_len = segs[0].ds_len; 955 r->bge_idx = i; 956 957 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 958 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 959 960 return (0); 961} 962 963/* 964 * Initialize a jumbo receive ring descriptor. This allocates 965 * a jumbo buffer from the pool managed internally by the driver. 966 */ 967static int 968bge_newbuf_jumbo(struct bge_softc *sc, int i) 969{ 970 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 971 bus_dmamap_t map; 972 struct bge_extrx_bd *r; 973 struct mbuf *m; 974 int error, nsegs; 975 976 MGETHDR(m, M_DONTWAIT, MT_DATA); 977 if (m == NULL) 978 return (ENOBUFS); 979 980 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 981 if (!(m->m_flags & M_EXT)) { 982 m_freem(m); 983 return (ENOBUFS); 984 } 985 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 986 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 987 m_adj(m, ETHER_ALIGN); 988 989 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 990 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 991 if (error != 0) { 992 m_freem(m); 993 return (error); 994 } 995 996 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 997 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 998 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 999 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1000 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1001 } 1002 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1003 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1004 sc->bge_cdata.bge_rx_jumbo_sparemap; 1005 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1006 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1007 /* 1008 * Fill in the extended RX buffer descriptor. 1009 */ 1010 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1011 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1012 r->bge_idx = i; 1013 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1014 switch (nsegs) { 1015 case 4: 1016 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1017 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1018 r->bge_len3 = segs[3].ds_len; 1019 case 3: 1020 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1021 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1022 r->bge_len2 = segs[2].ds_len; 1023 case 2: 1024 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1025 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1026 r->bge_len1 = segs[1].ds_len; 1027 case 1: 1028 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1029 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1030 r->bge_len0 = segs[0].ds_len; 1031 break; 1032 default: 1033 panic("%s: %d segments\n", __func__, nsegs); 1034 } 1035 1036 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1037 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1038 1039 return (0); 1040} 1041 1042/* 1043 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1044 * that's 1MB or memory, which is a lot. For now, we fill only the first 1045 * 256 ring entries and hope that our CPU is fast enough to keep up with 1046 * the NIC. 1047 */ 1048static int 1049bge_init_rx_ring_std(struct bge_softc *sc) 1050{ 1051 int error, i; 1052 1053 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1054 sc->bge_std = 0; 1055 for (i = 0; i < BGE_SSLOTS; i++) { 1056 if ((error = bge_newbuf_std(sc, i)) != 0) 1057 return (error); 1058 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1059 }; 1060 1061 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1062 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1063 1064 sc->bge_std = i - 1; 1065 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1066 1067 return (0); 1068} 1069 1070static void 1071bge_free_rx_ring_std(struct bge_softc *sc) 1072{ 1073 int i; 1074 1075 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1076 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1077 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1078 sc->bge_cdata.bge_rx_std_dmamap[i], 1079 BUS_DMASYNC_POSTREAD); 1080 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1081 sc->bge_cdata.bge_rx_std_dmamap[i]); 1082 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1083 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1084 } 1085 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1086 sizeof(struct bge_rx_bd)); 1087 } 1088} 1089 1090static int 1091bge_init_rx_ring_jumbo(struct bge_softc *sc) 1092{ 1093 struct bge_rcb *rcb; 1094 int error, i; 1095 1096 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1097 sc->bge_jumbo = 0; 1098 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1099 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1100 return (error); 1101 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1102 }; 1103 1104 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1105 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1106 1107 sc->bge_jumbo = i - 1; 1108 1109 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1110 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1111 BGE_RCB_FLAG_USE_EXT_RX_BD); 1112 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1113 1114 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1115 1116 return (0); 1117} 1118 1119static void 1120bge_free_rx_ring_jumbo(struct bge_softc *sc) 1121{ 1122 int i; 1123 1124 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1125 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1126 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1127 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1128 BUS_DMASYNC_POSTREAD); 1129 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1130 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1131 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1132 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1133 } 1134 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1135 sizeof(struct bge_extrx_bd)); 1136 } 1137} 1138 1139static void 1140bge_free_tx_ring(struct bge_softc *sc) 1141{ 1142 int i; 1143 1144 if (sc->bge_ldata.bge_tx_ring == NULL) 1145 return; 1146 1147 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1148 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1149 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1150 sc->bge_cdata.bge_tx_dmamap[i], 1151 BUS_DMASYNC_POSTWRITE); 1152 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1153 sc->bge_cdata.bge_tx_dmamap[i]); 1154 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1155 sc->bge_cdata.bge_tx_chain[i] = NULL; 1156 } 1157 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1158 sizeof(struct bge_tx_bd)); 1159 } 1160} 1161 1162static int 1163bge_init_tx_ring(struct bge_softc *sc) 1164{ 1165 sc->bge_txcnt = 0; 1166 sc->bge_tx_saved_considx = 0; 1167 1168 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1169 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1170 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1171 1172 /* Initialize transmit producer index for host-memory send ring. */ 1173 sc->bge_tx_prodidx = 0; 1174 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1175 1176 /* 5700 b2 errata */ 1177 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1178 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1179 1180 /* NIC-memory send ring not used; initialize to zero. */ 1181 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1182 /* 5700 b2 errata */ 1183 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1184 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1185 1186 return (0); 1187} 1188 1189static void 1190bge_setpromisc(struct bge_softc *sc) 1191{ 1192 struct ifnet *ifp; 1193 1194 BGE_LOCK_ASSERT(sc); 1195 1196 ifp = sc->bge_ifp; 1197 1198 /* Enable or disable promiscuous mode as needed. */ 1199 if (ifp->if_flags & IFF_PROMISC) 1200 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1201 else 1202 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1203} 1204 1205static void 1206bge_setmulti(struct bge_softc *sc) 1207{ 1208 struct ifnet *ifp; 1209 struct ifmultiaddr *ifma; 1210 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1211 int h, i; 1212 1213 BGE_LOCK_ASSERT(sc); 1214 1215 ifp = sc->bge_ifp; 1216 1217 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1218 for (i = 0; i < 4; i++) 1219 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1220 return; 1221 } 1222 1223 /* First, zot all the existing filters. */ 1224 for (i = 0; i < 4; i++) 1225 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1226 1227 /* Now program new ones. */ 1228 if_maddr_rlock(ifp); 1229 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1230 if (ifma->ifma_addr->sa_family != AF_LINK) 1231 continue; 1232 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1233 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1234 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1235 } 1236 if_maddr_runlock(ifp); 1237 1238 for (i = 0; i < 4; i++) 1239 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1240} 1241 1242static void 1243bge_setvlan(struct bge_softc *sc) 1244{ 1245 struct ifnet *ifp; 1246 1247 BGE_LOCK_ASSERT(sc); 1248 1249 ifp = sc->bge_ifp; 1250 1251 /* Enable or disable VLAN tag stripping as needed. */ 1252 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1253 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1254 else 1255 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1256} 1257 1258static void 1259bge_sig_pre_reset(sc, type) 1260 struct bge_softc *sc; 1261 int type; 1262{ 1263 /* 1264 * Some chips don't like this so only do this if ASF is enabled 1265 */ 1266 if (sc->bge_asf_mode) 1267 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1268 1269 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1270 switch (type) { 1271 case BGE_RESET_START: 1272 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1273 break; 1274 case BGE_RESET_STOP: 1275 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1276 break; 1277 } 1278 } 1279} 1280 1281static void 1282bge_sig_post_reset(sc, type) 1283 struct bge_softc *sc; 1284 int type; 1285{ 1286 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1287 switch (type) { 1288 case BGE_RESET_START: 1289 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1290 /* START DONE */ 1291 break; 1292 case BGE_RESET_STOP: 1293 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1294 break; 1295 } 1296 } 1297} 1298 1299static void 1300bge_sig_legacy(sc, type) 1301 struct bge_softc *sc; 1302 int type; 1303{ 1304 if (sc->bge_asf_mode) { 1305 switch (type) { 1306 case BGE_RESET_START: 1307 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1308 break; 1309 case BGE_RESET_STOP: 1310 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1311 break; 1312 } 1313 } 1314} 1315 1316void bge_stop_fw(struct bge_softc *); 1317void 1318bge_stop_fw(sc) 1319 struct bge_softc *sc; 1320{ 1321 int i; 1322 1323 if (sc->bge_asf_mode) { 1324 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1325 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1326 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1327 1328 for (i = 0; i < 100; i++ ) { 1329 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1330 break; 1331 DELAY(10); 1332 } 1333 } 1334} 1335 1336/* 1337 * Do endian, PCI and DMA initialization. 1338 */ 1339static int 1340bge_chipinit(struct bge_softc *sc) 1341{ 1342 uint32_t dma_rw_ctl; 1343 int i; 1344 1345 /* Set endianness before we access any non-PCI registers. */ 1346 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1347 1348 /* Clear the MAC control register */ 1349 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1350 1351 /* 1352 * Clear the MAC statistics block in the NIC's 1353 * internal memory. 1354 */ 1355 for (i = BGE_STATS_BLOCK; 1356 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1357 BGE_MEMWIN_WRITE(sc, i, 0); 1358 1359 for (i = BGE_STATUS_BLOCK; 1360 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1361 BGE_MEMWIN_WRITE(sc, i, 0); 1362 1363 /* 1364 * Set up the PCI DMA control register. 1365 */ 1366 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1367 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1368 if (sc->bge_flags & BGE_FLAG_PCIE) { 1369 /* Read watermark not used, 128 bytes for write. */ 1370 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1371 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1372 if (BGE_IS_5714_FAMILY(sc)) { 1373 /* 256 bytes for read and write. */ 1374 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1375 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1376 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1377 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1378 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1379 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1380 /* 1536 bytes for read, 384 bytes for write. */ 1381 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1382 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1383 } else { 1384 /* 384 bytes for read and write. */ 1385 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1386 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1387 0x0F; 1388 } 1389 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1390 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1391 uint32_t tmp; 1392 1393 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1394 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1395 if (tmp == 6 || tmp == 7) 1396 dma_rw_ctl |= 1397 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1398 1399 /* Set PCI-X DMA write workaround. */ 1400 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1401 } 1402 } else { 1403 /* Conventional PCI bus: 256 bytes for read and write. */ 1404 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1405 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1406 1407 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1408 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1409 dma_rw_ctl |= 0x0F; 1410 } 1411 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1412 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1413 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1414 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1415 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1416 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1417 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1418 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1419 1420 /* 1421 * Set up general mode register. 1422 */ 1423 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1424 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1425 BGE_MODECTL_TX_NO_PHDR_CSUM); 1426 1427 /* 1428 * BCM5701 B5 have a bug causing data corruption when using 1429 * 64-bit DMA reads, which can be terminated early and then 1430 * completed later as 32-bit accesses, in combination with 1431 * certain bridges. 1432 */ 1433 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1434 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1435 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1436 1437 /* 1438 * Tell the firmware the driver is running 1439 */ 1440 if (sc->bge_asf_mode & ASF_STACKUP) 1441 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1442 1443 /* 1444 * Disable memory write invalidate. Apparently it is not supported 1445 * properly by these devices. Also ensure that INTx isn't disabled, 1446 * as these chips need it even when using MSI. 1447 */ 1448 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1449 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1450 1451 /* Set the timer prescaler (always 66Mhz) */ 1452 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1453 1454 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1455 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1456 DELAY(40); /* XXX */ 1457 1458 /* Put PHY into ready state */ 1459 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1460 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1461 DELAY(40); 1462 } 1463 1464 return (0); 1465} 1466 1467static int 1468bge_blockinit(struct bge_softc *sc) 1469{ 1470 struct bge_rcb *rcb; 1471 bus_size_t vrcb; 1472 bge_hostaddr taddr; 1473 uint32_t val; 1474 int i; 1475 1476 /* 1477 * Initialize the memory window pointer register so that 1478 * we can access the first 32K of internal NIC RAM. This will 1479 * allow us to set up the TX send ring RCBs and the RX return 1480 * ring RCBs, plus other things which live in NIC memory. 1481 */ 1482 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1483 1484 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1485 1486 if (!(BGE_IS_5705_PLUS(sc))) { 1487 /* Configure mbuf memory pool */ 1488 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1489 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1490 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1491 else 1492 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1493 1494 /* Configure DMA resource pool */ 1495 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1496 BGE_DMA_DESCRIPTORS); 1497 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1498 } 1499 1500 /* Configure mbuf pool watermarks */ 1501 if (!BGE_IS_5705_PLUS(sc)) { 1502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1503 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1505 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1507 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1509 } else { 1510 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1511 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1513 } 1514 1515 /* Configure DMA resource watermarks */ 1516 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1517 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1518 1519 /* Enable buffer manager */ 1520 if (!(BGE_IS_5705_PLUS(sc))) { 1521 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1522 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1523 1524 /* Poll for buffer manager start indication */ 1525 for (i = 0; i < BGE_TIMEOUT; i++) { 1526 DELAY(10); 1527 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1528 break; 1529 } 1530 1531 if (i == BGE_TIMEOUT) { 1532 device_printf(sc->bge_dev, 1533 "buffer manager failed to start\n"); 1534 return (ENXIO); 1535 } 1536 } 1537 1538 /* Enable flow-through queues */ 1539 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1540 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1541 1542 /* Wait until queue initialization is complete */ 1543 for (i = 0; i < BGE_TIMEOUT; i++) { 1544 DELAY(10); 1545 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1546 break; 1547 } 1548 1549 if (i == BGE_TIMEOUT) { 1550 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1551 return (ENXIO); 1552 } 1553 1554 /* Initialize the standard RX ring control block */ 1555 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1556 rcb->bge_hostaddr.bge_addr_lo = 1557 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1558 rcb->bge_hostaddr.bge_addr_hi = 1559 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1560 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1561 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1562 if (BGE_IS_5705_PLUS(sc)) 1563 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1564 else 1565 rcb->bge_maxlen_flags = 1566 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1567 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1568 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1569 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1570 1571 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1572 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1573 1574 /* 1575 * Initialize the jumbo RX ring control block 1576 * We set the 'ring disabled' bit in the flags 1577 * field until we're actually ready to start 1578 * using this ring (i.e. once we set the MTU 1579 * high enough to require it). 1580 */ 1581 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1582 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1583 1584 rcb->bge_hostaddr.bge_addr_lo = 1585 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1586 rcb->bge_hostaddr.bge_addr_hi = 1587 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1588 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1589 sc->bge_cdata.bge_rx_jumbo_ring_map, 1590 BUS_DMASYNC_PREREAD); 1591 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1592 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1593 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1594 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1595 rcb->bge_hostaddr.bge_addr_hi); 1596 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1597 rcb->bge_hostaddr.bge_addr_lo); 1598 1599 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1600 rcb->bge_maxlen_flags); 1601 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1602 1603 /* Set up dummy disabled mini ring RCB */ 1604 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1605 rcb->bge_maxlen_flags = 1606 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1607 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1608 rcb->bge_maxlen_flags); 1609 } 1610 1611 /* 1612 * Set the BD ring replentish thresholds. The recommended 1613 * values are 1/8th the number of descriptors allocated to 1614 * each ring. 1615 * XXX The 5754 requires a lower threshold, so it might be a 1616 * requirement of all 575x family chips. The Linux driver sets 1617 * the lower threshold for all 5705 family chips as well, but there 1618 * are reports that it might not need to be so strict. 1619 * 1620 * XXX Linux does some extra fiddling here for the 5906 parts as 1621 * well. 1622 */ 1623 if (BGE_IS_5705_PLUS(sc)) 1624 val = 8; 1625 else 1626 val = BGE_STD_RX_RING_CNT / 8; 1627 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1628 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1629 1630 /* 1631 * Disable all unused send rings by setting the 'ring disabled' 1632 * bit in the flags field of all the TX send ring control blocks. 1633 * These are located in NIC memory. 1634 */ 1635 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1636 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1637 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1638 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1639 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1640 vrcb += sizeof(struct bge_rcb); 1641 } 1642 1643 /* Configure TX RCB 0 (we use only the first ring) */ 1644 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1645 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1646 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1647 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1648 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1649 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1650 if (!(BGE_IS_5705_PLUS(sc))) 1651 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1652 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1653 1654 /* Disable all unused RX return rings */ 1655 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1656 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1657 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1658 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1659 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1660 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1661 BGE_RCB_FLAG_RING_DISABLED)); 1662 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1663 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1664 (i * (sizeof(uint64_t))), 0); 1665 vrcb += sizeof(struct bge_rcb); 1666 } 1667 1668 /* Initialize RX ring indexes */ 1669 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1670 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1671 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1672 1673 /* 1674 * Set up RX return ring 0 1675 * Note that the NIC address for RX return rings is 0x00000000. 1676 * The return rings live entirely within the host, so the 1677 * nicaddr field in the RCB isn't used. 1678 */ 1679 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1680 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1681 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1682 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1683 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1684 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1685 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1686 1687 /* Set random backoff seed for TX */ 1688 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1689 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1690 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1691 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1692 BGE_TX_BACKOFF_SEED_MASK); 1693 1694 /* Set inter-packet gap */ 1695 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1696 1697 /* 1698 * Specify which ring to use for packets that don't match 1699 * any RX rules. 1700 */ 1701 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1702 1703 /* 1704 * Configure number of RX lists. One interrupt distribution 1705 * list, sixteen active lists, one bad frames class. 1706 */ 1707 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1708 1709 /* Inialize RX list placement stats mask. */ 1710 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1711 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1712 1713 /* Disable host coalescing until we get it set up */ 1714 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1715 1716 /* Poll to make sure it's shut down. */ 1717 for (i = 0; i < BGE_TIMEOUT; i++) { 1718 DELAY(10); 1719 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1720 break; 1721 } 1722 1723 if (i == BGE_TIMEOUT) { 1724 device_printf(sc->bge_dev, 1725 "host coalescing engine failed to idle\n"); 1726 return (ENXIO); 1727 } 1728 1729 /* Set up host coalescing defaults */ 1730 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1731 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1732 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1733 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1734 if (!(BGE_IS_5705_PLUS(sc))) { 1735 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1736 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1737 } 1738 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1739 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1740 1741 /* Set up address of statistics block */ 1742 if (!(BGE_IS_5705_PLUS(sc))) { 1743 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1744 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1745 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1746 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1747 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1748 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1749 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1750 } 1751 1752 /* Set up address of status block */ 1753 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1754 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1755 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1756 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1757 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1758 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1759 1760 /* Set up status block size. */ 1761 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1762 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 1763 val = BGE_STATBLKSZ_FULL; 1764 else 1765 val = BGE_STATBLKSZ_32BYTE; 1766 1767 /* Turn on host coalescing state machine */ 1768 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1769 1770 /* Turn on RX BD completion state machine and enable attentions */ 1771 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1772 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1773 1774 /* Turn on RX list placement state machine */ 1775 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1776 1777 /* Turn on RX list selector state machine. */ 1778 if (!(BGE_IS_5705_PLUS(sc))) 1779 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1780 1781 /* Turn on DMA, clear stats */ 1782 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1783 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1784 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1785 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1786 ((sc->bge_flags & BGE_FLAG_TBI) ? 1787 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1788 1789 /* Set misc. local control, enable interrupts on attentions */ 1790 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1791 1792#ifdef notdef 1793 /* Assert GPIO pins for PHY reset */ 1794 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1795 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1796 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1797 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1798#endif 1799 1800 /* Turn on DMA completion state machine */ 1801 if (!(BGE_IS_5705_PLUS(sc))) 1802 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1803 1804 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1805 1806 /* Enable host coalescing bug fix. */ 1807 if (BGE_IS_5755_PLUS(sc)) 1808 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1809 1810 /* Turn on write DMA state machine */ 1811 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1812 DELAY(40); 1813 1814 /* Turn on read DMA state machine */ 1815 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1816 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1817 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1818 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1819 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1820 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1821 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1822 if (sc->bge_flags & BGE_FLAG_PCIE) 1823 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1824 if (sc->bge_flags & BGE_FLAG_TSO) 1825 val |= BGE_RDMAMODE_TSO4_ENABLE; 1826 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1827 DELAY(40); 1828 1829 /* Turn on RX data completion state machine */ 1830 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1831 1832 /* Turn on RX BD initiator state machine */ 1833 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1834 1835 /* Turn on RX data and RX BD initiator state machine */ 1836 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1837 1838 /* Turn on Mbuf cluster free state machine */ 1839 if (!(BGE_IS_5705_PLUS(sc))) 1840 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1841 1842 /* Turn on send BD completion state machine */ 1843 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1844 1845 /* Turn on send data completion state machine */ 1846 val = BGE_SDCMODE_ENABLE; 1847 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1848 val |= BGE_SDCMODE_CDELAY; 1849 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1850 1851 /* Turn on send data initiator state machine */ 1852 if (sc->bge_flags & BGE_FLAG_TSO) 1853 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1854 else 1855 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1856 1857 /* Turn on send BD initiator state machine */ 1858 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1859 1860 /* Turn on send BD selector state machine */ 1861 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1862 1863 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1864 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1865 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1866 1867 /* ack/clear link change events */ 1868 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1869 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1870 BGE_MACSTAT_LINK_CHANGED); 1871 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1872 1873 /* Enable PHY auto polling (for MII/GMII only) */ 1874 if (sc->bge_flags & BGE_FLAG_TBI) { 1875 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1876 } else { 1877 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1878 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1879 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1880 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1881 BGE_EVTENB_MI_INTERRUPT); 1882 } 1883 1884 /* 1885 * Clear any pending link state attention. 1886 * Otherwise some link state change events may be lost until attention 1887 * is cleared by bge_intr() -> bge_link_upd() sequence. 1888 * It's not necessary on newer BCM chips - perhaps enabling link 1889 * state change attentions implies clearing pending attention. 1890 */ 1891 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1892 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1893 BGE_MACSTAT_LINK_CHANGED); 1894 1895 /* Enable link state change attentions. */ 1896 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1897 1898 return (0); 1899} 1900 1901const struct bge_revision * 1902bge_lookup_rev(uint32_t chipid) 1903{ 1904 const struct bge_revision *br; 1905 1906 for (br = bge_revisions; br->br_name != NULL; br++) { 1907 if (br->br_chipid == chipid) 1908 return (br); 1909 } 1910 1911 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1912 if (br->br_chipid == BGE_ASICREV(chipid)) 1913 return (br); 1914 } 1915 1916 return (NULL); 1917} 1918 1919const struct bge_vendor * 1920bge_lookup_vendor(uint16_t vid) 1921{ 1922 const struct bge_vendor *v; 1923 1924 for (v = bge_vendors; v->v_name != NULL; v++) 1925 if (v->v_id == vid) 1926 return (v); 1927 1928 panic("%s: unknown vendor %d", __func__, vid); 1929 return (NULL); 1930} 1931 1932/* 1933 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1934 * against our list and return its name if we find a match. 1935 * 1936 * Note that since the Broadcom controller contains VPD support, we 1937 * try to get the device name string from the controller itself instead 1938 * of the compiled-in string. It guarantees we'll always announce the 1939 * right product name. We fall back to the compiled-in string when 1940 * VPD is unavailable or corrupt. 1941 */ 1942static int 1943bge_probe(device_t dev) 1944{ 1945 const struct bge_type *t = bge_devs; 1946 struct bge_softc *sc = device_get_softc(dev); 1947 uint16_t vid, did; 1948 1949 sc->bge_dev = dev; 1950 vid = pci_get_vendor(dev); 1951 did = pci_get_device(dev); 1952 while(t->bge_vid != 0) { 1953 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1954 char model[64], buf[96]; 1955 const struct bge_revision *br; 1956 const struct bge_vendor *v; 1957 uint32_t id; 1958 1959 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1960 BGE_PCIMISCCTL_ASICREV_SHIFT; 1961 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 1962 id = pci_read_config(dev, 1963 BGE_PCI_PRODID_ASICREV, 4); 1964 br = bge_lookup_rev(id); 1965 v = bge_lookup_vendor(vid); 1966 { 1967#if __FreeBSD_version > 700024 1968 const char *pname; 1969 1970 if (bge_has_eaddr(sc) && 1971 pci_get_vpd_ident(dev, &pname) == 0) 1972 snprintf(model, 64, "%s", pname); 1973 else 1974#endif 1975 snprintf(model, 64, "%s %s", 1976 v->v_name, 1977 br != NULL ? br->br_name : 1978 "NetXtreme Ethernet Controller"); 1979 } 1980 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 1981 br != NULL ? "" : "unknown ", id); 1982 device_set_desc_copy(dev, buf); 1983 if (pci_get_subvendor(dev) == DELL_VENDORID) 1984 sc->bge_flags |= BGE_FLAG_NO_3LED; 1985 if (did == BCOM_DEVICEID_BCM5755M) 1986 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1987 return (0); 1988 } 1989 t++; 1990 } 1991 1992 return (ENXIO); 1993} 1994 1995static void 1996bge_dma_free(struct bge_softc *sc) 1997{ 1998 int i; 1999 2000 /* Destroy DMA maps for RX buffers. */ 2001 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2002 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2003 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2004 sc->bge_cdata.bge_rx_std_dmamap[i]); 2005 } 2006 if (sc->bge_cdata.bge_rx_std_sparemap) 2007 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2008 sc->bge_cdata.bge_rx_std_sparemap); 2009 2010 /* Destroy DMA maps for jumbo RX buffers. */ 2011 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2012 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2013 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2014 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2015 } 2016 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2017 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2018 sc->bge_cdata.bge_rx_jumbo_sparemap); 2019 2020 /* Destroy DMA maps for TX buffers. */ 2021 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2022 if (sc->bge_cdata.bge_tx_dmamap[i]) 2023 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2024 sc->bge_cdata.bge_tx_dmamap[i]); 2025 } 2026 2027 if (sc->bge_cdata.bge_rx_mtag) 2028 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2029 if (sc->bge_cdata.bge_tx_mtag) 2030 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2031 2032 2033 /* Destroy standard RX ring. */ 2034 if (sc->bge_cdata.bge_rx_std_ring_map) 2035 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2036 sc->bge_cdata.bge_rx_std_ring_map); 2037 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2038 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2039 sc->bge_ldata.bge_rx_std_ring, 2040 sc->bge_cdata.bge_rx_std_ring_map); 2041 2042 if (sc->bge_cdata.bge_rx_std_ring_tag) 2043 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2044 2045 /* Destroy jumbo RX ring. */ 2046 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2047 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2048 sc->bge_cdata.bge_rx_jumbo_ring_map); 2049 2050 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2051 sc->bge_ldata.bge_rx_jumbo_ring) 2052 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2053 sc->bge_ldata.bge_rx_jumbo_ring, 2054 sc->bge_cdata.bge_rx_jumbo_ring_map); 2055 2056 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2057 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2058 2059 /* Destroy RX return ring. */ 2060 if (sc->bge_cdata.bge_rx_return_ring_map) 2061 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2062 sc->bge_cdata.bge_rx_return_ring_map); 2063 2064 if (sc->bge_cdata.bge_rx_return_ring_map && 2065 sc->bge_ldata.bge_rx_return_ring) 2066 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2067 sc->bge_ldata.bge_rx_return_ring, 2068 sc->bge_cdata.bge_rx_return_ring_map); 2069 2070 if (sc->bge_cdata.bge_rx_return_ring_tag) 2071 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2072 2073 /* Destroy TX ring. */ 2074 if (sc->bge_cdata.bge_tx_ring_map) 2075 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2076 sc->bge_cdata.bge_tx_ring_map); 2077 2078 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2079 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2080 sc->bge_ldata.bge_tx_ring, 2081 sc->bge_cdata.bge_tx_ring_map); 2082 2083 if (sc->bge_cdata.bge_tx_ring_tag) 2084 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2085 2086 /* Destroy status block. */ 2087 if (sc->bge_cdata.bge_status_map) 2088 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2089 sc->bge_cdata.bge_status_map); 2090 2091 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2092 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2093 sc->bge_ldata.bge_status_block, 2094 sc->bge_cdata.bge_status_map); 2095 2096 if (sc->bge_cdata.bge_status_tag) 2097 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2098 2099 /* Destroy statistics block. */ 2100 if (sc->bge_cdata.bge_stats_map) 2101 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2102 sc->bge_cdata.bge_stats_map); 2103 2104 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2105 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2106 sc->bge_ldata.bge_stats, 2107 sc->bge_cdata.bge_stats_map); 2108 2109 if (sc->bge_cdata.bge_stats_tag) 2110 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2111 2112 /* Destroy the parent tag. */ 2113 if (sc->bge_cdata.bge_parent_tag) 2114 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2115} 2116 2117static int 2118bge_dma_alloc(device_t dev) 2119{ 2120 struct bge_dmamap_arg ctx; 2121 struct bge_softc *sc; 2122 bus_addr_t lowaddr; 2123 bus_size_t sbsz, txsegsz, txmaxsegsz; 2124 int i, error; 2125 2126 sc = device_get_softc(dev); 2127 2128 lowaddr = BUS_SPACE_MAXADDR; 2129 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2130 lowaddr = BGE_DMA_MAXADDR; 2131 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2132 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2133 /* 2134 * Allocate the parent bus DMA tag appropriate for PCI. 2135 */ 2136 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2137 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2138 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2139 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2140 2141 if (error != 0) { 2142 device_printf(sc->bge_dev, 2143 "could not allocate parent dma tag\n"); 2144 return (ENOMEM); 2145 } 2146 2147 /* 2148 * Create tag for Tx mbufs. 2149 */ 2150 if (sc->bge_flags & BGE_FLAG_TSO) { 2151 txsegsz = BGE_TSOSEG_SZ; 2152 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2153 } else { 2154 txsegsz = MCLBYTES; 2155 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2156 } 2157 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2158 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2159 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2160 &sc->bge_cdata.bge_tx_mtag); 2161 2162 if (error) { 2163 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2164 return (ENOMEM); 2165 } 2166 2167 /* 2168 * Create tag for Rx mbufs. 2169 */ 2170 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 2171 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2172 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2173 2174 if (error) { 2175 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2176 return (ENOMEM); 2177 } 2178 2179 /* Create DMA maps for RX buffers. */ 2180 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2181 &sc->bge_cdata.bge_rx_std_sparemap); 2182 if (error) { 2183 device_printf(sc->bge_dev, 2184 "can't create spare DMA map for RX\n"); 2185 return (ENOMEM); 2186 } 2187 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2188 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2189 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2190 if (error) { 2191 device_printf(sc->bge_dev, 2192 "can't create DMA map for RX\n"); 2193 return (ENOMEM); 2194 } 2195 } 2196 2197 /* Create DMA maps for TX buffers. */ 2198 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2199 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2200 &sc->bge_cdata.bge_tx_dmamap[i]); 2201 if (error) { 2202 device_printf(sc->bge_dev, 2203 "can't create DMA map for TX\n"); 2204 return (ENOMEM); 2205 } 2206 } 2207 2208 /* Create tag for standard RX ring. */ 2209 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2210 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2211 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2212 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2213 2214 if (error) { 2215 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2216 return (ENOMEM); 2217 } 2218 2219 /* Allocate DMA'able memory for standard RX ring. */ 2220 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2221 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2222 &sc->bge_cdata.bge_rx_std_ring_map); 2223 if (error) 2224 return (ENOMEM); 2225 2226 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2227 2228 /* Load the address of the standard RX ring. */ 2229 ctx.bge_maxsegs = 1; 2230 ctx.sc = sc; 2231 2232 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2233 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2234 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2235 2236 if (error) 2237 return (ENOMEM); 2238 2239 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2240 2241 /* Create tags for jumbo mbufs. */ 2242 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2243 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2244 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2245 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2246 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2247 if (error) { 2248 device_printf(sc->bge_dev, 2249 "could not allocate jumbo dma tag\n"); 2250 return (ENOMEM); 2251 } 2252 2253 /* Create tag for jumbo RX ring. */ 2254 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2255 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2256 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2257 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2258 2259 if (error) { 2260 device_printf(sc->bge_dev, 2261 "could not allocate jumbo ring dma tag\n"); 2262 return (ENOMEM); 2263 } 2264 2265 /* Allocate DMA'able memory for jumbo RX ring. */ 2266 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2267 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2268 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2269 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2270 if (error) 2271 return (ENOMEM); 2272 2273 /* Load the address of the jumbo RX ring. */ 2274 ctx.bge_maxsegs = 1; 2275 ctx.sc = sc; 2276 2277 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2278 sc->bge_cdata.bge_rx_jumbo_ring_map, 2279 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2280 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2281 2282 if (error) 2283 return (ENOMEM); 2284 2285 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2286 2287 /* Create DMA maps for jumbo RX buffers. */ 2288 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2289 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2290 if (error) { 2291 device_printf(sc->bge_dev, 2292 "can't create spare DMA map for jumbo RX\n"); 2293 return (ENOMEM); 2294 } 2295 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2296 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2297 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2298 if (error) { 2299 device_printf(sc->bge_dev, 2300 "can't create DMA map for jumbo RX\n"); 2301 return (ENOMEM); 2302 } 2303 } 2304 2305 } 2306 2307 /* Create tag for RX return ring. */ 2308 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2309 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2310 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2311 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2312 2313 if (error) { 2314 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2315 return (ENOMEM); 2316 } 2317 2318 /* Allocate DMA'able memory for RX return ring. */ 2319 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2320 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2321 &sc->bge_cdata.bge_rx_return_ring_map); 2322 if (error) 2323 return (ENOMEM); 2324 2325 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2326 BGE_RX_RTN_RING_SZ(sc)); 2327 2328 /* Load the address of the RX return ring. */ 2329 ctx.bge_maxsegs = 1; 2330 ctx.sc = sc; 2331 2332 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2333 sc->bge_cdata.bge_rx_return_ring_map, 2334 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2335 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2336 2337 if (error) 2338 return (ENOMEM); 2339 2340 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2341 2342 /* Create tag for TX ring. */ 2343 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2344 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2345 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2346 &sc->bge_cdata.bge_tx_ring_tag); 2347 2348 if (error) { 2349 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2350 return (ENOMEM); 2351 } 2352 2353 /* Allocate DMA'able memory for TX ring. */ 2354 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2355 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2356 &sc->bge_cdata.bge_tx_ring_map); 2357 if (error) 2358 return (ENOMEM); 2359 2360 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2361 2362 /* Load the address of the TX ring. */ 2363 ctx.bge_maxsegs = 1; 2364 ctx.sc = sc; 2365 2366 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2367 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2368 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2369 2370 if (error) 2371 return (ENOMEM); 2372 2373 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2374 2375 /* 2376 * Create tag for status block. 2377 * Because we only use single Tx/Rx/Rx return ring, use 2378 * minimum status block size except BCM5700 AX/BX which 2379 * seems to want to see full status block size regardless 2380 * of configured number of ring. 2381 */ 2382 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2383 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2384 sbsz = BGE_STATUS_BLK_SZ; 2385 else 2386 sbsz = 32; 2387 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2388 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2389 NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag); 2390 2391 if (error) { 2392 device_printf(sc->bge_dev, 2393 "could not allocate status dma tag\n"); 2394 return (ENOMEM); 2395 } 2396 2397 /* Allocate DMA'able memory for status block. */ 2398 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2399 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2400 &sc->bge_cdata.bge_status_map); 2401 if (error) 2402 return (ENOMEM); 2403 2404 bzero((char *)sc->bge_ldata.bge_status_block, sbsz); 2405 2406 /* Load the address of the status block. */ 2407 ctx.sc = sc; 2408 ctx.bge_maxsegs = 1; 2409 2410 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2411 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2412 sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2413 2414 if (error) 2415 return (ENOMEM); 2416 2417 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2418 2419 /* Create tag for statistics block. */ 2420 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2421 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2422 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2423 &sc->bge_cdata.bge_stats_tag); 2424 2425 if (error) { 2426 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2427 return (ENOMEM); 2428 } 2429 2430 /* Allocate DMA'able memory for statistics block. */ 2431 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2432 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2433 &sc->bge_cdata.bge_stats_map); 2434 if (error) 2435 return (ENOMEM); 2436 2437 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2438 2439 /* Load the address of the statstics block. */ 2440 ctx.sc = sc; 2441 ctx.bge_maxsegs = 1; 2442 2443 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2444 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2445 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2446 2447 if (error) 2448 return (ENOMEM); 2449 2450 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2451 2452 return (0); 2453} 2454 2455/* 2456 * Return true if this device has more than one port. 2457 */ 2458static int 2459bge_has_multiple_ports(struct bge_softc *sc) 2460{ 2461 device_t dev = sc->bge_dev; 2462 u_int b, d, f, fscan, s; 2463 2464 d = pci_get_domain(dev); 2465 b = pci_get_bus(dev); 2466 s = pci_get_slot(dev); 2467 f = pci_get_function(dev); 2468 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2469 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2470 return (1); 2471 return (0); 2472} 2473 2474/* 2475 * Return true if MSI can be used with this device. 2476 */ 2477static int 2478bge_can_use_msi(struct bge_softc *sc) 2479{ 2480 int can_use_msi = 0; 2481 2482 switch (sc->bge_asicrev) { 2483 case BGE_ASICREV_BCM5714_A0: 2484 case BGE_ASICREV_BCM5714: 2485 /* 2486 * Apparently, MSI doesn't work when these chips are 2487 * configured in single-port mode. 2488 */ 2489 if (bge_has_multiple_ports(sc)) 2490 can_use_msi = 1; 2491 break; 2492 case BGE_ASICREV_BCM5750: 2493 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2494 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2495 can_use_msi = 1; 2496 break; 2497 default: 2498 if (BGE_IS_575X_PLUS(sc)) 2499 can_use_msi = 1; 2500 } 2501 return (can_use_msi); 2502} 2503 2504static int 2505bge_attach(device_t dev) 2506{ 2507 struct ifnet *ifp; 2508 struct bge_softc *sc; 2509 uint32_t hwcfg = 0, misccfg; 2510 u_char eaddr[ETHER_ADDR_LEN]; 2511 int error, msicount, reg, rid, trys; 2512 2513 sc = device_get_softc(dev); 2514 sc->bge_dev = dev; 2515 2516 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2517 2518 /* 2519 * Map control/status registers. 2520 */ 2521 pci_enable_busmaster(dev); 2522 2523 rid = BGE_PCI_BAR0; 2524 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2525 RF_ACTIVE); 2526 2527 if (sc->bge_res == NULL) { 2528 device_printf (sc->bge_dev, "couldn't map memory\n"); 2529 error = ENXIO; 2530 goto fail; 2531 } 2532 2533 /* Save various chip information. */ 2534 sc->bge_chipid = 2535 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2536 BGE_PCIMISCCTL_ASICREV_SHIFT; 2537 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2538 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2539 4); 2540 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2541 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2542 2543 /* 2544 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2545 * 5705 A0 and A1 chips. 2546 */ 2547 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2548 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2549 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2550 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2551 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2552 2553 if (bge_has_eaddr(sc)) 2554 sc->bge_flags |= BGE_FLAG_EADDR; 2555 2556 /* Save chipset family. */ 2557 switch (sc->bge_asicrev) { 2558 case BGE_ASICREV_BCM5755: 2559 case BGE_ASICREV_BCM5761: 2560 case BGE_ASICREV_BCM5784: 2561 case BGE_ASICREV_BCM5785: 2562 case BGE_ASICREV_BCM5787: 2563 case BGE_ASICREV_BCM57780: 2564 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2565 BGE_FLAG_5705_PLUS; 2566 break; 2567 case BGE_ASICREV_BCM5700: 2568 case BGE_ASICREV_BCM5701: 2569 case BGE_ASICREV_BCM5703: 2570 case BGE_ASICREV_BCM5704: 2571 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2572 break; 2573 case BGE_ASICREV_BCM5714_A0: 2574 case BGE_ASICREV_BCM5780: 2575 case BGE_ASICREV_BCM5714: 2576 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2577 /* FALLTHROUGH */ 2578 case BGE_ASICREV_BCM5750: 2579 case BGE_ASICREV_BCM5752: 2580 case BGE_ASICREV_BCM5906: 2581 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2582 /* FALLTHROUGH */ 2583 case BGE_ASICREV_BCM5705: 2584 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2585 break; 2586 } 2587 2588 /* Set various bug flags. */ 2589 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2590 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2591 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2592 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2593 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2594 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2595 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2596 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2597 if (BGE_IS_5705_PLUS(sc) && 2598 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2599 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2600 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2601 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2602 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2603 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0) 2604 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2605 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2606 sc->bge_flags |= BGE_FLAG_BER_BUG; 2607 } 2608 2609 /* 2610 * All controllers that are not 5755 or higher have 4GB 2611 * boundary DMA bug. 2612 * Whenever an address crosses a multiple of the 4GB boundary 2613 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2614 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2615 * state machine will lockup and cause the device to hang. 2616 */ 2617 if (BGE_IS_5755_PLUS(sc) == 0) 2618 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2619 2620 /* 2621 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2622 * but I do not know the DEVICEID for the 5788M. 2623 */ 2624 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2625 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2626 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2627 sc->bge_flags |= BGE_FLAG_5788; 2628 2629 /* 2630 * Some controllers seem to require a special firmware to use 2631 * TSO. But the firmware is not available to FreeBSD and Linux 2632 * claims that the TSO performed by the firmware is slower than 2633 * hardware based TSO. Moreover the firmware based TSO has one 2634 * known bug which can't handle TSO if ethernet header + IP/TCP 2635 * header is greater than 80 bytes. The workaround for the TSO 2636 * bug exist but it seems it's too expensive than not using 2637 * TSO at all. Some hardwares also have the TSO bug so limit 2638 * the TSO to the controllers that are not affected TSO issues 2639 * (e.g. 5755 or higher). 2640 */ 2641 if (BGE_IS_5755_PLUS(sc)) 2642 sc->bge_flags |= BGE_FLAG_TSO; 2643 2644 /* 2645 * Check if this is a PCI-X or PCI Express device. 2646 */ 2647 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2648 /* 2649 * Found a PCI Express capabilities register, this 2650 * must be a PCI Express device. 2651 */ 2652 sc->bge_flags |= BGE_FLAG_PCIE; 2653 sc->bge_expcap = reg; 2654 bge_set_max_readrq(sc); 2655 } else { 2656 /* 2657 * Check if the device is in PCI-X Mode. 2658 * (This bit is not valid on PCI Express controllers.) 2659 */ 2660 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 2661 sc->bge_pcixcap = reg; 2662 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2663 BGE_PCISTATE_PCI_BUSMODE) == 0) 2664 sc->bge_flags |= BGE_FLAG_PCIX; 2665 } 2666 2667 /* 2668 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2669 * not actually a MAC controller bug but an issue with the embedded 2670 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2671 */ 2672 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2673 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2674 /* 2675 * Allocate the interrupt, using MSI if possible. These devices 2676 * support 8 MSI messages, but only the first one is used in 2677 * normal operation. 2678 */ 2679 rid = 0; 2680 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) != 0) { 2681 sc->bge_msicap = reg; 2682 if (bge_can_use_msi(sc)) { 2683 msicount = pci_msi_count(dev); 2684 if (msicount > 1) 2685 msicount = 1; 2686 } else 2687 msicount = 0; 2688 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2689 rid = 1; 2690 sc->bge_flags |= BGE_FLAG_MSI; 2691 } 2692 } 2693 2694 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2695 RF_SHAREABLE | RF_ACTIVE); 2696 2697 if (sc->bge_irq == NULL) { 2698 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2699 error = ENXIO; 2700 goto fail; 2701 } 2702 2703 if (bootverbose) 2704 device_printf(dev, 2705 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2706 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2707 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2708 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2709 2710 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2711 2712 /* Try to reset the chip. */ 2713 if (bge_reset(sc)) { 2714 device_printf(sc->bge_dev, "chip reset failed\n"); 2715 error = ENXIO; 2716 goto fail; 2717 } 2718 2719 sc->bge_asf_mode = 0; 2720 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2721 == BGE_MAGIC_NUMBER)) { 2722 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2723 & BGE_HWCFG_ASF) { 2724 sc->bge_asf_mode |= ASF_ENABLE; 2725 sc->bge_asf_mode |= ASF_STACKUP; 2726 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2727 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2728 } 2729 } 2730 } 2731 2732 /* Try to reset the chip again the nice way. */ 2733 bge_stop_fw(sc); 2734 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2735 if (bge_reset(sc)) { 2736 device_printf(sc->bge_dev, "chip reset failed\n"); 2737 error = ENXIO; 2738 goto fail; 2739 } 2740 2741 bge_sig_legacy(sc, BGE_RESET_STOP); 2742 bge_sig_post_reset(sc, BGE_RESET_STOP); 2743 2744 if (bge_chipinit(sc)) { 2745 device_printf(sc->bge_dev, "chip initialization failed\n"); 2746 error = ENXIO; 2747 goto fail; 2748 } 2749 2750 error = bge_get_eaddr(sc, eaddr); 2751 if (error) { 2752 device_printf(sc->bge_dev, 2753 "failed to read station address\n"); 2754 error = ENXIO; 2755 goto fail; 2756 } 2757 2758 /* 5705 limits RX return ring to 512 entries. */ 2759 if (BGE_IS_5705_PLUS(sc)) 2760 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2761 else 2762 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2763 2764 if (bge_dma_alloc(dev)) { 2765 device_printf(sc->bge_dev, 2766 "failed to allocate DMA resources\n"); 2767 error = ENXIO; 2768 goto fail; 2769 } 2770 2771 /* Set default tuneable values. */ 2772 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2773 sc->bge_rx_coal_ticks = 150; 2774 sc->bge_tx_coal_ticks = 150; 2775 sc->bge_rx_max_coal_bds = 10; 2776 sc->bge_tx_max_coal_bds = 10; 2777 2778 /* Set up ifnet structure */ 2779 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2780 if (ifp == NULL) { 2781 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2782 error = ENXIO; 2783 goto fail; 2784 } 2785 ifp->if_softc = sc; 2786 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2787 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2788 ifp->if_ioctl = bge_ioctl; 2789 ifp->if_start = bge_start; 2790 ifp->if_init = bge_init; 2791 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2792 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2793 IFQ_SET_READY(&ifp->if_snd); 2794 ifp->if_hwassist = BGE_CSUM_FEATURES; 2795 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2796 IFCAP_VLAN_MTU; 2797 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2798 ifp->if_hwassist |= CSUM_TSO; 2799 ifp->if_capabilities |= IFCAP_TSO4; 2800 } 2801#ifdef IFCAP_VLAN_HWCSUM 2802 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2803#endif 2804 ifp->if_capenable = ifp->if_capabilities; 2805#ifdef DEVICE_POLLING 2806 ifp->if_capabilities |= IFCAP_POLLING; 2807#endif 2808 2809 /* 2810 * 5700 B0 chips do not support checksumming correctly due 2811 * to hardware bugs. 2812 */ 2813 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2814 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2815 ifp->if_capenable &= ~IFCAP_HWCSUM; 2816 ifp->if_hwassist = 0; 2817 } 2818 2819 /* 2820 * Figure out what sort of media we have by checking the 2821 * hardware config word in the first 32k of NIC internal memory, 2822 * or fall back to examining the EEPROM if necessary. 2823 * Note: on some BCM5700 cards, this value appears to be unset. 2824 * If that's the case, we have to rely on identifying the NIC 2825 * by its PCI subsystem ID, as we do below for the SysKonnect 2826 * SK-9D41. 2827 */ 2828 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2829 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2830 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2831 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2832 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2833 sizeof(hwcfg))) { 2834 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2835 error = ENXIO; 2836 goto fail; 2837 } 2838 hwcfg = ntohl(hwcfg); 2839 } 2840 2841 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2842 sc->bge_flags |= BGE_FLAG_TBI; 2843 2844 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2845 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2846 sc->bge_flags |= BGE_FLAG_TBI; 2847 2848 if (sc->bge_flags & BGE_FLAG_TBI) { 2849 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2850 bge_ifmedia_sts); 2851 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2852 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2853 0, NULL); 2854 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2855 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2856 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2857 } else { 2858 /* 2859 * Do transceiver setup and tell the firmware the 2860 * driver is down so we can try to get access the 2861 * probe if ASF is running. Retry a couple of times 2862 * if we get a conflict with the ASF firmware accessing 2863 * the PHY. 2864 */ 2865 trys = 0; 2866 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2867again: 2868 bge_asf_driver_up(sc); 2869 2870 if (mii_phy_probe(dev, &sc->bge_miibus, 2871 bge_ifmedia_upd, bge_ifmedia_sts)) { 2872 if (trys++ < 4) { 2873 device_printf(sc->bge_dev, "Try again\n"); 2874 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2875 BMCR_RESET); 2876 goto again; 2877 } 2878 2879 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2880 error = ENXIO; 2881 goto fail; 2882 } 2883 2884 /* 2885 * Now tell the firmware we are going up after probing the PHY 2886 */ 2887 if (sc->bge_asf_mode & ASF_STACKUP) 2888 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2889 } 2890 2891 /* 2892 * When using the BCM5701 in PCI-X mode, data corruption has 2893 * been observed in the first few bytes of some received packets. 2894 * Aligning the packet buffer in memory eliminates the corruption. 2895 * Unfortunately, this misaligns the packet payloads. On platforms 2896 * which do not support unaligned accesses, we will realign the 2897 * payloads by copying the received packets. 2898 */ 2899 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2900 sc->bge_flags & BGE_FLAG_PCIX) 2901 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2902 2903 /* 2904 * Call MI attach routine. 2905 */ 2906 ether_ifattach(ifp, eaddr); 2907 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2908 2909 /* Tell upper layer we support long frames. */ 2910 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2911 2912 /* 2913 * Hookup IRQ last. 2914 */ 2915#if __FreeBSD_version > 700030 2916 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 2917 /* Take advantage of single-shot MSI. */ 2918 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 2919 taskqueue_thread_enqueue, &sc->bge_tq); 2920 if (sc->bge_tq == NULL) { 2921 device_printf(dev, "could not create taskqueue.\n"); 2922 ether_ifdetach(ifp); 2923 error = ENXIO; 2924 goto fail; 2925 } 2926 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 2927 device_get_nameunit(sc->bge_dev)); 2928 error = bus_setup_intr(dev, sc->bge_irq, 2929 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 2930 &sc->bge_intrhand); 2931 if (error) 2932 ether_ifdetach(ifp); 2933 } else 2934 error = bus_setup_intr(dev, sc->bge_irq, 2935 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 2936 &sc->bge_intrhand); 2937#else 2938 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2939 bge_intr, sc, &sc->bge_intrhand); 2940#endif 2941 2942 if (error) { 2943 bge_detach(dev); 2944 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2945 } 2946 2947 bge_add_sysctls(sc); 2948 2949 return (0); 2950 2951fail: 2952 bge_release_resources(sc); 2953 2954 return (error); 2955} 2956 2957static int 2958bge_detach(device_t dev) 2959{ 2960 struct bge_softc *sc; 2961 struct ifnet *ifp; 2962 2963 sc = device_get_softc(dev); 2964 ifp = sc->bge_ifp; 2965 2966#ifdef DEVICE_POLLING 2967 if (ifp->if_capenable & IFCAP_POLLING) 2968 ether_poll_deregister(ifp); 2969#endif 2970 2971 BGE_LOCK(sc); 2972 bge_stop(sc); 2973 bge_reset(sc); 2974 BGE_UNLOCK(sc); 2975 2976 callout_drain(&sc->bge_stat_ch); 2977 2978 if (sc->bge_tq) 2979 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 2980 ether_ifdetach(ifp); 2981 2982 if (sc->bge_flags & BGE_FLAG_TBI) { 2983 ifmedia_removeall(&sc->bge_ifmedia); 2984 } else { 2985 bus_generic_detach(dev); 2986 device_delete_child(dev, sc->bge_miibus); 2987 } 2988 2989 bge_release_resources(sc); 2990 2991 return (0); 2992} 2993 2994static void 2995bge_release_resources(struct bge_softc *sc) 2996{ 2997 device_t dev; 2998 2999 dev = sc->bge_dev; 3000 3001 if (sc->bge_tq != NULL) 3002 taskqueue_free(sc->bge_tq); 3003 3004 if (sc->bge_intrhand != NULL) 3005 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3006 3007 if (sc->bge_irq != NULL) 3008 bus_release_resource(dev, SYS_RES_IRQ, 3009 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3010 3011 if (sc->bge_flags & BGE_FLAG_MSI) 3012 pci_release_msi(dev); 3013 3014 if (sc->bge_res != NULL) 3015 bus_release_resource(dev, SYS_RES_MEMORY, 3016 BGE_PCI_BAR0, sc->bge_res); 3017 3018 if (sc->bge_ifp != NULL) 3019 if_free(sc->bge_ifp); 3020 3021 bge_dma_free(sc); 3022 3023 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3024 BGE_LOCK_DESTROY(sc); 3025} 3026 3027static int 3028bge_reset(struct bge_softc *sc) 3029{ 3030 device_t dev; 3031 uint32_t cachesize, command, pcistate, reset, val; 3032 void (*write_op)(struct bge_softc *, int, int); 3033 uint16_t devctl; 3034 int i; 3035 3036 dev = sc->bge_dev; 3037 3038 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3039 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3040 if (sc->bge_flags & BGE_FLAG_PCIE) 3041 write_op = bge_writemem_direct; 3042 else 3043 write_op = bge_writemem_ind; 3044 } else 3045 write_op = bge_writereg_ind; 3046 3047 /* Save some important PCI state. */ 3048 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3049 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3050 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3051 3052 pci_write_config(dev, BGE_PCI_MISC_CTL, 3053 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3054 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3055 3056 /* Disable fastboot on controllers that support it. */ 3057 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3058 BGE_IS_5755_PLUS(sc)) { 3059 if (bootverbose) 3060 device_printf(sc->bge_dev, "Disabling fastboot\n"); 3061 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3062 } 3063 3064 /* 3065 * Write the magic number to SRAM at offset 0xB50. 3066 * When firmware finishes its initialization it will 3067 * write ~BGE_MAGIC_NUMBER to the same location. 3068 */ 3069 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3070 3071 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3072 3073 /* XXX: Broadcom Linux driver. */ 3074 if (sc->bge_flags & BGE_FLAG_PCIE) { 3075 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3076 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3077 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3078 /* Prevent PCIE link training during global reset */ 3079 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3080 reset |= 1 << 29; 3081 } 3082 } 3083 3084 /* 3085 * Set GPHY Power Down Override to leave GPHY 3086 * powered up in D0 uninitialized. 3087 */ 3088 if (BGE_IS_5705_PLUS(sc)) 3089 reset |= 0x04000000; 3090 3091 /* Issue global reset */ 3092 write_op(sc, BGE_MISC_CFG, reset); 3093 3094 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3095 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3096 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3097 val | BGE_VCPU_STATUS_DRV_RESET); 3098 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3099 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3100 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3101 } 3102 3103 DELAY(1000); 3104 3105 /* XXX: Broadcom Linux driver. */ 3106 if (sc->bge_flags & BGE_FLAG_PCIE) { 3107 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3108 DELAY(500000); /* wait for link training to complete */ 3109 val = pci_read_config(dev, 0xC4, 4); 3110 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3111 } 3112 devctl = pci_read_config(dev, 3113 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3114 /* Clear enable no snoop and disable relaxed ordering. */ 3115 devctl &= ~(0x0010 | 0x0800); 3116 /* Set PCIE max payload size to 128. */ 3117 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3118 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3119 devctl, 2); 3120 /* Clear error status. */ 3121 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3122 0, 2); 3123 } 3124 3125 /* Reset some of the PCI state that got zapped by reset. */ 3126 pci_write_config(dev, BGE_PCI_MISC_CTL, 3127 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3128 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3129 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3130 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3131 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3132 3133 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 3134 if (BGE_IS_5714_FAMILY(sc)) { 3135 /* This chip disables MSI on reset. */ 3136 if (sc->bge_flags & BGE_FLAG_MSI) { 3137 val = pci_read_config(dev, 3138 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3139 pci_write_config(dev, 3140 sc->bge_msicap + PCIR_MSI_CTRL, 3141 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3142 val = CSR_READ_4(sc, BGE_MSI_MODE); 3143 CSR_WRITE_4(sc, BGE_MSI_MODE, 3144 val | BGE_MSIMODE_ENABLE); 3145 } 3146 val = CSR_READ_4(sc, BGE_MARB_MODE); 3147 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3148 } else 3149 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3150 3151 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3152 for (i = 0; i < BGE_TIMEOUT; i++) { 3153 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3154 if (val & BGE_VCPU_STATUS_INIT_DONE) 3155 break; 3156 DELAY(100); 3157 } 3158 if (i == BGE_TIMEOUT) { 3159 device_printf(sc->bge_dev, "reset timed out\n"); 3160 return (1); 3161 } 3162 } else { 3163 /* 3164 * Poll until we see the 1's complement of the magic number. 3165 * This indicates that the firmware initialization is complete. 3166 * We expect this to fail if no chip containing the Ethernet 3167 * address is fitted though. 3168 */ 3169 for (i = 0; i < BGE_TIMEOUT; i++) { 3170 DELAY(10); 3171 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3172 if (val == ~BGE_MAGIC_NUMBER) 3173 break; 3174 } 3175 3176 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3177 device_printf(sc->bge_dev, "firmware handshake timed out, " 3178 "found 0x%08x\n", val); 3179 } 3180 3181 /* 3182 * XXX Wait for the value of the PCISTATE register to 3183 * return to its original pre-reset state. This is a 3184 * fairly good indicator of reset completion. If we don't 3185 * wait for the reset to fully complete, trying to read 3186 * from the device's non-PCI registers may yield garbage 3187 * results. 3188 */ 3189 for (i = 0; i < BGE_TIMEOUT; i++) { 3190 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3191 break; 3192 DELAY(10); 3193 } 3194 3195 if (sc->bge_flags & BGE_FLAG_PCIE) { 3196 reset = bge_readmem_ind(sc, 0x7C00); 3197 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 3198 } 3199 3200 /* Fix up byte swapping. */ 3201 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3202 BGE_MODECTL_BYTESWAP_DATA); 3203 3204 /* Tell the ASF firmware we are up */ 3205 if (sc->bge_asf_mode & ASF_STACKUP) 3206 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3207 3208 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3209 3210 /* 3211 * The 5704 in TBI mode apparently needs some special 3212 * adjustment to insure the SERDES drive level is set 3213 * to 1.2V. 3214 */ 3215 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3216 sc->bge_flags & BGE_FLAG_TBI) { 3217 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3218 val = (val & ~0xFFF) | 0x880; 3219 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3220 } 3221 3222 /* XXX: Broadcom Linux driver. */ 3223 if (sc->bge_flags & BGE_FLAG_PCIE && 3224 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3225 val = CSR_READ_4(sc, 0x7C00); 3226 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3227 } 3228 DELAY(10000); 3229 3230 return(0); 3231} 3232 3233/* 3234 * Frame reception handling. This is called if there's a frame 3235 * on the receive return list. 3236 * 3237 * Note: we have to be able to handle two possibilities here: 3238 * 1) the frame is from the jumbo receive ring 3239 * 2) the frame is from the standard receive ring 3240 */ 3241 3242static int 3243bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3244{ 3245 struct ifnet *ifp; 3246 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3247 uint16_t rx_cons; 3248 3249 rx_cons = sc->bge_rx_saved_considx; 3250 3251 /* Nothing to do. */ 3252 if (rx_cons == rx_prod) 3253 return (rx_npkts); 3254 3255 ifp = sc->bge_ifp; 3256 3257 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3258 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3259 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3260 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3261 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3262 (MCLBYTES - ETHER_ALIGN)) 3263 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3264 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3265 3266 while (rx_cons != rx_prod) { 3267 struct bge_rx_bd *cur_rx; 3268 uint32_t rxidx; 3269 struct mbuf *m = NULL; 3270 uint16_t vlan_tag = 0; 3271 int have_tag = 0; 3272 3273#ifdef DEVICE_POLLING 3274 if (ifp->if_capenable & IFCAP_POLLING) { 3275 if (sc->rxcycles <= 0) 3276 break; 3277 sc->rxcycles--; 3278 } 3279#endif 3280 3281 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3282 3283 rxidx = cur_rx->bge_idx; 3284 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3285 3286 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3287 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3288 have_tag = 1; 3289 vlan_tag = cur_rx->bge_vlan_tag; 3290 } 3291 3292 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3293 jumbocnt++; 3294 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3295 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3296 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3297 continue; 3298 } 3299 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3300 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3301 ifp->if_iqdrops++; 3302 continue; 3303 } 3304 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3305 } else { 3306 stdcnt++; 3307 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3308 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3309 continue; 3310 } 3311 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3312 if (bge_newbuf_std(sc, rxidx) != 0) { 3313 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3314 ifp->if_iqdrops++; 3315 continue; 3316 } 3317 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3318 } 3319 3320 ifp->if_ipackets++; 3321#ifndef __NO_STRICT_ALIGNMENT 3322 /* 3323 * For architectures with strict alignment we must make sure 3324 * the payload is aligned. 3325 */ 3326 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3327 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3328 cur_rx->bge_len); 3329 m->m_data += ETHER_ALIGN; 3330 } 3331#endif 3332 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3333 m->m_pkthdr.rcvif = ifp; 3334 3335 if (ifp->if_capenable & IFCAP_RXCSUM) { 3336 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3337 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3338 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3339 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3340 } 3341 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3342 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3343 m->m_pkthdr.csum_data = 3344 cur_rx->bge_tcp_udp_csum; 3345 m->m_pkthdr.csum_flags |= 3346 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3347 } 3348 } 3349 3350 /* 3351 * If we received a packet with a vlan tag, 3352 * attach that information to the packet. 3353 */ 3354 if (have_tag) { 3355#if __FreeBSD_version > 700022 3356 m->m_pkthdr.ether_vtag = vlan_tag; 3357 m->m_flags |= M_VLANTAG; 3358#else 3359 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3360 if (m == NULL) 3361 continue; 3362#endif 3363 } 3364 3365 if (holdlck != 0) { 3366 BGE_UNLOCK(sc); 3367 (*ifp->if_input)(ifp, m); 3368 BGE_LOCK(sc); 3369 } else 3370 (*ifp->if_input)(ifp, m); 3371 rx_npkts++; 3372 3373 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3374 return (rx_npkts); 3375 } 3376 3377 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3378 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3379 if (stdcnt > 0) 3380 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3381 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3382 3383 if (jumbocnt > 0) 3384 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3385 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3386 3387 sc->bge_rx_saved_considx = rx_cons; 3388 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3389 if (stdcnt) 3390 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3391 if (jumbocnt) 3392 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3393#ifdef notyet 3394 /* 3395 * This register wraps very quickly under heavy packet drops. 3396 * If you need correct statistics, you can enable this check. 3397 */ 3398 if (BGE_IS_5705_PLUS(sc)) 3399 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3400#endif 3401 return (rx_npkts); 3402} 3403 3404static void 3405bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3406{ 3407 struct bge_tx_bd *cur_tx = NULL; 3408 struct ifnet *ifp; 3409 3410 BGE_LOCK_ASSERT(sc); 3411 3412 /* Nothing to do. */ 3413 if (sc->bge_tx_saved_considx == tx_cons) 3414 return; 3415 3416 ifp = sc->bge_ifp; 3417 3418 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3419 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3420 /* 3421 * Go through our tx ring and free mbufs for those 3422 * frames that have been sent. 3423 */ 3424 while (sc->bge_tx_saved_considx != tx_cons) { 3425 uint32_t idx = 0; 3426 3427 idx = sc->bge_tx_saved_considx; 3428 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3429 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3430 ifp->if_opackets++; 3431 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3432 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3433 sc->bge_cdata.bge_tx_dmamap[idx], 3434 BUS_DMASYNC_POSTWRITE); 3435 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3436 sc->bge_cdata.bge_tx_dmamap[idx]); 3437 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3438 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3439 } 3440 sc->bge_txcnt--; 3441 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3442 } 3443 3444 if (cur_tx != NULL) 3445 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3446 if (sc->bge_txcnt == 0) 3447 sc->bge_timer = 0; 3448} 3449 3450#ifdef DEVICE_POLLING 3451static int 3452bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3453{ 3454 struct bge_softc *sc = ifp->if_softc; 3455 uint16_t rx_prod, tx_cons; 3456 uint32_t statusword; 3457 int rx_npkts = 0; 3458 3459 BGE_LOCK(sc); 3460 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3461 BGE_UNLOCK(sc); 3462 return (rx_npkts); 3463 } 3464 3465 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3466 sc->bge_cdata.bge_status_map, 3467 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3468 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3469 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3470 3471 statusword = atomic_readandclear_32( 3472 &sc->bge_ldata.bge_status_block->bge_status); 3473 3474 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3475 sc->bge_cdata.bge_status_map, 3476 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3477 3478 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3479 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3480 sc->bge_link_evt++; 3481 3482 if (cmd == POLL_AND_CHECK_STATUS) 3483 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3484 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3485 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3486 bge_link_upd(sc); 3487 3488 sc->rxcycles = count; 3489 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3490 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3491 BGE_UNLOCK(sc); 3492 return (rx_npkts); 3493 } 3494 bge_txeof(sc, tx_cons); 3495 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3496 bge_start_locked(ifp); 3497 3498 BGE_UNLOCK(sc); 3499 return (rx_npkts); 3500} 3501#endif /* DEVICE_POLLING */ 3502 3503static int 3504bge_msi_intr(void *arg) 3505{ 3506 struct bge_softc *sc; 3507 3508 sc = (struct bge_softc *)arg; 3509 /* 3510 * This interrupt is not shared and controller already 3511 * disabled further interrupt. 3512 */ 3513 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3514 return (FILTER_HANDLED); 3515} 3516 3517static void 3518bge_intr_task(void *arg, int pending) 3519{ 3520 struct bge_softc *sc; 3521 struct ifnet *ifp; 3522 uint32_t status; 3523 uint16_t rx_prod, tx_cons; 3524 3525 sc = (struct bge_softc *)arg; 3526 ifp = sc->bge_ifp; 3527 3528 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3529 return; 3530 3531 /* Get updated status block. */ 3532 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3533 sc->bge_cdata.bge_status_map, 3534 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3535 3536 /* Save producer/consumer indexess. */ 3537 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3538 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3539 status = sc->bge_ldata.bge_status_block->bge_status; 3540 sc->bge_ldata.bge_status_block->bge_status = 0; 3541 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3542 sc->bge_cdata.bge_status_map, 3543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3544 /* Let controller work. */ 3545 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3546 3547 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) { 3548 BGE_LOCK(sc); 3549 bge_link_upd(sc); 3550 BGE_UNLOCK(sc); 3551 } 3552 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3553 /* Check RX return ring producer/consumer. */ 3554 bge_rxeof(sc, rx_prod, 0); 3555 } 3556 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3557 BGE_LOCK(sc); 3558 /* Check TX ring producer/consumer. */ 3559 bge_txeof(sc, tx_cons); 3560 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3561 bge_start_locked(ifp); 3562 BGE_UNLOCK(sc); 3563 } 3564} 3565 3566static void 3567bge_intr(void *xsc) 3568{ 3569 struct bge_softc *sc; 3570 struct ifnet *ifp; 3571 uint32_t statusword; 3572 uint16_t rx_prod, tx_cons; 3573 3574 sc = xsc; 3575 3576 BGE_LOCK(sc); 3577 3578 ifp = sc->bge_ifp; 3579 3580#ifdef DEVICE_POLLING 3581 if (ifp->if_capenable & IFCAP_POLLING) { 3582 BGE_UNLOCK(sc); 3583 return; 3584 } 3585#endif 3586 3587 /* 3588 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3589 * disable interrupts by writing nonzero like we used to, since with 3590 * our current organization this just gives complications and 3591 * pessimizations for re-enabling interrupts. We used to have races 3592 * instead of the necessary complications. Disabling interrupts 3593 * would just reduce the chance of a status update while we are 3594 * running (by switching to the interrupt-mode coalescence 3595 * parameters), but this chance is already very low so it is more 3596 * efficient to get another interrupt than prevent it. 3597 * 3598 * We do the ack first to ensure another interrupt if there is a 3599 * status update after the ack. We don't check for the status 3600 * changing later because it is more efficient to get another 3601 * interrupt than prevent it, not quite as above (not checking is 3602 * a smaller optimization than not toggling the interrupt enable, 3603 * since checking doesn't involve PCI accesses and toggling require 3604 * the status check). So toggling would probably be a pessimization 3605 * even with MSI. It would only be needed for using a task queue. 3606 */ 3607 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3608 3609 /* 3610 * Do the mandatory PCI flush as well as get the link status. 3611 */ 3612 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3613 3614 /* Make sure the descriptor ring indexes are coherent. */ 3615 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3616 sc->bge_cdata.bge_status_map, 3617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3618 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3619 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3620 sc->bge_ldata.bge_status_block->bge_status = 0; 3621 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3622 sc->bge_cdata.bge_status_map, 3623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3624 3625 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3626 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3627 statusword || sc->bge_link_evt) 3628 bge_link_upd(sc); 3629 3630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3631 /* Check RX return ring producer/consumer. */ 3632 bge_rxeof(sc, rx_prod, 1); 3633 } 3634 3635 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3636 /* Check TX ring producer/consumer. */ 3637 bge_txeof(sc, tx_cons); 3638 } 3639 3640 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3641 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3642 bge_start_locked(ifp); 3643 3644 BGE_UNLOCK(sc); 3645} 3646 3647static void 3648bge_asf_driver_up(struct bge_softc *sc) 3649{ 3650 if (sc->bge_asf_mode & ASF_STACKUP) { 3651 /* Send ASF heartbeat aprox. every 2s */ 3652 if (sc->bge_asf_count) 3653 sc->bge_asf_count --; 3654 else { 3655 sc->bge_asf_count = 5; 3656 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3657 BGE_FW_DRV_ALIVE); 3658 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3659 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3660 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3661 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3662 } 3663 } 3664} 3665 3666static void 3667bge_tick(void *xsc) 3668{ 3669 struct bge_softc *sc = xsc; 3670 struct mii_data *mii = NULL; 3671 3672 BGE_LOCK_ASSERT(sc); 3673 3674 /* Synchronize with possible callout reset/stop. */ 3675 if (callout_pending(&sc->bge_stat_ch) || 3676 !callout_active(&sc->bge_stat_ch)) 3677 return; 3678 3679 if (BGE_IS_5705_PLUS(sc)) 3680 bge_stats_update_regs(sc); 3681 else 3682 bge_stats_update(sc); 3683 3684 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3685 mii = device_get_softc(sc->bge_miibus); 3686 /* 3687 * Do not touch PHY if we have link up. This could break 3688 * IPMI/ASF mode or produce extra input errors 3689 * (extra errors was reported for bcm5701 & bcm5704). 3690 */ 3691 if (!sc->bge_link) 3692 mii_tick(mii); 3693 } else { 3694 /* 3695 * Since in TBI mode auto-polling can't be used we should poll 3696 * link status manually. Here we register pending link event 3697 * and trigger interrupt. 3698 */ 3699#ifdef DEVICE_POLLING 3700 /* In polling mode we poll link state in bge_poll(). */ 3701 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3702#endif 3703 { 3704 sc->bge_link_evt++; 3705 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3706 sc->bge_flags & BGE_FLAG_5788) 3707 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3708 else 3709 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3710 } 3711 } 3712 3713 bge_asf_driver_up(sc); 3714 bge_watchdog(sc); 3715 3716 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3717} 3718 3719static void 3720bge_stats_update_regs(struct bge_softc *sc) 3721{ 3722 struct ifnet *ifp; 3723 3724 ifp = sc->bge_ifp; 3725 3726 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3727 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3728 3729 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3730 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3731 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3732} 3733 3734static void 3735bge_stats_update(struct bge_softc *sc) 3736{ 3737 struct ifnet *ifp; 3738 bus_size_t stats; 3739 uint32_t cnt; /* current register value */ 3740 3741 ifp = sc->bge_ifp; 3742 3743 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3744 3745#define READ_STAT(sc, stats, stat) \ 3746 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3747 3748 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3749 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3750 sc->bge_tx_collisions = cnt; 3751 3752 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3753 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3754 sc->bge_rx_discards = cnt; 3755 3756 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3757 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3758 sc->bge_tx_discards = cnt; 3759 3760#undef READ_STAT 3761} 3762 3763/* 3764 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3765 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3766 * but when such padded frames employ the bge IP/TCP checksum offload, 3767 * the hardware checksum assist gives incorrect results (possibly 3768 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3769 * If we pad such runts with zeros, the onboard checksum comes out correct. 3770 */ 3771static __inline int 3772bge_cksum_pad(struct mbuf *m) 3773{ 3774 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3775 struct mbuf *last; 3776 3777 /* If there's only the packet-header and we can pad there, use it. */ 3778 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3779 M_TRAILINGSPACE(m) >= padlen) { 3780 last = m; 3781 } else { 3782 /* 3783 * Walk packet chain to find last mbuf. We will either 3784 * pad there, or append a new mbuf and pad it. 3785 */ 3786 for (last = m; last->m_next != NULL; last = last->m_next); 3787 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3788 /* Allocate new empty mbuf, pad it. Compact later. */ 3789 struct mbuf *n; 3790 3791 MGET(n, M_DONTWAIT, MT_DATA); 3792 if (n == NULL) 3793 return (ENOBUFS); 3794 n->m_len = 0; 3795 last->m_next = n; 3796 last = n; 3797 } 3798 } 3799 3800 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3801 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3802 last->m_len += padlen; 3803 m->m_pkthdr.len += padlen; 3804 3805 return (0); 3806} 3807 3808static struct mbuf * 3809bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 3810{ 3811 struct ether_header *eh; 3812 struct ip *ip; 3813 struct tcphdr *tcp; 3814 struct mbuf *n; 3815 uint16_t hlen; 3816 uint32_t ip_off, poff; 3817 3818 if (M_WRITABLE(m) == 0) { 3819 /* Get a writable copy. */ 3820 n = m_dup(m, M_DONTWAIT); 3821 m_freem(m); 3822 if (n == NULL) 3823 return (NULL); 3824 m = n; 3825 } 3826 ip_off = sizeof(struct ether_header); 3827 m = m_pullup(m, ip_off); 3828 if (m == NULL) 3829 return (NULL); 3830 eh = mtod(m, struct ether_header *); 3831 /* Check the existence of VLAN tag. */ 3832 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 3833 ip_off = sizeof(struct ether_vlan_header); 3834 m = m_pullup(m, ip_off); 3835 if (m == NULL) 3836 return (NULL); 3837 } 3838 m = m_pullup(m, ip_off + sizeof(struct ip)); 3839 if (m == NULL) 3840 return (NULL); 3841 ip = (struct ip *)(mtod(m, char *) + ip_off); 3842 poff = ip_off + (ip->ip_hl << 2); 3843 m = m_pullup(m, poff + sizeof(struct tcphdr)); 3844 if (m == NULL) 3845 return (NULL); 3846 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 3847 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off); 3848 if (m == NULL) 3849 return (NULL); 3850 /* 3851 * It seems controller doesn't modify IP length and TCP pseudo 3852 * checksum. These checksum computed by upper stack should be 0. 3853 */ 3854 *mss = m->m_pkthdr.tso_segsz; 3855 ip->ip_sum = 0; 3856 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 3857 /* Clear pseudo checksum computed by TCP stack. */ 3858 tcp->th_sum = 0; 3859 /* 3860 * Broadcom controllers uses different descriptor format for 3861 * TSO depending on ASIC revision. Due to TSO-capable firmware 3862 * license issue and lower performance of firmware based TSO 3863 * we only support hardware based TSO which is applicable for 3864 * BCM5755 or newer controllers. Hardware based TSO uses 11 3865 * bits to store MSS and upper 5 bits are used to store IP/TCP 3866 * header length(including IP/TCP options). The header length 3867 * is expressed as 32 bits unit. 3868 */ 3869 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 3870 *mss |= (hlen << 11); 3871 return (m); 3872} 3873 3874/* 3875 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3876 * pointers to descriptors. 3877 */ 3878static int 3879bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3880{ 3881 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3882 bus_dmamap_t map; 3883 struct bge_tx_bd *d; 3884 struct mbuf *m = *m_head; 3885 uint32_t idx = *txidx; 3886 uint16_t csum_flags, mss, vlan_tag; 3887 int nsegs, i, error; 3888 3889 csum_flags = 0; 3890 mss = 0; 3891 vlan_tag = 0; 3892 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 3893 *m_head = m = bge_setup_tso(sc, m, &mss); 3894 if (*m_head == NULL) 3895 return (ENOBUFS); 3896 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 3897 BGE_TXBDFLAG_CPU_POST_DMA; 3898 } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) { 3899 if (m->m_pkthdr.csum_flags & CSUM_IP) 3900 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3901 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3902 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3903 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3904 (error = bge_cksum_pad(m)) != 0) { 3905 m_freem(m); 3906 *m_head = NULL; 3907 return (error); 3908 } 3909 } 3910 if (m->m_flags & M_LASTFRAG) 3911 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3912 else if (m->m_flags & M_FRAG) 3913 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3914 } 3915 3916 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3917 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 3918 &nsegs, BUS_DMA_NOWAIT); 3919 if (error == EFBIG) { 3920 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 3921 if (m == NULL) { 3922 m_freem(*m_head); 3923 *m_head = NULL; 3924 return (ENOBUFS); 3925 } 3926 *m_head = m; 3927 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 3928 m, segs, &nsegs, BUS_DMA_NOWAIT); 3929 if (error) { 3930 m_freem(m); 3931 *m_head = NULL; 3932 return (error); 3933 } 3934 } else if (error != 0) 3935 return (error); 3936 3937 /* Check if we have enough free send BDs. */ 3938 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 3939 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 3940 return (ENOBUFS); 3941 } 3942 3943 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 3944 3945#if __FreeBSD_version > 700022 3946 if (m->m_flags & M_VLANTAG) { 3947 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3948 vlan_tag = m->m_pkthdr.ether_vtag; 3949 } 3950#else 3951 { 3952 struct m_tag *mtag; 3953 3954 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3955 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 3956 vlan_tag = VLAN_TAG_VALUE(mtag); 3957 } 3958 } 3959#endif 3960 for (i = 0; ; i++) { 3961 d = &sc->bge_ldata.bge_tx_ring[idx]; 3962 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3963 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3964 d->bge_len = segs[i].ds_len; 3965 d->bge_flags = csum_flags; 3966 d->bge_vlan_tag = vlan_tag; 3967 d->bge_mss = mss; 3968 if (i == nsegs - 1) 3969 break; 3970 BGE_INC(idx, BGE_TX_RING_CNT); 3971 } 3972 3973 /* Mark the last segment as end of packet... */ 3974 d->bge_flags |= BGE_TXBDFLAG_END; 3975 3976 /* 3977 * Insure that the map for this transmission 3978 * is placed at the array index of the last descriptor 3979 * in this chain. 3980 */ 3981 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3982 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3983 sc->bge_cdata.bge_tx_chain[idx] = m; 3984 sc->bge_txcnt += nsegs; 3985 3986 BGE_INC(idx, BGE_TX_RING_CNT); 3987 *txidx = idx; 3988 3989 return (0); 3990} 3991 3992/* 3993 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3994 * to the mbuf data regions directly in the transmit descriptors. 3995 */ 3996static void 3997bge_start_locked(struct ifnet *ifp) 3998{ 3999 struct bge_softc *sc; 4000 struct mbuf *m_head; 4001 uint32_t prodidx; 4002 int count; 4003 4004 sc = ifp->if_softc; 4005 BGE_LOCK_ASSERT(sc); 4006 4007 if (!sc->bge_link || 4008 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4009 IFF_DRV_RUNNING) 4010 return; 4011 4012 prodidx = sc->bge_tx_prodidx; 4013 4014 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4015 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4016 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4017 break; 4018 } 4019 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4020 if (m_head == NULL) 4021 break; 4022 4023 /* 4024 * XXX 4025 * The code inside the if() block is never reached since we 4026 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4027 * requests to checksum TCP/UDP in a fragmented packet. 4028 * 4029 * XXX 4030 * safety overkill. If this is a fragmented packet chain 4031 * with delayed TCP/UDP checksums, then only encapsulate 4032 * it if we have enough descriptors to handle the entire 4033 * chain at once. 4034 * (paranoia -- may not actually be needed) 4035 */ 4036 if (m_head->m_flags & M_FIRSTFRAG && 4037 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4038 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4039 m_head->m_pkthdr.csum_data + 16) { 4040 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4041 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4042 break; 4043 } 4044 } 4045 4046 /* 4047 * Pack the data into the transmit ring. If we 4048 * don't have room, set the OACTIVE flag and wait 4049 * for the NIC to drain the ring. 4050 */ 4051 if (bge_encap(sc, &m_head, &prodidx)) { 4052 if (m_head == NULL) 4053 break; 4054 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4055 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4056 break; 4057 } 4058 ++count; 4059 4060 /* 4061 * If there's a BPF listener, bounce a copy of this frame 4062 * to him. 4063 */ 4064#ifdef ETHER_BPF_MTAP 4065 ETHER_BPF_MTAP(ifp, m_head); 4066#else 4067 BPF_MTAP(ifp, m_head); 4068#endif 4069 } 4070 4071 if (count > 0) { 4072 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4073 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4074 /* Transmit. */ 4075 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4076 /* 5700 b2 errata */ 4077 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4078 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4079 4080 sc->bge_tx_prodidx = prodidx; 4081 4082 /* 4083 * Set a timeout in case the chip goes out to lunch. 4084 */ 4085 sc->bge_timer = 5; 4086 } 4087} 4088 4089/* 4090 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4091 * to the mbuf data regions directly in the transmit descriptors. 4092 */ 4093static void 4094bge_start(struct ifnet *ifp) 4095{ 4096 struct bge_softc *sc; 4097 4098 sc = ifp->if_softc; 4099 BGE_LOCK(sc); 4100 bge_start_locked(ifp); 4101 BGE_UNLOCK(sc); 4102} 4103 4104static void 4105bge_init_locked(struct bge_softc *sc) 4106{ 4107 struct ifnet *ifp; 4108 uint16_t *m; 4109 4110 BGE_LOCK_ASSERT(sc); 4111 4112 ifp = sc->bge_ifp; 4113 4114 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4115 return; 4116 4117 /* Cancel pending I/O and flush buffers. */ 4118 bge_stop(sc); 4119 4120 bge_stop_fw(sc); 4121 bge_sig_pre_reset(sc, BGE_RESET_START); 4122 bge_reset(sc); 4123 bge_sig_legacy(sc, BGE_RESET_START); 4124 bge_sig_post_reset(sc, BGE_RESET_START); 4125 4126 bge_chipinit(sc); 4127 4128 /* 4129 * Init the various state machines, ring 4130 * control blocks and firmware. 4131 */ 4132 if (bge_blockinit(sc)) { 4133 device_printf(sc->bge_dev, "initialization failure\n"); 4134 return; 4135 } 4136 4137 ifp = sc->bge_ifp; 4138 4139 /* Specify MTU. */ 4140 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4141 ETHER_HDR_LEN + ETHER_CRC_LEN + 4142 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4143 4144 /* Load our MAC address. */ 4145 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4146 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4147 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4148 4149 /* Program promiscuous mode. */ 4150 bge_setpromisc(sc); 4151 4152 /* Program multicast filter. */ 4153 bge_setmulti(sc); 4154 4155 /* Program VLAN tag stripping. */ 4156 bge_setvlan(sc); 4157 4158 /* Init RX ring. */ 4159 if (bge_init_rx_ring_std(sc) != 0) { 4160 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4161 bge_stop(sc); 4162 return; 4163 } 4164 4165 /* 4166 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4167 * memory to insure that the chip has in fact read the first 4168 * entry of the ring. 4169 */ 4170 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4171 uint32_t v, i; 4172 for (i = 0; i < 10; i++) { 4173 DELAY(20); 4174 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4175 if (v == (MCLBYTES - ETHER_ALIGN)) 4176 break; 4177 } 4178 if (i == 10) 4179 device_printf (sc->bge_dev, 4180 "5705 A0 chip failed to load RX ring\n"); 4181 } 4182 4183 /* Init jumbo RX ring. */ 4184 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4185 (MCLBYTES - ETHER_ALIGN)) { 4186 if (bge_init_rx_ring_jumbo(sc) != 0) { 4187 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4188 bge_stop(sc); 4189 return; 4190 } 4191 } 4192 4193 /* Init our RX return ring index. */ 4194 sc->bge_rx_saved_considx = 0; 4195 4196 /* Init our RX/TX stat counters. */ 4197 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4198 4199 /* Init TX ring. */ 4200 bge_init_tx_ring(sc); 4201 4202 /* Turn on transmitter. */ 4203 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4204 4205 /* Turn on receiver. */ 4206 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4207 4208 /* Tell firmware we're alive. */ 4209 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4210 4211#ifdef DEVICE_POLLING 4212 /* Disable interrupts if we are polling. */ 4213 if (ifp->if_capenable & IFCAP_POLLING) { 4214 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4215 BGE_PCIMISCCTL_MASK_PCI_INTR); 4216 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4217 } else 4218#endif 4219 4220 /* Enable host interrupts. */ 4221 { 4222 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4223 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4224 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4225 } 4226 4227 bge_ifmedia_upd_locked(ifp); 4228 4229 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4230 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4231 4232 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4233} 4234 4235static void 4236bge_init(void *xsc) 4237{ 4238 struct bge_softc *sc = xsc; 4239 4240 BGE_LOCK(sc); 4241 bge_init_locked(sc); 4242 BGE_UNLOCK(sc); 4243} 4244 4245/* 4246 * Set media options. 4247 */ 4248static int 4249bge_ifmedia_upd(struct ifnet *ifp) 4250{ 4251 struct bge_softc *sc = ifp->if_softc; 4252 int res; 4253 4254 BGE_LOCK(sc); 4255 res = bge_ifmedia_upd_locked(ifp); 4256 BGE_UNLOCK(sc); 4257 4258 return (res); 4259} 4260 4261static int 4262bge_ifmedia_upd_locked(struct ifnet *ifp) 4263{ 4264 struct bge_softc *sc = ifp->if_softc; 4265 struct mii_data *mii; 4266 struct mii_softc *miisc; 4267 struct ifmedia *ifm; 4268 4269 BGE_LOCK_ASSERT(sc); 4270 4271 ifm = &sc->bge_ifmedia; 4272 4273 /* If this is a 1000baseX NIC, enable the TBI port. */ 4274 if (sc->bge_flags & BGE_FLAG_TBI) { 4275 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4276 return (EINVAL); 4277 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4278 case IFM_AUTO: 4279 /* 4280 * The BCM5704 ASIC appears to have a special 4281 * mechanism for programming the autoneg 4282 * advertisement registers in TBI mode. 4283 */ 4284 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4285 uint32_t sgdig; 4286 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4287 if (sgdig & BGE_SGDIGSTS_DONE) { 4288 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4289 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4290 sgdig |= BGE_SGDIGCFG_AUTO | 4291 BGE_SGDIGCFG_PAUSE_CAP | 4292 BGE_SGDIGCFG_ASYM_PAUSE; 4293 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4294 sgdig | BGE_SGDIGCFG_SEND); 4295 DELAY(5); 4296 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4297 } 4298 } 4299 break; 4300 case IFM_1000_SX: 4301 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4302 BGE_CLRBIT(sc, BGE_MAC_MODE, 4303 BGE_MACMODE_HALF_DUPLEX); 4304 } else { 4305 BGE_SETBIT(sc, BGE_MAC_MODE, 4306 BGE_MACMODE_HALF_DUPLEX); 4307 } 4308 break; 4309 default: 4310 return (EINVAL); 4311 } 4312 return (0); 4313 } 4314 4315 sc->bge_link_evt++; 4316 mii = device_get_softc(sc->bge_miibus); 4317 if (mii->mii_instance) 4318 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4319 mii_phy_reset(miisc); 4320 mii_mediachg(mii); 4321 4322 /* 4323 * Force an interrupt so that we will call bge_link_upd 4324 * if needed and clear any pending link state attention. 4325 * Without this we are not getting any further interrupts 4326 * for link state changes and thus will not UP the link and 4327 * not be able to send in bge_start_locked. The only 4328 * way to get things working was to receive a packet and 4329 * get an RX intr. 4330 * bge_tick should help for fiber cards and we might not 4331 * need to do this here if BGE_FLAG_TBI is set but as 4332 * we poll for fiber anyway it should not harm. 4333 */ 4334 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4335 sc->bge_flags & BGE_FLAG_5788) 4336 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4337 else 4338 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4339 4340 return (0); 4341} 4342 4343/* 4344 * Report current media status. 4345 */ 4346static void 4347bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4348{ 4349 struct bge_softc *sc = ifp->if_softc; 4350 struct mii_data *mii; 4351 4352 BGE_LOCK(sc); 4353 4354 if (sc->bge_flags & BGE_FLAG_TBI) { 4355 ifmr->ifm_status = IFM_AVALID; 4356 ifmr->ifm_active = IFM_ETHER; 4357 if (CSR_READ_4(sc, BGE_MAC_STS) & 4358 BGE_MACSTAT_TBI_PCS_SYNCHED) 4359 ifmr->ifm_status |= IFM_ACTIVE; 4360 else { 4361 ifmr->ifm_active |= IFM_NONE; 4362 BGE_UNLOCK(sc); 4363 return; 4364 } 4365 ifmr->ifm_active |= IFM_1000_SX; 4366 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4367 ifmr->ifm_active |= IFM_HDX; 4368 else 4369 ifmr->ifm_active |= IFM_FDX; 4370 BGE_UNLOCK(sc); 4371 return; 4372 } 4373 4374 mii = device_get_softc(sc->bge_miibus); 4375 mii_pollstat(mii); 4376 ifmr->ifm_active = mii->mii_media_active; 4377 ifmr->ifm_status = mii->mii_media_status; 4378 4379 BGE_UNLOCK(sc); 4380} 4381 4382static int 4383bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4384{ 4385 struct bge_softc *sc = ifp->if_softc; 4386 struct ifreq *ifr = (struct ifreq *) data; 4387 struct mii_data *mii; 4388 int flags, mask, error = 0; 4389 4390 switch (command) { 4391 case SIOCSIFMTU: 4392 if (ifr->ifr_mtu < ETHERMIN || 4393 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4394 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4395 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4396 ifr->ifr_mtu > ETHERMTU)) 4397 error = EINVAL; 4398 else if (ifp->if_mtu != ifr->ifr_mtu) { 4399 ifp->if_mtu = ifr->ifr_mtu; 4400 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4401 bge_init(sc); 4402 } 4403 break; 4404 case SIOCSIFFLAGS: 4405 BGE_LOCK(sc); 4406 if (ifp->if_flags & IFF_UP) { 4407 /* 4408 * If only the state of the PROMISC flag changed, 4409 * then just use the 'set promisc mode' command 4410 * instead of reinitializing the entire NIC. Doing 4411 * a full re-init means reloading the firmware and 4412 * waiting for it to start up, which may take a 4413 * second or two. Similarly for ALLMULTI. 4414 */ 4415 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4416 flags = ifp->if_flags ^ sc->bge_if_flags; 4417 if (flags & IFF_PROMISC) 4418 bge_setpromisc(sc); 4419 if (flags & IFF_ALLMULTI) 4420 bge_setmulti(sc); 4421 } else 4422 bge_init_locked(sc); 4423 } else { 4424 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4425 bge_stop(sc); 4426 } 4427 } 4428 sc->bge_if_flags = ifp->if_flags; 4429 BGE_UNLOCK(sc); 4430 error = 0; 4431 break; 4432 case SIOCADDMULTI: 4433 case SIOCDELMULTI: 4434 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4435 BGE_LOCK(sc); 4436 bge_setmulti(sc); 4437 BGE_UNLOCK(sc); 4438 error = 0; 4439 } 4440 break; 4441 case SIOCSIFMEDIA: 4442 case SIOCGIFMEDIA: 4443 if (sc->bge_flags & BGE_FLAG_TBI) { 4444 error = ifmedia_ioctl(ifp, ifr, 4445 &sc->bge_ifmedia, command); 4446 } else { 4447 mii = device_get_softc(sc->bge_miibus); 4448 error = ifmedia_ioctl(ifp, ifr, 4449 &mii->mii_media, command); 4450 } 4451 break; 4452 case SIOCSIFCAP: 4453 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4454#ifdef DEVICE_POLLING 4455 if (mask & IFCAP_POLLING) { 4456 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4457 error = ether_poll_register(bge_poll, ifp); 4458 if (error) 4459 return (error); 4460 BGE_LOCK(sc); 4461 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4462 BGE_PCIMISCCTL_MASK_PCI_INTR); 4463 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4464 ifp->if_capenable |= IFCAP_POLLING; 4465 BGE_UNLOCK(sc); 4466 } else { 4467 error = ether_poll_deregister(ifp); 4468 /* Enable interrupt even in error case */ 4469 BGE_LOCK(sc); 4470 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4471 BGE_PCIMISCCTL_MASK_PCI_INTR); 4472 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4473 ifp->if_capenable &= ~IFCAP_POLLING; 4474 BGE_UNLOCK(sc); 4475 } 4476 } 4477#endif 4478 if (mask & IFCAP_HWCSUM) { 4479 ifp->if_capenable ^= IFCAP_HWCSUM; 4480 if (IFCAP_HWCSUM & ifp->if_capenable && 4481 IFCAP_HWCSUM & ifp->if_capabilities) 4482 ifp->if_hwassist |= BGE_CSUM_FEATURES; 4483 else 4484 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 4485#ifdef VLAN_CAPABILITIES 4486 VLAN_CAPABILITIES(ifp); 4487#endif 4488 } 4489 4490 if ((mask & IFCAP_TSO4) != 0 && 4491 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4492 ifp->if_capenable ^= IFCAP_TSO4; 4493 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4494 ifp->if_hwassist |= CSUM_TSO; 4495 else 4496 ifp->if_hwassist &= ~CSUM_TSO; 4497 } 4498 4499 if (mask & IFCAP_VLAN_MTU) { 4500 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4501 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4502 bge_init(sc); 4503 } 4504 4505 if (mask & IFCAP_VLAN_HWTAGGING) { 4506 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4507 BGE_LOCK(sc); 4508 bge_setvlan(sc); 4509 BGE_UNLOCK(sc); 4510#ifdef VLAN_CAPABILITIES 4511 VLAN_CAPABILITIES(ifp); 4512#endif 4513 } 4514 4515 break; 4516 default: 4517 error = ether_ioctl(ifp, command, data); 4518 break; 4519 } 4520 4521 return (error); 4522} 4523 4524static void 4525bge_watchdog(struct bge_softc *sc) 4526{ 4527 struct ifnet *ifp; 4528 4529 BGE_LOCK_ASSERT(sc); 4530 4531 if (sc->bge_timer == 0 || --sc->bge_timer) 4532 return; 4533 4534 ifp = sc->bge_ifp; 4535 4536 if_printf(ifp, "watchdog timeout -- resetting\n"); 4537 4538 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4539 bge_init_locked(sc); 4540 4541 ifp->if_oerrors++; 4542} 4543 4544/* 4545 * Stop the adapter and free any mbufs allocated to the 4546 * RX and TX lists. 4547 */ 4548static void 4549bge_stop(struct bge_softc *sc) 4550{ 4551 struct ifnet *ifp; 4552 struct ifmedia_entry *ifm; 4553 struct mii_data *mii = NULL; 4554 int mtmp, itmp; 4555 4556 BGE_LOCK_ASSERT(sc); 4557 4558 ifp = sc->bge_ifp; 4559 4560 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 4561 mii = device_get_softc(sc->bge_miibus); 4562 4563 callout_stop(&sc->bge_stat_ch); 4564 4565 /* Disable host interrupts. */ 4566 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4567 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4568 4569 /* 4570 * Tell firmware we're shutting down. 4571 */ 4572 bge_stop_fw(sc); 4573 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4574 4575 /* 4576 * Disable all of the receiver blocks. 4577 */ 4578 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4579 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4580 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4581 if (!(BGE_IS_5705_PLUS(sc))) 4582 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4583 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4584 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4585 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4586 4587 /* 4588 * Disable all of the transmit blocks. 4589 */ 4590 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4591 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4592 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4593 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4594 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4595 if (!(BGE_IS_5705_PLUS(sc))) 4596 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4597 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4598 4599 /* 4600 * Shut down all of the memory managers and related 4601 * state machines. 4602 */ 4603 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4604 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4605 if (!(BGE_IS_5705_PLUS(sc))) 4606 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4607 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4608 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4609 if (!(BGE_IS_5705_PLUS(sc))) { 4610 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4611 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4612 } 4613 4614 bge_reset(sc); 4615 bge_sig_legacy(sc, BGE_RESET_STOP); 4616 bge_sig_post_reset(sc, BGE_RESET_STOP); 4617 4618 /* 4619 * Keep the ASF firmware running if up. 4620 */ 4621 if (sc->bge_asf_mode & ASF_STACKUP) 4622 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4623 else 4624 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4625 4626 /* Free the RX lists. */ 4627 bge_free_rx_ring_std(sc); 4628 4629 /* Free jumbo RX list. */ 4630 if (BGE_IS_JUMBO_CAPABLE(sc)) 4631 bge_free_rx_ring_jumbo(sc); 4632 4633 /* Free TX buffers. */ 4634 bge_free_tx_ring(sc); 4635 4636 /* 4637 * Isolate/power down the PHY, but leave the media selection 4638 * unchanged so that things will be put back to normal when 4639 * we bring the interface back up. 4640 */ 4641 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4642 itmp = ifp->if_flags; 4643 ifp->if_flags |= IFF_UP; 4644 /* 4645 * If we are called from bge_detach(), mii is already NULL. 4646 */ 4647 if (mii != NULL) { 4648 ifm = mii->mii_media.ifm_cur; 4649 mtmp = ifm->ifm_media; 4650 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4651 mii_mediachg(mii); 4652 ifm->ifm_media = mtmp; 4653 } 4654 ifp->if_flags = itmp; 4655 } 4656 4657 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4658 4659 /* Clear MAC's link state (PHY may still have link UP). */ 4660 if (bootverbose && sc->bge_link) 4661 if_printf(sc->bge_ifp, "link DOWN\n"); 4662 sc->bge_link = 0; 4663 4664 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4665} 4666 4667/* 4668 * Stop all chip I/O so that the kernel's probe routines don't 4669 * get confused by errant DMAs when rebooting. 4670 */ 4671static int 4672bge_shutdown(device_t dev) 4673{ 4674 struct bge_softc *sc; 4675 4676 sc = device_get_softc(dev); 4677 BGE_LOCK(sc); 4678 bge_stop(sc); 4679 bge_reset(sc); 4680 BGE_UNLOCK(sc); 4681 4682 return (0); 4683} 4684 4685static int 4686bge_suspend(device_t dev) 4687{ 4688 struct bge_softc *sc; 4689 4690 sc = device_get_softc(dev); 4691 BGE_LOCK(sc); 4692 bge_stop(sc); 4693 BGE_UNLOCK(sc); 4694 4695 return (0); 4696} 4697 4698static int 4699bge_resume(device_t dev) 4700{ 4701 struct bge_softc *sc; 4702 struct ifnet *ifp; 4703 4704 sc = device_get_softc(dev); 4705 BGE_LOCK(sc); 4706 ifp = sc->bge_ifp; 4707 if (ifp->if_flags & IFF_UP) { 4708 bge_init_locked(sc); 4709 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4710 bge_start_locked(ifp); 4711 } 4712 BGE_UNLOCK(sc); 4713 4714 return (0); 4715} 4716 4717static void 4718bge_link_upd(struct bge_softc *sc) 4719{ 4720 struct mii_data *mii; 4721 uint32_t link, status; 4722 4723 BGE_LOCK_ASSERT(sc); 4724 4725 /* Clear 'pending link event' flag. */ 4726 sc->bge_link_evt = 0; 4727 4728 /* 4729 * Process link state changes. 4730 * Grrr. The link status word in the status block does 4731 * not work correctly on the BCM5700 rev AX and BX chips, 4732 * according to all available information. Hence, we have 4733 * to enable MII interrupts in order to properly obtain 4734 * async link changes. Unfortunately, this also means that 4735 * we have to read the MAC status register to detect link 4736 * changes, thereby adding an additional register access to 4737 * the interrupt handler. 4738 * 4739 * XXX: perhaps link state detection procedure used for 4740 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4741 */ 4742 4743 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4744 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4745 status = CSR_READ_4(sc, BGE_MAC_STS); 4746 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4747 mii = device_get_softc(sc->bge_miibus); 4748 mii_pollstat(mii); 4749 if (!sc->bge_link && 4750 mii->mii_media_status & IFM_ACTIVE && 4751 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4752 sc->bge_link++; 4753 if (bootverbose) 4754 if_printf(sc->bge_ifp, "link UP\n"); 4755 } else if (sc->bge_link && 4756 (!(mii->mii_media_status & IFM_ACTIVE) || 4757 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4758 sc->bge_link = 0; 4759 if (bootverbose) 4760 if_printf(sc->bge_ifp, "link DOWN\n"); 4761 } 4762 4763 /* Clear the interrupt. */ 4764 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4765 BGE_EVTENB_MI_INTERRUPT); 4766 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4767 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4768 BRGPHY_INTRS); 4769 } 4770 return; 4771 } 4772 4773 if (sc->bge_flags & BGE_FLAG_TBI) { 4774 status = CSR_READ_4(sc, BGE_MAC_STS); 4775 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4776 if (!sc->bge_link) { 4777 sc->bge_link++; 4778 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4779 BGE_CLRBIT(sc, BGE_MAC_MODE, 4780 BGE_MACMODE_TBI_SEND_CFGS); 4781 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4782 if (bootverbose) 4783 if_printf(sc->bge_ifp, "link UP\n"); 4784 if_link_state_change(sc->bge_ifp, 4785 LINK_STATE_UP); 4786 } 4787 } else if (sc->bge_link) { 4788 sc->bge_link = 0; 4789 if (bootverbose) 4790 if_printf(sc->bge_ifp, "link DOWN\n"); 4791 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4792 } 4793 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4794 /* 4795 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4796 * in status word always set. Workaround this bug by reading 4797 * PHY link status directly. 4798 */ 4799 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4800 4801 if (link != sc->bge_link || 4802 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4803 mii = device_get_softc(sc->bge_miibus); 4804 mii_pollstat(mii); 4805 if (!sc->bge_link && 4806 mii->mii_media_status & IFM_ACTIVE && 4807 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4808 sc->bge_link++; 4809 if (bootverbose) 4810 if_printf(sc->bge_ifp, "link UP\n"); 4811 } else if (sc->bge_link && 4812 (!(mii->mii_media_status & IFM_ACTIVE) || 4813 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4814 sc->bge_link = 0; 4815 if (bootverbose) 4816 if_printf(sc->bge_ifp, "link DOWN\n"); 4817 } 4818 } 4819 } else { 4820 /* 4821 * Discard link events for MII/GMII controllers 4822 * if MI auto-polling is disabled. 4823 */ 4824 } 4825 4826 /* Clear the attention. */ 4827 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4828 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4829 BGE_MACSTAT_LINK_CHANGED); 4830} 4831 4832#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4833 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4834 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4835 desc) 4836 4837static void 4838bge_add_sysctls(struct bge_softc *sc) 4839{ 4840 struct sysctl_ctx_list *ctx; 4841 struct sysctl_oid_list *children, *schildren; 4842 struct sysctl_oid *tree; 4843 4844 ctx = device_get_sysctl_ctx(sc->bge_dev); 4845 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4846 4847#ifdef BGE_REGISTER_DEBUG 4848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4849 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4850 "Debug Information"); 4851 4852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4853 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4854 "Register Read"); 4855 4856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4857 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4858 "Memory Read"); 4859 4860#endif 4861 4862 if (BGE_IS_5705_PLUS(sc)) 4863 return; 4864 4865 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4866 NULL, "BGE Statistics"); 4867 schildren = children = SYSCTL_CHILDREN(tree); 4868 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4869 children, COSFramesDroppedDueToFilters, 4870 "FramesDroppedDueToFilters"); 4871 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4872 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4873 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4874 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4875 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4876 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4877 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4878 children, ifInDiscards, "InputDiscards"); 4879 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4880 children, ifInErrors, "InputErrors"); 4881 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4882 children, nicRecvThresholdHit, "RecvThresholdHit"); 4883 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4884 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4885 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4886 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4887 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4888 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4889 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4890 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4891 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4892 children, nicRingStatusUpdate, "RingStatusUpdate"); 4893 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4894 children, nicInterrupts, "Interrupts"); 4895 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4896 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4897 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4898 children, nicSendThresholdHit, "SendThresholdHit"); 4899 4900 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4901 NULL, "BGE RX Statistics"); 4902 children = SYSCTL_CHILDREN(tree); 4903 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4904 children, rxstats.ifHCInOctets, "Octets"); 4905 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4906 children, rxstats.etherStatsFragments, "Fragments"); 4907 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4908 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4909 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4910 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4911 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4912 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4913 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4914 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4915 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4916 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4917 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4918 children, rxstats.xoffPauseFramesReceived, 4919 "xoffPauseFramesReceived"); 4920 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4921 children, rxstats.macControlFramesReceived, 4922 "ControlFramesReceived"); 4923 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4924 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4925 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4926 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4927 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4928 children, rxstats.etherStatsJabbers, "Jabbers"); 4929 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4930 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4931 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4932 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4933 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4934 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4935 4936 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4937 NULL, "BGE TX Statistics"); 4938 children = SYSCTL_CHILDREN(tree); 4939 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4940 children, txstats.ifHCOutOctets, "Octets"); 4941 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4942 children, txstats.etherStatsCollisions, "Collisions"); 4943 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4944 children, txstats.outXonSent, "XonSent"); 4945 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4946 children, txstats.outXoffSent, "XoffSent"); 4947 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4948 children, txstats.flowControlDone, "flowControlDone"); 4949 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4950 children, txstats.dot3StatsInternalMacTransmitErrors, 4951 "InternalMacTransmitErrors"); 4952 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4953 children, txstats.dot3StatsSingleCollisionFrames, 4954 "SingleCollisionFrames"); 4955 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4956 children, txstats.dot3StatsMultipleCollisionFrames, 4957 "MultipleCollisionFrames"); 4958 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4959 children, txstats.dot3StatsDeferredTransmissions, 4960 "DeferredTransmissions"); 4961 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4962 children, txstats.dot3StatsExcessiveCollisions, 4963 "ExcessiveCollisions"); 4964 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4965 children, txstats.dot3StatsLateCollisions, 4966 "LateCollisions"); 4967 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4968 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4969 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4970 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4971 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4972 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4973 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4974 children, txstats.dot3StatsCarrierSenseErrors, 4975 "CarrierSenseErrors"); 4976 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4977 children, txstats.ifOutDiscards, "Discards"); 4978 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4979 children, txstats.ifOutErrors, "Errors"); 4980} 4981 4982static int 4983bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4984{ 4985 struct bge_softc *sc; 4986 uint32_t result; 4987 int offset; 4988 4989 sc = (struct bge_softc *)arg1; 4990 offset = arg2; 4991 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 4992 offsetof(bge_hostaddr, bge_addr_lo)); 4993 return (sysctl_handle_int(oidp, &result, 0, req)); 4994} 4995 4996#ifdef BGE_REGISTER_DEBUG 4997static int 4998bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4999{ 5000 struct bge_softc *sc; 5001 uint16_t *sbdata; 5002 int error; 5003 int result; 5004 int i, j; 5005 5006 result = -1; 5007 error = sysctl_handle_int(oidp, &result, 0, req); 5008 if (error || (req->newptr == NULL)) 5009 return (error); 5010 5011 if (result == 1) { 5012 sc = (struct bge_softc *)arg1; 5013 5014 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5015 printf("Status Block:\n"); 5016 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5017 printf("%06x:", i); 5018 for (j = 0; j < 8; j++) { 5019 printf(" %04x", sbdata[i]); 5020 i += 4; 5021 } 5022 printf("\n"); 5023 } 5024 5025 printf("Registers:\n"); 5026 for (i = 0x800; i < 0xA00; ) { 5027 printf("%06x:", i); 5028 for (j = 0; j < 8; j++) { 5029 printf(" %08x", CSR_READ_4(sc, i)); 5030 i += 4; 5031 } 5032 printf("\n"); 5033 } 5034 5035 printf("Hardware Flags:\n"); 5036 if (BGE_IS_5755_PLUS(sc)) 5037 printf(" - 5755 Plus\n"); 5038 if (BGE_IS_575X_PLUS(sc)) 5039 printf(" - 575X Plus\n"); 5040 if (BGE_IS_5705_PLUS(sc)) 5041 printf(" - 5705 Plus\n"); 5042 if (BGE_IS_5714_FAMILY(sc)) 5043 printf(" - 5714 Family\n"); 5044 if (BGE_IS_5700_FAMILY(sc)) 5045 printf(" - 5700 Family\n"); 5046 if (sc->bge_flags & BGE_FLAG_JUMBO) 5047 printf(" - Supports Jumbo Frames\n"); 5048 if (sc->bge_flags & BGE_FLAG_PCIX) 5049 printf(" - PCI-X Bus\n"); 5050 if (sc->bge_flags & BGE_FLAG_PCIE) 5051 printf(" - PCI Express Bus\n"); 5052 if (sc->bge_flags & BGE_FLAG_NO_3LED) 5053 printf(" - No 3 LEDs\n"); 5054 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5055 printf(" - RX Alignment Bug\n"); 5056 } 5057 5058 return (error); 5059} 5060 5061static int 5062bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5063{ 5064 struct bge_softc *sc; 5065 int error; 5066 uint16_t result; 5067 uint32_t val; 5068 5069 result = -1; 5070 error = sysctl_handle_int(oidp, &result, 0, req); 5071 if (error || (req->newptr == NULL)) 5072 return (error); 5073 5074 if (result < 0x8000) { 5075 sc = (struct bge_softc *)arg1; 5076 val = CSR_READ_4(sc, result); 5077 printf("reg 0x%06X = 0x%08X\n", result, val); 5078 } 5079 5080 return (error); 5081} 5082 5083static int 5084bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5085{ 5086 struct bge_softc *sc; 5087 int error; 5088 uint16_t result; 5089 uint32_t val; 5090 5091 result = -1; 5092 error = sysctl_handle_int(oidp, &result, 0, req); 5093 if (error || (req->newptr == NULL)) 5094 return (error); 5095 5096 if (result < 0x8000) { 5097 sc = (struct bge_softc *)arg1; 5098 val = bge_readmem_ind(sc, result); 5099 printf("mem 0x%06X = 0x%08X\n", result, val); 5100 } 5101 5102 return (error); 5103} 5104#endif 5105 5106static int 5107bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5108{ 5109 5110 if (sc->bge_flags & BGE_FLAG_EADDR) 5111 return (1); 5112 5113#ifdef __sparc64__ 5114 OF_getetheraddr(sc->bge_dev, ether_addr); 5115 return (0); 5116#endif 5117 return (1); 5118} 5119 5120static int 5121bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5122{ 5123 uint32_t mac_addr; 5124 5125 mac_addr = bge_readmem_ind(sc, 0x0c14); 5126 if ((mac_addr >> 16) == 0x484b) { 5127 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5128 ether_addr[1] = (uint8_t)mac_addr; 5129 mac_addr = bge_readmem_ind(sc, 0x0c18); 5130 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5131 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5132 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5133 ether_addr[5] = (uint8_t)mac_addr; 5134 return (0); 5135 } 5136 return (1); 5137} 5138 5139static int 5140bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5141{ 5142 int mac_offset = BGE_EE_MAC_OFFSET; 5143 5144 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5145 mac_offset = BGE_EE_MAC_OFFSET_5906; 5146 5147 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5148 ETHER_ADDR_LEN)); 5149} 5150 5151static int 5152bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5153{ 5154 5155 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5156 return (1); 5157 5158 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5159 ETHER_ADDR_LEN)); 5160} 5161 5162static int 5163bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5164{ 5165 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5166 /* NOTE: Order is critical */ 5167 bge_get_eaddr_fw, 5168 bge_get_eaddr_mem, 5169 bge_get_eaddr_nvram, 5170 bge_get_eaddr_eeprom, 5171 NULL 5172 }; 5173 const bge_eaddr_fcn_t *func; 5174 5175 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5176 if ((*func)(sc, eaddr) == 0) 5177 break; 5178 } 5179 return (*func == NULL ? ENXIO : 0); 5180} 5181