1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: releng/10.3/sys/dev/bge/if_bge.c 278399 2015-02-08 20:44:44Z marius $"); 36 37/* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69#ifdef HAVE_KERNEL_OPTION_HEADERS 70#include "opt_device_polling.h" 71#endif 72 73#include <sys/param.h> 74#include <sys/endian.h> 75#include <sys/systm.h> 76#include <sys/sockio.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/module.h> 81#include <sys/socket.h> 82#include <sys/sysctl.h> 83#include <sys/taskqueue.h> 84 85#include <net/if.h> 86#include <net/if_arp.h> 87#include <net/ethernet.h> 88#include <net/if_dl.h> 89#include <net/if_media.h> 90 91#include <net/bpf.h> 92 93#include <net/if_types.h> 94#include <net/if_vlan_var.h> 95 96#include <netinet/in_systm.h> 97#include <netinet/in.h> 98#include <netinet/ip.h> 99#include <netinet/tcp.h> 100 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include "miidevs.h" 109#include <dev/mii/brgphyreg.h> 110 111#ifdef __sparc64__ 112#include <dev/ofw/ofw_bus.h> 113#include <dev/ofw/openfirm.h> 114#include <machine/ofw_machdep.h> 115#include <machine/ver.h> 116#endif 117 118#include <dev/pci/pcireg.h> 119#include <dev/pci/pcivar.h> 120 121#include <dev/bge/if_bgereg.h> 122 123#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126MODULE_DEPEND(bge, pci, 1, 1, 1); 127MODULE_DEPEND(bge, ether, 1, 1, 1); 128MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130/* "device miibus" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133/* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142} bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 237 238 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 239 240 { TC_VENDORID, TC_DEVICEID_3C996 }, 241 242 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 244 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 245 246 { 0, 0 } 247}; 248 249static const struct bge_vendor { 250 uint16_t v_id; 251 const char *v_name; 252} bge_vendors[] = { 253 { ALTEON_VENDORID, "Alteon" }, 254 { ALTIMA_VENDORID, "Altima" }, 255 { APPLE_VENDORID, "Apple" }, 256 { BCOM_VENDORID, "Broadcom" }, 257 { SK_VENDORID, "SysKonnect" }, 258 { TC_VENDORID, "3Com" }, 259 { FJTSU_VENDORID, "Fujitsu" }, 260 261 { 0, NULL } 262}; 263 264static const struct bge_revision { 265 uint32_t br_chipid; 266 const char *br_name; 267} bge_revisions[] = { 268 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 269 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 270 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 271 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 272 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 273 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 274 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 275 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 276 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 277 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 278 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 279 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 280 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 281 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 282 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 283 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 284 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 285 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 286 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 287 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 288 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 289 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 290 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 291 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 292 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 293 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 294 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 295 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 296 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 297 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 298 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 299 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 300 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 301 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 302 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 303 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 304 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 305 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 306 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 307 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 308 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 309 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 310 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 311 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 312 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 313 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 314 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 315 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 316 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 317 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 318 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 319 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 320 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 321 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 322 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 323 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 324 /* 5754 and 5787 share the same ASIC ID */ 325 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 326 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 327 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 328 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 329 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 330 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 331 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 332 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 333 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 334 335 { 0, NULL } 336}; 337 338/* 339 * Some defaults for major revisions, so that newer steppings 340 * that we don't know about have a shot at working. 341 */ 342static const struct bge_revision bge_majorrevs[] = { 343 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 344 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 345 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 346 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 347 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 348 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 349 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 350 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 351 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 352 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 353 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 354 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 355 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 356 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 357 /* 5754 and 5787 share the same ASIC ID */ 358 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 359 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 360 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 361 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 362 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 363 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 364 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 365 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 366 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 367 368 { 0, NULL } 369}; 370 371#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 372#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 373#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 374#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 375#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 376#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 377#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 378#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 379 380static uint32_t bge_chipid(device_t); 381static const struct bge_vendor * bge_lookup_vendor(uint16_t); 382static const struct bge_revision * bge_lookup_rev(uint32_t); 383 384typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 385 386static int bge_probe(device_t); 387static int bge_attach(device_t); 388static int bge_detach(device_t); 389static int bge_suspend(device_t); 390static int bge_resume(device_t); 391static void bge_release_resources(struct bge_softc *); 392static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 393static int bge_dma_alloc(struct bge_softc *); 394static void bge_dma_free(struct bge_softc *); 395static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 396 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 397 398static void bge_devinfo(struct bge_softc *); 399static int bge_mbox_reorder(struct bge_softc *); 400 401static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 402static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 403static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 404static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 405static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 406 407static void bge_txeof(struct bge_softc *, uint16_t); 408static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 409static int bge_rxeof(struct bge_softc *, uint16_t, int); 410 411static void bge_asf_driver_up (struct bge_softc *); 412static void bge_tick(void *); 413static void bge_stats_clear_regs(struct bge_softc *); 414static void bge_stats_update(struct bge_softc *); 415static void bge_stats_update_regs(struct bge_softc *); 416static struct mbuf *bge_check_short_dma(struct mbuf *); 417static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 418 uint16_t *, uint16_t *); 419static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 420 421static void bge_intr(void *); 422static int bge_msi_intr(void *); 423static void bge_intr_task(void *, int); 424static void bge_start_locked(struct ifnet *); 425static void bge_start(struct ifnet *); 426static int bge_ioctl(struct ifnet *, u_long, caddr_t); 427static void bge_init_locked(struct bge_softc *); 428static void bge_init(void *); 429static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 430static void bge_stop(struct bge_softc *); 431static void bge_watchdog(struct bge_softc *); 432static int bge_shutdown(device_t); 433static int bge_ifmedia_upd_locked(struct ifnet *); 434static int bge_ifmedia_upd(struct ifnet *); 435static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 436 437static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 438static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 439 440static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 441static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 442 443static void bge_setpromisc(struct bge_softc *); 444static void bge_setmulti(struct bge_softc *); 445static void bge_setvlan(struct bge_softc *); 446 447static __inline void bge_rxreuse_std(struct bge_softc *, int); 448static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 449static int bge_newbuf_std(struct bge_softc *, int); 450static int bge_newbuf_jumbo(struct bge_softc *, int); 451static int bge_init_rx_ring_std(struct bge_softc *); 452static void bge_free_rx_ring_std(struct bge_softc *); 453static int bge_init_rx_ring_jumbo(struct bge_softc *); 454static void bge_free_rx_ring_jumbo(struct bge_softc *); 455static void bge_free_tx_ring(struct bge_softc *); 456static int bge_init_tx_ring(struct bge_softc *); 457 458static int bge_chipinit(struct bge_softc *); 459static int bge_blockinit(struct bge_softc *); 460static uint32_t bge_dma_swap_options(struct bge_softc *); 461 462static int bge_has_eaddr(struct bge_softc *); 463static uint32_t bge_readmem_ind(struct bge_softc *, int); 464static void bge_writemem_ind(struct bge_softc *, int, int); 465static void bge_writembx(struct bge_softc *, int, int); 466#ifdef notdef 467static uint32_t bge_readreg_ind(struct bge_softc *, int); 468#endif 469static void bge_writemem_direct(struct bge_softc *, int, int); 470static void bge_writereg_ind(struct bge_softc *, int, int); 471 472static int bge_miibus_readreg(device_t, int, int); 473static int bge_miibus_writereg(device_t, int, int, int); 474static void bge_miibus_statchg(device_t); 475#ifdef DEVICE_POLLING 476static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 477#endif 478 479#define BGE_RESET_SHUTDOWN 0 480#define BGE_RESET_START 1 481#define BGE_RESET_SUSPEND 2 482static void bge_sig_post_reset(struct bge_softc *, int); 483static void bge_sig_legacy(struct bge_softc *, int); 484static void bge_sig_pre_reset(struct bge_softc *, int); 485static void bge_stop_fw(struct bge_softc *); 486static int bge_reset(struct bge_softc *); 487static void bge_link_upd(struct bge_softc *); 488 489static void bge_ape_lock_init(struct bge_softc *); 490static void bge_ape_read_fw_ver(struct bge_softc *); 491static int bge_ape_lock(struct bge_softc *, int); 492static void bge_ape_unlock(struct bge_softc *, int); 493static void bge_ape_send_event(struct bge_softc *, uint32_t); 494static void bge_ape_driver_state_change(struct bge_softc *, int); 495 496/* 497 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 498 * leak information to untrusted users. It is also known to cause alignment 499 * traps on certain architectures. 500 */ 501#ifdef BGE_REGISTER_DEBUG 502static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 503static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 504static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 505static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 506#endif 507static void bge_add_sysctls(struct bge_softc *); 508static void bge_add_sysctl_stats_regs(struct bge_softc *, 509 struct sysctl_ctx_list *, struct sysctl_oid_list *); 510static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 511 struct sysctl_oid_list *); 512static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 513 514static device_method_t bge_methods[] = { 515 /* Device interface */ 516 DEVMETHOD(device_probe, bge_probe), 517 DEVMETHOD(device_attach, bge_attach), 518 DEVMETHOD(device_detach, bge_detach), 519 DEVMETHOD(device_shutdown, bge_shutdown), 520 DEVMETHOD(device_suspend, bge_suspend), 521 DEVMETHOD(device_resume, bge_resume), 522 523 /* MII interface */ 524 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 525 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 526 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 527 528 DEVMETHOD_END 529}; 530 531static driver_t bge_driver = { 532 "bge", 533 bge_methods, 534 sizeof(struct bge_softc) 535}; 536 537static devclass_t bge_devclass; 538 539DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 540DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 541 542static int bge_allow_asf = 1; 543 544TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 545 546static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 547SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 548 "Allow ASF mode if available"); 549 550#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 551#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 552#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 553#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 554#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 555 556static int 557bge_has_eaddr(struct bge_softc *sc) 558{ 559#ifdef __sparc64__ 560 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 561 device_t dev; 562 uint32_t subvendor; 563 564 dev = sc->bge_dev; 565 566 /* 567 * The on-board BGEs found in sun4u machines aren't fitted with 568 * an EEPROM which means that we have to obtain the MAC address 569 * via OFW and that some tests will always fail. We distinguish 570 * such BGEs by the subvendor ID, which also has to be obtained 571 * from OFW instead of the PCI configuration space as the latter 572 * indicates Broadcom as the subvendor of the netboot interface. 573 * For early Blade 1500 and 2500 we even have to check the OFW 574 * device path as the subvendor ID always defaults to Broadcom 575 * there. 576 */ 577 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 578 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 579 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 580 return (0); 581 memset(buf, 0, sizeof(buf)); 582 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 583 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 584 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 585 return (0); 586 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 587 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 588 return (0); 589 } 590#endif 591 return (1); 592} 593 594static uint32_t 595bge_readmem_ind(struct bge_softc *sc, int off) 596{ 597 device_t dev; 598 uint32_t val; 599 600 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 601 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 602 return (0); 603 604 dev = sc->bge_dev; 605 606 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 607 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 608 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 609 return (val); 610} 611 612static void 613bge_writemem_ind(struct bge_softc *sc, int off, int val) 614{ 615 device_t dev; 616 617 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 618 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 619 return; 620 621 dev = sc->bge_dev; 622 623 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 624 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 625 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 626} 627 628#ifdef notdef 629static uint32_t 630bge_readreg_ind(struct bge_softc *sc, int off) 631{ 632 device_t dev; 633 634 dev = sc->bge_dev; 635 636 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 637 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 638} 639#endif 640 641static void 642bge_writereg_ind(struct bge_softc *sc, int off, int val) 643{ 644 device_t dev; 645 646 dev = sc->bge_dev; 647 648 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 649 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 650} 651 652static void 653bge_writemem_direct(struct bge_softc *sc, int off, int val) 654{ 655 CSR_WRITE_4(sc, off, val); 656} 657 658static void 659bge_writembx(struct bge_softc *sc, int off, int val) 660{ 661 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 662 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 663 664 CSR_WRITE_4(sc, off, val); 665 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 666 CSR_READ_4(sc, off); 667} 668 669/* 670 * Clear all stale locks and select the lock for this driver instance. 671 */ 672static void 673bge_ape_lock_init(struct bge_softc *sc) 674{ 675 uint32_t bit, regbase; 676 int i; 677 678 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 679 regbase = BGE_APE_LOCK_GRANT; 680 else 681 regbase = BGE_APE_PER_LOCK_GRANT; 682 683 /* Clear any stale locks. */ 684 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 685 switch (i) { 686 case BGE_APE_LOCK_PHY0: 687 case BGE_APE_LOCK_PHY1: 688 case BGE_APE_LOCK_PHY2: 689 case BGE_APE_LOCK_PHY3: 690 bit = BGE_APE_LOCK_GRANT_DRIVER0; 691 break; 692 default: 693 if (sc->bge_func_addr == 0) 694 bit = BGE_APE_LOCK_GRANT_DRIVER0; 695 else 696 bit = (1 << sc->bge_func_addr); 697 } 698 APE_WRITE_4(sc, regbase + 4 * i, bit); 699 } 700 701 /* Select the PHY lock based on the device's function number. */ 702 switch (sc->bge_func_addr) { 703 case 0: 704 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 705 break; 706 case 1: 707 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 708 break; 709 case 2: 710 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 711 break; 712 case 3: 713 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 714 break; 715 default: 716 device_printf(sc->bge_dev, 717 "PHY lock not supported on this function\n"); 718 } 719} 720 721/* 722 * Check for APE firmware, set flags, and print version info. 723 */ 724static void 725bge_ape_read_fw_ver(struct bge_softc *sc) 726{ 727 const char *fwtype; 728 uint32_t apedata, features; 729 730 /* Check for a valid APE signature in shared memory. */ 731 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 732 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 733 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 734 return; 735 } 736 737 /* Check if APE firmware is running. */ 738 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 739 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 740 device_printf(sc->bge_dev, "APE signature found " 741 "but FW status not ready! 0x%08x\n", apedata); 742 return; 743 } 744 745 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 746 747 /* Fetch the APE firwmare type and version. */ 748 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 749 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 750 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 751 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 752 fwtype = "NCSI"; 753 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 754 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 755 fwtype = "DASH"; 756 } else 757 fwtype = "UNKN"; 758 759 /* Print the APE firmware version. */ 760 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 761 fwtype, 762 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 763 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 764 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 765 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 766} 767 768static int 769bge_ape_lock(struct bge_softc *sc, int locknum) 770{ 771 uint32_t bit, gnt, req, status; 772 int i, off; 773 774 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 775 return (0); 776 777 /* Lock request/grant registers have different bases. */ 778 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 779 req = BGE_APE_LOCK_REQ; 780 gnt = BGE_APE_LOCK_GRANT; 781 } else { 782 req = BGE_APE_PER_LOCK_REQ; 783 gnt = BGE_APE_PER_LOCK_GRANT; 784 } 785 786 off = 4 * locknum; 787 788 switch (locknum) { 789 case BGE_APE_LOCK_GPIO: 790 /* Lock required when using GPIO. */ 791 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 792 return (0); 793 if (sc->bge_func_addr == 0) 794 bit = BGE_APE_LOCK_REQ_DRIVER0; 795 else 796 bit = (1 << sc->bge_func_addr); 797 break; 798 case BGE_APE_LOCK_GRC: 799 /* Lock required to reset the device. */ 800 if (sc->bge_func_addr == 0) 801 bit = BGE_APE_LOCK_REQ_DRIVER0; 802 else 803 bit = (1 << sc->bge_func_addr); 804 break; 805 case BGE_APE_LOCK_MEM: 806 /* Lock required when accessing certain APE memory. */ 807 if (sc->bge_func_addr == 0) 808 bit = BGE_APE_LOCK_REQ_DRIVER0; 809 else 810 bit = (1 << sc->bge_func_addr); 811 break; 812 case BGE_APE_LOCK_PHY0: 813 case BGE_APE_LOCK_PHY1: 814 case BGE_APE_LOCK_PHY2: 815 case BGE_APE_LOCK_PHY3: 816 /* Lock required when accessing PHYs. */ 817 bit = BGE_APE_LOCK_REQ_DRIVER0; 818 break; 819 default: 820 return (EINVAL); 821 } 822 823 /* Request a lock. */ 824 APE_WRITE_4(sc, req + off, bit); 825 826 /* Wait up to 1 second to acquire lock. */ 827 for (i = 0; i < 20000; i++) { 828 status = APE_READ_4(sc, gnt + off); 829 if (status == bit) 830 break; 831 DELAY(50); 832 } 833 834 /* Handle any errors. */ 835 if (status != bit) { 836 device_printf(sc->bge_dev, "APE lock %d request failed! " 837 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 838 locknum, req + off, bit & 0xFFFF, gnt + off, 839 status & 0xFFFF); 840 /* Revoke the lock request. */ 841 APE_WRITE_4(sc, gnt + off, bit); 842 return (EBUSY); 843 } 844 845 return (0); 846} 847 848static void 849bge_ape_unlock(struct bge_softc *sc, int locknum) 850{ 851 uint32_t bit, gnt; 852 int off; 853 854 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 855 return; 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 858 gnt = BGE_APE_LOCK_GRANT; 859 else 860 gnt = BGE_APE_PER_LOCK_GRANT; 861 862 off = 4 * locknum; 863 864 switch (locknum) { 865 case BGE_APE_LOCK_GPIO: 866 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 867 return; 868 if (sc->bge_func_addr == 0) 869 bit = BGE_APE_LOCK_GRANT_DRIVER0; 870 else 871 bit = (1 << sc->bge_func_addr); 872 break; 873 case BGE_APE_LOCK_GRC: 874 if (sc->bge_func_addr == 0) 875 bit = BGE_APE_LOCK_GRANT_DRIVER0; 876 else 877 bit = (1 << sc->bge_func_addr); 878 break; 879 case BGE_APE_LOCK_MEM: 880 if (sc->bge_func_addr == 0) 881 bit = BGE_APE_LOCK_GRANT_DRIVER0; 882 else 883 bit = (1 << sc->bge_func_addr); 884 break; 885 case BGE_APE_LOCK_PHY0: 886 case BGE_APE_LOCK_PHY1: 887 case BGE_APE_LOCK_PHY2: 888 case BGE_APE_LOCK_PHY3: 889 bit = BGE_APE_LOCK_GRANT_DRIVER0; 890 break; 891 default: 892 return; 893 } 894 895 APE_WRITE_4(sc, gnt + off, bit); 896} 897 898/* 899 * Send an event to the APE firmware. 900 */ 901static void 902bge_ape_send_event(struct bge_softc *sc, uint32_t event) 903{ 904 uint32_t apedata; 905 int i; 906 907 /* NCSI does not support APE events. */ 908 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 909 return; 910 911 /* Wait up to 1ms for APE to service previous event. */ 912 for (i = 10; i > 0; i--) { 913 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 914 break; 915 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 916 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 917 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 918 BGE_APE_EVENT_STATUS_EVENT_PENDING); 919 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 920 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 921 break; 922 } 923 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 924 DELAY(100); 925 } 926 if (i == 0) 927 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 928 event); 929} 930 931static void 932bge_ape_driver_state_change(struct bge_softc *sc, int kind) 933{ 934 uint32_t apedata, event; 935 936 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 937 return; 938 939 switch (kind) { 940 case BGE_RESET_START: 941 /* If this is the first load, clear the load counter. */ 942 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 943 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 944 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 945 else { 946 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 947 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 948 } 949 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 950 BGE_APE_HOST_SEG_SIG_MAGIC); 951 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 952 BGE_APE_HOST_SEG_LEN_MAGIC); 953 954 /* Add some version info if bge(4) supports it. */ 955 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 956 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 957 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 958 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 959 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 960 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 961 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 962 BGE_APE_HOST_DRVR_STATE_START); 963 event = BGE_APE_EVENT_STATUS_STATE_START; 964 break; 965 case BGE_RESET_SHUTDOWN: 966 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 967 BGE_APE_HOST_DRVR_STATE_UNLOAD); 968 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 969 break; 970 case BGE_RESET_SUSPEND: 971 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 972 break; 973 default: 974 return; 975 } 976 977 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 978 BGE_APE_EVENT_STATUS_STATE_CHNGE); 979} 980 981/* 982 * Map a single buffer address. 983 */ 984 985static void 986bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 987{ 988 struct bge_dmamap_arg *ctx; 989 990 if (error) 991 return; 992 993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 994 995 ctx = arg; 996 ctx->bge_busaddr = segs->ds_addr; 997} 998 999static uint8_t 1000bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1001{ 1002 uint32_t access, byte = 0; 1003 int i; 1004 1005 /* Lock. */ 1006 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1007 for (i = 0; i < 8000; i++) { 1008 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1009 break; 1010 DELAY(20); 1011 } 1012 if (i == 8000) 1013 return (1); 1014 1015 /* Enable access. */ 1016 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1017 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1018 1019 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1020 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1021 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1022 DELAY(10); 1023 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1024 DELAY(10); 1025 break; 1026 } 1027 } 1028 1029 if (i == BGE_TIMEOUT * 10) { 1030 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1031 return (1); 1032 } 1033 1034 /* Get result. */ 1035 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1036 1037 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1038 1039 /* Disable access. */ 1040 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1041 1042 /* Unlock. */ 1043 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1044 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1045 1046 return (0); 1047} 1048 1049/* 1050 * Read a sequence of bytes from NVRAM. 1051 */ 1052static int 1053bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1054{ 1055 int err = 0, i; 1056 uint8_t byte = 0; 1057 1058 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1059 return (1); 1060 1061 for (i = 0; i < cnt; i++) { 1062 err = bge_nvram_getbyte(sc, off + i, &byte); 1063 if (err) 1064 break; 1065 *(dest + i) = byte; 1066 } 1067 1068 return (err ? 1 : 0); 1069} 1070 1071/* 1072 * Read a byte of data stored in the EEPROM at address 'addr.' The 1073 * BCM570x supports both the traditional bitbang interface and an 1074 * auto access interface for reading the EEPROM. We use the auto 1075 * access method. 1076 */ 1077static uint8_t 1078bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1079{ 1080 int i; 1081 uint32_t byte = 0; 1082 1083 /* 1084 * Enable use of auto EEPROM access so we can avoid 1085 * having to use the bitbang method. 1086 */ 1087 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1088 1089 /* Reset the EEPROM, load the clock period. */ 1090 CSR_WRITE_4(sc, BGE_EE_ADDR, 1091 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1092 DELAY(20); 1093 1094 /* Issue the read EEPROM command. */ 1095 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1096 1097 /* Wait for completion */ 1098 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1099 DELAY(10); 1100 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1101 break; 1102 } 1103 1104 if (i == BGE_TIMEOUT * 10) { 1105 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1106 return (1); 1107 } 1108 1109 /* Get result. */ 1110 byte = CSR_READ_4(sc, BGE_EE_DATA); 1111 1112 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1113 1114 return (0); 1115} 1116 1117/* 1118 * Read a sequence of bytes from the EEPROM. 1119 */ 1120static int 1121bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1122{ 1123 int i, error = 0; 1124 uint8_t byte = 0; 1125 1126 for (i = 0; i < cnt; i++) { 1127 error = bge_eeprom_getbyte(sc, off + i, &byte); 1128 if (error) 1129 break; 1130 *(dest + i) = byte; 1131 } 1132 1133 return (error ? 1 : 0); 1134} 1135 1136static int 1137bge_miibus_readreg(device_t dev, int phy, int reg) 1138{ 1139 struct bge_softc *sc; 1140 uint32_t val; 1141 int i; 1142 1143 sc = device_get_softc(dev); 1144 1145 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1146 return (0); 1147 1148 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1149 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1150 CSR_WRITE_4(sc, BGE_MI_MODE, 1151 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1152 DELAY(80); 1153 } 1154 1155 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1156 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1157 1158 /* Poll for the PHY register access to complete. */ 1159 for (i = 0; i < BGE_TIMEOUT; i++) { 1160 DELAY(10); 1161 val = CSR_READ_4(sc, BGE_MI_COMM); 1162 if ((val & BGE_MICOMM_BUSY) == 0) { 1163 DELAY(5); 1164 val = CSR_READ_4(sc, BGE_MI_COMM); 1165 break; 1166 } 1167 } 1168 1169 if (i == BGE_TIMEOUT) { 1170 device_printf(sc->bge_dev, 1171 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1172 phy, reg, val); 1173 val = 0; 1174 } 1175 1176 /* Restore the autopoll bit if necessary. */ 1177 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1178 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1179 DELAY(80); 1180 } 1181 1182 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1183 1184 if (val & BGE_MICOMM_READFAIL) 1185 return (0); 1186 1187 return (val & 0xFFFF); 1188} 1189 1190static int 1191bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1192{ 1193 struct bge_softc *sc; 1194 int i; 1195 1196 sc = device_get_softc(dev); 1197 1198 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1199 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1200 return (0); 1201 1202 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1203 return (0); 1204 1205 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1206 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1207 CSR_WRITE_4(sc, BGE_MI_MODE, 1208 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1209 DELAY(80); 1210 } 1211 1212 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1213 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1214 1215 for (i = 0; i < BGE_TIMEOUT; i++) { 1216 DELAY(10); 1217 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1218 DELAY(5); 1219 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1220 break; 1221 } 1222 } 1223 1224 /* Restore the autopoll bit if necessary. */ 1225 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1226 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1227 DELAY(80); 1228 } 1229 1230 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1231 1232 if (i == BGE_TIMEOUT) 1233 device_printf(sc->bge_dev, 1234 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1235 phy, reg, val); 1236 1237 return (0); 1238} 1239 1240static void 1241bge_miibus_statchg(device_t dev) 1242{ 1243 struct bge_softc *sc; 1244 struct mii_data *mii; 1245 uint32_t mac_mode, rx_mode, tx_mode; 1246 1247 sc = device_get_softc(dev); 1248 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1249 return; 1250 mii = device_get_softc(sc->bge_miibus); 1251 1252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1253 (IFM_ACTIVE | IFM_AVALID)) { 1254 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1255 case IFM_10_T: 1256 case IFM_100_TX: 1257 sc->bge_link = 1; 1258 break; 1259 case IFM_1000_T: 1260 case IFM_1000_SX: 1261 case IFM_2500_SX: 1262 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1263 sc->bge_link = 1; 1264 else 1265 sc->bge_link = 0; 1266 break; 1267 default: 1268 sc->bge_link = 0; 1269 break; 1270 } 1271 } else 1272 sc->bge_link = 0; 1273 if (sc->bge_link == 0) 1274 return; 1275 1276 /* 1277 * APE firmware touches these registers to keep the MAC 1278 * connected to the outside world. Try to keep the 1279 * accesses atomic. 1280 */ 1281 1282 /* Set the port mode (MII/GMII) to match the link speed. */ 1283 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1284 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1285 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1286 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1287 1288 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1289 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1290 mac_mode |= BGE_PORTMODE_GMII; 1291 else 1292 mac_mode |= BGE_PORTMODE_MII; 1293 1294 /* Set MAC flow control behavior to match link flow control settings. */ 1295 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1296 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1299 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1300 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1301 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1302 } else 1303 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1304 1305 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1306 DELAY(40); 1307 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1308 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1309} 1310 1311/* 1312 * Intialize a standard receive ring descriptor. 1313 */ 1314static int 1315bge_newbuf_std(struct bge_softc *sc, int i) 1316{ 1317 struct mbuf *m; 1318 struct bge_rx_bd *r; 1319 bus_dma_segment_t segs[1]; 1320 bus_dmamap_t map; 1321 int error, nsegs; 1322 1323 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1324 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1325 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1326 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1327 if (m == NULL) 1328 return (ENOBUFS); 1329 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1330 } else { 1331 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1332 if (m == NULL) 1333 return (ENOBUFS); 1334 m->m_len = m->m_pkthdr.len = MCLBYTES; 1335 } 1336 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1337 m_adj(m, ETHER_ALIGN); 1338 1339 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1340 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1341 if (error != 0) { 1342 m_freem(m); 1343 return (error); 1344 } 1345 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1346 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1347 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1348 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1349 sc->bge_cdata.bge_rx_std_dmamap[i]); 1350 } 1351 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1352 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1353 sc->bge_cdata.bge_rx_std_sparemap = map; 1354 sc->bge_cdata.bge_rx_std_chain[i] = m; 1355 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1356 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1357 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1358 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1359 r->bge_flags = BGE_RXBDFLAG_END; 1360 r->bge_len = segs[0].ds_len; 1361 r->bge_idx = i; 1362 1363 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1364 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1365 1366 return (0); 1367} 1368 1369/* 1370 * Initialize a jumbo receive ring descriptor. This allocates 1371 * a jumbo buffer from the pool managed internally by the driver. 1372 */ 1373static int 1374bge_newbuf_jumbo(struct bge_softc *sc, int i) 1375{ 1376 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1377 bus_dmamap_t map; 1378 struct bge_extrx_bd *r; 1379 struct mbuf *m; 1380 int error, nsegs; 1381 1382 MGETHDR(m, M_NOWAIT, MT_DATA); 1383 if (m == NULL) 1384 return (ENOBUFS); 1385 1386 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1387 if (!(m->m_flags & M_EXT)) { 1388 m_freem(m); 1389 return (ENOBUFS); 1390 } 1391 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1392 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1393 m_adj(m, ETHER_ALIGN); 1394 1395 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1396 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1397 if (error != 0) { 1398 m_freem(m); 1399 return (error); 1400 } 1401 1402 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1403 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1404 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1405 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1406 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1407 } 1408 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1409 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1410 sc->bge_cdata.bge_rx_jumbo_sparemap; 1411 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1412 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1413 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1416 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1417 1418 /* 1419 * Fill in the extended RX buffer descriptor. 1420 */ 1421 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1422 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1423 r->bge_idx = i; 1424 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1425 switch (nsegs) { 1426 case 4: 1427 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1428 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1429 r->bge_len3 = segs[3].ds_len; 1430 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1431 case 3: 1432 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1433 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1434 r->bge_len2 = segs[2].ds_len; 1435 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1436 case 2: 1437 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1438 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1439 r->bge_len1 = segs[1].ds_len; 1440 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1441 case 1: 1442 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1443 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1444 r->bge_len0 = segs[0].ds_len; 1445 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1446 break; 1447 default: 1448 panic("%s: %d segments\n", __func__, nsegs); 1449 } 1450 1451 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1452 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1453 1454 return (0); 1455} 1456 1457static int 1458bge_init_rx_ring_std(struct bge_softc *sc) 1459{ 1460 int error, i; 1461 1462 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1463 sc->bge_std = 0; 1464 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1465 if ((error = bge_newbuf_std(sc, i)) != 0) 1466 return (error); 1467 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1468 } 1469 1470 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1471 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1472 1473 sc->bge_std = 0; 1474 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1475 1476 return (0); 1477} 1478 1479static void 1480bge_free_rx_ring_std(struct bge_softc *sc) 1481{ 1482 int i; 1483 1484 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1485 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1486 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1487 sc->bge_cdata.bge_rx_std_dmamap[i], 1488 BUS_DMASYNC_POSTREAD); 1489 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1490 sc->bge_cdata.bge_rx_std_dmamap[i]); 1491 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1492 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1493 } 1494 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1495 sizeof(struct bge_rx_bd)); 1496 } 1497} 1498 1499static int 1500bge_init_rx_ring_jumbo(struct bge_softc *sc) 1501{ 1502 struct bge_rcb *rcb; 1503 int error, i; 1504 1505 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1506 sc->bge_jumbo = 0; 1507 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1508 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1509 return (error); 1510 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1511 } 1512 1513 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1514 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1515 1516 sc->bge_jumbo = 0; 1517 1518 /* Enable the jumbo receive producer ring. */ 1519 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1520 rcb->bge_maxlen_flags = 1521 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1522 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1523 1524 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1525 1526 return (0); 1527} 1528 1529static void 1530bge_free_rx_ring_jumbo(struct bge_softc *sc) 1531{ 1532 int i; 1533 1534 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1535 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1536 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1537 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1538 BUS_DMASYNC_POSTREAD); 1539 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1540 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1541 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1542 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1543 } 1544 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1545 sizeof(struct bge_extrx_bd)); 1546 } 1547} 1548 1549static void 1550bge_free_tx_ring(struct bge_softc *sc) 1551{ 1552 int i; 1553 1554 if (sc->bge_ldata.bge_tx_ring == NULL) 1555 return; 1556 1557 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1558 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1559 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1560 sc->bge_cdata.bge_tx_dmamap[i], 1561 BUS_DMASYNC_POSTWRITE); 1562 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1563 sc->bge_cdata.bge_tx_dmamap[i]); 1564 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1565 sc->bge_cdata.bge_tx_chain[i] = NULL; 1566 } 1567 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1568 sizeof(struct bge_tx_bd)); 1569 } 1570} 1571 1572static int 1573bge_init_tx_ring(struct bge_softc *sc) 1574{ 1575 sc->bge_txcnt = 0; 1576 sc->bge_tx_saved_considx = 0; 1577 1578 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1579 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1580 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1581 1582 /* Initialize transmit producer index for host-memory send ring. */ 1583 sc->bge_tx_prodidx = 0; 1584 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1585 1586 /* 5700 b2 errata */ 1587 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1588 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1589 1590 /* NIC-memory send ring not used; initialize to zero. */ 1591 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1592 /* 5700 b2 errata */ 1593 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1594 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1595 1596 return (0); 1597} 1598 1599static void 1600bge_setpromisc(struct bge_softc *sc) 1601{ 1602 struct ifnet *ifp; 1603 1604 BGE_LOCK_ASSERT(sc); 1605 1606 ifp = sc->bge_ifp; 1607 1608 /* Enable or disable promiscuous mode as needed. */ 1609 if (ifp->if_flags & IFF_PROMISC) 1610 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1611 else 1612 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1613} 1614 1615static void 1616bge_setmulti(struct bge_softc *sc) 1617{ 1618 struct ifnet *ifp; 1619 struct ifmultiaddr *ifma; 1620 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1621 int h, i; 1622 1623 BGE_LOCK_ASSERT(sc); 1624 1625 ifp = sc->bge_ifp; 1626 1627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1628 for (i = 0; i < 4; i++) 1629 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1630 return; 1631 } 1632 1633 /* First, zot all the existing filters. */ 1634 for (i = 0; i < 4; i++) 1635 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1636 1637 /* Now program new ones. */ 1638 if_maddr_rlock(ifp); 1639 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1640 if (ifma->ifma_addr->sa_family != AF_LINK) 1641 continue; 1642 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1643 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1644 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1645 } 1646 if_maddr_runlock(ifp); 1647 1648 for (i = 0; i < 4; i++) 1649 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1650} 1651 1652static void 1653bge_setvlan(struct bge_softc *sc) 1654{ 1655 struct ifnet *ifp; 1656 1657 BGE_LOCK_ASSERT(sc); 1658 1659 ifp = sc->bge_ifp; 1660 1661 /* Enable or disable VLAN tag stripping as needed. */ 1662 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1663 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1664 else 1665 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1666} 1667 1668static void 1669bge_sig_pre_reset(struct bge_softc *sc, int type) 1670{ 1671 1672 /* 1673 * Some chips don't like this so only do this if ASF is enabled 1674 */ 1675 if (sc->bge_asf_mode) 1676 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1677 1678 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1679 switch (type) { 1680 case BGE_RESET_START: 1681 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1682 BGE_FW_DRV_STATE_START); 1683 break; 1684 case BGE_RESET_SHUTDOWN: 1685 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1686 BGE_FW_DRV_STATE_UNLOAD); 1687 break; 1688 case BGE_RESET_SUSPEND: 1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1690 BGE_FW_DRV_STATE_SUSPEND); 1691 break; 1692 } 1693 } 1694 1695 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1696 bge_ape_driver_state_change(sc, type); 1697} 1698 1699static void 1700bge_sig_post_reset(struct bge_softc *sc, int type) 1701{ 1702 1703 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1704 switch (type) { 1705 case BGE_RESET_START: 1706 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1707 BGE_FW_DRV_STATE_START_DONE); 1708 /* START DONE */ 1709 break; 1710 case BGE_RESET_SHUTDOWN: 1711 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1712 BGE_FW_DRV_STATE_UNLOAD_DONE); 1713 break; 1714 } 1715 } 1716 if (type == BGE_RESET_SHUTDOWN) 1717 bge_ape_driver_state_change(sc, type); 1718} 1719 1720static void 1721bge_sig_legacy(struct bge_softc *sc, int type) 1722{ 1723 1724 if (sc->bge_asf_mode) { 1725 switch (type) { 1726 case BGE_RESET_START: 1727 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1728 BGE_FW_DRV_STATE_START); 1729 break; 1730 case BGE_RESET_SHUTDOWN: 1731 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1732 BGE_FW_DRV_STATE_UNLOAD); 1733 break; 1734 } 1735 } 1736} 1737 1738static void 1739bge_stop_fw(struct bge_softc *sc) 1740{ 1741 int i; 1742 1743 if (sc->bge_asf_mode) { 1744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1745 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1746 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1747 1748 for (i = 0; i < 100; i++ ) { 1749 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1750 BGE_RX_CPU_DRV_EVENT)) 1751 break; 1752 DELAY(10); 1753 } 1754 } 1755} 1756 1757static uint32_t 1758bge_dma_swap_options(struct bge_softc *sc) 1759{ 1760 uint32_t dma_options; 1761 1762 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1763 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1764#if BYTE_ORDER == BIG_ENDIAN 1765 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1766#endif 1767 return (dma_options); 1768} 1769 1770/* 1771 * Do endian, PCI and DMA initialization. 1772 */ 1773static int 1774bge_chipinit(struct bge_softc *sc) 1775{ 1776 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1777 uint16_t val; 1778 int i; 1779 1780 /* Set endianness before we access any non-PCI registers. */ 1781 misc_ctl = BGE_INIT; 1782 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1783 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1784 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1785 1786 /* 1787 * Clear the MAC statistics block in the NIC's 1788 * internal memory. 1789 */ 1790 for (i = BGE_STATS_BLOCK; 1791 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1792 BGE_MEMWIN_WRITE(sc, i, 0); 1793 1794 for (i = BGE_STATUS_BLOCK; 1795 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1796 BGE_MEMWIN_WRITE(sc, i, 0); 1797 1798 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1799 /* 1800 * Fix data corruption caused by non-qword write with WB. 1801 * Fix master abort in PCI mode. 1802 * Fix PCI latency timer. 1803 */ 1804 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1805 val |= (1 << 10) | (1 << 12) | (1 << 13); 1806 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1807 } 1808 1809 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1810 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1811 /* 1812 * For the 57766 and non Ax versions of 57765, bootcode 1813 * needs to setup the PCIE Fast Training Sequence (FTS) 1814 * value to prevent transmit hangs. 1815 */ 1816 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1817 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1818 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1819 BGE_CPMU_PADRNG_CTL_RDIV2); 1820 } 1821 } 1822 1823 /* 1824 * Set up the PCI DMA control register. 1825 */ 1826 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1827 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1828 if (sc->bge_flags & BGE_FLAG_PCIE) { 1829 if (sc->bge_mps >= 256) 1830 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1831 else 1832 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1833 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1834 if (BGE_IS_5714_FAMILY(sc)) { 1835 /* 256 bytes for read and write. */ 1836 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1837 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1838 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1839 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1840 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1841 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1842 /* 1843 * In the BCM5703, the DMA read watermark should 1844 * be set to less than or equal to the maximum 1845 * memory read byte count of the PCI-X command 1846 * register. 1847 */ 1848 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1849 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1850 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1851 /* 1536 bytes for read, 384 bytes for write. */ 1852 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1853 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1854 } else { 1855 /* 384 bytes for read and write. */ 1856 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1857 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1858 0x0F; 1859 } 1860 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1861 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1862 uint32_t tmp; 1863 1864 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1865 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1866 if (tmp == 6 || tmp == 7) 1867 dma_rw_ctl |= 1868 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1869 1870 /* Set PCI-X DMA write workaround. */ 1871 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1872 } 1873 } else { 1874 /* Conventional PCI bus: 256 bytes for read and write. */ 1875 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1876 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1877 1878 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1879 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1880 dma_rw_ctl |= 0x0F; 1881 } 1882 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1883 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1884 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1885 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1886 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1887 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1888 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1889 if (BGE_IS_5717_PLUS(sc)) { 1890 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1891 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1892 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1893 /* 1894 * Enable HW workaround for controllers that misinterpret 1895 * a status tag update and leave interrupts permanently 1896 * disabled. 1897 */ 1898 if (!BGE_IS_57765_PLUS(sc) && 1899 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1900 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1901 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1902 } 1903 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1904 1905 /* 1906 * Set up general mode register. 1907 */ 1908 mode_ctl = bge_dma_swap_options(sc); 1909 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1910 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1911 /* Retain Host-2-BMC settings written by APE firmware. */ 1912 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1913 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1914 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1915 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1916 } 1917 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1918 BGE_MODECTL_TX_NO_PHDR_CSUM; 1919 1920 /* 1921 * BCM5701 B5 have a bug causing data corruption when using 1922 * 64-bit DMA reads, which can be terminated early and then 1923 * completed later as 32-bit accesses, in combination with 1924 * certain bridges. 1925 */ 1926 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1927 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1928 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1929 1930 /* 1931 * Tell the firmware the driver is running 1932 */ 1933 if (sc->bge_asf_mode & ASF_STACKUP) 1934 mode_ctl |= BGE_MODECTL_STACKUP; 1935 1936 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1937 1938 /* 1939 * Disable memory write invalidate. Apparently it is not supported 1940 * properly by these devices. 1941 */ 1942 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1943 1944 /* Set the timer prescaler (always 66 MHz). */ 1945 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1946 1947 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1948 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1949 DELAY(40); /* XXX */ 1950 1951 /* Put PHY into ready state */ 1952 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1953 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1954 DELAY(40); 1955 } 1956 1957 return (0); 1958} 1959 1960static int 1961bge_blockinit(struct bge_softc *sc) 1962{ 1963 struct bge_rcb *rcb; 1964 bus_size_t vrcb; 1965 bge_hostaddr taddr; 1966 uint32_t dmactl, rdmareg, val; 1967 int i, limit; 1968 1969 /* 1970 * Initialize the memory window pointer register so that 1971 * we can access the first 32K of internal NIC RAM. This will 1972 * allow us to set up the TX send ring RCBs and the RX return 1973 * ring RCBs, plus other things which live in NIC memory. 1974 */ 1975 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1976 1977 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1978 1979 if (!(BGE_IS_5705_PLUS(sc))) { 1980 /* Configure mbuf memory pool */ 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1982 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1984 else 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1986 1987 /* Configure DMA resource pool */ 1988 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1989 BGE_DMA_DESCRIPTORS); 1990 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1991 } 1992 1993 /* Configure mbuf pool watermarks */ 1994 if (BGE_IS_5717_PLUS(sc)) { 1995 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1996 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1997 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1998 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1999 } else { 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2001 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2002 } 2003 } else if (!BGE_IS_5705_PLUS(sc)) { 2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2005 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2007 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2010 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2011 } else { 2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2015 } 2016 2017 /* Configure DMA resource watermarks */ 2018 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2019 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2020 2021 /* Enable buffer manager */ 2022 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2023 /* 2024 * Change the arbitration algorithm of TXMBUF read request to 2025 * round-robin instead of priority based for BCM5719. When 2026 * TXFIFO is almost empty, RDMA will hold its request until 2027 * TXFIFO is not almost empty. 2028 */ 2029 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2030 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2031 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2032 2033 /* Poll for buffer manager start indication */ 2034 for (i = 0; i < BGE_TIMEOUT; i++) { 2035 DELAY(10); 2036 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2037 break; 2038 } 2039 2040 if (i == BGE_TIMEOUT) { 2041 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2042 return (ENXIO); 2043 } 2044 2045 /* Enable flow-through queues */ 2046 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2047 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2048 2049 /* Wait until queue initialization is complete */ 2050 for (i = 0; i < BGE_TIMEOUT; i++) { 2051 DELAY(10); 2052 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2053 break; 2054 } 2055 2056 if (i == BGE_TIMEOUT) { 2057 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2058 return (ENXIO); 2059 } 2060 2061 /* 2062 * Summary of rings supported by the controller: 2063 * 2064 * Standard Receive Producer Ring 2065 * - This ring is used to feed receive buffers for "standard" 2066 * sized frames (typically 1536 bytes) to the controller. 2067 * 2068 * Jumbo Receive Producer Ring 2069 * - This ring is used to feed receive buffers for jumbo sized 2070 * frames (i.e. anything bigger than the "standard" frames) 2071 * to the controller. 2072 * 2073 * Mini Receive Producer Ring 2074 * - This ring is used to feed receive buffers for "mini" 2075 * sized frames to the controller. 2076 * - This feature required external memory for the controller 2077 * but was never used in a production system. Should always 2078 * be disabled. 2079 * 2080 * Receive Return Ring 2081 * - After the controller has placed an incoming frame into a 2082 * receive buffer that buffer is moved into a receive return 2083 * ring. The driver is then responsible to passing the 2084 * buffer up to the stack. Many versions of the controller 2085 * support multiple RR rings. 2086 * 2087 * Send Ring 2088 * - This ring is used for outgoing frames. Many versions of 2089 * the controller support multiple send rings. 2090 */ 2091 2092 /* Initialize the standard receive producer ring control block. */ 2093 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2094 rcb->bge_hostaddr.bge_addr_lo = 2095 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2096 rcb->bge_hostaddr.bge_addr_hi = 2097 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2098 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2099 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2100 if (BGE_IS_5717_PLUS(sc)) { 2101 /* 2102 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2103 * Bits 15-2 : Maximum RX frame size 2104 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2105 * Bit 0 : Reserved 2106 */ 2107 rcb->bge_maxlen_flags = 2108 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2109 } else if (BGE_IS_5705_PLUS(sc)) { 2110 /* 2111 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2112 * Bits 15-2 : Reserved (should be 0) 2113 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2114 * Bit 0 : Reserved 2115 */ 2116 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2117 } else { 2118 /* 2119 * Ring size is always XXX entries 2120 * Bits 31-16: Maximum RX frame size 2121 * Bits 15-2 : Reserved (should be 0) 2122 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2123 * Bit 0 : Reserved 2124 */ 2125 rcb->bge_maxlen_flags = 2126 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2127 } 2128 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2129 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2130 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2131 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2132 else 2133 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2134 /* Write the standard receive producer ring control block. */ 2135 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2136 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2137 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2139 2140 /* Reset the standard receive producer ring producer index. */ 2141 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2142 2143 /* 2144 * Initialize the jumbo RX producer ring control 2145 * block. We set the 'ring disabled' bit in the 2146 * flags field until we're actually ready to start 2147 * using this ring (i.e. once we set the MTU 2148 * high enough to require it). 2149 */ 2150 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2151 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2152 /* Get the jumbo receive producer ring RCB parameters. */ 2153 rcb->bge_hostaddr.bge_addr_lo = 2154 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2155 rcb->bge_hostaddr.bge_addr_hi = 2156 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2157 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2158 sc->bge_cdata.bge_rx_jumbo_ring_map, 2159 BUS_DMASYNC_PREREAD); 2160 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2161 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2162 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2163 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2164 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2165 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2166 else 2167 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2168 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2169 rcb->bge_hostaddr.bge_addr_hi); 2170 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2171 rcb->bge_hostaddr.bge_addr_lo); 2172 /* Program the jumbo receive producer ring RCB parameters. */ 2173 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2174 rcb->bge_maxlen_flags); 2175 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2176 /* Reset the jumbo receive producer ring producer index. */ 2177 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2178 } 2179 2180 /* Disable the mini receive producer ring RCB. */ 2181 if (BGE_IS_5700_FAMILY(sc)) { 2182 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2183 rcb->bge_maxlen_flags = 2184 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2185 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2186 rcb->bge_maxlen_flags); 2187 /* Reset the mini receive producer ring producer index. */ 2188 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2189 } 2190 2191 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2192 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2193 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2194 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2195 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2196 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2197 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2198 } 2199 /* 2200 * The BD ring replenish thresholds control how often the 2201 * hardware fetches new BD's from the producer rings in host 2202 * memory. Setting the value too low on a busy system can 2203 * starve the hardware and recue the throughpout. 2204 * 2205 * Set the BD ring replentish thresholds. The recommended 2206 * values are 1/8th the number of descriptors allocated to 2207 * each ring. 2208 * XXX The 5754 requires a lower threshold, so it might be a 2209 * requirement of all 575x family chips. The Linux driver sets 2210 * the lower threshold for all 5705 family chips as well, but there 2211 * are reports that it might not need to be so strict. 2212 * 2213 * XXX Linux does some extra fiddling here for the 5906 parts as 2214 * well. 2215 */ 2216 if (BGE_IS_5705_PLUS(sc)) 2217 val = 8; 2218 else 2219 val = BGE_STD_RX_RING_CNT / 8; 2220 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2221 if (BGE_IS_JUMBO_CAPABLE(sc)) 2222 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2223 BGE_JUMBO_RX_RING_CNT/8); 2224 if (BGE_IS_5717_PLUS(sc)) { 2225 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2226 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2227 } 2228 2229 /* 2230 * Disable all send rings by setting the 'ring disabled' bit 2231 * in the flags field of all the TX send ring control blocks, 2232 * located in NIC memory. 2233 */ 2234 if (!BGE_IS_5705_PLUS(sc)) 2235 /* 5700 to 5704 had 16 send rings. */ 2236 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2237 else if (BGE_IS_57765_PLUS(sc) || 2238 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2239 limit = 2; 2240 else if (BGE_IS_5717_PLUS(sc)) 2241 limit = 4; 2242 else 2243 limit = 1; 2244 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2245 for (i = 0; i < limit; i++) { 2246 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2247 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2248 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2249 vrcb += sizeof(struct bge_rcb); 2250 } 2251 2252 /* Configure send ring RCB 0 (we use only the first ring) */ 2253 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2254 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2255 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2256 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2257 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2258 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2259 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2260 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2261 else 2262 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2263 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2264 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2265 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2266 2267 /* 2268 * Disable all receive return rings by setting the 2269 * 'ring diabled' bit in the flags field of all the receive 2270 * return ring control blocks, located in NIC memory. 2271 */ 2272 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2273 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2274 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2275 /* Should be 17, use 16 until we get an SRAM map. */ 2276 limit = 16; 2277 } else if (!BGE_IS_5705_PLUS(sc)) 2278 limit = BGE_RX_RINGS_MAX; 2279 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2280 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2281 BGE_IS_57765_PLUS(sc)) 2282 limit = 4; 2283 else 2284 limit = 1; 2285 /* Disable all receive return rings. */ 2286 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2287 for (i = 0; i < limit; i++) { 2288 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2289 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2290 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2291 BGE_RCB_FLAG_RING_DISABLED); 2292 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2293 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2294 (i * (sizeof(uint64_t))), 0); 2295 vrcb += sizeof(struct bge_rcb); 2296 } 2297 2298 /* 2299 * Set up receive return ring 0. Note that the NIC address 2300 * for RX return rings is 0x0. The return rings live entirely 2301 * within the host, so the nicaddr field in the RCB isn't used. 2302 */ 2303 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2304 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2305 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2306 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2307 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2308 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2309 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2310 2311 /* Set random backoff seed for TX */ 2312 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2313 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2314 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2315 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2316 BGE_TX_BACKOFF_SEED_MASK); 2317 2318 /* Set inter-packet gap */ 2319 val = 0x2620; 2320 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2321 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2322 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2323 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2324 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2325 2326 /* 2327 * Specify which ring to use for packets that don't match 2328 * any RX rules. 2329 */ 2330 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2331 2332 /* 2333 * Configure number of RX lists. One interrupt distribution 2334 * list, sixteen active lists, one bad frames class. 2335 */ 2336 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2337 2338 /* Inialize RX list placement stats mask. */ 2339 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2340 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2341 2342 /* Disable host coalescing until we get it set up */ 2343 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2344 2345 /* Poll to make sure it's shut down. */ 2346 for (i = 0; i < BGE_TIMEOUT; i++) { 2347 DELAY(10); 2348 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2349 break; 2350 } 2351 2352 if (i == BGE_TIMEOUT) { 2353 device_printf(sc->bge_dev, 2354 "host coalescing engine failed to idle\n"); 2355 return (ENXIO); 2356 } 2357 2358 /* Set up host coalescing defaults */ 2359 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2360 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2361 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2362 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2363 if (!(BGE_IS_5705_PLUS(sc))) { 2364 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2365 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2366 } 2367 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2368 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2369 2370 /* Set up address of statistics block */ 2371 if (!(BGE_IS_5705_PLUS(sc))) { 2372 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2373 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2374 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2375 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2376 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2377 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2378 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2379 } 2380 2381 /* Set up address of status block */ 2382 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2383 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2384 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2385 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2386 2387 /* Set up status block size. */ 2388 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2389 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2390 val = BGE_STATBLKSZ_FULL; 2391 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2392 } else { 2393 val = BGE_STATBLKSZ_32BYTE; 2394 bzero(sc->bge_ldata.bge_status_block, 32); 2395 } 2396 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2397 sc->bge_cdata.bge_status_map, 2398 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2399 2400 /* Turn on host coalescing state machine */ 2401 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2402 2403 /* Turn on RX BD completion state machine and enable attentions */ 2404 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2405 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2406 2407 /* Turn on RX list placement state machine */ 2408 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2409 2410 /* Turn on RX list selector state machine. */ 2411 if (!(BGE_IS_5705_PLUS(sc))) 2412 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2413 2414 /* Turn on DMA, clear stats. */ 2415 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2416 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2417 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2418 BGE_MACMODE_FRMHDR_DMA_ENB; 2419 2420 if (sc->bge_flags & BGE_FLAG_TBI) 2421 val |= BGE_PORTMODE_TBI; 2422 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2423 val |= BGE_PORTMODE_GMII; 2424 else 2425 val |= BGE_PORTMODE_MII; 2426 2427 /* Allow APE to send/receive frames. */ 2428 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2429 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2430 2431 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2432 DELAY(40); 2433 2434 /* Set misc. local control, enable interrupts on attentions */ 2435 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2436 2437#ifdef notdef 2438 /* Assert GPIO pins for PHY reset */ 2439 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2440 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2441 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2442 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2443#endif 2444 2445 /* Turn on DMA completion state machine */ 2446 if (!(BGE_IS_5705_PLUS(sc))) 2447 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2448 2449 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2450 2451 /* Enable host coalescing bug fix. */ 2452 if (BGE_IS_5755_PLUS(sc)) 2453 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2454 2455 /* Request larger DMA burst size to get better performance. */ 2456 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2457 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2458 2459 /* Turn on write DMA state machine */ 2460 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2461 DELAY(40); 2462 2463 /* Turn on read DMA state machine */ 2464 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2465 2466 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2467 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2468 2469 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2470 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2471 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2472 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2473 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2474 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2475 if (sc->bge_flags & BGE_FLAG_PCIE) 2476 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2477 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2478 val |= BGE_RDMAMODE_TSO4_ENABLE; 2479 if (sc->bge_flags & BGE_FLAG_TSO3 || 2480 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2481 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2482 val |= BGE_RDMAMODE_TSO6_ENABLE; 2483 } 2484 2485 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2486 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2487 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2488 BGE_RDMAMODE_H2BNC_VLAN_DET; 2489 /* 2490 * Allow multiple outstanding read requests from 2491 * non-LSO read DMA engine. 2492 */ 2493 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2494 } 2495 2496 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2497 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2498 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2499 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2500 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2501 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2502 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2503 else 2504 rdmareg = BGE_RDMA_RSRVCTRL; 2505 dmactl = CSR_READ_4(sc, rdmareg); 2506 /* 2507 * Adjust tx margin to prevent TX data corruption and 2508 * fix internal FIFO overflow. 2509 */ 2510 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2511 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2512 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2513 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2514 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2515 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2516 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2517 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2518 } 2519 /* 2520 * Enable fix for read DMA FIFO overruns. 2521 * The fix is to limit the number of RX BDs 2522 * the hardware would fetch at a fime. 2523 */ 2524 CSR_WRITE_4(sc, rdmareg, dmactl | 2525 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2526 } 2527 2528 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2529 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2530 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2531 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2532 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2533 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2534 /* 2535 * Allow 4KB burst length reads for non-LSO frames. 2536 * Enable 512B burst length reads for buffer descriptors. 2537 */ 2538 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2539 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2540 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2541 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2542 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2543 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2544 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2545 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2546 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2547 } 2548 2549 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2550 DELAY(40); 2551 2552 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2553 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2554 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2555 if ((val & 0xFFFF) > BGE_FRAMELEN) 2556 break; 2557 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2558 break; 2559 } 2560 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2561 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2562 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2563 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2564 else 2565 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2566 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2567 } 2568 } 2569 2570 /* Turn on RX data completion state machine */ 2571 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2572 2573 /* Turn on RX BD initiator state machine */ 2574 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2575 2576 /* Turn on RX data and RX BD initiator state machine */ 2577 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2578 2579 /* Turn on Mbuf cluster free state machine */ 2580 if (!(BGE_IS_5705_PLUS(sc))) 2581 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2582 2583 /* Turn on send BD completion state machine */ 2584 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2585 2586 /* Turn on send data completion state machine */ 2587 val = BGE_SDCMODE_ENABLE; 2588 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2589 val |= BGE_SDCMODE_CDELAY; 2590 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2591 2592 /* Turn on send data initiator state machine */ 2593 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2594 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2595 BGE_SDIMODE_HW_LSO_PRE_DMA); 2596 else 2597 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2598 2599 /* Turn on send BD initiator state machine */ 2600 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2601 2602 /* Turn on send BD selector state machine */ 2603 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2604 2605 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2606 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2607 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2608 2609 /* ack/clear link change events */ 2610 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2611 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2612 BGE_MACSTAT_LINK_CHANGED); 2613 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2614 2615 /* 2616 * Enable attention when the link has changed state for 2617 * devices that use auto polling. 2618 */ 2619 if (sc->bge_flags & BGE_FLAG_TBI) { 2620 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2621 } else { 2622 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2623 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2624 DELAY(80); 2625 } 2626 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2627 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2628 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2629 BGE_EVTENB_MI_INTERRUPT); 2630 } 2631 2632 /* 2633 * Clear any pending link state attention. 2634 * Otherwise some link state change events may be lost until attention 2635 * is cleared by bge_intr() -> bge_link_upd() sequence. 2636 * It's not necessary on newer BCM chips - perhaps enabling link 2637 * state change attentions implies clearing pending attention. 2638 */ 2639 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2640 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2641 BGE_MACSTAT_LINK_CHANGED); 2642 2643 /* Enable link state change attentions. */ 2644 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2645 2646 return (0); 2647} 2648 2649static const struct bge_revision * 2650bge_lookup_rev(uint32_t chipid) 2651{ 2652 const struct bge_revision *br; 2653 2654 for (br = bge_revisions; br->br_name != NULL; br++) { 2655 if (br->br_chipid == chipid) 2656 return (br); 2657 } 2658 2659 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2660 if (br->br_chipid == BGE_ASICREV(chipid)) 2661 return (br); 2662 } 2663 2664 return (NULL); 2665} 2666 2667static const struct bge_vendor * 2668bge_lookup_vendor(uint16_t vid) 2669{ 2670 const struct bge_vendor *v; 2671 2672 for (v = bge_vendors; v->v_name != NULL; v++) 2673 if (v->v_id == vid) 2674 return (v); 2675 2676 return (NULL); 2677} 2678 2679static uint32_t 2680bge_chipid(device_t dev) 2681{ 2682 uint32_t id; 2683 2684 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2685 BGE_PCIMISCCTL_ASICREV_SHIFT; 2686 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2687 /* 2688 * Find the ASCI revision. Different chips use different 2689 * registers. 2690 */ 2691 switch (pci_get_device(dev)) { 2692 case BCOM_DEVICEID_BCM5717: 2693 case BCOM_DEVICEID_BCM5718: 2694 case BCOM_DEVICEID_BCM5719: 2695 case BCOM_DEVICEID_BCM5720: 2696 case BCOM_DEVICEID_BCM5725: 2697 case BCOM_DEVICEID_BCM5727: 2698 case BCOM_DEVICEID_BCM5762: 2699 case BCOM_DEVICEID_BCM57764: 2700 case BCOM_DEVICEID_BCM57767: 2701 case BCOM_DEVICEID_BCM57787: 2702 id = pci_read_config(dev, 2703 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2704 break; 2705 case BCOM_DEVICEID_BCM57761: 2706 case BCOM_DEVICEID_BCM57762: 2707 case BCOM_DEVICEID_BCM57765: 2708 case BCOM_DEVICEID_BCM57766: 2709 case BCOM_DEVICEID_BCM57781: 2710 case BCOM_DEVICEID_BCM57782: 2711 case BCOM_DEVICEID_BCM57785: 2712 case BCOM_DEVICEID_BCM57786: 2713 case BCOM_DEVICEID_BCM57791: 2714 case BCOM_DEVICEID_BCM57795: 2715 id = pci_read_config(dev, 2716 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2717 break; 2718 default: 2719 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2720 } 2721 } 2722 return (id); 2723} 2724 2725/* 2726 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2727 * against our list and return its name if we find a match. 2728 * 2729 * Note that since the Broadcom controller contains VPD support, we 2730 * try to get the device name string from the controller itself instead 2731 * of the compiled-in string. It guarantees we'll always announce the 2732 * right product name. We fall back to the compiled-in string when 2733 * VPD is unavailable or corrupt. 2734 */ 2735static int 2736bge_probe(device_t dev) 2737{ 2738 char buf[96]; 2739 char model[64]; 2740 const struct bge_revision *br; 2741 const char *pname; 2742 struct bge_softc *sc; 2743 const struct bge_type *t = bge_devs; 2744 const struct bge_vendor *v; 2745 uint32_t id; 2746 uint16_t did, vid; 2747 2748 sc = device_get_softc(dev); 2749 sc->bge_dev = dev; 2750 vid = pci_get_vendor(dev); 2751 did = pci_get_device(dev); 2752 while(t->bge_vid != 0) { 2753 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2754 id = bge_chipid(dev); 2755 br = bge_lookup_rev(id); 2756 if (bge_has_eaddr(sc) && 2757 pci_get_vpd_ident(dev, &pname) == 0) 2758 snprintf(model, sizeof(model), "%s", pname); 2759 else { 2760 v = bge_lookup_vendor(vid); 2761 snprintf(model, sizeof(model), "%s %s", 2762 v != NULL ? v->v_name : "Unknown", 2763 br != NULL ? br->br_name : 2764 "NetXtreme/NetLink Ethernet Controller"); 2765 } 2766 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2767 model, br != NULL ? "" : "unknown ", id); 2768 device_set_desc_copy(dev, buf); 2769 return (BUS_PROBE_DEFAULT); 2770 } 2771 t++; 2772 } 2773 2774 return (ENXIO); 2775} 2776 2777static void 2778bge_dma_free(struct bge_softc *sc) 2779{ 2780 int i; 2781 2782 /* Destroy DMA maps for RX buffers. */ 2783 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2784 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2785 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2786 sc->bge_cdata.bge_rx_std_dmamap[i]); 2787 } 2788 if (sc->bge_cdata.bge_rx_std_sparemap) 2789 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2790 sc->bge_cdata.bge_rx_std_sparemap); 2791 2792 /* Destroy DMA maps for jumbo RX buffers. */ 2793 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2794 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2795 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2796 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2797 } 2798 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2799 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2800 sc->bge_cdata.bge_rx_jumbo_sparemap); 2801 2802 /* Destroy DMA maps for TX buffers. */ 2803 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2804 if (sc->bge_cdata.bge_tx_dmamap[i]) 2805 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2806 sc->bge_cdata.bge_tx_dmamap[i]); 2807 } 2808 2809 if (sc->bge_cdata.bge_rx_mtag) 2810 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2811 if (sc->bge_cdata.bge_mtag_jumbo) 2812 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2813 if (sc->bge_cdata.bge_tx_mtag) 2814 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2815 2816 /* Destroy standard RX ring. */ 2817 if (sc->bge_cdata.bge_rx_std_ring_map) 2818 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2819 sc->bge_cdata.bge_rx_std_ring_map); 2820 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2821 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2822 sc->bge_ldata.bge_rx_std_ring, 2823 sc->bge_cdata.bge_rx_std_ring_map); 2824 2825 if (sc->bge_cdata.bge_rx_std_ring_tag) 2826 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2827 2828 /* Destroy jumbo RX ring. */ 2829 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2830 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2831 sc->bge_cdata.bge_rx_jumbo_ring_map); 2832 2833 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2834 sc->bge_ldata.bge_rx_jumbo_ring) 2835 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2836 sc->bge_ldata.bge_rx_jumbo_ring, 2837 sc->bge_cdata.bge_rx_jumbo_ring_map); 2838 2839 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2840 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2841 2842 /* Destroy RX return ring. */ 2843 if (sc->bge_cdata.bge_rx_return_ring_map) 2844 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2845 sc->bge_cdata.bge_rx_return_ring_map); 2846 2847 if (sc->bge_cdata.bge_rx_return_ring_map && 2848 sc->bge_ldata.bge_rx_return_ring) 2849 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2850 sc->bge_ldata.bge_rx_return_ring, 2851 sc->bge_cdata.bge_rx_return_ring_map); 2852 2853 if (sc->bge_cdata.bge_rx_return_ring_tag) 2854 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2855 2856 /* Destroy TX ring. */ 2857 if (sc->bge_cdata.bge_tx_ring_map) 2858 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2859 sc->bge_cdata.bge_tx_ring_map); 2860 2861 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2862 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2863 sc->bge_ldata.bge_tx_ring, 2864 sc->bge_cdata.bge_tx_ring_map); 2865 2866 if (sc->bge_cdata.bge_tx_ring_tag) 2867 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2868 2869 /* Destroy status block. */ 2870 if (sc->bge_cdata.bge_status_map) 2871 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2872 sc->bge_cdata.bge_status_map); 2873 2874 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2875 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2876 sc->bge_ldata.bge_status_block, 2877 sc->bge_cdata.bge_status_map); 2878 2879 if (sc->bge_cdata.bge_status_tag) 2880 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2881 2882 /* Destroy statistics block. */ 2883 if (sc->bge_cdata.bge_stats_map) 2884 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2885 sc->bge_cdata.bge_stats_map); 2886 2887 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2888 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2889 sc->bge_ldata.bge_stats, 2890 sc->bge_cdata.bge_stats_map); 2891 2892 if (sc->bge_cdata.bge_stats_tag) 2893 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2894 2895 if (sc->bge_cdata.bge_buffer_tag) 2896 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2897 2898 /* Destroy the parent tag. */ 2899 if (sc->bge_cdata.bge_parent_tag) 2900 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2901} 2902 2903static int 2904bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2905 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2906 bus_addr_t *paddr, const char *msg) 2907{ 2908 struct bge_dmamap_arg ctx; 2909 int error; 2910 2911 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2912 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2913 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2914 if (error != 0) { 2915 device_printf(sc->bge_dev, 2916 "could not create %s dma tag\n", msg); 2917 return (ENOMEM); 2918 } 2919 /* Allocate DMA'able memory for ring. */ 2920 error = bus_dmamem_alloc(*tag, (void **)ring, 2921 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2922 if (error != 0) { 2923 device_printf(sc->bge_dev, 2924 "could not allocate DMA'able memory for %s\n", msg); 2925 return (ENOMEM); 2926 } 2927 /* Load the address of the ring. */ 2928 ctx.bge_busaddr = 0; 2929 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2930 &ctx, BUS_DMA_NOWAIT); 2931 if (error != 0) { 2932 device_printf(sc->bge_dev, 2933 "could not load DMA'able memory for %s\n", msg); 2934 return (ENOMEM); 2935 } 2936 *paddr = ctx.bge_busaddr; 2937 return (0); 2938} 2939 2940static int 2941bge_dma_alloc(struct bge_softc *sc) 2942{ 2943 bus_addr_t lowaddr; 2944 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2945 int i, error; 2946 2947 lowaddr = BUS_SPACE_MAXADDR; 2948 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2949 lowaddr = BGE_DMA_MAXADDR; 2950 /* 2951 * Allocate the parent bus DMA tag appropriate for PCI. 2952 */ 2953 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2954 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2955 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2956 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2957 if (error != 0) { 2958 device_printf(sc->bge_dev, 2959 "could not allocate parent dma tag\n"); 2960 return (ENOMEM); 2961 } 2962 2963 /* Create tag for standard RX ring. */ 2964 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2965 &sc->bge_cdata.bge_rx_std_ring_tag, 2966 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2967 &sc->bge_cdata.bge_rx_std_ring_map, 2968 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2969 if (error) 2970 return (error); 2971 2972 /* Create tag for RX return ring. */ 2973 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2974 &sc->bge_cdata.bge_rx_return_ring_tag, 2975 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2976 &sc->bge_cdata.bge_rx_return_ring_map, 2977 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2978 if (error) 2979 return (error); 2980 2981 /* Create tag for TX ring. */ 2982 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2983 &sc->bge_cdata.bge_tx_ring_tag, 2984 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2985 &sc->bge_cdata.bge_tx_ring_map, 2986 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2987 if (error) 2988 return (error); 2989 2990 /* 2991 * Create tag for status block. 2992 * Because we only use single Tx/Rx/Rx return ring, use 2993 * minimum status block size except BCM5700 AX/BX which 2994 * seems to want to see full status block size regardless 2995 * of configured number of ring. 2996 */ 2997 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2998 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2999 sbsz = BGE_STATUS_BLK_SZ; 3000 else 3001 sbsz = 32; 3002 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3003 &sc->bge_cdata.bge_status_tag, 3004 (uint8_t **)&sc->bge_ldata.bge_status_block, 3005 &sc->bge_cdata.bge_status_map, 3006 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3007 if (error) 3008 return (error); 3009 3010 /* Create tag for statistics block. */ 3011 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3012 &sc->bge_cdata.bge_stats_tag, 3013 (uint8_t **)&sc->bge_ldata.bge_stats, 3014 &sc->bge_cdata.bge_stats_map, 3015 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3016 if (error) 3017 return (error); 3018 3019 /* Create tag for jumbo RX ring. */ 3020 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3021 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3022 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3023 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3024 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3025 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3026 if (error) 3027 return (error); 3028 } 3029 3030 /* Create parent tag for buffers. */ 3031 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3032 /* 3033 * XXX 3034 * watchdog timeout issue was observed on BCM5704 which 3035 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3036 * Both limiting DMA address space to 32bits and flushing 3037 * mailbox write seem to address the issue. 3038 */ 3039 if (sc->bge_pcixcap != 0) 3040 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3041 } 3042 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3043 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3044 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3045 &sc->bge_cdata.bge_buffer_tag); 3046 if (error != 0) { 3047 device_printf(sc->bge_dev, 3048 "could not allocate buffer dma tag\n"); 3049 return (ENOMEM); 3050 } 3051 /* Create tag for Tx mbufs. */ 3052 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3053 txsegsz = BGE_TSOSEG_SZ; 3054 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3055 } else { 3056 txsegsz = MCLBYTES; 3057 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3058 } 3059 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3060 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3061 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3062 &sc->bge_cdata.bge_tx_mtag); 3063 3064 if (error) { 3065 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3066 return (ENOMEM); 3067 } 3068 3069 /* Create tag for Rx mbufs. */ 3070 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3071 rxmaxsegsz = MJUM9BYTES; 3072 else 3073 rxmaxsegsz = MCLBYTES; 3074 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3075 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3076 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3077 3078 if (error) { 3079 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3080 return (ENOMEM); 3081 } 3082 3083 /* Create DMA maps for RX buffers. */ 3084 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3085 &sc->bge_cdata.bge_rx_std_sparemap); 3086 if (error) { 3087 device_printf(sc->bge_dev, 3088 "can't create spare DMA map for RX\n"); 3089 return (ENOMEM); 3090 } 3091 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3092 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3093 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3094 if (error) { 3095 device_printf(sc->bge_dev, 3096 "can't create DMA map for RX\n"); 3097 return (ENOMEM); 3098 } 3099 } 3100 3101 /* Create DMA maps for TX buffers. */ 3102 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3103 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3104 &sc->bge_cdata.bge_tx_dmamap[i]); 3105 if (error) { 3106 device_printf(sc->bge_dev, 3107 "can't create DMA map for TX\n"); 3108 return (ENOMEM); 3109 } 3110 } 3111 3112 /* Create tags for jumbo RX buffers. */ 3113 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3114 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3115 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3116 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3117 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3118 if (error) { 3119 device_printf(sc->bge_dev, 3120 "could not allocate jumbo dma tag\n"); 3121 return (ENOMEM); 3122 } 3123 /* Create DMA maps for jumbo RX buffers. */ 3124 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3125 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3126 if (error) { 3127 device_printf(sc->bge_dev, 3128 "can't create spare DMA map for jumbo RX\n"); 3129 return (ENOMEM); 3130 } 3131 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3132 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3133 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3134 if (error) { 3135 device_printf(sc->bge_dev, 3136 "can't create DMA map for jumbo RX\n"); 3137 return (ENOMEM); 3138 } 3139 } 3140 } 3141 3142 return (0); 3143} 3144 3145/* 3146 * Return true if this device has more than one port. 3147 */ 3148static int 3149bge_has_multiple_ports(struct bge_softc *sc) 3150{ 3151 device_t dev = sc->bge_dev; 3152 u_int b, d, f, fscan, s; 3153 3154 d = pci_get_domain(dev); 3155 b = pci_get_bus(dev); 3156 s = pci_get_slot(dev); 3157 f = pci_get_function(dev); 3158 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3159 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3160 return (1); 3161 return (0); 3162} 3163 3164/* 3165 * Return true if MSI can be used with this device. 3166 */ 3167static int 3168bge_can_use_msi(struct bge_softc *sc) 3169{ 3170 int can_use_msi = 0; 3171 3172 if (sc->bge_msi == 0) 3173 return (0); 3174 3175 /* Disable MSI for polling(4). */ 3176#ifdef DEVICE_POLLING 3177 return (0); 3178#endif 3179 switch (sc->bge_asicrev) { 3180 case BGE_ASICREV_BCM5714_A0: 3181 case BGE_ASICREV_BCM5714: 3182 /* 3183 * Apparently, MSI doesn't work when these chips are 3184 * configured in single-port mode. 3185 */ 3186 if (bge_has_multiple_ports(sc)) 3187 can_use_msi = 1; 3188 break; 3189 case BGE_ASICREV_BCM5750: 3190 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3191 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3192 can_use_msi = 1; 3193 break; 3194 default: 3195 if (BGE_IS_575X_PLUS(sc)) 3196 can_use_msi = 1; 3197 } 3198 return (can_use_msi); 3199} 3200 3201static int 3202bge_mbox_reorder(struct bge_softc *sc) 3203{ 3204 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3205 static const struct mbox_reorder { 3206 const uint16_t vendor; 3207 const uint16_t device; 3208 const char *desc; 3209 } mbox_reorder_lists[] = { 3210 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3211 }; 3212 devclass_t pci, pcib; 3213 device_t bus, dev; 3214 int i; 3215 3216 pci = devclass_find("pci"); 3217 pcib = devclass_find("pcib"); 3218 dev = sc->bge_dev; 3219 bus = device_get_parent(dev); 3220 for (;;) { 3221 dev = device_get_parent(bus); 3222 bus = device_get_parent(dev); 3223 if (device_get_devclass(dev) != pcib) 3224 break; 3225 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3226 if (pci_get_vendor(dev) == 3227 mbox_reorder_lists[i].vendor && 3228 pci_get_device(dev) == 3229 mbox_reorder_lists[i].device) { 3230 device_printf(sc->bge_dev, 3231 "enabling MBOX workaround for %s\n", 3232 mbox_reorder_lists[i].desc); 3233 return (1); 3234 } 3235 } 3236 if (device_get_devclass(bus) != pci) 3237 break; 3238 } 3239 return (0); 3240} 3241 3242static void 3243bge_devinfo(struct bge_softc *sc) 3244{ 3245 uint32_t cfg, clk; 3246 3247 device_printf(sc->bge_dev, 3248 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3249 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3250 if (sc->bge_flags & BGE_FLAG_PCIE) 3251 printf("PCI-E\n"); 3252 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3253 printf("PCI-X "); 3254 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3255 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3256 clk = 133; 3257 else { 3258 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3259 switch (clk) { 3260 case 0: 3261 clk = 33; 3262 break; 3263 case 2: 3264 clk = 50; 3265 break; 3266 case 4: 3267 clk = 66; 3268 break; 3269 case 6: 3270 clk = 100; 3271 break; 3272 case 7: 3273 clk = 133; 3274 break; 3275 } 3276 } 3277 printf("%u MHz\n", clk); 3278 } else { 3279 if (sc->bge_pcixcap != 0) 3280 printf("PCI on PCI-X "); 3281 else 3282 printf("PCI "); 3283 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3284 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3285 clk = 66; 3286 else 3287 clk = 33; 3288 if (cfg & BGE_PCISTATE_32BIT_BUS) 3289 printf("%u MHz; 32bit\n", clk); 3290 else 3291 printf("%u MHz; 64bit\n", clk); 3292 } 3293} 3294 3295static int 3296bge_attach(device_t dev) 3297{ 3298 struct ifnet *ifp; 3299 struct bge_softc *sc; 3300 uint32_t hwcfg = 0, misccfg, pcistate; 3301 u_char eaddr[ETHER_ADDR_LEN]; 3302 int capmask, error, reg, rid, trys; 3303 3304 sc = device_get_softc(dev); 3305 sc->bge_dev = dev; 3306 3307 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3308 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3309 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3310 3311 pci_enable_busmaster(dev); 3312 3313 /* 3314 * Allocate control/status registers. 3315 */ 3316 rid = PCIR_BAR(0); 3317 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3318 RF_ACTIVE); 3319 3320 if (sc->bge_res == NULL) { 3321 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3322 error = ENXIO; 3323 goto fail; 3324 } 3325 3326 /* Save various chip information. */ 3327 sc->bge_func_addr = pci_get_function(dev); 3328 sc->bge_chipid = bge_chipid(dev); 3329 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3330 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3331 3332 /* Set default PHY address. */ 3333 sc->bge_phy_addr = 1; 3334 /* 3335 * PHY address mapping for various devices. 3336 * 3337 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3338 * ---------+-------+-------+-------+-------+ 3339 * BCM57XX | 1 | X | X | X | 3340 * BCM5704 | 1 | X | 1 | X | 3341 * BCM5717 | 1 | 8 | 2 | 9 | 3342 * BCM5719 | 1 | 8 | 2 | 9 | 3343 * BCM5720 | 1 | 8 | 2 | 9 | 3344 * 3345 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3346 * ---------+-------+-------+-------+-------+ 3347 * BCM57XX | X | X | X | X | 3348 * BCM5704 | X | X | X | X | 3349 * BCM5717 | X | X | X | X | 3350 * BCM5719 | 3 | 10 | 4 | 11 | 3351 * BCM5720 | X | X | X | X | 3352 * 3353 * Other addresses may respond but they are not 3354 * IEEE compliant PHYs and should be ignored. 3355 */ 3356 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3357 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3358 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3359 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3360 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3361 BGE_SGDIGSTS_IS_SERDES) 3362 sc->bge_phy_addr = sc->bge_func_addr + 8; 3363 else 3364 sc->bge_phy_addr = sc->bge_func_addr + 1; 3365 } else { 3366 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3367 BGE_CPMU_PHY_STRAP_IS_SERDES) 3368 sc->bge_phy_addr = sc->bge_func_addr + 8; 3369 else 3370 sc->bge_phy_addr = sc->bge_func_addr + 1; 3371 } 3372 } 3373 3374 if (bge_has_eaddr(sc)) 3375 sc->bge_flags |= BGE_FLAG_EADDR; 3376 3377 /* Save chipset family. */ 3378 switch (sc->bge_asicrev) { 3379 case BGE_ASICREV_BCM5762: 3380 case BGE_ASICREV_BCM57765: 3381 case BGE_ASICREV_BCM57766: 3382 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3383 /* FALLTHROUGH */ 3384 case BGE_ASICREV_BCM5717: 3385 case BGE_ASICREV_BCM5719: 3386 case BGE_ASICREV_BCM5720: 3387 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3388 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3389 BGE_FLAG_JUMBO_FRAME; 3390 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3391 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3392 /* 3393 * Enable work around for DMA engine miscalculation 3394 * of TXMBUF available space. 3395 */ 3396 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3397 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3398 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3399 /* Jumbo frame on BCM5719 A0 does not work. */ 3400 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3401 } 3402 } 3403 break; 3404 case BGE_ASICREV_BCM5755: 3405 case BGE_ASICREV_BCM5761: 3406 case BGE_ASICREV_BCM5784: 3407 case BGE_ASICREV_BCM5785: 3408 case BGE_ASICREV_BCM5787: 3409 case BGE_ASICREV_BCM57780: 3410 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3411 BGE_FLAG_5705_PLUS; 3412 break; 3413 case BGE_ASICREV_BCM5700: 3414 case BGE_ASICREV_BCM5701: 3415 case BGE_ASICREV_BCM5703: 3416 case BGE_ASICREV_BCM5704: 3417 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3418 break; 3419 case BGE_ASICREV_BCM5714_A0: 3420 case BGE_ASICREV_BCM5780: 3421 case BGE_ASICREV_BCM5714: 3422 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3423 /* FALLTHROUGH */ 3424 case BGE_ASICREV_BCM5750: 3425 case BGE_ASICREV_BCM5752: 3426 case BGE_ASICREV_BCM5906: 3427 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3428 /* FALLTHROUGH */ 3429 case BGE_ASICREV_BCM5705: 3430 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3431 break; 3432 } 3433 3434 /* Identify chips with APE processor. */ 3435 switch (sc->bge_asicrev) { 3436 case BGE_ASICREV_BCM5717: 3437 case BGE_ASICREV_BCM5719: 3438 case BGE_ASICREV_BCM5720: 3439 case BGE_ASICREV_BCM5761: 3440 case BGE_ASICREV_BCM5762: 3441 sc->bge_flags |= BGE_FLAG_APE; 3442 break; 3443 } 3444 3445 /* Chips with APE need BAR2 access for APE registers/memory. */ 3446 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3447 rid = PCIR_BAR(2); 3448 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3449 RF_ACTIVE); 3450 if (sc->bge_res2 == NULL) { 3451 device_printf (sc->bge_dev, 3452 "couldn't map BAR2 memory\n"); 3453 error = ENXIO; 3454 goto fail; 3455 } 3456 3457 /* Enable APE register/memory access by host driver. */ 3458 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3459 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3460 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3461 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3462 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3463 3464 bge_ape_lock_init(sc); 3465 bge_ape_read_fw_ver(sc); 3466 } 3467 3468 /* Add SYSCTLs, requires the chipset family to be set. */ 3469 bge_add_sysctls(sc); 3470 3471 /* Identify the chips that use an CPMU. */ 3472 if (BGE_IS_5717_PLUS(sc) || 3473 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3474 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3475 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3476 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3477 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3478 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3479 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3480 else 3481 sc->bge_mi_mode = BGE_MIMODE_BASE; 3482 /* Enable auto polling for BCM570[0-5]. */ 3483 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3484 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3485 3486 /* 3487 * All Broadcom controllers have 4GB boundary DMA bug. 3488 * Whenever an address crosses a multiple of the 4GB boundary 3489 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3490 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3491 * state machine will lockup and cause the device to hang. 3492 */ 3493 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3494 3495 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3496 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3497 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3498 3499 /* 3500 * BCM5719 cannot handle DMA requests for DMA segments that 3501 * have larger than 4KB in size. However the maximum DMA 3502 * segment size created in DMA tag is 4KB for TSO, so we 3503 * wouldn't encounter the issue here. 3504 */ 3505 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3506 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3507 3508 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3509 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3510 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3511 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3512 sc->bge_flags |= BGE_FLAG_5788; 3513 } 3514 3515 capmask = BMSR_DEFCAPMASK; 3516 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3517 (misccfg == 0x4000 || misccfg == 0x8000)) || 3518 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3519 pci_get_vendor(dev) == BCOM_VENDORID && 3520 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3521 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3522 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3523 (pci_get_vendor(dev) == BCOM_VENDORID && 3524 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3525 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3526 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3527 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3528 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3529 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3530 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3531 /* These chips are 10/100 only. */ 3532 capmask &= ~BMSR_EXTSTAT; 3533 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3534 } 3535 3536 /* 3537 * Some controllers seem to require a special firmware to use 3538 * TSO. But the firmware is not available to FreeBSD and Linux 3539 * claims that the TSO performed by the firmware is slower than 3540 * hardware based TSO. Moreover the firmware based TSO has one 3541 * known bug which can't handle TSO if Ethernet header + IP/TCP 3542 * header is greater than 80 bytes. A workaround for the TSO 3543 * bug exist but it seems it's too expensive than not using 3544 * TSO at all. Some hardwares also have the TSO bug so limit 3545 * the TSO to the controllers that are not affected TSO issues 3546 * (e.g. 5755 or higher). 3547 */ 3548 if (BGE_IS_5717_PLUS(sc)) { 3549 /* BCM5717 requires different TSO configuration. */ 3550 sc->bge_flags |= BGE_FLAG_TSO3; 3551 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3552 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3553 /* TSO on BCM5719 A0 does not work. */ 3554 sc->bge_flags &= ~BGE_FLAG_TSO3; 3555 } 3556 } else if (BGE_IS_5755_PLUS(sc)) { 3557 /* 3558 * BCM5754 and BCM5787 shares the same ASIC id so 3559 * explicit device id check is required. 3560 * Due to unknown reason TSO does not work on BCM5755M. 3561 */ 3562 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3563 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3564 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3565 sc->bge_flags |= BGE_FLAG_TSO; 3566 } 3567 3568 /* 3569 * Check if this is a PCI-X or PCI Express device. 3570 */ 3571 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3572 /* 3573 * Found a PCI Express capabilities register, this 3574 * must be a PCI Express device. 3575 */ 3576 sc->bge_flags |= BGE_FLAG_PCIE; 3577 sc->bge_expcap = reg; 3578 /* Extract supported maximum payload size. */ 3579 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3580 PCIER_DEVICE_CAP, 2); 3581 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3582 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3583 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3584 sc->bge_expmrq = 2048; 3585 else 3586 sc->bge_expmrq = 4096; 3587 pci_set_max_read_req(dev, sc->bge_expmrq); 3588 } else { 3589 /* 3590 * Check if the device is in PCI-X Mode. 3591 * (This bit is not valid on PCI Express controllers.) 3592 */ 3593 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3594 sc->bge_pcixcap = reg; 3595 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3596 BGE_PCISTATE_PCI_BUSMODE) == 0) 3597 sc->bge_flags |= BGE_FLAG_PCIX; 3598 } 3599 3600 /* 3601 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3602 * not actually a MAC controller bug but an issue with the embedded 3603 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3604 */ 3605 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3606 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3607 /* 3608 * Some PCI-X bridges are known to trigger write reordering to 3609 * the mailbox registers. Typical phenomena is watchdog timeouts 3610 * caused by out-of-order TX completions. Enable workaround for 3611 * PCI-X devices that live behind these bridges. 3612 * Note, PCI-X controllers can run in PCI mode so we can't use 3613 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3614 */ 3615 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3616 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3617 /* 3618 * Allocate the interrupt, using MSI if possible. These devices 3619 * support 8 MSI messages, but only the first one is used in 3620 * normal operation. 3621 */ 3622 rid = 0; 3623 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3624 sc->bge_msicap = reg; 3625 reg = 1; 3626 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3627 rid = 1; 3628 sc->bge_flags |= BGE_FLAG_MSI; 3629 } 3630 } 3631 3632 /* 3633 * All controllers except BCM5700 supports tagged status but 3634 * we use tagged status only for MSI case on BCM5717. Otherwise 3635 * MSI on BCM5717 does not work. 3636 */ 3637#ifndef DEVICE_POLLING 3638 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3639 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3640#endif 3641 3642 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3643 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3644 3645 if (sc->bge_irq == NULL) { 3646 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3647 error = ENXIO; 3648 goto fail; 3649 } 3650 3651 bge_devinfo(sc); 3652 3653 sc->bge_asf_mode = 0; 3654 /* No ASF if APE present. */ 3655 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3656 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3657 BGE_SRAM_DATA_SIG_MAGIC)) { 3658 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3659 BGE_HWCFG_ASF) { 3660 sc->bge_asf_mode |= ASF_ENABLE; 3661 sc->bge_asf_mode |= ASF_STACKUP; 3662 if (BGE_IS_575X_PLUS(sc)) 3663 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3664 } 3665 } 3666 } 3667 3668 bge_stop_fw(sc); 3669 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3670 if (bge_reset(sc)) { 3671 device_printf(sc->bge_dev, "chip reset failed\n"); 3672 error = ENXIO; 3673 goto fail; 3674 } 3675 3676 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3677 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3678 3679 if (bge_chipinit(sc)) { 3680 device_printf(sc->bge_dev, "chip initialization failed\n"); 3681 error = ENXIO; 3682 goto fail; 3683 } 3684 3685 error = bge_get_eaddr(sc, eaddr); 3686 if (error) { 3687 device_printf(sc->bge_dev, 3688 "failed to read station address\n"); 3689 error = ENXIO; 3690 goto fail; 3691 } 3692 3693 /* 5705 limits RX return ring to 512 entries. */ 3694 if (BGE_IS_5717_PLUS(sc)) 3695 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3696 else if (BGE_IS_5705_PLUS(sc)) 3697 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3698 else 3699 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3700 3701 if (bge_dma_alloc(sc)) { 3702 device_printf(sc->bge_dev, 3703 "failed to allocate DMA resources\n"); 3704 error = ENXIO; 3705 goto fail; 3706 } 3707 3708 /* Set default tuneable values. */ 3709 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3710 sc->bge_rx_coal_ticks = 150; 3711 sc->bge_tx_coal_ticks = 150; 3712 sc->bge_rx_max_coal_bds = 10; 3713 sc->bge_tx_max_coal_bds = 10; 3714 3715 /* Initialize checksum features to use. */ 3716 sc->bge_csum_features = BGE_CSUM_FEATURES; 3717 if (sc->bge_forced_udpcsum != 0) 3718 sc->bge_csum_features |= CSUM_UDP; 3719 3720 /* Set up ifnet structure */ 3721 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3722 if (ifp == NULL) { 3723 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3724 error = ENXIO; 3725 goto fail; 3726 } 3727 ifp->if_softc = sc; 3728 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3730 ifp->if_ioctl = bge_ioctl; 3731 ifp->if_start = bge_start; 3732 ifp->if_init = bge_init; 3733 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3734 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3735 IFQ_SET_READY(&ifp->if_snd); 3736 ifp->if_hwassist = sc->bge_csum_features; 3737 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3738 IFCAP_VLAN_MTU; 3739 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3740 ifp->if_hwassist |= CSUM_TSO; 3741 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3742 } 3743#ifdef IFCAP_VLAN_HWCSUM 3744 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3745#endif 3746 ifp->if_capenable = ifp->if_capabilities; 3747#ifdef DEVICE_POLLING 3748 ifp->if_capabilities |= IFCAP_POLLING; 3749#endif 3750 3751 /* 3752 * 5700 B0 chips do not support checksumming correctly due 3753 * to hardware bugs. 3754 */ 3755 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3756 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3757 ifp->if_capenable &= ~IFCAP_HWCSUM; 3758 ifp->if_hwassist = 0; 3759 } 3760 3761 /* 3762 * Figure out what sort of media we have by checking the 3763 * hardware config word in the first 32k of NIC internal memory, 3764 * or fall back to examining the EEPROM if necessary. 3765 * Note: on some BCM5700 cards, this value appears to be unset. 3766 * If that's the case, we have to rely on identifying the NIC 3767 * by its PCI subsystem ID, as we do below for the SysKonnect 3768 * SK-9D41. 3769 */ 3770 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3771 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3772 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3773 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3774 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3775 sizeof(hwcfg))) { 3776 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3777 error = ENXIO; 3778 goto fail; 3779 } 3780 hwcfg = ntohl(hwcfg); 3781 } 3782 3783 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3784 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3785 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3786 if (BGE_IS_5705_PLUS(sc)) { 3787 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3788 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3789 } else 3790 sc->bge_flags |= BGE_FLAG_TBI; 3791 } 3792 3793 /* Set various PHY bug flags. */ 3794 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3795 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3796 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3797 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3798 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3799 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3800 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3801 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3802 if (pci_get_subvendor(dev) == DELL_VENDORID) 3803 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3804 if ((BGE_IS_5705_PLUS(sc)) && 3805 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3806 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3807 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3808 !BGE_IS_5717_PLUS(sc)) { 3809 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3810 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3811 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3812 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3813 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3814 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3815 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3816 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3817 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3818 } else 3819 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3820 } 3821 3822 /* 3823 * Don't enable Ethernet@WireSpeed for the 5700 or the 3824 * 5705 A0 and A1 chips. 3825 */ 3826 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3827 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3828 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3829 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3830 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3831 3832 if (sc->bge_flags & BGE_FLAG_TBI) { 3833 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3834 bge_ifmedia_sts); 3835 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3836 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3837 0, NULL); 3838 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3839 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3840 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3841 } else { 3842 /* 3843 * Do transceiver setup and tell the firmware the 3844 * driver is down so we can try to get access the 3845 * probe if ASF is running. Retry a couple of times 3846 * if we get a conflict with the ASF firmware accessing 3847 * the PHY. 3848 */ 3849 trys = 0; 3850 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3851again: 3852 bge_asf_driver_up(sc); 3853 3854 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3855 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3856 MIIF_DOPAUSE); 3857 if (error != 0) { 3858 if (trys++ < 4) { 3859 device_printf(sc->bge_dev, "Try again\n"); 3860 bge_miibus_writereg(sc->bge_dev, 3861 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3862 goto again; 3863 } 3864 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3865 goto fail; 3866 } 3867 3868 /* 3869 * Now tell the firmware we are going up after probing the PHY 3870 */ 3871 if (sc->bge_asf_mode & ASF_STACKUP) 3872 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3873 } 3874 3875 /* 3876 * When using the BCM5701 in PCI-X mode, data corruption has 3877 * been observed in the first few bytes of some received packets. 3878 * Aligning the packet buffer in memory eliminates the corruption. 3879 * Unfortunately, this misaligns the packet payloads. On platforms 3880 * which do not support unaligned accesses, we will realign the 3881 * payloads by copying the received packets. 3882 */ 3883 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3884 sc->bge_flags & BGE_FLAG_PCIX) 3885 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3886 3887 /* 3888 * Call MI attach routine. 3889 */ 3890 ether_ifattach(ifp, eaddr); 3891 3892 /* Tell upper layer we support long frames. */ 3893 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3894 3895 /* 3896 * Hookup IRQ last. 3897 */ 3898 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3899 /* Take advantage of single-shot MSI. */ 3900 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3901 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3902 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3903 taskqueue_thread_enqueue, &sc->bge_tq); 3904 if (sc->bge_tq == NULL) { 3905 device_printf(dev, "could not create taskqueue.\n"); 3906 ether_ifdetach(ifp); 3907 error = ENOMEM; 3908 goto fail; 3909 } 3910 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3911 "%s taskq", device_get_nameunit(sc->bge_dev)); 3912 if (error != 0) { 3913 device_printf(dev, "could not start threads.\n"); 3914 ether_ifdetach(ifp); 3915 goto fail; 3916 } 3917 error = bus_setup_intr(dev, sc->bge_irq, 3918 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3919 &sc->bge_intrhand); 3920 } else 3921 error = bus_setup_intr(dev, sc->bge_irq, 3922 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3923 &sc->bge_intrhand); 3924 3925 if (error) { 3926 ether_ifdetach(ifp); 3927 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3928 } 3929 3930fail: 3931 if (error) 3932 bge_detach(dev); 3933 return (error); 3934} 3935 3936static int 3937bge_detach(device_t dev) 3938{ 3939 struct bge_softc *sc; 3940 struct ifnet *ifp; 3941 3942 sc = device_get_softc(dev); 3943 ifp = sc->bge_ifp; 3944 3945#ifdef DEVICE_POLLING 3946 if (ifp->if_capenable & IFCAP_POLLING) 3947 ether_poll_deregister(ifp); 3948#endif 3949 3950 if (device_is_attached(dev)) { 3951 ether_ifdetach(ifp); 3952 BGE_LOCK(sc); 3953 bge_stop(sc); 3954 BGE_UNLOCK(sc); 3955 callout_drain(&sc->bge_stat_ch); 3956 } 3957 3958 if (sc->bge_tq) 3959 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3960 3961 if (sc->bge_flags & BGE_FLAG_TBI) 3962 ifmedia_removeall(&sc->bge_ifmedia); 3963 else if (sc->bge_miibus != NULL) { 3964 bus_generic_detach(dev); 3965 device_delete_child(dev, sc->bge_miibus); 3966 } 3967 3968 bge_release_resources(sc); 3969 3970 return (0); 3971} 3972 3973static void 3974bge_release_resources(struct bge_softc *sc) 3975{ 3976 device_t dev; 3977 3978 dev = sc->bge_dev; 3979 3980 if (sc->bge_tq != NULL) 3981 taskqueue_free(sc->bge_tq); 3982 3983 if (sc->bge_intrhand != NULL) 3984 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3985 3986 if (sc->bge_irq != NULL) { 3987 bus_release_resource(dev, SYS_RES_IRQ, 3988 rman_get_rid(sc->bge_irq), sc->bge_irq); 3989 pci_release_msi(dev); 3990 } 3991 3992 if (sc->bge_res != NULL) 3993 bus_release_resource(dev, SYS_RES_MEMORY, 3994 rman_get_rid(sc->bge_res), sc->bge_res); 3995 3996 if (sc->bge_res2 != NULL) 3997 bus_release_resource(dev, SYS_RES_MEMORY, 3998 rman_get_rid(sc->bge_res2), sc->bge_res2); 3999 4000 if (sc->bge_ifp != NULL) 4001 if_free(sc->bge_ifp); 4002 4003 bge_dma_free(sc); 4004 4005 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4006 BGE_LOCK_DESTROY(sc); 4007} 4008 4009static int 4010bge_reset(struct bge_softc *sc) 4011{ 4012 device_t dev; 4013 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4014 void (*write_op)(struct bge_softc *, int, int); 4015 uint16_t devctl; 4016 int i; 4017 4018 dev = sc->bge_dev; 4019 4020 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4021 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4022 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4023 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4024 4025 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4026 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4027 if (sc->bge_flags & BGE_FLAG_PCIE) 4028 write_op = bge_writemem_direct; 4029 else 4030 write_op = bge_writemem_ind; 4031 } else 4032 write_op = bge_writereg_ind; 4033 4034 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4035 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4036 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4037 for (i = 0; i < 8000; i++) { 4038 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4039 BGE_NVRAMSWARB_GNT1) 4040 break; 4041 DELAY(20); 4042 } 4043 if (i == 8000) { 4044 if (bootverbose) 4045 device_printf(dev, "NVRAM lock timedout!\n"); 4046 } 4047 } 4048 /* Take APE lock when performing reset. */ 4049 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4050 4051 /* Save some important PCI state. */ 4052 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4053 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4054 4055 pci_write_config(dev, BGE_PCI_MISC_CTL, 4056 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4057 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4058 4059 /* Disable fastboot on controllers that support it. */ 4060 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4061 BGE_IS_5755_PLUS(sc)) { 4062 if (bootverbose) 4063 device_printf(dev, "Disabling fastboot\n"); 4064 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4065 } 4066 4067 /* 4068 * Write the magic number to SRAM at offset 0xB50. 4069 * When firmware finishes its initialization it will 4070 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4071 */ 4072 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4073 4074 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4075 4076 /* XXX: Broadcom Linux driver. */ 4077 if (sc->bge_flags & BGE_FLAG_PCIE) { 4078 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4079 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4080 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4081 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4082 } 4083 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4084 /* Prevent PCIE link training during global reset */ 4085 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4086 reset |= 1 << 29; 4087 } 4088 } 4089 4090 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4091 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4092 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4093 val | BGE_VCPU_STATUS_DRV_RESET); 4094 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4095 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4096 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4097 } 4098 4099 /* 4100 * Set GPHY Power Down Override to leave GPHY 4101 * powered up in D0 uninitialized. 4102 */ 4103 if (BGE_IS_5705_PLUS(sc) && 4104 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4105 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4106 4107 /* Issue global reset */ 4108 write_op(sc, BGE_MISC_CFG, reset); 4109 4110 if (sc->bge_flags & BGE_FLAG_PCIE) 4111 DELAY(100 * 1000); 4112 else 4113 DELAY(1000); 4114 4115 /* XXX: Broadcom Linux driver. */ 4116 if (sc->bge_flags & BGE_FLAG_PCIE) { 4117 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4118 DELAY(500000); /* wait for link training to complete */ 4119 val = pci_read_config(dev, 0xC4, 4); 4120 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4121 } 4122 devctl = pci_read_config(dev, 4123 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4124 /* Clear enable no snoop and disable relaxed ordering. */ 4125 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4126 PCIEM_CTL_NOSNOOP_ENABLE); 4127 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4128 devctl, 2); 4129 pci_set_max_read_req(dev, sc->bge_expmrq); 4130 /* Clear error status. */ 4131 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4132 PCIEM_STA_CORRECTABLE_ERROR | 4133 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4134 PCIEM_STA_UNSUPPORTED_REQ, 2); 4135 } 4136 4137 /* Reset some of the PCI state that got zapped by reset. */ 4138 pci_write_config(dev, BGE_PCI_MISC_CTL, 4139 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4140 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4141 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4142 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4143 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4144 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4145 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4146 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4147 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4148 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4149 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4150 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4151 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4152 /* 4153 * Disable PCI-X relaxed ordering to ensure status block update 4154 * comes first then packet buffer DMA. Otherwise driver may 4155 * read stale status block. 4156 */ 4157 if (sc->bge_flags & BGE_FLAG_PCIX) { 4158 devctl = pci_read_config(dev, 4159 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4160 devctl &= ~PCIXM_COMMAND_ERO; 4161 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4162 devctl &= ~PCIXM_COMMAND_MAX_READ; 4163 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4164 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4165 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4166 PCIXM_COMMAND_MAX_READ); 4167 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4168 } 4169 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4170 devctl, 2); 4171 } 4172 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4173 if (BGE_IS_5714_FAMILY(sc)) { 4174 /* This chip disables MSI on reset. */ 4175 if (sc->bge_flags & BGE_FLAG_MSI) { 4176 val = pci_read_config(dev, 4177 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4178 pci_write_config(dev, 4179 sc->bge_msicap + PCIR_MSI_CTRL, 4180 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4181 val = CSR_READ_4(sc, BGE_MSI_MODE); 4182 CSR_WRITE_4(sc, BGE_MSI_MODE, 4183 val | BGE_MSIMODE_ENABLE); 4184 } 4185 val = CSR_READ_4(sc, BGE_MARB_MODE); 4186 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4187 } else 4188 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4189 4190 /* Fix up byte swapping. */ 4191 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4192 4193 val = CSR_READ_4(sc, BGE_MAC_MODE); 4194 val = (val & ~mac_mode_mask) | mac_mode; 4195 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4196 DELAY(40); 4197 4198 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4199 4200 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4201 for (i = 0; i < BGE_TIMEOUT; i++) { 4202 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4203 if (val & BGE_VCPU_STATUS_INIT_DONE) 4204 break; 4205 DELAY(100); 4206 } 4207 if (i == BGE_TIMEOUT) { 4208 device_printf(dev, "reset timed out\n"); 4209 return (1); 4210 } 4211 } else { 4212 /* 4213 * Poll until we see the 1's complement of the magic number. 4214 * This indicates that the firmware initialization is complete. 4215 * We expect this to fail if no chip containing the Ethernet 4216 * address is fitted though. 4217 */ 4218 for (i = 0; i < BGE_TIMEOUT; i++) { 4219 DELAY(10); 4220 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4221 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4222 break; 4223 } 4224 4225 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4226 device_printf(dev, 4227 "firmware handshake timed out, found 0x%08x\n", 4228 val); 4229 /* BCM57765 A0 needs additional time before accessing. */ 4230 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4231 DELAY(10 * 1000); /* XXX */ 4232 } 4233 4234 /* 4235 * The 5704 in TBI mode apparently needs some special 4236 * adjustment to insure the SERDES drive level is set 4237 * to 1.2V. 4238 */ 4239 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4240 sc->bge_flags & BGE_FLAG_TBI) { 4241 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4242 val = (val & ~0xFFF) | 0x880; 4243 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4244 } 4245 4246 /* XXX: Broadcom Linux driver. */ 4247 if (sc->bge_flags & BGE_FLAG_PCIE && 4248 !BGE_IS_5717_PLUS(sc) && 4249 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4250 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4251 /* Enable Data FIFO protection. */ 4252 val = CSR_READ_4(sc, 0x7C00); 4253 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4254 } 4255 4256 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4257 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4258 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4259 4260 return (0); 4261} 4262 4263static __inline void 4264bge_rxreuse_std(struct bge_softc *sc, int i) 4265{ 4266 struct bge_rx_bd *r; 4267 4268 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4269 r->bge_flags = BGE_RXBDFLAG_END; 4270 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4271 r->bge_idx = i; 4272 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4273} 4274 4275static __inline void 4276bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4277{ 4278 struct bge_extrx_bd *r; 4279 4280 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4281 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4282 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4283 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4284 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4285 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4286 r->bge_idx = i; 4287 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4288} 4289 4290/* 4291 * Frame reception handling. This is called if there's a frame 4292 * on the receive return list. 4293 * 4294 * Note: we have to be able to handle two possibilities here: 4295 * 1) the frame is from the jumbo receive ring 4296 * 2) the frame is from the standard receive ring 4297 */ 4298 4299static int 4300bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4301{ 4302 struct ifnet *ifp; 4303 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4304 uint16_t rx_cons; 4305 4306 rx_cons = sc->bge_rx_saved_considx; 4307 4308 /* Nothing to do. */ 4309 if (rx_cons == rx_prod) 4310 return (rx_npkts); 4311 4312 ifp = sc->bge_ifp; 4313 4314 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4315 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4316 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4317 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4318 if (BGE_IS_JUMBO_CAPABLE(sc) && 4319 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4320 (MCLBYTES - ETHER_ALIGN)) 4321 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4322 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4323 4324 while (rx_cons != rx_prod) { 4325 struct bge_rx_bd *cur_rx; 4326 uint32_t rxidx; 4327 struct mbuf *m = NULL; 4328 uint16_t vlan_tag = 0; 4329 int have_tag = 0; 4330 4331#ifdef DEVICE_POLLING 4332 if (ifp->if_capenable & IFCAP_POLLING) { 4333 if (sc->rxcycles <= 0) 4334 break; 4335 sc->rxcycles--; 4336 } 4337#endif 4338 4339 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4340 4341 rxidx = cur_rx->bge_idx; 4342 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4343 4344 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4345 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4346 have_tag = 1; 4347 vlan_tag = cur_rx->bge_vlan_tag; 4348 } 4349 4350 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4351 jumbocnt++; 4352 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4353 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4354 bge_rxreuse_jumbo(sc, rxidx); 4355 continue; 4356 } 4357 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4358 bge_rxreuse_jumbo(sc, rxidx); 4359 ifp->if_iqdrops++; 4360 continue; 4361 } 4362 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4363 } else { 4364 stdcnt++; 4365 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4366 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4367 bge_rxreuse_std(sc, rxidx); 4368 continue; 4369 } 4370 if (bge_newbuf_std(sc, rxidx) != 0) { 4371 bge_rxreuse_std(sc, rxidx); 4372 ifp->if_iqdrops++; 4373 continue; 4374 } 4375 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4376 } 4377 4378 ifp->if_ipackets++; 4379#ifndef __NO_STRICT_ALIGNMENT 4380 /* 4381 * For architectures with strict alignment we must make sure 4382 * the payload is aligned. 4383 */ 4384 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4385 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4386 cur_rx->bge_len); 4387 m->m_data += ETHER_ALIGN; 4388 } 4389#endif 4390 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4391 m->m_pkthdr.rcvif = ifp; 4392 4393 if (ifp->if_capenable & IFCAP_RXCSUM) 4394 bge_rxcsum(sc, cur_rx, m); 4395 4396 /* 4397 * If we received a packet with a vlan tag, 4398 * attach that information to the packet. 4399 */ 4400 if (have_tag) { 4401 m->m_pkthdr.ether_vtag = vlan_tag; 4402 m->m_flags |= M_VLANTAG; 4403 } 4404 4405 if (holdlck != 0) { 4406 BGE_UNLOCK(sc); 4407 (*ifp->if_input)(ifp, m); 4408 BGE_LOCK(sc); 4409 } else 4410 (*ifp->if_input)(ifp, m); 4411 rx_npkts++; 4412 4413 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4414 return (rx_npkts); 4415 } 4416 4417 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4418 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4419 if (stdcnt > 0) 4420 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4421 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4422 4423 if (jumbocnt > 0) 4424 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4425 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4426 4427 sc->bge_rx_saved_considx = rx_cons; 4428 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4429 if (stdcnt) 4430 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4431 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4432 if (jumbocnt) 4433 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4434 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4435#ifdef notyet 4436 /* 4437 * This register wraps very quickly under heavy packet drops. 4438 * If you need correct statistics, you can enable this check. 4439 */ 4440 if (BGE_IS_5705_PLUS(sc)) 4441 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4442#endif 4443 return (rx_npkts); 4444} 4445 4446static void 4447bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4448{ 4449 4450 if (BGE_IS_5717_PLUS(sc)) { 4451 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4452 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4453 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4454 if ((cur_rx->bge_error_flag & 4455 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4456 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4457 } 4458 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4459 m->m_pkthdr.csum_data = 4460 cur_rx->bge_tcp_udp_csum; 4461 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4462 CSUM_PSEUDO_HDR; 4463 } 4464 } 4465 } else { 4466 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4467 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4468 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4469 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4470 } 4471 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4472 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4473 m->m_pkthdr.csum_data = 4474 cur_rx->bge_tcp_udp_csum; 4475 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4476 CSUM_PSEUDO_HDR; 4477 } 4478 } 4479} 4480 4481static void 4482bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4483{ 4484 struct bge_tx_bd *cur_tx; 4485 struct ifnet *ifp; 4486 4487 BGE_LOCK_ASSERT(sc); 4488 4489 /* Nothing to do. */ 4490 if (sc->bge_tx_saved_considx == tx_cons) 4491 return; 4492 4493 ifp = sc->bge_ifp; 4494 4495 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4496 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4497 /* 4498 * Go through our tx ring and free mbufs for those 4499 * frames that have been sent. 4500 */ 4501 while (sc->bge_tx_saved_considx != tx_cons) { 4502 uint32_t idx; 4503 4504 idx = sc->bge_tx_saved_considx; 4505 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4506 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4507 ifp->if_opackets++; 4508 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4509 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4510 sc->bge_cdata.bge_tx_dmamap[idx], 4511 BUS_DMASYNC_POSTWRITE); 4512 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4513 sc->bge_cdata.bge_tx_dmamap[idx]); 4514 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4515 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4516 } 4517 sc->bge_txcnt--; 4518 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4519 } 4520 4521 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4522 if (sc->bge_txcnt == 0) 4523 sc->bge_timer = 0; 4524} 4525 4526#ifdef DEVICE_POLLING 4527static int 4528bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4529{ 4530 struct bge_softc *sc = ifp->if_softc; 4531 uint16_t rx_prod, tx_cons; 4532 uint32_t statusword; 4533 int rx_npkts = 0; 4534 4535 BGE_LOCK(sc); 4536 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4537 BGE_UNLOCK(sc); 4538 return (rx_npkts); 4539 } 4540 4541 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4542 sc->bge_cdata.bge_status_map, 4543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4544 /* Fetch updates from the status block. */ 4545 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4546 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4547 4548 statusword = sc->bge_ldata.bge_status_block->bge_status; 4549 /* Clear the status so the next pass only sees the changes. */ 4550 sc->bge_ldata.bge_status_block->bge_status = 0; 4551 4552 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4553 sc->bge_cdata.bge_status_map, 4554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4555 4556 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4557 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4558 sc->bge_link_evt++; 4559 4560 if (cmd == POLL_AND_CHECK_STATUS) 4561 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4562 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4563 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4564 bge_link_upd(sc); 4565 4566 sc->rxcycles = count; 4567 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4568 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4569 BGE_UNLOCK(sc); 4570 return (rx_npkts); 4571 } 4572 bge_txeof(sc, tx_cons); 4573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4574 bge_start_locked(ifp); 4575 4576 BGE_UNLOCK(sc); 4577 return (rx_npkts); 4578} 4579#endif /* DEVICE_POLLING */ 4580 4581static int 4582bge_msi_intr(void *arg) 4583{ 4584 struct bge_softc *sc; 4585 4586 sc = (struct bge_softc *)arg; 4587 /* 4588 * This interrupt is not shared and controller already 4589 * disabled further interrupt. 4590 */ 4591 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4592 return (FILTER_HANDLED); 4593} 4594 4595static void 4596bge_intr_task(void *arg, int pending) 4597{ 4598 struct bge_softc *sc; 4599 struct ifnet *ifp; 4600 uint32_t status, status_tag; 4601 uint16_t rx_prod, tx_cons; 4602 4603 sc = (struct bge_softc *)arg; 4604 ifp = sc->bge_ifp; 4605 4606 BGE_LOCK(sc); 4607 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4608 BGE_UNLOCK(sc); 4609 return; 4610 } 4611 4612 /* Get updated status block. */ 4613 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4614 sc->bge_cdata.bge_status_map, 4615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4616 4617 /* Save producer/consumer indices. */ 4618 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4619 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4620 status = sc->bge_ldata.bge_status_block->bge_status; 4621 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4622 /* Dirty the status flag. */ 4623 sc->bge_ldata.bge_status_block->bge_status = 0; 4624 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4625 sc->bge_cdata.bge_status_map, 4626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4627 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4628 status_tag = 0; 4629 4630 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4631 bge_link_upd(sc); 4632 4633 /* Let controller work. */ 4634 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4635 4636 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4637 sc->bge_rx_saved_considx != rx_prod) { 4638 /* Check RX return ring producer/consumer. */ 4639 BGE_UNLOCK(sc); 4640 bge_rxeof(sc, rx_prod, 0); 4641 BGE_LOCK(sc); 4642 } 4643 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4644 /* Check TX ring producer/consumer. */ 4645 bge_txeof(sc, tx_cons); 4646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4647 bge_start_locked(ifp); 4648 } 4649 BGE_UNLOCK(sc); 4650} 4651 4652static void 4653bge_intr(void *xsc) 4654{ 4655 struct bge_softc *sc; 4656 struct ifnet *ifp; 4657 uint32_t statusword; 4658 uint16_t rx_prod, tx_cons; 4659 4660 sc = xsc; 4661 4662 BGE_LOCK(sc); 4663 4664 ifp = sc->bge_ifp; 4665 4666#ifdef DEVICE_POLLING 4667 if (ifp->if_capenable & IFCAP_POLLING) { 4668 BGE_UNLOCK(sc); 4669 return; 4670 } 4671#endif 4672 4673 /* 4674 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4675 * disable interrupts by writing nonzero like we used to, since with 4676 * our current organization this just gives complications and 4677 * pessimizations for re-enabling interrupts. We used to have races 4678 * instead of the necessary complications. Disabling interrupts 4679 * would just reduce the chance of a status update while we are 4680 * running (by switching to the interrupt-mode coalescence 4681 * parameters), but this chance is already very low so it is more 4682 * efficient to get another interrupt than prevent it. 4683 * 4684 * We do the ack first to ensure another interrupt if there is a 4685 * status update after the ack. We don't check for the status 4686 * changing later because it is more efficient to get another 4687 * interrupt than prevent it, not quite as above (not checking is 4688 * a smaller optimization than not toggling the interrupt enable, 4689 * since checking doesn't involve PCI accesses and toggling require 4690 * the status check). So toggling would probably be a pessimization 4691 * even with MSI. It would only be needed for using a task queue. 4692 */ 4693 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4694 4695 /* 4696 * Do the mandatory PCI flush as well as get the link status. 4697 */ 4698 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4699 4700 /* Make sure the descriptor ring indexes are coherent. */ 4701 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4702 sc->bge_cdata.bge_status_map, 4703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4704 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4705 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4706 sc->bge_ldata.bge_status_block->bge_status = 0; 4707 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4708 sc->bge_cdata.bge_status_map, 4709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4710 4711 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4712 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4713 statusword || sc->bge_link_evt) 4714 bge_link_upd(sc); 4715 4716 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4717 /* Check RX return ring producer/consumer. */ 4718 bge_rxeof(sc, rx_prod, 1); 4719 } 4720 4721 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4722 /* Check TX ring producer/consumer. */ 4723 bge_txeof(sc, tx_cons); 4724 } 4725 4726 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4727 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4728 bge_start_locked(ifp); 4729 4730 BGE_UNLOCK(sc); 4731} 4732 4733static void 4734bge_asf_driver_up(struct bge_softc *sc) 4735{ 4736 if (sc->bge_asf_mode & ASF_STACKUP) { 4737 /* Send ASF heartbeat aprox. every 2s */ 4738 if (sc->bge_asf_count) 4739 sc->bge_asf_count --; 4740 else { 4741 sc->bge_asf_count = 2; 4742 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4743 BGE_FW_CMD_DRV_ALIVE); 4744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4746 BGE_FW_HB_TIMEOUT_SEC); 4747 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4748 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4749 BGE_RX_CPU_DRV_EVENT); 4750 } 4751 } 4752} 4753 4754static void 4755bge_tick(void *xsc) 4756{ 4757 struct bge_softc *sc = xsc; 4758 struct mii_data *mii = NULL; 4759 4760 BGE_LOCK_ASSERT(sc); 4761 4762 /* Synchronize with possible callout reset/stop. */ 4763 if (callout_pending(&sc->bge_stat_ch) || 4764 !callout_active(&sc->bge_stat_ch)) 4765 return; 4766 4767 if (BGE_IS_5705_PLUS(sc)) 4768 bge_stats_update_regs(sc); 4769 else 4770 bge_stats_update(sc); 4771 4772 /* XXX Add APE heartbeat check here? */ 4773 4774 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4775 mii = device_get_softc(sc->bge_miibus); 4776 /* 4777 * Do not touch PHY if we have link up. This could break 4778 * IPMI/ASF mode or produce extra input errors 4779 * (extra errors was reported for bcm5701 & bcm5704). 4780 */ 4781 if (!sc->bge_link) 4782 mii_tick(mii); 4783 } else { 4784 /* 4785 * Since in TBI mode auto-polling can't be used we should poll 4786 * link status manually. Here we register pending link event 4787 * and trigger interrupt. 4788 */ 4789#ifdef DEVICE_POLLING 4790 /* In polling mode we poll link state in bge_poll(). */ 4791 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4792#endif 4793 { 4794 sc->bge_link_evt++; 4795 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4796 sc->bge_flags & BGE_FLAG_5788) 4797 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4798 else 4799 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4800 } 4801 } 4802 4803 bge_asf_driver_up(sc); 4804 bge_watchdog(sc); 4805 4806 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4807} 4808 4809static void 4810bge_stats_update_regs(struct bge_softc *sc) 4811{ 4812 struct ifnet *ifp; 4813 struct bge_mac_stats *stats; 4814 uint32_t val; 4815 4816 ifp = sc->bge_ifp; 4817 stats = &sc->bge_mac_stats; 4818 4819 stats->ifHCOutOctets += 4820 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4821 stats->etherStatsCollisions += 4822 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4823 stats->outXonSent += 4824 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4825 stats->outXoffSent += 4826 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4827 stats->dot3StatsInternalMacTransmitErrors += 4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4829 stats->dot3StatsSingleCollisionFrames += 4830 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4831 stats->dot3StatsMultipleCollisionFrames += 4832 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4833 stats->dot3StatsDeferredTransmissions += 4834 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4835 stats->dot3StatsExcessiveCollisions += 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4837 stats->dot3StatsLateCollisions += 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4839 stats->ifHCOutUcastPkts += 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4841 stats->ifHCOutMulticastPkts += 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4843 stats->ifHCOutBroadcastPkts += 4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4845 4846 stats->ifHCInOctets += 4847 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4848 stats->etherStatsFragments += 4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4850 stats->ifHCInUcastPkts += 4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4852 stats->ifHCInMulticastPkts += 4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4854 stats->ifHCInBroadcastPkts += 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4856 stats->dot3StatsFCSErrors += 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4858 stats->dot3StatsAlignmentErrors += 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4860 stats->xonPauseFramesReceived += 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4862 stats->xoffPauseFramesReceived += 4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4864 stats->macControlFramesReceived += 4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4866 stats->xoffStateEntered += 4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4868 stats->dot3StatsFramesTooLong += 4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4870 stats->etherStatsJabbers += 4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4872 stats->etherStatsUndersizePkts += 4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4874 4875 stats->FramesDroppedDueToFilters += 4876 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4877 stats->DmaWriteQueueFull += 4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4879 stats->DmaWriteHighPriQueueFull += 4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4881 stats->NoMoreRxBDs += 4882 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4883 /* 4884 * XXX 4885 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4886 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4887 * includes number of unwanted multicast frames. This comes 4888 * from silicon bug and known workaround to get rough(not 4889 * exact) counter is to enable interrupt on MBUF low water 4890 * attention. This can be accomplished by setting 4891 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4892 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4893 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4894 * However that change would generate more interrupts and 4895 * there are still possibilities of losing multiple frames 4896 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4897 * Given that the workaround still would not get correct 4898 * counter I don't think it's worth to implement it. So 4899 * ignore reading the counter on controllers that have the 4900 * silicon bug. 4901 */ 4902 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4903 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4904 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4905 stats->InputDiscards += 4906 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4907 stats->InputErrors += 4908 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4909 stats->RecvThresholdHit += 4910 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4911 4912 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4913 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4914 stats->InputErrors); 4915 4916 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4917 /* 4918 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4919 * frames, it's safe to disable workaround for DMA engine's 4920 * miscalculation of TXMBUF space. 4921 */ 4922 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4923 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4924 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4925 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4926 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4927 else 4928 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4929 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4930 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4931 } 4932 } 4933} 4934 4935static void 4936bge_stats_clear_regs(struct bge_softc *sc) 4937{ 4938 4939 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4952 4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4967 4968 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4969 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4970 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4975} 4976 4977static void 4978bge_stats_update(struct bge_softc *sc) 4979{ 4980 struct ifnet *ifp; 4981 bus_size_t stats; 4982 uint32_t cnt; /* current register value */ 4983 4984 ifp = sc->bge_ifp; 4985 4986 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4987 4988#define READ_STAT(sc, stats, stat) \ 4989 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4990 4991 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4992 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4993 sc->bge_tx_collisions = cnt; 4994 4995 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4996 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4997 sc->bge_rx_nobds = cnt; 4998 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4999 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 5000 sc->bge_rx_inerrs = cnt; 5001 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5002 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 5003 sc->bge_rx_discards = cnt; 5004 5005 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5006 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 5007 sc->bge_tx_discards = cnt; 5008 5009#undef READ_STAT 5010} 5011 5012/* 5013 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5014 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5015 * but when such padded frames employ the bge IP/TCP checksum offload, 5016 * the hardware checksum assist gives incorrect results (possibly 5017 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5018 * If we pad such runts with zeros, the onboard checksum comes out correct. 5019 */ 5020static __inline int 5021bge_cksum_pad(struct mbuf *m) 5022{ 5023 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5024 struct mbuf *last; 5025 5026 /* If there's only the packet-header and we can pad there, use it. */ 5027 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5028 M_TRAILINGSPACE(m) >= padlen) { 5029 last = m; 5030 } else { 5031 /* 5032 * Walk packet chain to find last mbuf. We will either 5033 * pad there, or append a new mbuf and pad it. 5034 */ 5035 for (last = m; last->m_next != NULL; last = last->m_next); 5036 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5037 /* Allocate new empty mbuf, pad it. Compact later. */ 5038 struct mbuf *n; 5039 5040 MGET(n, M_NOWAIT, MT_DATA); 5041 if (n == NULL) 5042 return (ENOBUFS); 5043 n->m_len = 0; 5044 last->m_next = n; 5045 last = n; 5046 } 5047 } 5048 5049 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5050 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5051 last->m_len += padlen; 5052 m->m_pkthdr.len += padlen; 5053 5054 return (0); 5055} 5056 5057static struct mbuf * 5058bge_check_short_dma(struct mbuf *m) 5059{ 5060 struct mbuf *n; 5061 int found; 5062 5063 /* 5064 * If device receive two back-to-back send BDs with less than 5065 * or equal to 8 total bytes then the device may hang. The two 5066 * back-to-back send BDs must in the same frame for this failure 5067 * to occur. Scan mbuf chains and see whether two back-to-back 5068 * send BDs are there. If this is the case, allocate new mbuf 5069 * and copy the frame to workaround the silicon bug. 5070 */ 5071 for (n = m, found = 0; n != NULL; n = n->m_next) { 5072 if (n->m_len < 8) { 5073 found++; 5074 if (found > 1) 5075 break; 5076 continue; 5077 } 5078 found = 0; 5079 } 5080 5081 if (found > 1) { 5082 n = m_defrag(m, M_NOWAIT); 5083 if (n == NULL) 5084 m_freem(m); 5085 } else 5086 n = m; 5087 return (n); 5088} 5089 5090static struct mbuf * 5091bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5092 uint16_t *flags) 5093{ 5094 struct ip *ip; 5095 struct tcphdr *tcp; 5096 struct mbuf *n; 5097 uint16_t hlen; 5098 uint32_t poff; 5099 5100 if (M_WRITABLE(m) == 0) { 5101 /* Get a writable copy. */ 5102 n = m_dup(m, M_NOWAIT); 5103 m_freem(m); 5104 if (n == NULL) 5105 return (NULL); 5106 m = n; 5107 } 5108 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5109 if (m == NULL) 5110 return (NULL); 5111 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5112 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5113 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5114 if (m == NULL) 5115 return (NULL); 5116 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5117 m = m_pullup(m, poff + (tcp->th_off << 2)); 5118 if (m == NULL) 5119 return (NULL); 5120 /* 5121 * It seems controller doesn't modify IP length and TCP pseudo 5122 * checksum. These checksum computed by upper stack should be 0. 5123 */ 5124 *mss = m->m_pkthdr.tso_segsz; 5125 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5126 ip->ip_sum = 0; 5127 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5128 /* Clear pseudo checksum computed by TCP stack. */ 5129 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5130 tcp->th_sum = 0; 5131 /* 5132 * Broadcom controllers uses different descriptor format for 5133 * TSO depending on ASIC revision. Due to TSO-capable firmware 5134 * license issue and lower performance of firmware based TSO 5135 * we only support hardware based TSO. 5136 */ 5137 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5138 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5139 if (sc->bge_flags & BGE_FLAG_TSO3) { 5140 /* 5141 * For BCM5717 and newer controllers, hardware based TSO 5142 * uses the 14 lower bits of the bge_mss field to store the 5143 * MSS and the upper 2 bits to store the lowest 2 bits of 5144 * the IP/TCP header length. The upper 6 bits of the header 5145 * length are stored in the bge_flags[14:10,4] field. Jumbo 5146 * frames are supported. 5147 */ 5148 *mss |= ((hlen & 0x3) << 14); 5149 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5150 } else { 5151 /* 5152 * For BCM5755 and newer controllers, hardware based TSO uses 5153 * the lower 11 bits to store the MSS and the upper 5 bits to 5154 * store the IP/TCP header length. Jumbo frames are not 5155 * supported. 5156 */ 5157 *mss |= (hlen << 11); 5158 } 5159 return (m); 5160} 5161 5162/* 5163 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5164 * pointers to descriptors. 5165 */ 5166static int 5167bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5168{ 5169 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5170 bus_dmamap_t map; 5171 struct bge_tx_bd *d; 5172 struct mbuf *m = *m_head; 5173 uint32_t idx = *txidx; 5174 uint16_t csum_flags, mss, vlan_tag; 5175 int nsegs, i, error; 5176 5177 csum_flags = 0; 5178 mss = 0; 5179 vlan_tag = 0; 5180 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5181 m->m_next != NULL) { 5182 *m_head = bge_check_short_dma(m); 5183 if (*m_head == NULL) 5184 return (ENOBUFS); 5185 m = *m_head; 5186 } 5187 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5188 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5189 if (*m_head == NULL) 5190 return (ENOBUFS); 5191 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5192 BGE_TXBDFLAG_CPU_POST_DMA; 5193 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5194 if (m->m_pkthdr.csum_flags & CSUM_IP) 5195 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5196 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5197 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5198 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5199 (error = bge_cksum_pad(m)) != 0) { 5200 m_freem(m); 5201 *m_head = NULL; 5202 return (error); 5203 } 5204 } 5205 } 5206 5207 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5208 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5209 m->m_pkthdr.len > ETHER_MAX_LEN) 5210 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5211 if (sc->bge_forced_collapse > 0 && 5212 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5213 /* 5214 * Forcedly collapse mbuf chains to overcome hardware 5215 * limitation which only support a single outstanding 5216 * DMA read operation. 5217 */ 5218 if (sc->bge_forced_collapse == 1) 5219 m = m_defrag(m, M_NOWAIT); 5220 else 5221 m = m_collapse(m, M_NOWAIT, 5222 sc->bge_forced_collapse); 5223 if (m == NULL) 5224 m = *m_head; 5225 *m_head = m; 5226 } 5227 } 5228 5229 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5230 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5231 &nsegs, BUS_DMA_NOWAIT); 5232 if (error == EFBIG) { 5233 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5234 if (m == NULL) { 5235 m_freem(*m_head); 5236 *m_head = NULL; 5237 return (ENOBUFS); 5238 } 5239 *m_head = m; 5240 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5241 m, segs, &nsegs, BUS_DMA_NOWAIT); 5242 if (error) { 5243 m_freem(m); 5244 *m_head = NULL; 5245 return (error); 5246 } 5247 } else if (error != 0) 5248 return (error); 5249 5250 /* Check if we have enough free send BDs. */ 5251 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5252 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5253 return (ENOBUFS); 5254 } 5255 5256 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5257 5258 if (m->m_flags & M_VLANTAG) { 5259 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5260 vlan_tag = m->m_pkthdr.ether_vtag; 5261 } 5262 5263 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5264 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5265 /* 5266 * 5725 family of devices corrupts TSO packets when TSO DMA 5267 * buffers cross into regions which are within MSS bytes of 5268 * a 4GB boundary. If we encounter the condition, drop the 5269 * packet. 5270 */ 5271 for (i = 0; ; i++) { 5272 d = &sc->bge_ldata.bge_tx_ring[idx]; 5273 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5274 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5275 d->bge_len = segs[i].ds_len; 5276 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5277 d->bge_addr.bge_addr_lo) 5278 break; 5279 d->bge_flags = csum_flags; 5280 d->bge_vlan_tag = vlan_tag; 5281 d->bge_mss = mss; 5282 if (i == nsegs - 1) 5283 break; 5284 BGE_INC(idx, BGE_TX_RING_CNT); 5285 } 5286 if (i != nsegs - 1) { 5287 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5288 BUS_DMASYNC_POSTWRITE); 5289 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5290 m_freem(*m_head); 5291 *m_head = NULL; 5292 return (EIO); 5293 } 5294 } else { 5295 for (i = 0; ; i++) { 5296 d = &sc->bge_ldata.bge_tx_ring[idx]; 5297 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5298 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5299 d->bge_len = segs[i].ds_len; 5300 d->bge_flags = csum_flags; 5301 d->bge_vlan_tag = vlan_tag; 5302 d->bge_mss = mss; 5303 if (i == nsegs - 1) 5304 break; 5305 BGE_INC(idx, BGE_TX_RING_CNT); 5306 } 5307 } 5308 5309 /* Mark the last segment as end of packet... */ 5310 d->bge_flags |= BGE_TXBDFLAG_END; 5311 5312 /* 5313 * Insure that the map for this transmission 5314 * is placed at the array index of the last descriptor 5315 * in this chain. 5316 */ 5317 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5318 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5319 sc->bge_cdata.bge_tx_chain[idx] = m; 5320 sc->bge_txcnt += nsegs; 5321 5322 BGE_INC(idx, BGE_TX_RING_CNT); 5323 *txidx = idx; 5324 5325 return (0); 5326} 5327 5328/* 5329 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5330 * to the mbuf data regions directly in the transmit descriptors. 5331 */ 5332static void 5333bge_start_locked(struct ifnet *ifp) 5334{ 5335 struct bge_softc *sc; 5336 struct mbuf *m_head; 5337 uint32_t prodidx; 5338 int count; 5339 5340 sc = ifp->if_softc; 5341 BGE_LOCK_ASSERT(sc); 5342 5343 if (!sc->bge_link || 5344 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5345 IFF_DRV_RUNNING) 5346 return; 5347 5348 prodidx = sc->bge_tx_prodidx; 5349 5350 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5351 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5352 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5353 break; 5354 } 5355 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5356 if (m_head == NULL) 5357 break; 5358 5359 /* 5360 * Pack the data into the transmit ring. If we 5361 * don't have room, set the OACTIVE flag and wait 5362 * for the NIC to drain the ring. 5363 */ 5364 if (bge_encap(sc, &m_head, &prodidx)) { 5365 if (m_head == NULL) 5366 break; 5367 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5368 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5369 break; 5370 } 5371 ++count; 5372 5373 /* 5374 * If there's a BPF listener, bounce a copy of this frame 5375 * to him. 5376 */ 5377#ifdef ETHER_BPF_MTAP 5378 ETHER_BPF_MTAP(ifp, m_head); 5379#else 5380 BPF_MTAP(ifp, m_head); 5381#endif 5382 } 5383 5384 if (count > 0) { 5385 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5386 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5387 /* Transmit. */ 5388 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5389 /* 5700 b2 errata */ 5390 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5391 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5392 5393 sc->bge_tx_prodidx = prodidx; 5394 5395 /* 5396 * Set a timeout in case the chip goes out to lunch. 5397 */ 5398 sc->bge_timer = BGE_TX_TIMEOUT; 5399 } 5400} 5401 5402/* 5403 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5404 * to the mbuf data regions directly in the transmit descriptors. 5405 */ 5406static void 5407bge_start(struct ifnet *ifp) 5408{ 5409 struct bge_softc *sc; 5410 5411 sc = ifp->if_softc; 5412 BGE_LOCK(sc); 5413 bge_start_locked(ifp); 5414 BGE_UNLOCK(sc); 5415} 5416 5417static void 5418bge_init_locked(struct bge_softc *sc) 5419{ 5420 struct ifnet *ifp; 5421 uint16_t *m; 5422 uint32_t mode; 5423 5424 BGE_LOCK_ASSERT(sc); 5425 5426 ifp = sc->bge_ifp; 5427 5428 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5429 return; 5430 5431 /* Cancel pending I/O and flush buffers. */ 5432 bge_stop(sc); 5433 5434 bge_stop_fw(sc); 5435 bge_sig_pre_reset(sc, BGE_RESET_START); 5436 bge_reset(sc); 5437 bge_sig_legacy(sc, BGE_RESET_START); 5438 bge_sig_post_reset(sc, BGE_RESET_START); 5439 5440 bge_chipinit(sc); 5441 5442 /* 5443 * Init the various state machines, ring 5444 * control blocks and firmware. 5445 */ 5446 if (bge_blockinit(sc)) { 5447 device_printf(sc->bge_dev, "initialization failure\n"); 5448 return; 5449 } 5450 5451 ifp = sc->bge_ifp; 5452 5453 /* Specify MTU. */ 5454 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5455 ETHER_HDR_LEN + ETHER_CRC_LEN + 5456 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5457 5458 /* Load our MAC address. */ 5459 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5460 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5461 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5462 5463 /* Program promiscuous mode. */ 5464 bge_setpromisc(sc); 5465 5466 /* Program multicast filter. */ 5467 bge_setmulti(sc); 5468 5469 /* Program VLAN tag stripping. */ 5470 bge_setvlan(sc); 5471 5472 /* Override UDP checksum offloading. */ 5473 if (sc->bge_forced_udpcsum == 0) 5474 sc->bge_csum_features &= ~CSUM_UDP; 5475 else 5476 sc->bge_csum_features |= CSUM_UDP; 5477 if (ifp->if_capabilities & IFCAP_TXCSUM && 5478 ifp->if_capenable & IFCAP_TXCSUM) { 5479 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5480 ifp->if_hwassist |= sc->bge_csum_features; 5481 } 5482 5483 /* Init RX ring. */ 5484 if (bge_init_rx_ring_std(sc) != 0) { 5485 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5486 bge_stop(sc); 5487 return; 5488 } 5489 5490 /* 5491 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5492 * memory to insure that the chip has in fact read the first 5493 * entry of the ring. 5494 */ 5495 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5496 uint32_t v, i; 5497 for (i = 0; i < 10; i++) { 5498 DELAY(20); 5499 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5500 if (v == (MCLBYTES - ETHER_ALIGN)) 5501 break; 5502 } 5503 if (i == 10) 5504 device_printf (sc->bge_dev, 5505 "5705 A0 chip failed to load RX ring\n"); 5506 } 5507 5508 /* Init jumbo RX ring. */ 5509 if (BGE_IS_JUMBO_CAPABLE(sc) && 5510 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5511 (MCLBYTES - ETHER_ALIGN)) { 5512 if (bge_init_rx_ring_jumbo(sc) != 0) { 5513 device_printf(sc->bge_dev, 5514 "no memory for jumbo Rx buffers.\n"); 5515 bge_stop(sc); 5516 return; 5517 } 5518 } 5519 5520 /* Init our RX return ring index. */ 5521 sc->bge_rx_saved_considx = 0; 5522 5523 /* Init our RX/TX stat counters. */ 5524 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5525 5526 /* Init TX ring. */ 5527 bge_init_tx_ring(sc); 5528 5529 /* Enable TX MAC state machine lockup fix. */ 5530 mode = CSR_READ_4(sc, BGE_TX_MODE); 5531 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5532 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5533 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5534 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5535 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5536 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5537 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5538 } 5539 /* Turn on transmitter. */ 5540 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5541 DELAY(100); 5542 5543 /* Turn on receiver. */ 5544 mode = CSR_READ_4(sc, BGE_RX_MODE); 5545 if (BGE_IS_5755_PLUS(sc)) 5546 mode |= BGE_RXMODE_IPV6_ENABLE; 5547 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5548 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5549 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5550 DELAY(10); 5551 5552 /* 5553 * Set the number of good frames to receive after RX MBUF 5554 * Low Watermark has been reached. After the RX MAC receives 5555 * this number of frames, it will drop subsequent incoming 5556 * frames until the MBUF High Watermark is reached. 5557 */ 5558 if (BGE_IS_57765_PLUS(sc)) 5559 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5560 else 5561 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5562 5563 /* Clear MAC statistics. */ 5564 if (BGE_IS_5705_PLUS(sc)) 5565 bge_stats_clear_regs(sc); 5566 5567 /* Tell firmware we're alive. */ 5568 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5569 5570#ifdef DEVICE_POLLING 5571 /* Disable interrupts if we are polling. */ 5572 if (ifp->if_capenable & IFCAP_POLLING) { 5573 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5574 BGE_PCIMISCCTL_MASK_PCI_INTR); 5575 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5576 } else 5577#endif 5578 5579 /* Enable host interrupts. */ 5580 { 5581 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5582 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5583 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5584 } 5585 5586 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5587 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5588 5589 bge_ifmedia_upd_locked(ifp); 5590 5591 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5592} 5593 5594static void 5595bge_init(void *xsc) 5596{ 5597 struct bge_softc *sc = xsc; 5598 5599 BGE_LOCK(sc); 5600 bge_init_locked(sc); 5601 BGE_UNLOCK(sc); 5602} 5603 5604/* 5605 * Set media options. 5606 */ 5607static int 5608bge_ifmedia_upd(struct ifnet *ifp) 5609{ 5610 struct bge_softc *sc = ifp->if_softc; 5611 int res; 5612 5613 BGE_LOCK(sc); 5614 res = bge_ifmedia_upd_locked(ifp); 5615 BGE_UNLOCK(sc); 5616 5617 return (res); 5618} 5619 5620static int 5621bge_ifmedia_upd_locked(struct ifnet *ifp) 5622{ 5623 struct bge_softc *sc = ifp->if_softc; 5624 struct mii_data *mii; 5625 struct mii_softc *miisc; 5626 struct ifmedia *ifm; 5627 5628 BGE_LOCK_ASSERT(sc); 5629 5630 ifm = &sc->bge_ifmedia; 5631 5632 /* If this is a 1000baseX NIC, enable the TBI port. */ 5633 if (sc->bge_flags & BGE_FLAG_TBI) { 5634 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5635 return (EINVAL); 5636 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5637 case IFM_AUTO: 5638 /* 5639 * The BCM5704 ASIC appears to have a special 5640 * mechanism for programming the autoneg 5641 * advertisement registers in TBI mode. 5642 */ 5643 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5644 uint32_t sgdig; 5645 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5646 if (sgdig & BGE_SGDIGSTS_DONE) { 5647 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5648 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5649 sgdig |= BGE_SGDIGCFG_AUTO | 5650 BGE_SGDIGCFG_PAUSE_CAP | 5651 BGE_SGDIGCFG_ASYM_PAUSE; 5652 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5653 sgdig | BGE_SGDIGCFG_SEND); 5654 DELAY(5); 5655 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5656 } 5657 } 5658 break; 5659 case IFM_1000_SX: 5660 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5661 BGE_CLRBIT(sc, BGE_MAC_MODE, 5662 BGE_MACMODE_HALF_DUPLEX); 5663 } else { 5664 BGE_SETBIT(sc, BGE_MAC_MODE, 5665 BGE_MACMODE_HALF_DUPLEX); 5666 } 5667 DELAY(40); 5668 break; 5669 default: 5670 return (EINVAL); 5671 } 5672 return (0); 5673 } 5674 5675 sc->bge_link_evt++; 5676 mii = device_get_softc(sc->bge_miibus); 5677 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5678 PHY_RESET(miisc); 5679 mii_mediachg(mii); 5680 5681 /* 5682 * Force an interrupt so that we will call bge_link_upd 5683 * if needed and clear any pending link state attention. 5684 * Without this we are not getting any further interrupts 5685 * for link state changes and thus will not UP the link and 5686 * not be able to send in bge_start_locked. The only 5687 * way to get things working was to receive a packet and 5688 * get an RX intr. 5689 * bge_tick should help for fiber cards and we might not 5690 * need to do this here if BGE_FLAG_TBI is set but as 5691 * we poll for fiber anyway it should not harm. 5692 */ 5693 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5694 sc->bge_flags & BGE_FLAG_5788) 5695 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5696 else 5697 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5698 5699 return (0); 5700} 5701 5702/* 5703 * Report current media status. 5704 */ 5705static void 5706bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5707{ 5708 struct bge_softc *sc = ifp->if_softc; 5709 struct mii_data *mii; 5710 5711 BGE_LOCK(sc); 5712 5713 if ((ifp->if_flags & IFF_UP) == 0) { 5714 BGE_UNLOCK(sc); 5715 return; 5716 } 5717 if (sc->bge_flags & BGE_FLAG_TBI) { 5718 ifmr->ifm_status = IFM_AVALID; 5719 ifmr->ifm_active = IFM_ETHER; 5720 if (CSR_READ_4(sc, BGE_MAC_STS) & 5721 BGE_MACSTAT_TBI_PCS_SYNCHED) 5722 ifmr->ifm_status |= IFM_ACTIVE; 5723 else { 5724 ifmr->ifm_active |= IFM_NONE; 5725 BGE_UNLOCK(sc); 5726 return; 5727 } 5728 ifmr->ifm_active |= IFM_1000_SX; 5729 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5730 ifmr->ifm_active |= IFM_HDX; 5731 else 5732 ifmr->ifm_active |= IFM_FDX; 5733 BGE_UNLOCK(sc); 5734 return; 5735 } 5736 5737 mii = device_get_softc(sc->bge_miibus); 5738 mii_pollstat(mii); 5739 ifmr->ifm_active = mii->mii_media_active; 5740 ifmr->ifm_status = mii->mii_media_status; 5741 5742 BGE_UNLOCK(sc); 5743} 5744 5745static int 5746bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5747{ 5748 struct bge_softc *sc = ifp->if_softc; 5749 struct ifreq *ifr = (struct ifreq *) data; 5750 struct mii_data *mii; 5751 int flags, mask, error = 0; 5752 5753 switch (command) { 5754 case SIOCSIFMTU: 5755 if (BGE_IS_JUMBO_CAPABLE(sc) || 5756 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5757 if (ifr->ifr_mtu < ETHERMIN || 5758 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5759 error = EINVAL; 5760 break; 5761 } 5762 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5763 error = EINVAL; 5764 break; 5765 } 5766 BGE_LOCK(sc); 5767 if (ifp->if_mtu != ifr->ifr_mtu) { 5768 ifp->if_mtu = ifr->ifr_mtu; 5769 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5770 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5771 bge_init_locked(sc); 5772 } 5773 } 5774 BGE_UNLOCK(sc); 5775 break; 5776 case SIOCSIFFLAGS: 5777 BGE_LOCK(sc); 5778 if (ifp->if_flags & IFF_UP) { 5779 /* 5780 * If only the state of the PROMISC flag changed, 5781 * then just use the 'set promisc mode' command 5782 * instead of reinitializing the entire NIC. Doing 5783 * a full re-init means reloading the firmware and 5784 * waiting for it to start up, which may take a 5785 * second or two. Similarly for ALLMULTI. 5786 */ 5787 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5788 flags = ifp->if_flags ^ sc->bge_if_flags; 5789 if (flags & IFF_PROMISC) 5790 bge_setpromisc(sc); 5791 if (flags & IFF_ALLMULTI) 5792 bge_setmulti(sc); 5793 } else 5794 bge_init_locked(sc); 5795 } else { 5796 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5797 bge_stop(sc); 5798 } 5799 } 5800 sc->bge_if_flags = ifp->if_flags; 5801 BGE_UNLOCK(sc); 5802 error = 0; 5803 break; 5804 case SIOCADDMULTI: 5805 case SIOCDELMULTI: 5806 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5807 BGE_LOCK(sc); 5808 bge_setmulti(sc); 5809 BGE_UNLOCK(sc); 5810 error = 0; 5811 } 5812 break; 5813 case SIOCSIFMEDIA: 5814 case SIOCGIFMEDIA: 5815 if (sc->bge_flags & BGE_FLAG_TBI) { 5816 error = ifmedia_ioctl(ifp, ifr, 5817 &sc->bge_ifmedia, command); 5818 } else { 5819 mii = device_get_softc(sc->bge_miibus); 5820 error = ifmedia_ioctl(ifp, ifr, 5821 &mii->mii_media, command); 5822 } 5823 break; 5824 case SIOCSIFCAP: 5825 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5826#ifdef DEVICE_POLLING 5827 if (mask & IFCAP_POLLING) { 5828 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5829 error = ether_poll_register(bge_poll, ifp); 5830 if (error) 5831 return (error); 5832 BGE_LOCK(sc); 5833 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5834 BGE_PCIMISCCTL_MASK_PCI_INTR); 5835 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5836 ifp->if_capenable |= IFCAP_POLLING; 5837 BGE_UNLOCK(sc); 5838 } else { 5839 error = ether_poll_deregister(ifp); 5840 /* Enable interrupt even in error case */ 5841 BGE_LOCK(sc); 5842 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5843 BGE_PCIMISCCTL_MASK_PCI_INTR); 5844 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5845 ifp->if_capenable &= ~IFCAP_POLLING; 5846 BGE_UNLOCK(sc); 5847 } 5848 } 5849#endif 5850 if ((mask & IFCAP_TXCSUM) != 0 && 5851 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5852 ifp->if_capenable ^= IFCAP_TXCSUM; 5853 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5854 ifp->if_hwassist |= sc->bge_csum_features; 5855 else 5856 ifp->if_hwassist &= ~sc->bge_csum_features; 5857 } 5858 5859 if ((mask & IFCAP_RXCSUM) != 0 && 5860 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5861 ifp->if_capenable ^= IFCAP_RXCSUM; 5862 5863 if ((mask & IFCAP_TSO4) != 0 && 5864 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5865 ifp->if_capenable ^= IFCAP_TSO4; 5866 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5867 ifp->if_hwassist |= CSUM_TSO; 5868 else 5869 ifp->if_hwassist &= ~CSUM_TSO; 5870 } 5871 5872 if (mask & IFCAP_VLAN_MTU) { 5873 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5874 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5875 bge_init(sc); 5876 } 5877 5878 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5879 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5880 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5881 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5882 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5883 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5884 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5885 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5886 BGE_LOCK(sc); 5887 bge_setvlan(sc); 5888 BGE_UNLOCK(sc); 5889 } 5890#ifdef VLAN_CAPABILITIES 5891 VLAN_CAPABILITIES(ifp); 5892#endif 5893 break; 5894 default: 5895 error = ether_ioctl(ifp, command, data); 5896 break; 5897 } 5898 5899 return (error); 5900} 5901 5902static void 5903bge_watchdog(struct bge_softc *sc) 5904{ 5905 struct ifnet *ifp; 5906 uint32_t status; 5907 5908 BGE_LOCK_ASSERT(sc); 5909 5910 if (sc->bge_timer == 0 || --sc->bge_timer) 5911 return; 5912 5913 /* If pause frames are active then don't reset the hardware. */ 5914 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5915 status = CSR_READ_4(sc, BGE_RX_STS); 5916 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5917 /* 5918 * If link partner has us in XOFF state then wait for 5919 * the condition to clear. 5920 */ 5921 CSR_WRITE_4(sc, BGE_RX_STS, status); 5922 sc->bge_timer = BGE_TX_TIMEOUT; 5923 return; 5924 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5925 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5926 /* 5927 * If link partner has us in XOFF state then wait for 5928 * the condition to clear. 5929 */ 5930 CSR_WRITE_4(sc, BGE_RX_STS, status); 5931 sc->bge_timer = BGE_TX_TIMEOUT; 5932 return; 5933 } 5934 /* 5935 * Any other condition is unexpected and the controller 5936 * should be reset. 5937 */ 5938 } 5939 5940 ifp = sc->bge_ifp; 5941 5942 if_printf(ifp, "watchdog timeout -- resetting\n"); 5943 5944 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5945 bge_init_locked(sc); 5946 5947 ifp->if_oerrors++; 5948} 5949 5950static void 5951bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5952{ 5953 int i; 5954 5955 BGE_CLRBIT(sc, reg, bit); 5956 5957 for (i = 0; i < BGE_TIMEOUT; i++) { 5958 if ((CSR_READ_4(sc, reg) & bit) == 0) 5959 return; 5960 DELAY(100); 5961 } 5962} 5963 5964/* 5965 * Stop the adapter and free any mbufs allocated to the 5966 * RX and TX lists. 5967 */ 5968static void 5969bge_stop(struct bge_softc *sc) 5970{ 5971 struct ifnet *ifp; 5972 5973 BGE_LOCK_ASSERT(sc); 5974 5975 ifp = sc->bge_ifp; 5976 5977 callout_stop(&sc->bge_stat_ch); 5978 5979 /* Disable host interrupts. */ 5980 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5981 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5982 5983 /* 5984 * Tell firmware we're shutting down. 5985 */ 5986 bge_stop_fw(sc); 5987 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5988 5989 /* 5990 * Disable all of the receiver blocks. 5991 */ 5992 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5993 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5995 if (BGE_IS_5700_FAMILY(sc)) 5996 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5997 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5998 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6000 6001 /* 6002 * Disable all of the transmit blocks. 6003 */ 6004 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6005 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6006 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6007 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6008 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6009 if (BGE_IS_5700_FAMILY(sc)) 6010 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6011 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6012 6013 /* 6014 * Shut down all of the memory managers and related 6015 * state machines. 6016 */ 6017 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6018 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6019 if (BGE_IS_5700_FAMILY(sc)) 6020 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6021 6022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6024 if (!(BGE_IS_5705_PLUS(sc))) { 6025 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6026 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6027 } 6028 /* Update MAC statistics. */ 6029 if (BGE_IS_5705_PLUS(sc)) 6030 bge_stats_update_regs(sc); 6031 6032 bge_reset(sc); 6033 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6034 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6035 6036 /* 6037 * Keep the ASF firmware running if up. 6038 */ 6039 if (sc->bge_asf_mode & ASF_STACKUP) 6040 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6041 else 6042 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6043 6044 /* Free the RX lists. */ 6045 bge_free_rx_ring_std(sc); 6046 6047 /* Free jumbo RX list. */ 6048 if (BGE_IS_JUMBO_CAPABLE(sc)) 6049 bge_free_rx_ring_jumbo(sc); 6050 6051 /* Free TX buffers. */ 6052 bge_free_tx_ring(sc); 6053 6054 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6055 6056 /* Clear MAC's link state (PHY may still have link UP). */ 6057 if (bootverbose && sc->bge_link) 6058 if_printf(sc->bge_ifp, "link DOWN\n"); 6059 sc->bge_link = 0; 6060 6061 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6062} 6063 6064/* 6065 * Stop all chip I/O so that the kernel's probe routines don't 6066 * get confused by errant DMAs when rebooting. 6067 */ 6068static int 6069bge_shutdown(device_t dev) 6070{ 6071 struct bge_softc *sc; 6072 6073 sc = device_get_softc(dev); 6074 BGE_LOCK(sc); 6075 bge_stop(sc); 6076 BGE_UNLOCK(sc); 6077 6078 return (0); 6079} 6080 6081static int 6082bge_suspend(device_t dev) 6083{ 6084 struct bge_softc *sc; 6085 6086 sc = device_get_softc(dev); 6087 BGE_LOCK(sc); 6088 bge_stop(sc); 6089 BGE_UNLOCK(sc); 6090 6091 return (0); 6092} 6093 6094static int 6095bge_resume(device_t dev) 6096{ 6097 struct bge_softc *sc; 6098 struct ifnet *ifp; 6099 6100 sc = device_get_softc(dev); 6101 BGE_LOCK(sc); 6102 ifp = sc->bge_ifp; 6103 if (ifp->if_flags & IFF_UP) { 6104 bge_init_locked(sc); 6105 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6106 bge_start_locked(ifp); 6107 } 6108 BGE_UNLOCK(sc); 6109 6110 return (0); 6111} 6112 6113static void 6114bge_link_upd(struct bge_softc *sc) 6115{ 6116 struct mii_data *mii; 6117 uint32_t link, status; 6118 6119 BGE_LOCK_ASSERT(sc); 6120 6121 /* Clear 'pending link event' flag. */ 6122 sc->bge_link_evt = 0; 6123 6124 /* 6125 * Process link state changes. 6126 * Grrr. The link status word in the status block does 6127 * not work correctly on the BCM5700 rev AX and BX chips, 6128 * according to all available information. Hence, we have 6129 * to enable MII interrupts in order to properly obtain 6130 * async link changes. Unfortunately, this also means that 6131 * we have to read the MAC status register to detect link 6132 * changes, thereby adding an additional register access to 6133 * the interrupt handler. 6134 * 6135 * XXX: perhaps link state detection procedure used for 6136 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6137 */ 6138 6139 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6140 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6141 status = CSR_READ_4(sc, BGE_MAC_STS); 6142 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6143 mii = device_get_softc(sc->bge_miibus); 6144 mii_pollstat(mii); 6145 if (!sc->bge_link && 6146 mii->mii_media_status & IFM_ACTIVE && 6147 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6148 sc->bge_link++; 6149 if (bootverbose) 6150 if_printf(sc->bge_ifp, "link UP\n"); 6151 } else if (sc->bge_link && 6152 (!(mii->mii_media_status & IFM_ACTIVE) || 6153 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6154 sc->bge_link = 0; 6155 if (bootverbose) 6156 if_printf(sc->bge_ifp, "link DOWN\n"); 6157 } 6158 6159 /* Clear the interrupt. */ 6160 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6161 BGE_EVTENB_MI_INTERRUPT); 6162 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6163 BRGPHY_MII_ISR); 6164 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6165 BRGPHY_MII_IMR, BRGPHY_INTRS); 6166 } 6167 return; 6168 } 6169 6170 if (sc->bge_flags & BGE_FLAG_TBI) { 6171 status = CSR_READ_4(sc, BGE_MAC_STS); 6172 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6173 if (!sc->bge_link) { 6174 sc->bge_link++; 6175 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6176 BGE_CLRBIT(sc, BGE_MAC_MODE, 6177 BGE_MACMODE_TBI_SEND_CFGS); 6178 DELAY(40); 6179 } 6180 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6181 if (bootverbose) 6182 if_printf(sc->bge_ifp, "link UP\n"); 6183 if_link_state_change(sc->bge_ifp, 6184 LINK_STATE_UP); 6185 } 6186 } else if (sc->bge_link) { 6187 sc->bge_link = 0; 6188 if (bootverbose) 6189 if_printf(sc->bge_ifp, "link DOWN\n"); 6190 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6191 } 6192 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6193 /* 6194 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6195 * in status word always set. Workaround this bug by reading 6196 * PHY link status directly. 6197 */ 6198 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6199 6200 if (link != sc->bge_link || 6201 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6202 mii = device_get_softc(sc->bge_miibus); 6203 mii_pollstat(mii); 6204 if (!sc->bge_link && 6205 mii->mii_media_status & IFM_ACTIVE && 6206 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6207 sc->bge_link++; 6208 if (bootverbose) 6209 if_printf(sc->bge_ifp, "link UP\n"); 6210 } else if (sc->bge_link && 6211 (!(mii->mii_media_status & IFM_ACTIVE) || 6212 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6213 sc->bge_link = 0; 6214 if (bootverbose) 6215 if_printf(sc->bge_ifp, "link DOWN\n"); 6216 } 6217 } 6218 } else { 6219 /* 6220 * For controllers that call mii_tick, we have to poll 6221 * link status. 6222 */ 6223 mii = device_get_softc(sc->bge_miibus); 6224 mii_pollstat(mii); 6225 bge_miibus_statchg(sc->bge_dev); 6226 } 6227 6228 /* Disable MAC attention when link is up. */ 6229 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6230 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6231 BGE_MACSTAT_LINK_CHANGED); 6232} 6233 6234static void 6235bge_add_sysctls(struct bge_softc *sc) 6236{ 6237 struct sysctl_ctx_list *ctx; 6238 struct sysctl_oid_list *children; 6239 char tn[32]; 6240 int unit; 6241 6242 ctx = device_get_sysctl_ctx(sc->bge_dev); 6243 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6244 6245#ifdef BGE_REGISTER_DEBUG 6246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6247 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6248 "Debug Information"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6251 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6252 "MAC Register Read"); 6253 6254 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6255 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6256 "APE Register Read"); 6257 6258 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6259 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6260 "Memory Read"); 6261 6262#endif 6263 6264 unit = device_get_unit(sc->bge_dev); 6265 /* 6266 * A common design characteristic for many Broadcom client controllers 6267 * is that they only support a single outstanding DMA read operation 6268 * on the PCIe bus. This means that it will take twice as long to fetch 6269 * a TX frame that is split into header and payload buffers as it does 6270 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6271 * these controllers, coalescing buffers to reduce the number of memory 6272 * reads is effective way to get maximum performance(about 940Mbps). 6273 * Without collapsing TX buffers the maximum TCP bulk transfer 6274 * performance is about 850Mbps. However forcing coalescing mbufs 6275 * consumes a lot of CPU cycles, so leave it off by default. 6276 */ 6277 sc->bge_forced_collapse = 0; 6278 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6279 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6280 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6281 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6282 "Number of fragmented TX buffers of a frame allowed before " 6283 "forced collapsing"); 6284 6285 sc->bge_msi = 1; 6286 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6287 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6288 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6289 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6290 6291 /* 6292 * It seems all Broadcom controllers have a bug that can generate UDP 6293 * datagrams with checksum value 0 when TX UDP checksum offloading is 6294 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6295 * Even though the probability of generating such UDP datagrams is 6296 * low, I don't want to see FreeBSD boxes to inject such datagrams 6297 * into network so disable UDP checksum offloading by default. Users 6298 * still override this behavior by setting a sysctl variable, 6299 * dev.bge.0.forced_udpcsum. 6300 */ 6301 sc->bge_forced_udpcsum = 0; 6302 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6303 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6304 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6305 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6306 "Enable UDP checksum offloading even if controller can " 6307 "generate UDP checksum value 0"); 6308 6309 if (BGE_IS_5705_PLUS(sc)) 6310 bge_add_sysctl_stats_regs(sc, ctx, children); 6311 else 6312 bge_add_sysctl_stats(sc, ctx, children); 6313} 6314 6315#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6316 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6317 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6318 desc) 6319 6320static void 6321bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6322 struct sysctl_oid_list *parent) 6323{ 6324 struct sysctl_oid *tree; 6325 struct sysctl_oid_list *children, *schildren; 6326 6327 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6328 NULL, "BGE Statistics"); 6329 schildren = children = SYSCTL_CHILDREN(tree); 6330 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6331 children, COSFramesDroppedDueToFilters, 6332 "FramesDroppedDueToFilters"); 6333 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6334 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6335 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6336 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6337 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6338 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6339 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6340 children, ifInDiscards, "InputDiscards"); 6341 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6342 children, ifInErrors, "InputErrors"); 6343 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6344 children, nicRecvThresholdHit, "RecvThresholdHit"); 6345 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6346 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6347 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6348 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6349 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6350 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6351 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6352 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6353 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6354 children, nicRingStatusUpdate, "RingStatusUpdate"); 6355 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6356 children, nicInterrupts, "Interrupts"); 6357 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6358 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6359 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6360 children, nicSendThresholdHit, "SendThresholdHit"); 6361 6362 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6363 NULL, "BGE RX Statistics"); 6364 children = SYSCTL_CHILDREN(tree); 6365 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6366 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6367 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6368 children, rxstats.etherStatsFragments, "Fragments"); 6369 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6370 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6371 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6372 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6373 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6374 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6375 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6376 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6377 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6378 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6379 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6380 children, rxstats.xoffPauseFramesReceived, 6381 "xoffPauseFramesReceived"); 6382 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6383 children, rxstats.macControlFramesReceived, 6384 "ControlFramesReceived"); 6385 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6386 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6387 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6388 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6389 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6390 children, rxstats.etherStatsJabbers, "Jabbers"); 6391 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6392 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6393 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6394 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6395 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6396 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6397 6398 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6399 NULL, "BGE TX Statistics"); 6400 children = SYSCTL_CHILDREN(tree); 6401 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6402 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6403 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6404 children, txstats.etherStatsCollisions, "Collisions"); 6405 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6406 children, txstats.outXonSent, "XonSent"); 6407 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6408 children, txstats.outXoffSent, "XoffSent"); 6409 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6410 children, txstats.flowControlDone, "flowControlDone"); 6411 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6412 children, txstats.dot3StatsInternalMacTransmitErrors, 6413 "InternalMacTransmitErrors"); 6414 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6415 children, txstats.dot3StatsSingleCollisionFrames, 6416 "SingleCollisionFrames"); 6417 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6418 children, txstats.dot3StatsMultipleCollisionFrames, 6419 "MultipleCollisionFrames"); 6420 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6421 children, txstats.dot3StatsDeferredTransmissions, 6422 "DeferredTransmissions"); 6423 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6424 children, txstats.dot3StatsExcessiveCollisions, 6425 "ExcessiveCollisions"); 6426 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6427 children, txstats.dot3StatsLateCollisions, 6428 "LateCollisions"); 6429 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6430 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6431 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6432 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6433 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6434 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6435 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6436 children, txstats.dot3StatsCarrierSenseErrors, 6437 "CarrierSenseErrors"); 6438 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6439 children, txstats.ifOutDiscards, "Discards"); 6440 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6441 children, txstats.ifOutErrors, "Errors"); 6442} 6443 6444#undef BGE_SYSCTL_STAT 6445 6446#define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6447 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6448 6449static void 6450bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6451 struct sysctl_oid_list *parent) 6452{ 6453 struct sysctl_oid *tree; 6454 struct sysctl_oid_list *child, *schild; 6455 struct bge_mac_stats *stats; 6456 6457 stats = &sc->bge_mac_stats; 6458 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6459 NULL, "BGE Statistics"); 6460 schild = child = SYSCTL_CHILDREN(tree); 6461 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6462 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6463 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6464 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6465 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6466 &stats->DmaWriteHighPriQueueFull, 6467 "NIC DMA Write High Priority Queue Full"); 6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6469 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6470 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6471 &stats->InputDiscards, "Discarded Input Frames"); 6472 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6473 &stats->InputErrors, "Input Errors"); 6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6475 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6476 6477 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6478 NULL, "BGE RX Statistics"); 6479 child = SYSCTL_CHILDREN(tree); 6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6481 &stats->ifHCInOctets, "Inbound Octets"); 6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6483 &stats->etherStatsFragments, "Fragments"); 6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6485 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6487 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6489 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6491 &stats->dot3StatsFCSErrors, "FCS Errors"); 6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6493 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6494 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6495 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6496 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6497 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6499 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6501 &stats->xoffStateEntered, "XOFF State Entered"); 6502 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6503 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6504 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6505 &stats->etherStatsJabbers, "Jabbers"); 6506 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6507 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6508 6509 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6510 NULL, "BGE TX Statistics"); 6511 child = SYSCTL_CHILDREN(tree); 6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6513 &stats->ifHCOutOctets, "Outbound Octets"); 6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6515 &stats->etherStatsCollisions, "TX Collisions"); 6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6517 &stats->outXonSent, "XON Sent"); 6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6519 &stats->outXoffSent, "XOFF Sent"); 6520 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6521 &stats->dot3StatsInternalMacTransmitErrors, 6522 "Internal MAC TX Errors"); 6523 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6524 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6525 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6526 &stats->dot3StatsMultipleCollisionFrames, 6527 "Multiple Collision Frames"); 6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6529 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6531 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6533 &stats->dot3StatsLateCollisions, "Late Collisions"); 6534 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6535 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6536 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6537 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6538 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6539 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6540} 6541 6542#undef BGE_SYSCTL_STAT_ADD64 6543 6544static int 6545bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6546{ 6547 struct bge_softc *sc; 6548 uint32_t result; 6549 int offset; 6550 6551 sc = (struct bge_softc *)arg1; 6552 offset = arg2; 6553 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6554 offsetof(bge_hostaddr, bge_addr_lo)); 6555 return (sysctl_handle_int(oidp, &result, 0, req)); 6556} 6557 6558#ifdef BGE_REGISTER_DEBUG 6559static int 6560bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6561{ 6562 struct bge_softc *sc; 6563 uint16_t *sbdata; 6564 int error, result, sbsz; 6565 int i, j; 6566 6567 result = -1; 6568 error = sysctl_handle_int(oidp, &result, 0, req); 6569 if (error || (req->newptr == NULL)) 6570 return (error); 6571 6572 if (result == 1) { 6573 sc = (struct bge_softc *)arg1; 6574 6575 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6576 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6577 sbsz = BGE_STATUS_BLK_SZ; 6578 else 6579 sbsz = 32; 6580 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6581 printf("Status Block:\n"); 6582 BGE_LOCK(sc); 6583 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6584 sc->bge_cdata.bge_status_map, 6585 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6586 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6587 printf("%06x:", i); 6588 for (j = 0; j < 8; j++) 6589 printf(" %04x", sbdata[i++]); 6590 printf("\n"); 6591 } 6592 6593 printf("Registers:\n"); 6594 for (i = 0x800; i < 0xA00; ) { 6595 printf("%06x:", i); 6596 for (j = 0; j < 8; j++) { 6597 printf(" %08x", CSR_READ_4(sc, i)); 6598 i += 4; 6599 } 6600 printf("\n"); 6601 } 6602 BGE_UNLOCK(sc); 6603 6604 printf("Hardware Flags:\n"); 6605 if (BGE_IS_5717_PLUS(sc)) 6606 printf(" - 5717 Plus\n"); 6607 if (BGE_IS_5755_PLUS(sc)) 6608 printf(" - 5755 Plus\n"); 6609 if (BGE_IS_575X_PLUS(sc)) 6610 printf(" - 575X Plus\n"); 6611 if (BGE_IS_5705_PLUS(sc)) 6612 printf(" - 5705 Plus\n"); 6613 if (BGE_IS_5714_FAMILY(sc)) 6614 printf(" - 5714 Family\n"); 6615 if (BGE_IS_5700_FAMILY(sc)) 6616 printf(" - 5700 Family\n"); 6617 if (sc->bge_flags & BGE_FLAG_JUMBO) 6618 printf(" - Supports Jumbo Frames\n"); 6619 if (sc->bge_flags & BGE_FLAG_PCIX) 6620 printf(" - PCI-X Bus\n"); 6621 if (sc->bge_flags & BGE_FLAG_PCIE) 6622 printf(" - PCI Express Bus\n"); 6623 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6624 printf(" - No 3 LEDs\n"); 6625 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6626 printf(" - RX Alignment Bug\n"); 6627 } 6628 6629 return (error); 6630} 6631 6632static int 6633bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6634{ 6635 struct bge_softc *sc; 6636 int error; 6637 uint16_t result; 6638 uint32_t val; 6639 6640 result = -1; 6641 error = sysctl_handle_int(oidp, &result, 0, req); 6642 if (error || (req->newptr == NULL)) 6643 return (error); 6644 6645 if (result < 0x8000) { 6646 sc = (struct bge_softc *)arg1; 6647 val = CSR_READ_4(sc, result); 6648 printf("reg 0x%06X = 0x%08X\n", result, val); 6649 } 6650 6651 return (error); 6652} 6653 6654static int 6655bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6656{ 6657 struct bge_softc *sc; 6658 int error; 6659 uint16_t result; 6660 uint32_t val; 6661 6662 result = -1; 6663 error = sysctl_handle_int(oidp, &result, 0, req); 6664 if (error || (req->newptr == NULL)) 6665 return (error); 6666 6667 if (result < 0x8000) { 6668 sc = (struct bge_softc *)arg1; 6669 val = APE_READ_4(sc, result); 6670 printf("reg 0x%06X = 0x%08X\n", result, val); 6671 } 6672 6673 return (error); 6674} 6675 6676static int 6677bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6678{ 6679 struct bge_softc *sc; 6680 int error; 6681 uint16_t result; 6682 uint32_t val; 6683 6684 result = -1; 6685 error = sysctl_handle_int(oidp, &result, 0, req); 6686 if (error || (req->newptr == NULL)) 6687 return (error); 6688 6689 if (result < 0x8000) { 6690 sc = (struct bge_softc *)arg1; 6691 val = bge_readmem_ind(sc, result); 6692 printf("mem 0x%06X = 0x%08X\n", result, val); 6693 } 6694 6695 return (error); 6696} 6697#endif 6698 6699static int 6700bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6701{ 6702 6703 if (sc->bge_flags & BGE_FLAG_EADDR) 6704 return (1); 6705 6706#ifdef __sparc64__ 6707 OF_getetheraddr(sc->bge_dev, ether_addr); 6708 return (0); 6709#endif 6710 return (1); 6711} 6712 6713static int 6714bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6715{ 6716 uint32_t mac_addr; 6717 6718 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6719 if ((mac_addr >> 16) == 0x484b) { 6720 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6721 ether_addr[1] = (uint8_t)mac_addr; 6722 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6723 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6724 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6725 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6726 ether_addr[5] = (uint8_t)mac_addr; 6727 return (0); 6728 } 6729 return (1); 6730} 6731 6732static int 6733bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6734{ 6735 int mac_offset = BGE_EE_MAC_OFFSET; 6736 6737 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6738 mac_offset = BGE_EE_MAC_OFFSET_5906; 6739 6740 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6741 ETHER_ADDR_LEN)); 6742} 6743 6744static int 6745bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6746{ 6747 6748 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6749 return (1); 6750 6751 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6752 ETHER_ADDR_LEN)); 6753} 6754 6755static int 6756bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6757{ 6758 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6759 /* NOTE: Order is critical */ 6760 bge_get_eaddr_fw, 6761 bge_get_eaddr_mem, 6762 bge_get_eaddr_nvram, 6763 bge_get_eaddr_eeprom, 6764 NULL 6765 }; 6766 const bge_eaddr_fcn_t *func; 6767 6768 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6769 if ((*func)(sc, eaddr) == 0) 6770 break; 6771 } 6772 return (*func == NULL ? ENXIO : 0); 6773} 6774