1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-ciu-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon ciu. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_CIU_DEFS_H__ 53#define __CVMX_CIU_DEFS_H__ 54 55#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) 56#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 57#define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC() 58static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void) 59{ 60 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 61 cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n"); 62 return CVMX_ADD_IO_SEG(0x00010700000007C0ull); 63} 64#else 65#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) 66#endif 67#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_CIU_EN2_IOX_INT(unsigned long offset) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 73 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 74 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 75 cvmx_warn("CVMX_CIU_EN2_IOX_INT(%lu) is invalid on this chip\n", offset); 76 return CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8; 77} 78#else 79#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1C(unsigned long offset) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 86 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 87 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 88 cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1C(%lu) is invalid on this chip\n", offset); 89 return CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8; 90} 91#else 92#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1S(unsigned long offset) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 99 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 100 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 101 cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1S(%lu) is invalid on this chip\n", offset); 102 return CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8; 103} 104#else 105#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_CIU_EN2_PPX_IP2(unsigned long offset) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 112 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 114 cvmx_warn("CVMX_CIU_EN2_PPX_IP2(%lu) is invalid on this chip\n", offset); 115 return CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8; 116} 117#else 118#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1C(unsigned long offset) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 125 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 126 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 127 cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1C(%lu) is invalid on this chip\n", offset); 128 return CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8; 129} 130#else 131#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1S(unsigned long offset) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 138 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 139 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 140 cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1S(%lu) is invalid on this chip\n", offset); 141 return CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8; 142} 143#else 144#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_CIU_EN2_PPX_IP3(unsigned long offset) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 152 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 153 cvmx_warn("CVMX_CIU_EN2_PPX_IP3(%lu) is invalid on this chip\n", offset); 154 return CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8; 155} 156#else 157#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1C(unsigned long offset) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 164 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 165 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 166 cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1C(%lu) is invalid on this chip\n", offset); 167 return CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8; 168} 169#else 170#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1S(unsigned long offset) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 177 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 178 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 179 cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1S(%lu) is invalid on this chip\n", offset); 180 return CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8; 181} 182#else 183#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_CIU_EN2_PPX_IP4(unsigned long offset) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 190 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 191 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 192 cvmx_warn("CVMX_CIU_EN2_PPX_IP4(%lu) is invalid on this chip\n", offset); 193 return CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8; 194} 195#else 196#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1C(unsigned long offset) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 203 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 204 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 205 cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1C(%lu) is invalid on this chip\n", offset); 206 return CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8; 207} 208#else 209#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1S(unsigned long offset) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 216 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 217 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 218 cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1S(%lu) is invalid on this chip\n", offset); 219 return CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8; 220} 221#else 222#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) 223#endif 224#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 225#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) 226#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 227#define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC() 228static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void) 229{ 230 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 231 cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n"); 232 return CVMX_ADD_IO_SEG(0x0001070000000110ull); 233} 234#else 235#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 242 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 243 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 244 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 246 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 247 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 249 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 250 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 251 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 252 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset); 253 return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16; 254} 255#else 256#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 257#endif 258#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 259static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset) 260{ 261 if (!( 262 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 263 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 264 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 265 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 266 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 267 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 268 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 269 cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset); 270 return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16; 271} 272#else 273#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 280 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 281 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 285 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 286 cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset); 287 return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16; 288} 289#else 290#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 291#endif 292#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 293static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset) 294{ 295 if (!( 296 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 297 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 298 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 299 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 300 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 301 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 302 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 303 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 304 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 305 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 306 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 307 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset); 308 return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16; 309} 310#else 311#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 312#endif 313#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 314static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset) 315{ 316 if (!( 317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 319 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 320 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 321 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 322 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 323 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 324 cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset); 325 return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16; 326} 327#else 328#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset) 332{ 333 if (!( 334 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 335 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 336 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 337 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) || 338 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) || 339 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) || 340 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))))) 341 cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset); 342 return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16; 343} 344#else 345#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 346#endif 347#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 348static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset) 349{ 350 if (!( 351 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 352 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 353 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 355 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 357 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 358 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 359 cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset); 360 return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16; 361} 362#else 363#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16) 364#endif 365#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 366static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset) 367{ 368 if (!( 369 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 370 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 371 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 372 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 373 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 374 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 375 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 376 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset); 377 return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16; 378} 379#else 380#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16) 381#endif 382#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 383static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset) 384{ 385 if (!( 386 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 387 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 388 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 389 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 390 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 391 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 392 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 393 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset); 394 return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16; 395} 396#else 397#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16) 398#endif 399#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 400static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset) 401{ 402 if (!( 403 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 404 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 405 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 406 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 407 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 408 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 409 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 410 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 411 cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset); 412 return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16; 413} 414#else 415#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16) 416#endif 417#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset) 419{ 420 if (!( 421 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 422 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 423 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 424 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 425 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 426 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 427 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 428 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset); 429 return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16; 430} 431#else 432#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16) 433#endif 434#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 435static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset) 436{ 437 if (!( 438 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 439 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 440 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 441 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 442 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 443 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 444 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 445 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset); 446 return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16; 447} 448#else 449#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset) 453{ 454 if (!( 455 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 456 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 457 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 458 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 459 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 460 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 461 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 462 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || (offset == 32))) || 463 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32))) || 464 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || (offset == 32))) || 465 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || (offset == 32))))) 466 cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset); 467 return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8; 468} 469#else 470#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 471#endif 472#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 473static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset) 474{ 475 if (!( 476 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 477 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 478 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 479 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 480 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 481 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 482 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 483 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 484 cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset); 485 return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8; 486} 487#else 488#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) 489#endif 490#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 491#define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC() 492static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void) 493{ 494 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 495 cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n"); 496 return CVMX_ADD_IO_SEG(0x00010700000007D0ull); 497} 498#else 499#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) 500#endif 501#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 502#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC() 503static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void) 504{ 505 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 506 cvmx_warn("CVMX_CIU_INT_SUM1 not supported on this chip\n"); 507 return CVMX_ADD_IO_SEG(0x0001070000000108ull); 508} 509#else 510#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 511#endif 512static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 513{ 514 switch(cvmx_get_octeon_family()) { 515 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 516 if ((offset == 0)) 517 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 0) * 8; 518 break; 519 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 520 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 521 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 522 if ((offset <= 3)) 523 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8; 524 break; 525 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 526 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 527 if ((offset <= 1)) 528 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 1) * 8; 529 break; 530 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 531 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 532 if ((offset <= 15)) 533 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8; 534 break; 535 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 536 if ((offset <= 11)) 537 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8; 538 break; 539 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 540 if ((offset <= 9)) 541 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8; 542 break; 543 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 544 if ((offset <= 5)) 545 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 7) * 8; 546 break; 547 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 548 if ((offset <= 31)) 549 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + ((offset) & 31) * 8; 550 break; 551 } 552 cvmx_warn("CVMX_CIU_MBOX_CLRX (offset = %lu) not supported on this chip\n", offset); 553 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8; 554} 555static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 556{ 557 switch(cvmx_get_octeon_family()) { 558 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 559 if ((offset == 0)) 560 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 0) * 8; 561 break; 562 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 563 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 564 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 565 if ((offset <= 3)) 566 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8; 567 break; 568 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 569 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 570 if ((offset <= 1)) 571 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 1) * 8; 572 break; 573 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 574 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 575 if ((offset <= 15)) 576 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8; 577 break; 578 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 579 if ((offset <= 11)) 580 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8; 581 break; 582 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 583 if ((offset <= 9)) 584 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8; 585 break; 586 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 587 if ((offset <= 5)) 588 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 7) * 8; 589 break; 590 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 591 if ((offset <= 31)) 592 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + ((offset) & 31) * 8; 593 break; 594 } 595 cvmx_warn("CVMX_CIU_MBOX_SETX (offset = %lu) not supported on this chip\n", offset); 596 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8; 597} 598#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 599#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 600#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 601#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_PP_BIST_STAT_FUNC() 602static inline uint64_t CVMX_CIU_PP_BIST_STAT_FUNC(void) 603{ 604 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 605 cvmx_warn("CVMX_CIU_PP_BIST_STAT not supported on this chip\n"); 606 return CVMX_ADD_IO_SEG(0x00010700000007E0ull); 607} 608#else 609#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 610#endif 611#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 612static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 613{ 614 switch(cvmx_get_octeon_family()) { 615 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 616 if ((offset == 0)) 617 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 0) * 8; 618 break; 619 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 620 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 621 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 622 if ((offset <= 3)) 623 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8; 624 break; 625 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 626 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 627 if ((offset <= 1)) 628 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 1) * 8; 629 break; 630 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 631 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 632 if ((offset <= 15)) 633 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8; 634 break; 635 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 636 if ((offset <= 11)) 637 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8; 638 break; 639 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 640 if ((offset <= 9)) 641 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8; 642 break; 643 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 644 if ((offset <= 5)) 645 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 7) * 8; 646 break; 647 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 648 if ((offset <= 31)) 649 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + ((offset) & 31) * 8; 650 break; 651 } 652 cvmx_warn("CVMX_CIU_PP_POKEX (offset = %lu) not supported on this chip\n", offset); 653 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8; 654} 655#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 656#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 657#define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC() 658static inline uint64_t CVMX_CIU_QLM0_FUNC(void) 659{ 660 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 661 cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n"); 662 return CVMX_ADD_IO_SEG(0x0001070000000780ull); 663} 664#else 665#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 666#endif 667#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 668#define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC() 669static inline uint64_t CVMX_CIU_QLM1_FUNC(void) 670{ 671 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 672 cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n"); 673 return CVMX_ADD_IO_SEG(0x0001070000000788ull); 674} 675#else 676#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 677#endif 678#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 679#define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC() 680static inline uint64_t CVMX_CIU_QLM2_FUNC(void) 681{ 682 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 683 cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n"); 684 return CVMX_ADD_IO_SEG(0x0001070000000790ull); 685} 686#else 687#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) 688#endif 689#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 690#define CVMX_CIU_QLM3 CVMX_CIU_QLM3_FUNC() 691static inline uint64_t CVMX_CIU_QLM3_FUNC(void) 692{ 693 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 694 cvmx_warn("CVMX_CIU_QLM3 not supported on this chip\n"); 695 return CVMX_ADD_IO_SEG(0x0001070000000798ull); 696} 697#else 698#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) 699#endif 700#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 701#define CVMX_CIU_QLM4 CVMX_CIU_QLM4_FUNC() 702static inline uint64_t CVMX_CIU_QLM4_FUNC(void) 703{ 704 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 705 cvmx_warn("CVMX_CIU_QLM4 not supported on this chip\n"); 706 return CVMX_ADD_IO_SEG(0x00010700000007A0ull); 707} 708#else 709#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) 710#endif 711#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 712#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC() 713static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void) 714{ 715 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 716 cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n"); 717 return CVMX_ADD_IO_SEG(0x0001070000000760ull); 718} 719#else 720#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) 721#endif 722#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 723#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC() 724static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void) 725{ 726 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 727 cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n"); 728 return CVMX_ADD_IO_SEG(0x0001070000000768ull); 729} 730#else 731#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 732#endif 733#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 734#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC() 735static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void) 736{ 737 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 738 cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n"); 739 return CVMX_ADD_IO_SEG(0x0001070000000770ull); 740} 741#else 742#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 743#endif 744#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 745#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 746#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 747#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC() 748static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void) 749{ 750 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 751 cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n"); 752 return CVMX_ADD_IO_SEG(0x0001070000000758ull); 753} 754#else 755#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 756#endif 757#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 758#define CVMX_CIU_SOFT_PRST2 CVMX_CIU_SOFT_PRST2_FUNC() 759static inline uint64_t CVMX_CIU_SOFT_PRST2_FUNC(void) 760{ 761 if (!(OCTEON_IS_MODEL(OCTEON_CN66XX))) 762 cvmx_warn("CVMX_CIU_SOFT_PRST2 not supported on this chip\n"); 763 return CVMX_ADD_IO_SEG(0x00010700000007D8ull); 764} 765#else 766#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) 767#endif 768#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 769#define CVMX_CIU_SOFT_PRST3 CVMX_CIU_SOFT_PRST3_FUNC() 770static inline uint64_t CVMX_CIU_SOFT_PRST3_FUNC(void) 771{ 772 if (!(OCTEON_IS_MODEL(OCTEON_CN66XX))) 773 cvmx_warn("CVMX_CIU_SOFT_PRST3 not supported on this chip\n"); 774 return CVMX_ADD_IO_SEG(0x00010700000007E0ull); 775} 776#else 777#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 778#endif 779#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 780#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 781static inline uint64_t CVMX_CIU_SUM1_IOX_INT(unsigned long offset) 782{ 783 if (!( 784 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 785 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 786 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 787 cvmx_warn("CVMX_CIU_SUM1_IOX_INT(%lu) is invalid on this chip\n", offset); 788 return CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8; 789} 790#else 791#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) 792#endif 793#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 794static inline uint64_t CVMX_CIU_SUM1_PPX_IP2(unsigned long offset) 795{ 796 if (!( 797 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 798 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 799 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 800 cvmx_warn("CVMX_CIU_SUM1_PPX_IP2(%lu) is invalid on this chip\n", offset); 801 return CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8; 802} 803#else 804#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) 805#endif 806#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 807static inline uint64_t CVMX_CIU_SUM1_PPX_IP3(unsigned long offset) 808{ 809 if (!( 810 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 811 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 812 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 813 cvmx_warn("CVMX_CIU_SUM1_PPX_IP3(%lu) is invalid on this chip\n", offset); 814 return CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8; 815} 816#else 817#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) 818#endif 819#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 820static inline uint64_t CVMX_CIU_SUM1_PPX_IP4(unsigned long offset) 821{ 822 if (!( 823 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 824 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 825 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 826 cvmx_warn("CVMX_CIU_SUM1_PPX_IP4(%lu) is invalid on this chip\n", offset); 827 return CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8; 828} 829#else 830#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) 831#endif 832#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 833static inline uint64_t CVMX_CIU_SUM2_IOX_INT(unsigned long offset) 834{ 835 if (!( 836 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 837 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 838 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 839 cvmx_warn("CVMX_CIU_SUM2_IOX_INT(%lu) is invalid on this chip\n", offset); 840 return CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8; 841} 842#else 843#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) 844#endif 845#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 846static inline uint64_t CVMX_CIU_SUM2_PPX_IP2(unsigned long offset) 847{ 848 if (!( 849 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 850 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 851 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 852 cvmx_warn("CVMX_CIU_SUM2_PPX_IP2(%lu) is invalid on this chip\n", offset); 853 return CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8; 854} 855#else 856#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) 857#endif 858#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 859static inline uint64_t CVMX_CIU_SUM2_PPX_IP3(unsigned long offset) 860{ 861 if (!( 862 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 863 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 864 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 865 cvmx_warn("CVMX_CIU_SUM2_PPX_IP3(%lu) is invalid on this chip\n", offset); 866 return CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8; 867} 868#else 869#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) 870#endif 871#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 872static inline uint64_t CVMX_CIU_SUM2_PPX_IP4(unsigned long offset) 873{ 874 if (!( 875 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 876 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 877 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 878 cvmx_warn("CVMX_CIU_SUM2_PPX_IP4(%lu) is invalid on this chip\n", offset); 879 return CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8; 880} 881#else 882#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) 883#endif 884#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 885static inline uint64_t CVMX_CIU_TIMX(unsigned long offset) 886{ 887 if (!( 888 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 889 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 890 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 891 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 892 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 893 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 894 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 895 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 9))) || 896 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) || 897 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 898 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 899 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 9))))) 900 cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset); 901 return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8; 902} 903#else 904#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) 905#endif 906#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 907#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_TIM_MULTI_CAST_FUNC() 908static inline uint64_t CVMX_CIU_TIM_MULTI_CAST_FUNC(void) 909{ 910 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 911 cvmx_warn("CVMX_CIU_TIM_MULTI_CAST not supported on this chip\n"); 912 return CVMX_ADD_IO_SEG(0x000107000000C200ull); 913} 914#else 915#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) 916#endif 917static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 918{ 919 switch(cvmx_get_octeon_family()) { 920 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 921 if ((offset == 0)) 922 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 0) * 8; 923 break; 924 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 925 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 926 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 927 if ((offset <= 3)) 928 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8; 929 break; 930 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 931 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 932 if ((offset <= 1)) 933 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 1) * 8; 934 break; 935 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 936 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 937 if ((offset <= 15)) 938 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8; 939 break; 940 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 941 if ((offset <= 11)) 942 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8; 943 break; 944 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 945 if ((offset <= 9)) 946 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8; 947 break; 948 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 949 if ((offset <= 5)) 950 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 7) * 8; 951 break; 952 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 953 if ((offset <= 31)) 954 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + ((offset) & 31) * 8; 955 break; 956 } 957 cvmx_warn("CVMX_CIU_WDOGX (offset = %lu) not supported on this chip\n", offset); 958 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8; 959} 960 961/** 962 * cvmx_ciu_bist 963 */ 964union cvmx_ciu_bist { 965 uint64_t u64; 966 struct cvmx_ciu_bist_s { 967#ifdef __BIG_ENDIAN_BITFIELD 968 uint64_t reserved_7_63 : 57; 969 uint64_t bist : 7; /**< BIST Results. 970 HW sets a bit in BIST for for memory that fails 971 BIST. */ 972#else 973 uint64_t bist : 7; 974 uint64_t reserved_7_63 : 57; 975#endif 976 } s; 977 struct cvmx_ciu_bist_cn30xx { 978#ifdef __BIG_ENDIAN_BITFIELD 979 uint64_t reserved_4_63 : 60; 980 uint64_t bist : 4; /**< BIST Results. 981 HW sets a bit in BIST for for memory that fails 982 BIST. */ 983#else 984 uint64_t bist : 4; 985 uint64_t reserved_4_63 : 60; 986#endif 987 } cn30xx; 988 struct cvmx_ciu_bist_cn30xx cn31xx; 989 struct cvmx_ciu_bist_cn30xx cn38xx; 990 struct cvmx_ciu_bist_cn30xx cn38xxp2; 991 struct cvmx_ciu_bist_cn50xx { 992#ifdef __BIG_ENDIAN_BITFIELD 993 uint64_t reserved_2_63 : 62; 994 uint64_t bist : 2; /**< BIST Results. 995 HW sets a bit in BIST for for memory that fails 996 BIST. */ 997#else 998 uint64_t bist : 2; 999 uint64_t reserved_2_63 : 62; 1000#endif 1001 } cn50xx; 1002 struct cvmx_ciu_bist_cn52xx { 1003#ifdef __BIG_ENDIAN_BITFIELD 1004 uint64_t reserved_3_63 : 61; 1005 uint64_t bist : 3; /**< BIST Results. 1006 HW sets a bit in BIST for for memory that fails 1007 BIST. */ 1008#else 1009 uint64_t bist : 3; 1010 uint64_t reserved_3_63 : 61; 1011#endif 1012 } cn52xx; 1013 struct cvmx_ciu_bist_cn52xx cn52xxp1; 1014 struct cvmx_ciu_bist_cn30xx cn56xx; 1015 struct cvmx_ciu_bist_cn30xx cn56xxp1; 1016 struct cvmx_ciu_bist_cn30xx cn58xx; 1017 struct cvmx_ciu_bist_cn30xx cn58xxp1; 1018 struct cvmx_ciu_bist_cn61xx { 1019#ifdef __BIG_ENDIAN_BITFIELD 1020 uint64_t reserved_6_63 : 58; 1021 uint64_t bist : 6; /**< BIST Results. 1022 HW sets a bit in BIST for for memory that fails 1023 BIST. */ 1024#else 1025 uint64_t bist : 6; 1026 uint64_t reserved_6_63 : 58; 1027#endif 1028 } cn61xx; 1029 struct cvmx_ciu_bist_cn63xx { 1030#ifdef __BIG_ENDIAN_BITFIELD 1031 uint64_t reserved_5_63 : 59; 1032 uint64_t bist : 5; /**< BIST Results. 1033 HW sets a bit in BIST for for memory that fails 1034 BIST. */ 1035#else 1036 uint64_t bist : 5; 1037 uint64_t reserved_5_63 : 59; 1038#endif 1039 } cn63xx; 1040 struct cvmx_ciu_bist_cn63xx cn63xxp1; 1041 struct cvmx_ciu_bist_cn61xx cn66xx; 1042 struct cvmx_ciu_bist_s cn68xx; 1043 struct cvmx_ciu_bist_s cn68xxp1; 1044 struct cvmx_ciu_bist_cn61xx cnf71xx; 1045}; 1046typedef union cvmx_ciu_bist cvmx_ciu_bist_t; 1047 1048/** 1049 * cvmx_ciu_block_int 1050 * 1051 * CIU_BLOCK_INT = CIU Blocks Interrupt 1052 * 1053 * The interrupt lines from the various chip blocks. 1054 */ 1055union cvmx_ciu_block_int { 1056 uint64_t u64; 1057 struct cvmx_ciu_block_int_s { 1058#ifdef __BIG_ENDIAN_BITFIELD 1059 uint64_t reserved_62_63 : 2; 1060 uint64_t srio3 : 1; /**< SRIO3 interrupt 1061 See SRIO3_INT_REG, SRIO3_INT2_REG */ 1062 uint64_t srio2 : 1; /**< SRIO2 interrupt 1063 See SRIO2_INT_REG, SRIO2_INT2_REG */ 1064 uint64_t reserved_43_59 : 17; 1065 uint64_t ptp : 1; /**< PTP interrupt 1066 See CIU_INT_SUM1[PTP] */ 1067 uint64_t dpi : 1; /**< DPI interrupt 1068 See DPI_INT_REG */ 1069 uint64_t dfm : 1; /**< DFM interrupt 1070 See DFM_FNT_STAT */ 1071 uint64_t reserved_34_39 : 6; 1072 uint64_t srio1 : 1; /**< SRIO1 interrupt 1073 See SRIO1_INT_REG */ 1074 uint64_t srio0 : 1; /**< SRIO0 interrupt 1075 See SRIO0_INT_REG, SRIO0_INT2_REG */ 1076 uint64_t reserved_31_31 : 1; 1077 uint64_t iob : 1; /**< IOB interrupt 1078 See IOB_INT_SUM */ 1079 uint64_t reserved_29_29 : 1; 1080 uint64_t agl : 1; /**< AGL interrupt 1081 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 1082 uint64_t reserved_27_27 : 1; 1083 uint64_t pem1 : 1; /**< PEM1 interrupt 1084 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 1085 uint64_t pem0 : 1; /**< PEM0 interrupt 1086 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 1087 uint64_t reserved_24_24 : 1; 1088 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */ 1089 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 1090 uint64_t reserved_21_21 : 1; 1091 uint64_t pip : 1; /**< PIP interrupt 1092 See PIP_INT_REG */ 1093 uint64_t reserved_18_19 : 2; 1094 uint64_t lmc0 : 1; /**< LMC0 interrupt 1095 See LMC0_INT */ 1096 uint64_t l2c : 1; /**< L2C interrupt 1097 See L2C_INT_REG */ 1098 uint64_t reserved_15_15 : 1; 1099 uint64_t rad : 1; /**< RAD interrupt 1100 See RAD_REG_ERROR */ 1101 uint64_t usb : 1; /**< USB UCTL0 interrupt 1102 See UCTL0_INT_REG */ 1103 uint64_t pow : 1; /**< POW err interrupt 1104 See POW_ECC_ERR */ 1105 uint64_t tim : 1; /**< TIM interrupt 1106 See TIM_REG_ERROR */ 1107 uint64_t pko : 1; /**< PKO interrupt 1108 See PKO_REG_ERROR */ 1109 uint64_t ipd : 1; /**< IPD interrupt 1110 See IPD_INT_SUM */ 1111 uint64_t reserved_8_8 : 1; 1112 uint64_t zip : 1; /**< ZIP interrupt 1113 See ZIP_ERROR */ 1114 uint64_t dfa : 1; /**< DFA interrupt 1115 See DFA_ERROR */ 1116 uint64_t fpa : 1; /**< FPA interrupt 1117 See FPA_INT_SUM */ 1118 uint64_t key : 1; /**< KEY interrupt 1119 See KEY_INT_SUM */ 1120 uint64_t sli : 1; /**< SLI interrupt 1121 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 1122 uint64_t gmx1 : 1; /**< GMX1 interrupt 1123 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */ 1124 uint64_t gmx0 : 1; /**< GMX0 interrupt 1125 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 1126 uint64_t mio : 1; /**< MIO boot interrupt 1127 See MIO_BOOT_ERR */ 1128#else 1129 uint64_t mio : 1; 1130 uint64_t gmx0 : 1; 1131 uint64_t gmx1 : 1; 1132 uint64_t sli : 1; 1133 uint64_t key : 1; 1134 uint64_t fpa : 1; 1135 uint64_t dfa : 1; 1136 uint64_t zip : 1; 1137 uint64_t reserved_8_8 : 1; 1138 uint64_t ipd : 1; 1139 uint64_t pko : 1; 1140 uint64_t tim : 1; 1141 uint64_t pow : 1; 1142 uint64_t usb : 1; 1143 uint64_t rad : 1; 1144 uint64_t reserved_15_15 : 1; 1145 uint64_t l2c : 1; 1146 uint64_t lmc0 : 1; 1147 uint64_t reserved_18_19 : 2; 1148 uint64_t pip : 1; 1149 uint64_t reserved_21_21 : 1; 1150 uint64_t asxpcs0 : 1; 1151 uint64_t asxpcs1 : 1; 1152 uint64_t reserved_24_24 : 1; 1153 uint64_t pem0 : 1; 1154 uint64_t pem1 : 1; 1155 uint64_t reserved_27_27 : 1; 1156 uint64_t agl : 1; 1157 uint64_t reserved_29_29 : 1; 1158 uint64_t iob : 1; 1159 uint64_t reserved_31_31 : 1; 1160 uint64_t srio0 : 1; 1161 uint64_t srio1 : 1; 1162 uint64_t reserved_34_39 : 6; 1163 uint64_t dfm : 1; 1164 uint64_t dpi : 1; 1165 uint64_t ptp : 1; 1166 uint64_t reserved_43_59 : 17; 1167 uint64_t srio2 : 1; 1168 uint64_t srio3 : 1; 1169 uint64_t reserved_62_63 : 2; 1170#endif 1171 } s; 1172 struct cvmx_ciu_block_int_cn61xx { 1173#ifdef __BIG_ENDIAN_BITFIELD 1174 uint64_t reserved_43_63 : 21; 1175 uint64_t ptp : 1; /**< PTP interrupt 1176 See CIU_INT_SUM1[PTP] */ 1177 uint64_t dpi : 1; /**< DPI interrupt 1178 See DPI_INT_REG */ 1179 uint64_t reserved_31_40 : 10; 1180 uint64_t iob : 1; /**< IOB interrupt 1181 See IOB_INT_SUM */ 1182 uint64_t reserved_29_29 : 1; 1183 uint64_t agl : 1; /**< AGL interrupt 1184 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 1185 uint64_t reserved_27_27 : 1; 1186 uint64_t pem1 : 1; /**< PEM1 interrupt 1187 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 1188 uint64_t pem0 : 1; /**< PEM0 interrupt 1189 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 1190 uint64_t reserved_24_24 : 1; 1191 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */ 1192 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 1193 uint64_t reserved_21_21 : 1; 1194 uint64_t pip : 1; /**< PIP interrupt 1195 See PIP_INT_REG */ 1196 uint64_t reserved_18_19 : 2; 1197 uint64_t lmc0 : 1; /**< LMC0 interrupt 1198 See LMC0_INT */ 1199 uint64_t l2c : 1; /**< L2C interrupt 1200 See L2C_INT_REG */ 1201 uint64_t reserved_15_15 : 1; 1202 uint64_t rad : 1; /**< RAD interrupt 1203 See RAD_REG_ERROR */ 1204 uint64_t usb : 1; /**< USB UCTL0 interrupt 1205 See UCTL0_INT_REG */ 1206 uint64_t pow : 1; /**< POW err interrupt 1207 See POW_ECC_ERR */ 1208 uint64_t tim : 1; /**< TIM interrupt 1209 See TIM_REG_ERROR */ 1210 uint64_t pko : 1; /**< PKO interrupt 1211 See PKO_REG_ERROR */ 1212 uint64_t ipd : 1; /**< IPD interrupt 1213 See IPD_INT_SUM */ 1214 uint64_t reserved_8_8 : 1; 1215 uint64_t zip : 1; /**< ZIP interrupt 1216 See ZIP_ERROR */ 1217 uint64_t dfa : 1; /**< DFA interrupt 1218 See DFA_ERROR */ 1219 uint64_t fpa : 1; /**< FPA interrupt 1220 See FPA_INT_SUM */ 1221 uint64_t key : 1; /**< KEY interrupt 1222 See KEY_INT_SUM */ 1223 uint64_t sli : 1; /**< SLI interrupt 1224 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 1225 uint64_t gmx1 : 1; /**< GMX1 interrupt 1226 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */ 1227 uint64_t gmx0 : 1; /**< GMX0 interrupt 1228 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 1229 uint64_t mio : 1; /**< MIO boot interrupt 1230 See MIO_BOOT_ERR */ 1231#else 1232 uint64_t mio : 1; 1233 uint64_t gmx0 : 1; 1234 uint64_t gmx1 : 1; 1235 uint64_t sli : 1; 1236 uint64_t key : 1; 1237 uint64_t fpa : 1; 1238 uint64_t dfa : 1; 1239 uint64_t zip : 1; 1240 uint64_t reserved_8_8 : 1; 1241 uint64_t ipd : 1; 1242 uint64_t pko : 1; 1243 uint64_t tim : 1; 1244 uint64_t pow : 1; 1245 uint64_t usb : 1; 1246 uint64_t rad : 1; 1247 uint64_t reserved_15_15 : 1; 1248 uint64_t l2c : 1; 1249 uint64_t lmc0 : 1; 1250 uint64_t reserved_18_19 : 2; 1251 uint64_t pip : 1; 1252 uint64_t reserved_21_21 : 1; 1253 uint64_t asxpcs0 : 1; 1254 uint64_t asxpcs1 : 1; 1255 uint64_t reserved_24_24 : 1; 1256 uint64_t pem0 : 1; 1257 uint64_t pem1 : 1; 1258 uint64_t reserved_27_27 : 1; 1259 uint64_t agl : 1; 1260 uint64_t reserved_29_29 : 1; 1261 uint64_t iob : 1; 1262 uint64_t reserved_31_40 : 10; 1263 uint64_t dpi : 1; 1264 uint64_t ptp : 1; 1265 uint64_t reserved_43_63 : 21; 1266#endif 1267 } cn61xx; 1268 struct cvmx_ciu_block_int_cn63xx { 1269#ifdef __BIG_ENDIAN_BITFIELD 1270 uint64_t reserved_43_63 : 21; 1271 uint64_t ptp : 1; /**< PTP interrupt 1272 See CIU_INT_SUM1[PTP] */ 1273 uint64_t dpi : 1; /**< DPI interrupt 1274 See DPI_INT_REG */ 1275 uint64_t dfm : 1; /**< DFM interrupt 1276 See DFM_FNT_STAT */ 1277 uint64_t reserved_34_39 : 6; 1278 uint64_t srio1 : 1; /**< SRIO1 interrupt 1279 See SRIO1_INT_REG, SRIO1_INT2_REG */ 1280 uint64_t srio0 : 1; /**< SRIO0 interrupt 1281 See SRIO0_INT_REG, SRIO0_INT2_REG */ 1282 uint64_t reserved_31_31 : 1; 1283 uint64_t iob : 1; /**< IOB interrupt 1284 See IOB_INT_SUM */ 1285 uint64_t reserved_29_29 : 1; 1286 uint64_t agl : 1; /**< AGL interrupt 1287 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 1288 uint64_t reserved_27_27 : 1; 1289 uint64_t pem1 : 1; /**< PEM1 interrupt 1290 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 1291 uint64_t pem0 : 1; /**< PEM0 interrupt 1292 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 1293 uint64_t reserved_23_24 : 2; 1294 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 1295 uint64_t reserved_21_21 : 1; 1296 uint64_t pip : 1; /**< PIP interrupt 1297 See PIP_INT_REG */ 1298 uint64_t reserved_18_19 : 2; 1299 uint64_t lmc0 : 1; /**< LMC0 interrupt 1300 See LMC0_INT */ 1301 uint64_t l2c : 1; /**< L2C interrupt 1302 See L2C_INT_REG */ 1303 uint64_t reserved_15_15 : 1; 1304 uint64_t rad : 1; /**< RAD interrupt 1305 See RAD_REG_ERROR */ 1306 uint64_t usb : 1; /**< USB UCTL0 interrupt 1307 See UCTL0_INT_REG */ 1308 uint64_t pow : 1; /**< POW err interrupt 1309 See POW_ECC_ERR */ 1310 uint64_t tim : 1; /**< TIM interrupt 1311 See TIM_REG_ERROR */ 1312 uint64_t pko : 1; /**< PKO interrupt 1313 See PKO_REG_ERROR */ 1314 uint64_t ipd : 1; /**< IPD interrupt 1315 See IPD_INT_SUM */ 1316 uint64_t reserved_8_8 : 1; 1317 uint64_t zip : 1; /**< ZIP interrupt 1318 See ZIP_ERROR */ 1319 uint64_t dfa : 1; /**< DFA interrupt 1320 See DFA_ERROR */ 1321 uint64_t fpa : 1; /**< FPA interrupt 1322 See FPA_INT_SUM */ 1323 uint64_t key : 1; /**< KEY interrupt 1324 See KEY_INT_SUM */ 1325 uint64_t sli : 1; /**< SLI interrupt 1326 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 1327 uint64_t reserved_2_2 : 1; 1328 uint64_t gmx0 : 1; /**< GMX0 interrupt 1329 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 1330 uint64_t mio : 1; /**< MIO boot interrupt 1331 See MIO_BOOT_ERR */ 1332#else 1333 uint64_t mio : 1; 1334 uint64_t gmx0 : 1; 1335 uint64_t reserved_2_2 : 1; 1336 uint64_t sli : 1; 1337 uint64_t key : 1; 1338 uint64_t fpa : 1; 1339 uint64_t dfa : 1; 1340 uint64_t zip : 1; 1341 uint64_t reserved_8_8 : 1; 1342 uint64_t ipd : 1; 1343 uint64_t pko : 1; 1344 uint64_t tim : 1; 1345 uint64_t pow : 1; 1346 uint64_t usb : 1; 1347 uint64_t rad : 1; 1348 uint64_t reserved_15_15 : 1; 1349 uint64_t l2c : 1; 1350 uint64_t lmc0 : 1; 1351 uint64_t reserved_18_19 : 2; 1352 uint64_t pip : 1; 1353 uint64_t reserved_21_21 : 1; 1354 uint64_t asxpcs0 : 1; 1355 uint64_t reserved_23_24 : 2; 1356 uint64_t pem0 : 1; 1357 uint64_t pem1 : 1; 1358 uint64_t reserved_27_27 : 1; 1359 uint64_t agl : 1; 1360 uint64_t reserved_29_29 : 1; 1361 uint64_t iob : 1; 1362 uint64_t reserved_31_31 : 1; 1363 uint64_t srio0 : 1; 1364 uint64_t srio1 : 1; 1365 uint64_t reserved_34_39 : 6; 1366 uint64_t dfm : 1; 1367 uint64_t dpi : 1; 1368 uint64_t ptp : 1; 1369 uint64_t reserved_43_63 : 21; 1370#endif 1371 } cn63xx; 1372 struct cvmx_ciu_block_int_cn63xx cn63xxp1; 1373 struct cvmx_ciu_block_int_cn66xx { 1374#ifdef __BIG_ENDIAN_BITFIELD 1375 uint64_t reserved_62_63 : 2; 1376 uint64_t srio3 : 1; /**< SRIO3 interrupt 1377 See SRIO3_INT_REG, SRIO3_INT2_REG */ 1378 uint64_t srio2 : 1; /**< SRIO2 interrupt 1379 See SRIO2_INT_REG, SRIO2_INT2_REG */ 1380 uint64_t reserved_43_59 : 17; 1381 uint64_t ptp : 1; /**< PTP interrupt 1382 See CIU_INT_SUM1[PTP] */ 1383 uint64_t dpi : 1; /**< DPI interrupt 1384 See DPI_INT_REG */ 1385 uint64_t dfm : 1; /**< DFM interrupt 1386 See DFM_FNT_STAT */ 1387 uint64_t reserved_33_39 : 7; 1388 uint64_t srio0 : 1; /**< SRIO0 interrupt 1389 See SRIO0_INT_REG, SRIO0_INT2_REG */ 1390 uint64_t reserved_31_31 : 1; 1391 uint64_t iob : 1; /**< IOB interrupt 1392 See IOB_INT_SUM */ 1393 uint64_t reserved_29_29 : 1; 1394 uint64_t agl : 1; /**< AGL interrupt 1395 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 1396 uint64_t reserved_27_27 : 1; 1397 uint64_t pem1 : 1; /**< PEM1 interrupt 1398 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 1399 uint64_t pem0 : 1; /**< PEM0 interrupt 1400 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 1401 uint64_t reserved_24_24 : 1; 1402 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */ 1403 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 1404 uint64_t reserved_21_21 : 1; 1405 uint64_t pip : 1; /**< PIP interrupt 1406 See PIP_INT_REG */ 1407 uint64_t reserved_18_19 : 2; 1408 uint64_t lmc0 : 1; /**< LMC0 interrupt 1409 See LMC0_INT */ 1410 uint64_t l2c : 1; /**< L2C interrupt 1411 See L2C_INT_REG */ 1412 uint64_t reserved_15_15 : 1; 1413 uint64_t rad : 1; /**< RAD interrupt 1414 See RAD_REG_ERROR */ 1415 uint64_t usb : 1; /**< USB UCTL0 interrupt 1416 See UCTL0_INT_REG */ 1417 uint64_t pow : 1; /**< POW err interrupt 1418 See POW_ECC_ERR */ 1419 uint64_t tim : 1; /**< TIM interrupt 1420 See TIM_REG_ERROR */ 1421 uint64_t pko : 1; /**< PKO interrupt 1422 See PKO_REG_ERROR */ 1423 uint64_t ipd : 1; /**< IPD interrupt 1424 See IPD_INT_SUM */ 1425 uint64_t reserved_8_8 : 1; 1426 uint64_t zip : 1; /**< ZIP interrupt 1427 See ZIP_ERROR */ 1428 uint64_t dfa : 1; /**< DFA interrupt 1429 See DFA_ERROR */ 1430 uint64_t fpa : 1; /**< FPA interrupt 1431 See FPA_INT_SUM */ 1432 uint64_t key : 1; /**< KEY interrupt 1433 See KEY_INT_SUM */ 1434 uint64_t sli : 1; /**< SLI interrupt 1435 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 1436 uint64_t gmx1 : 1; /**< GMX1 interrupt 1437 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */ 1438 uint64_t gmx0 : 1; /**< GMX0 interrupt 1439 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 1440 uint64_t mio : 1; /**< MIO boot interrupt 1441 See MIO_BOOT_ERR */ 1442#else 1443 uint64_t mio : 1; 1444 uint64_t gmx0 : 1; 1445 uint64_t gmx1 : 1; 1446 uint64_t sli : 1; 1447 uint64_t key : 1; 1448 uint64_t fpa : 1; 1449 uint64_t dfa : 1; 1450 uint64_t zip : 1; 1451 uint64_t reserved_8_8 : 1; 1452 uint64_t ipd : 1; 1453 uint64_t pko : 1; 1454 uint64_t tim : 1; 1455 uint64_t pow : 1; 1456 uint64_t usb : 1; 1457 uint64_t rad : 1; 1458 uint64_t reserved_15_15 : 1; 1459 uint64_t l2c : 1; 1460 uint64_t lmc0 : 1; 1461 uint64_t reserved_18_19 : 2; 1462 uint64_t pip : 1; 1463 uint64_t reserved_21_21 : 1; 1464 uint64_t asxpcs0 : 1; 1465 uint64_t asxpcs1 : 1; 1466 uint64_t reserved_24_24 : 1; 1467 uint64_t pem0 : 1; 1468 uint64_t pem1 : 1; 1469 uint64_t reserved_27_27 : 1; 1470 uint64_t agl : 1; 1471 uint64_t reserved_29_29 : 1; 1472 uint64_t iob : 1; 1473 uint64_t reserved_31_31 : 1; 1474 uint64_t srio0 : 1; 1475 uint64_t reserved_33_39 : 7; 1476 uint64_t dfm : 1; 1477 uint64_t dpi : 1; 1478 uint64_t ptp : 1; 1479 uint64_t reserved_43_59 : 17; 1480 uint64_t srio2 : 1; 1481 uint64_t srio3 : 1; 1482 uint64_t reserved_62_63 : 2; 1483#endif 1484 } cn66xx; 1485 struct cvmx_ciu_block_int_cnf71xx { 1486#ifdef __BIG_ENDIAN_BITFIELD 1487 uint64_t reserved_43_63 : 21; 1488 uint64_t ptp : 1; /**< PTP interrupt 1489 See CIU_INT_SUM1[PTP] */ 1490 uint64_t dpi : 1; /**< DPI interrupt 1491 See DPI_INT_REG */ 1492 uint64_t reserved_31_40 : 10; 1493 uint64_t iob : 1; /**< IOB interrupt 1494 See IOB_INT_SUM */ 1495 uint64_t reserved_27_29 : 3; 1496 uint64_t pem1 : 1; /**< PEM1 interrupt 1497 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 1498 uint64_t pem0 : 1; /**< PEM0 interrupt 1499 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 1500 uint64_t reserved_23_24 : 2; 1501 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 1502 uint64_t reserved_21_21 : 1; 1503 uint64_t pip : 1; /**< PIP interrupt 1504 See PIP_INT_REG */ 1505 uint64_t reserved_18_19 : 2; 1506 uint64_t lmc0 : 1; /**< LMC0 interrupt 1507 See LMC0_INT */ 1508 uint64_t l2c : 1; /**< L2C interrupt 1509 See L2C_INT_REG */ 1510 uint64_t reserved_15_15 : 1; 1511 uint64_t rad : 1; /**< RAD interrupt 1512 See RAD_REG_ERROR */ 1513 uint64_t usb : 1; /**< USB UCTL0 interrupt 1514 See UCTL0_INT_REG */ 1515 uint64_t pow : 1; /**< POW err interrupt 1516 See POW_ECC_ERR */ 1517 uint64_t tim : 1; /**< TIM interrupt 1518 See TIM_REG_ERROR */ 1519 uint64_t pko : 1; /**< PKO interrupt 1520 See PKO_REG_ERROR */ 1521 uint64_t ipd : 1; /**< IPD interrupt 1522 See IPD_INT_SUM */ 1523 uint64_t reserved_6_8 : 3; 1524 uint64_t fpa : 1; /**< FPA interrupt 1525 See FPA_INT_SUM */ 1526 uint64_t key : 1; /**< KEY interrupt 1527 See KEY_INT_SUM */ 1528 uint64_t sli : 1; /**< SLI interrupt 1529 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 1530 uint64_t reserved_2_2 : 1; 1531 uint64_t gmx0 : 1; /**< GMX0 interrupt 1532 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 1533 uint64_t mio : 1; /**< MIO boot interrupt 1534 See MIO_BOOT_ERR */ 1535#else 1536 uint64_t mio : 1; 1537 uint64_t gmx0 : 1; 1538 uint64_t reserved_2_2 : 1; 1539 uint64_t sli : 1; 1540 uint64_t key : 1; 1541 uint64_t fpa : 1; 1542 uint64_t reserved_6_8 : 3; 1543 uint64_t ipd : 1; 1544 uint64_t pko : 1; 1545 uint64_t tim : 1; 1546 uint64_t pow : 1; 1547 uint64_t usb : 1; 1548 uint64_t rad : 1; 1549 uint64_t reserved_15_15 : 1; 1550 uint64_t l2c : 1; 1551 uint64_t lmc0 : 1; 1552 uint64_t reserved_18_19 : 2; 1553 uint64_t pip : 1; 1554 uint64_t reserved_21_21 : 1; 1555 uint64_t asxpcs0 : 1; 1556 uint64_t reserved_23_24 : 2; 1557 uint64_t pem0 : 1; 1558 uint64_t pem1 : 1; 1559 uint64_t reserved_27_29 : 3; 1560 uint64_t iob : 1; 1561 uint64_t reserved_31_40 : 10; 1562 uint64_t dpi : 1; 1563 uint64_t ptp : 1; 1564 uint64_t reserved_43_63 : 21; 1565#endif 1566 } cnf71xx; 1567}; 1568typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t; 1569 1570/** 1571 * cvmx_ciu_dint 1572 */ 1573union cvmx_ciu_dint { 1574 uint64_t u64; 1575 struct cvmx_ciu_dint_s { 1576#ifdef __BIG_ENDIAN_BITFIELD 1577 uint64_t reserved_32_63 : 32; 1578 uint64_t dint : 32; /**< Send DINT pulse to PP vector */ 1579#else 1580 uint64_t dint : 32; 1581 uint64_t reserved_32_63 : 32; 1582#endif 1583 } s; 1584 struct cvmx_ciu_dint_cn30xx { 1585#ifdef __BIG_ENDIAN_BITFIELD 1586 uint64_t reserved_1_63 : 63; 1587 uint64_t dint : 1; /**< Send DINT pulse to PP vector */ 1588#else 1589 uint64_t dint : 1; 1590 uint64_t reserved_1_63 : 63; 1591#endif 1592 } cn30xx; 1593 struct cvmx_ciu_dint_cn31xx { 1594#ifdef __BIG_ENDIAN_BITFIELD 1595 uint64_t reserved_2_63 : 62; 1596 uint64_t dint : 2; /**< Send DINT pulse to PP vector */ 1597#else 1598 uint64_t dint : 2; 1599 uint64_t reserved_2_63 : 62; 1600#endif 1601 } cn31xx; 1602 struct cvmx_ciu_dint_cn38xx { 1603#ifdef __BIG_ENDIAN_BITFIELD 1604 uint64_t reserved_16_63 : 48; 1605 uint64_t dint : 16; /**< Send DINT pulse to PP vector */ 1606#else 1607 uint64_t dint : 16; 1608 uint64_t reserved_16_63 : 48; 1609#endif 1610 } cn38xx; 1611 struct cvmx_ciu_dint_cn38xx cn38xxp2; 1612 struct cvmx_ciu_dint_cn31xx cn50xx; 1613 struct cvmx_ciu_dint_cn52xx { 1614#ifdef __BIG_ENDIAN_BITFIELD 1615 uint64_t reserved_4_63 : 60; 1616 uint64_t dint : 4; /**< Send DINT pulse to PP vector */ 1617#else 1618 uint64_t dint : 4; 1619 uint64_t reserved_4_63 : 60; 1620#endif 1621 } cn52xx; 1622 struct cvmx_ciu_dint_cn52xx cn52xxp1; 1623 struct cvmx_ciu_dint_cn56xx { 1624#ifdef __BIG_ENDIAN_BITFIELD 1625 uint64_t reserved_12_63 : 52; 1626 uint64_t dint : 12; /**< Send DINT pulse to PP vector */ 1627#else 1628 uint64_t dint : 12; 1629 uint64_t reserved_12_63 : 52; 1630#endif 1631 } cn56xx; 1632 struct cvmx_ciu_dint_cn56xx cn56xxp1; 1633 struct cvmx_ciu_dint_cn38xx cn58xx; 1634 struct cvmx_ciu_dint_cn38xx cn58xxp1; 1635 struct cvmx_ciu_dint_cn52xx cn61xx; 1636 struct cvmx_ciu_dint_cn63xx { 1637#ifdef __BIG_ENDIAN_BITFIELD 1638 uint64_t reserved_6_63 : 58; 1639 uint64_t dint : 6; /**< Send DINT pulse to PP vector */ 1640#else 1641 uint64_t dint : 6; 1642 uint64_t reserved_6_63 : 58; 1643#endif 1644 } cn63xx; 1645 struct cvmx_ciu_dint_cn63xx cn63xxp1; 1646 struct cvmx_ciu_dint_cn66xx { 1647#ifdef __BIG_ENDIAN_BITFIELD 1648 uint64_t reserved_10_63 : 54; 1649 uint64_t dint : 10; /**< Send DINT pulse to PP vector */ 1650#else 1651 uint64_t dint : 10; 1652 uint64_t reserved_10_63 : 54; 1653#endif 1654 } cn66xx; 1655 struct cvmx_ciu_dint_s cn68xx; 1656 struct cvmx_ciu_dint_s cn68xxp1; 1657 struct cvmx_ciu_dint_cn52xx cnf71xx; 1658}; 1659typedef union cvmx_ciu_dint cvmx_ciu_dint_t; 1660 1661/** 1662 * cvmx_ciu_en2_io#_int 1663 * 1664 * Notes: 1665 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 1666 * 1667 */ 1668union cvmx_ciu_en2_iox_int { 1669 uint64_t u64; 1670 struct cvmx_ciu_en2_iox_int_s { 1671#ifdef __BIG_ENDIAN_BITFIELD 1672 uint64_t reserved_15_63 : 49; 1673 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */ 1674 uint64_t eoi : 1; /**< EOI rsl interrupt enable */ 1675 uint64_t reserved_10_11 : 2; 1676 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1677 uint64_t reserved_0_3 : 4; 1678#else 1679 uint64_t reserved_0_3 : 4; 1680 uint64_t timer : 6; 1681 uint64_t reserved_10_11 : 2; 1682 uint64_t eoi : 1; 1683 uint64_t endor : 2; 1684 uint64_t reserved_15_63 : 49; 1685#endif 1686 } s; 1687 struct cvmx_ciu_en2_iox_int_cn61xx { 1688#ifdef __BIG_ENDIAN_BITFIELD 1689 uint64_t reserved_10_63 : 54; 1690 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1691 uint64_t reserved_0_3 : 4; 1692#else 1693 uint64_t reserved_0_3 : 4; 1694 uint64_t timer : 6; 1695 uint64_t reserved_10_63 : 54; 1696#endif 1697 } cn61xx; 1698 struct cvmx_ciu_en2_iox_int_cn61xx cn66xx; 1699 struct cvmx_ciu_en2_iox_int_s cnf71xx; 1700}; 1701typedef union cvmx_ciu_en2_iox_int cvmx_ciu_en2_iox_int_t; 1702 1703/** 1704 * cvmx_ciu_en2_io#_int_w1c 1705 * 1706 * Notes: 1707 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 1708 * CIU_EN2_PP(IO)X_IPx(INT) value. 1709 */ 1710union cvmx_ciu_en2_iox_int_w1c { 1711 uint64_t u64; 1712 struct cvmx_ciu_en2_iox_int_w1c_s { 1713#ifdef __BIG_ENDIAN_BITFIELD 1714 uint64_t reserved_15_63 : 49; 1715 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */ 1716 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */ 1717 uint64_t reserved_10_11 : 2; 1718 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1719 uint64_t reserved_0_3 : 4; 1720#else 1721 uint64_t reserved_0_3 : 4; 1722 uint64_t timer : 6; 1723 uint64_t reserved_10_11 : 2; 1724 uint64_t eoi : 1; 1725 uint64_t endor : 2; 1726 uint64_t reserved_15_63 : 49; 1727#endif 1728 } s; 1729 struct cvmx_ciu_en2_iox_int_w1c_cn61xx { 1730#ifdef __BIG_ENDIAN_BITFIELD 1731 uint64_t reserved_10_63 : 54; 1732 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1733 uint64_t reserved_0_3 : 4; 1734#else 1735 uint64_t reserved_0_3 : 4; 1736 uint64_t timer : 6; 1737 uint64_t reserved_10_63 : 54; 1738#endif 1739 } cn61xx; 1740 struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx; 1741 struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx; 1742}; 1743typedef union cvmx_ciu_en2_iox_int_w1c cvmx_ciu_en2_iox_int_w1c_t; 1744 1745/** 1746 * cvmx_ciu_en2_io#_int_w1s 1747 * 1748 * Notes: 1749 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 1750 * CIU_EN2_PP(IO)X_IPx(INT) value. 1751 */ 1752union cvmx_ciu_en2_iox_int_w1s { 1753 uint64_t u64; 1754 struct cvmx_ciu_en2_iox_int_w1s_s { 1755#ifdef __BIG_ENDIAN_BITFIELD 1756 uint64_t reserved_15_63 : 49; 1757 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */ 1758 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */ 1759 uint64_t reserved_10_11 : 2; 1760 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 1761 uint64_t reserved_0_3 : 4; 1762#else 1763 uint64_t reserved_0_3 : 4; 1764 uint64_t timer : 6; 1765 uint64_t reserved_10_11 : 2; 1766 uint64_t eoi : 1; 1767 uint64_t endor : 2; 1768 uint64_t reserved_15_63 : 49; 1769#endif 1770 } s; 1771 struct cvmx_ciu_en2_iox_int_w1s_cn61xx { 1772#ifdef __BIG_ENDIAN_BITFIELD 1773 uint64_t reserved_10_63 : 54; 1774 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 1775 uint64_t reserved_0_3 : 4; 1776#else 1777 uint64_t reserved_0_3 : 4; 1778 uint64_t timer : 6; 1779 uint64_t reserved_10_63 : 54; 1780#endif 1781 } cn61xx; 1782 struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx; 1783 struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx; 1784}; 1785typedef union cvmx_ciu_en2_iox_int_w1s cvmx_ciu_en2_iox_int_w1s_t; 1786 1787/** 1788 * cvmx_ciu_en2_pp#_ip2 1789 * 1790 * Notes: 1791 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 1792 * 1793 */ 1794union cvmx_ciu_en2_ppx_ip2 { 1795 uint64_t u64; 1796 struct cvmx_ciu_en2_ppx_ip2_s { 1797#ifdef __BIG_ENDIAN_BITFIELD 1798 uint64_t reserved_15_63 : 49; 1799 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */ 1800 uint64_t eoi : 1; /**< EOI rsl interrupt enable */ 1801 uint64_t reserved_10_11 : 2; 1802 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1803 uint64_t reserved_0_3 : 4; 1804#else 1805 uint64_t reserved_0_3 : 4; 1806 uint64_t timer : 6; 1807 uint64_t reserved_10_11 : 2; 1808 uint64_t eoi : 1; 1809 uint64_t endor : 2; 1810 uint64_t reserved_15_63 : 49; 1811#endif 1812 } s; 1813 struct cvmx_ciu_en2_ppx_ip2_cn61xx { 1814#ifdef __BIG_ENDIAN_BITFIELD 1815 uint64_t reserved_10_63 : 54; 1816 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1817 uint64_t reserved_0_3 : 4; 1818#else 1819 uint64_t reserved_0_3 : 4; 1820 uint64_t timer : 6; 1821 uint64_t reserved_10_63 : 54; 1822#endif 1823 } cn61xx; 1824 struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx; 1825 struct cvmx_ciu_en2_ppx_ip2_s cnf71xx; 1826}; 1827typedef union cvmx_ciu_en2_ppx_ip2 cvmx_ciu_en2_ppx_ip2_t; 1828 1829/** 1830 * cvmx_ciu_en2_pp#_ip2_w1c 1831 * 1832 * Notes: 1833 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 1834 * CIU_EN2_PP(IO)X_IPx(INT) value. 1835 */ 1836union cvmx_ciu_en2_ppx_ip2_w1c { 1837 uint64_t u64; 1838 struct cvmx_ciu_en2_ppx_ip2_w1c_s { 1839#ifdef __BIG_ENDIAN_BITFIELD 1840 uint64_t reserved_15_63 : 49; 1841 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */ 1842 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */ 1843 uint64_t reserved_10_11 : 2; 1844 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1845 uint64_t reserved_0_3 : 4; 1846#else 1847 uint64_t reserved_0_3 : 4; 1848 uint64_t timer : 6; 1849 uint64_t reserved_10_11 : 2; 1850 uint64_t eoi : 1; 1851 uint64_t endor : 2; 1852 uint64_t reserved_15_63 : 49; 1853#endif 1854 } s; 1855 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx { 1856#ifdef __BIG_ENDIAN_BITFIELD 1857 uint64_t reserved_10_63 : 54; 1858 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1859 uint64_t reserved_0_3 : 4; 1860#else 1861 uint64_t reserved_0_3 : 4; 1862 uint64_t timer : 6; 1863 uint64_t reserved_10_63 : 54; 1864#endif 1865 } cn61xx; 1866 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx; 1867 struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx; 1868}; 1869typedef union cvmx_ciu_en2_ppx_ip2_w1c cvmx_ciu_en2_ppx_ip2_w1c_t; 1870 1871/** 1872 * cvmx_ciu_en2_pp#_ip2_w1s 1873 * 1874 * Notes: 1875 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 1876 * CIU_EN2_PP(IO)X_IPx(INT) value. 1877 */ 1878union cvmx_ciu_en2_ppx_ip2_w1s { 1879 uint64_t u64; 1880 struct cvmx_ciu_en2_ppx_ip2_w1s_s { 1881#ifdef __BIG_ENDIAN_BITFIELD 1882 uint64_t reserved_15_63 : 49; 1883 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */ 1884 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */ 1885 uint64_t reserved_10_11 : 2; 1886 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 1887 uint64_t reserved_0_3 : 4; 1888#else 1889 uint64_t reserved_0_3 : 4; 1890 uint64_t timer : 6; 1891 uint64_t reserved_10_11 : 2; 1892 uint64_t eoi : 1; 1893 uint64_t endor : 2; 1894 uint64_t reserved_15_63 : 49; 1895#endif 1896 } s; 1897 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx { 1898#ifdef __BIG_ENDIAN_BITFIELD 1899 uint64_t reserved_10_63 : 54; 1900 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 1901 uint64_t reserved_0_3 : 4; 1902#else 1903 uint64_t reserved_0_3 : 4; 1904 uint64_t timer : 6; 1905 uint64_t reserved_10_63 : 54; 1906#endif 1907 } cn61xx; 1908 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx; 1909 struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx; 1910}; 1911typedef union cvmx_ciu_en2_ppx_ip2_w1s cvmx_ciu_en2_ppx_ip2_w1s_t; 1912 1913/** 1914 * cvmx_ciu_en2_pp#_ip3 1915 * 1916 * Notes: 1917 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 1918 * 1919 */ 1920union cvmx_ciu_en2_ppx_ip3 { 1921 uint64_t u64; 1922 struct cvmx_ciu_en2_ppx_ip3_s { 1923#ifdef __BIG_ENDIAN_BITFIELD 1924 uint64_t reserved_15_63 : 49; 1925 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */ 1926 uint64_t eoi : 1; /**< EOI rsl interrupt enable */ 1927 uint64_t reserved_10_11 : 2; 1928 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1929 uint64_t reserved_0_3 : 4; 1930#else 1931 uint64_t reserved_0_3 : 4; 1932 uint64_t timer : 6; 1933 uint64_t reserved_10_11 : 2; 1934 uint64_t eoi : 1; 1935 uint64_t endor : 2; 1936 uint64_t reserved_15_63 : 49; 1937#endif 1938 } s; 1939 struct cvmx_ciu_en2_ppx_ip3_cn61xx { 1940#ifdef __BIG_ENDIAN_BITFIELD 1941 uint64_t reserved_10_63 : 54; 1942 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 1943 uint64_t reserved_0_3 : 4; 1944#else 1945 uint64_t reserved_0_3 : 4; 1946 uint64_t timer : 6; 1947 uint64_t reserved_10_63 : 54; 1948#endif 1949 } cn61xx; 1950 struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx; 1951 struct cvmx_ciu_en2_ppx_ip3_s cnf71xx; 1952}; 1953typedef union cvmx_ciu_en2_ppx_ip3 cvmx_ciu_en2_ppx_ip3_t; 1954 1955/** 1956 * cvmx_ciu_en2_pp#_ip3_w1c 1957 * 1958 * Notes: 1959 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 1960 * CIU_EN2_PP(IO)X_IPx(INT) value. 1961 */ 1962union cvmx_ciu_en2_ppx_ip3_w1c { 1963 uint64_t u64; 1964 struct cvmx_ciu_en2_ppx_ip3_w1c_s { 1965#ifdef __BIG_ENDIAN_BITFIELD 1966 uint64_t reserved_15_63 : 49; 1967 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */ 1968 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */ 1969 uint64_t reserved_10_11 : 2; 1970 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1971 uint64_t reserved_0_3 : 4; 1972#else 1973 uint64_t reserved_0_3 : 4; 1974 uint64_t timer : 6; 1975 uint64_t reserved_10_11 : 2; 1976 uint64_t eoi : 1; 1977 uint64_t endor : 2; 1978 uint64_t reserved_15_63 : 49; 1979#endif 1980 } s; 1981 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx { 1982#ifdef __BIG_ENDIAN_BITFIELD 1983 uint64_t reserved_10_63 : 54; 1984 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 1985 uint64_t reserved_0_3 : 4; 1986#else 1987 uint64_t reserved_0_3 : 4; 1988 uint64_t timer : 6; 1989 uint64_t reserved_10_63 : 54; 1990#endif 1991 } cn61xx; 1992 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx; 1993 struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx; 1994}; 1995typedef union cvmx_ciu_en2_ppx_ip3_w1c cvmx_ciu_en2_ppx_ip3_w1c_t; 1996 1997/** 1998 * cvmx_ciu_en2_pp#_ip3_w1s 1999 * 2000 * Notes: 2001 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 2002 * CIU_EN2_PP(IO)X_IPx(INT) value. 2003 */ 2004union cvmx_ciu_en2_ppx_ip3_w1s { 2005 uint64_t u64; 2006 struct cvmx_ciu_en2_ppx_ip3_w1s_s { 2007#ifdef __BIG_ENDIAN_BITFIELD 2008 uint64_t reserved_15_63 : 49; 2009 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */ 2010 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */ 2011 uint64_t reserved_10_11 : 2; 2012 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 2013 uint64_t reserved_0_3 : 4; 2014#else 2015 uint64_t reserved_0_3 : 4; 2016 uint64_t timer : 6; 2017 uint64_t reserved_10_11 : 2; 2018 uint64_t eoi : 1; 2019 uint64_t endor : 2; 2020 uint64_t reserved_15_63 : 49; 2021#endif 2022 } s; 2023 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx { 2024#ifdef __BIG_ENDIAN_BITFIELD 2025 uint64_t reserved_10_63 : 54; 2026 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 2027 uint64_t reserved_0_3 : 4; 2028#else 2029 uint64_t reserved_0_3 : 4; 2030 uint64_t timer : 6; 2031 uint64_t reserved_10_63 : 54; 2032#endif 2033 } cn61xx; 2034 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx; 2035 struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx; 2036}; 2037typedef union cvmx_ciu_en2_ppx_ip3_w1s cvmx_ciu_en2_ppx_ip3_w1s_t; 2038 2039/** 2040 * cvmx_ciu_en2_pp#_ip4 2041 * 2042 * Notes: 2043 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 2044 * 2045 */ 2046union cvmx_ciu_en2_ppx_ip4 { 2047 uint64_t u64; 2048 struct cvmx_ciu_en2_ppx_ip4_s { 2049#ifdef __BIG_ENDIAN_BITFIELD 2050 uint64_t reserved_15_63 : 49; 2051 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */ 2052 uint64_t eoi : 1; /**< EOI rsl interrupt enable */ 2053 uint64_t reserved_10_11 : 2; 2054 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 2055 uint64_t reserved_0_3 : 4; 2056#else 2057 uint64_t reserved_0_3 : 4; 2058 uint64_t timer : 6; 2059 uint64_t reserved_10_11 : 2; 2060 uint64_t eoi : 1; 2061 uint64_t endor : 2; 2062 uint64_t reserved_15_63 : 49; 2063#endif 2064 } s; 2065 struct cvmx_ciu_en2_ppx_ip4_cn61xx { 2066#ifdef __BIG_ENDIAN_BITFIELD 2067 uint64_t reserved_10_63 : 54; 2068 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */ 2069 uint64_t reserved_0_3 : 4; 2070#else 2071 uint64_t reserved_0_3 : 4; 2072 uint64_t timer : 6; 2073 uint64_t reserved_10_63 : 54; 2074#endif 2075 } cn61xx; 2076 struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx; 2077 struct cvmx_ciu_en2_ppx_ip4_s cnf71xx; 2078}; 2079typedef union cvmx_ciu_en2_ppx_ip4 cvmx_ciu_en2_ppx_ip4_t; 2080 2081/** 2082 * cvmx_ciu_en2_pp#_ip4_w1c 2083 * 2084 * Notes: 2085 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 2086 * CIU_EN2_PP(IO)X_IPx(INT) value. 2087 */ 2088union cvmx_ciu_en2_ppx_ip4_w1c { 2089 uint64_t u64; 2090 struct cvmx_ciu_en2_ppx_ip4_w1c_s { 2091#ifdef __BIG_ENDIAN_BITFIELD 2092 uint64_t reserved_15_63 : 49; 2093 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */ 2094 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */ 2095 uint64_t reserved_10_11 : 2; 2096 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 2097 uint64_t reserved_0_3 : 4; 2098#else 2099 uint64_t reserved_0_3 : 4; 2100 uint64_t timer : 6; 2101 uint64_t reserved_10_11 : 2; 2102 uint64_t eoi : 1; 2103 uint64_t endor : 2; 2104 uint64_t reserved_15_63 : 49; 2105#endif 2106 } s; 2107 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx { 2108#ifdef __BIG_ENDIAN_BITFIELD 2109 uint64_t reserved_10_63 : 54; 2110 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */ 2111 uint64_t reserved_0_3 : 4; 2112#else 2113 uint64_t reserved_0_3 : 4; 2114 uint64_t timer : 6; 2115 uint64_t reserved_10_63 : 54; 2116#endif 2117 } cn61xx; 2118 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx; 2119 struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx; 2120}; 2121typedef union cvmx_ciu_en2_ppx_ip4_w1c cvmx_ciu_en2_ppx_ip4_w1c_t; 2122 2123/** 2124 * cvmx_ciu_en2_pp#_ip4_w1s 2125 * 2126 * Notes: 2127 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding 2128 * CIU_EN2_PP(IO)X_IPx(INT) value. 2129 */ 2130union cvmx_ciu_en2_ppx_ip4_w1s { 2131 uint64_t u64; 2132 struct cvmx_ciu_en2_ppx_ip4_w1s_s { 2133#ifdef __BIG_ENDIAN_BITFIELD 2134 uint64_t reserved_15_63 : 49; 2135 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */ 2136 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */ 2137 uint64_t reserved_10_11 : 2; 2138 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 2139 uint64_t reserved_0_3 : 4; 2140#else 2141 uint64_t reserved_0_3 : 4; 2142 uint64_t timer : 6; 2143 uint64_t reserved_10_11 : 2; 2144 uint64_t eoi : 1; 2145 uint64_t endor : 2; 2146 uint64_t reserved_15_63 : 49; 2147#endif 2148 } s; 2149 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx { 2150#ifdef __BIG_ENDIAN_BITFIELD 2151 uint64_t reserved_10_63 : 54; 2152 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */ 2153 uint64_t reserved_0_3 : 4; 2154#else 2155 uint64_t reserved_0_3 : 4; 2156 uint64_t timer : 6; 2157 uint64_t reserved_10_63 : 54; 2158#endif 2159 } cn61xx; 2160 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx; 2161 struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx; 2162}; 2163typedef union cvmx_ciu_en2_ppx_ip4_w1s cvmx_ciu_en2_ppx_ip4_w1s_t; 2164 2165/** 2166 * cvmx_ciu_fuse 2167 */ 2168union cvmx_ciu_fuse { 2169 uint64_t u64; 2170 struct cvmx_ciu_fuse_s { 2171#ifdef __BIG_ENDIAN_BITFIELD 2172 uint64_t reserved_32_63 : 32; 2173 uint64_t fuse : 32; /**< Physical PP is present */ 2174#else 2175 uint64_t fuse : 32; 2176 uint64_t reserved_32_63 : 32; 2177#endif 2178 } s; 2179 struct cvmx_ciu_fuse_cn30xx { 2180#ifdef __BIG_ENDIAN_BITFIELD 2181 uint64_t reserved_1_63 : 63; 2182 uint64_t fuse : 1; /**< Physical PP is present */ 2183#else 2184 uint64_t fuse : 1; 2185 uint64_t reserved_1_63 : 63; 2186#endif 2187 } cn30xx; 2188 struct cvmx_ciu_fuse_cn31xx { 2189#ifdef __BIG_ENDIAN_BITFIELD 2190 uint64_t reserved_2_63 : 62; 2191 uint64_t fuse : 2; /**< Physical PP is present */ 2192#else 2193 uint64_t fuse : 2; 2194 uint64_t reserved_2_63 : 62; 2195#endif 2196 } cn31xx; 2197 struct cvmx_ciu_fuse_cn38xx { 2198#ifdef __BIG_ENDIAN_BITFIELD 2199 uint64_t reserved_16_63 : 48; 2200 uint64_t fuse : 16; /**< Physical PP is present */ 2201#else 2202 uint64_t fuse : 16; 2203 uint64_t reserved_16_63 : 48; 2204#endif 2205 } cn38xx; 2206 struct cvmx_ciu_fuse_cn38xx cn38xxp2; 2207 struct cvmx_ciu_fuse_cn31xx cn50xx; 2208 struct cvmx_ciu_fuse_cn52xx { 2209#ifdef __BIG_ENDIAN_BITFIELD 2210 uint64_t reserved_4_63 : 60; 2211 uint64_t fuse : 4; /**< Physical PP is present */ 2212#else 2213 uint64_t fuse : 4; 2214 uint64_t reserved_4_63 : 60; 2215#endif 2216 } cn52xx; 2217 struct cvmx_ciu_fuse_cn52xx cn52xxp1; 2218 struct cvmx_ciu_fuse_cn56xx { 2219#ifdef __BIG_ENDIAN_BITFIELD 2220 uint64_t reserved_12_63 : 52; 2221 uint64_t fuse : 12; /**< Physical PP is present */ 2222#else 2223 uint64_t fuse : 12; 2224 uint64_t reserved_12_63 : 52; 2225#endif 2226 } cn56xx; 2227 struct cvmx_ciu_fuse_cn56xx cn56xxp1; 2228 struct cvmx_ciu_fuse_cn38xx cn58xx; 2229 struct cvmx_ciu_fuse_cn38xx cn58xxp1; 2230 struct cvmx_ciu_fuse_cn52xx cn61xx; 2231 struct cvmx_ciu_fuse_cn63xx { 2232#ifdef __BIG_ENDIAN_BITFIELD 2233 uint64_t reserved_6_63 : 58; 2234 uint64_t fuse : 6; /**< Physical PP is present */ 2235#else 2236 uint64_t fuse : 6; 2237 uint64_t reserved_6_63 : 58; 2238#endif 2239 } cn63xx; 2240 struct cvmx_ciu_fuse_cn63xx cn63xxp1; 2241 struct cvmx_ciu_fuse_cn66xx { 2242#ifdef __BIG_ENDIAN_BITFIELD 2243 uint64_t reserved_10_63 : 54; 2244 uint64_t fuse : 10; /**< Physical PP is present */ 2245#else 2246 uint64_t fuse : 10; 2247 uint64_t reserved_10_63 : 54; 2248#endif 2249 } cn66xx; 2250 struct cvmx_ciu_fuse_s cn68xx; 2251 struct cvmx_ciu_fuse_s cn68xxp1; 2252 struct cvmx_ciu_fuse_cn52xx cnf71xx; 2253}; 2254typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t; 2255 2256/** 2257 * cvmx_ciu_gstop 2258 */ 2259union cvmx_ciu_gstop { 2260 uint64_t u64; 2261 struct cvmx_ciu_gstop_s { 2262#ifdef __BIG_ENDIAN_BITFIELD 2263 uint64_t reserved_1_63 : 63; 2264 uint64_t gstop : 1; /**< GSTOP bit */ 2265#else 2266 uint64_t gstop : 1; 2267 uint64_t reserved_1_63 : 63; 2268#endif 2269 } s; 2270 struct cvmx_ciu_gstop_s cn30xx; 2271 struct cvmx_ciu_gstop_s cn31xx; 2272 struct cvmx_ciu_gstop_s cn38xx; 2273 struct cvmx_ciu_gstop_s cn38xxp2; 2274 struct cvmx_ciu_gstop_s cn50xx; 2275 struct cvmx_ciu_gstop_s cn52xx; 2276 struct cvmx_ciu_gstop_s cn52xxp1; 2277 struct cvmx_ciu_gstop_s cn56xx; 2278 struct cvmx_ciu_gstop_s cn56xxp1; 2279 struct cvmx_ciu_gstop_s cn58xx; 2280 struct cvmx_ciu_gstop_s cn58xxp1; 2281 struct cvmx_ciu_gstop_s cn61xx; 2282 struct cvmx_ciu_gstop_s cn63xx; 2283 struct cvmx_ciu_gstop_s cn63xxp1; 2284 struct cvmx_ciu_gstop_s cn66xx; 2285 struct cvmx_ciu_gstop_s cn68xx; 2286 struct cvmx_ciu_gstop_s cn68xxp1; 2287 struct cvmx_ciu_gstop_s cnf71xx; 2288}; 2289typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t; 2290 2291/** 2292 * cvmx_ciu_int#_en0 2293 * 2294 * Notes: 2295 * CIU_INT0_EN0: PP0/IP2 2296 * CIU_INT1_EN0: PP0/IP3 2297 * CIU_INT2_EN0: PP1/IP2 2298 * CIU_INT3_EN0: PP1/IP3 2299 * CIU_INT4_EN0: PP2/IP2 2300 * CIU_INT5_EN0: PP2/IP3 2301 * CIU_INT6_EN0: PP3/IP2 2302 * CIU_INT7_EN0: PP3/IP3 2303 * ..... 2304 * 2305 * (hole) 2306 * CIU_INT32_EN0: IO 0 2307 * CIU_INT33_EN0: IO 1 2308 */ 2309union cvmx_ciu_intx_en0 { 2310 uint64_t u64; 2311 struct cvmx_ciu_intx_en0_s { 2312#ifdef __BIG_ENDIAN_BITFIELD 2313 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 2314 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 2315 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 2316 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 2317 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 2318 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 2319 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 2320 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 2321 uint64_t timer : 4; /**< General timer interrupt enables */ 2322 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2323 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 2324 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 2325 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 2326 uint64_t rml : 1; /**< RML Interrupt enable */ 2327 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 2328 uint64_t reserved_44_44 : 1; 2329 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 2330 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 2331 uint64_t uart : 2; /**< Two UART interrupt enables */ 2332 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */ 2333 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 2334 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 2335#else 2336 uint64_t workq : 16; 2337 uint64_t gpio : 16; 2338 uint64_t mbox : 2; 2339 uint64_t uart : 2; 2340 uint64_t pci_int : 4; 2341 uint64_t pci_msi : 4; 2342 uint64_t reserved_44_44 : 1; 2343 uint64_t twsi : 1; 2344 uint64_t rml : 1; 2345 uint64_t trace : 1; 2346 uint64_t gmx_drp : 2; 2347 uint64_t ipd_drp : 1; 2348 uint64_t key_zero : 1; 2349 uint64_t timer : 4; 2350 uint64_t usb : 1; 2351 uint64_t pcm : 1; 2352 uint64_t mpi : 1; 2353 uint64_t twsi2 : 1; 2354 uint64_t powiq : 1; 2355 uint64_t ipdppthr : 1; 2356 uint64_t mii : 1; 2357 uint64_t bootdma : 1; 2358#endif 2359 } s; 2360 struct cvmx_ciu_intx_en0_cn30xx { 2361#ifdef __BIG_ENDIAN_BITFIELD 2362 uint64_t reserved_59_63 : 5; 2363 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 2364 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 2365 uint64_t usb : 1; /**< USB interrupt */ 2366 uint64_t timer : 4; /**< General timer interrupts */ 2367 uint64_t reserved_51_51 : 1; 2368 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2369 uint64_t reserved_49_49 : 1; 2370 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2371 uint64_t reserved_47_47 : 1; 2372 uint64_t rml : 1; /**< RML Interrupt */ 2373 uint64_t twsi : 1; /**< TWSI Interrupt */ 2374 uint64_t reserved_44_44 : 1; 2375 uint64_t pci_msi : 4; /**< PCI MSI */ 2376 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2377 uint64_t uart : 2; /**< Two UART interrupts */ 2378 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2379 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2380 uint64_t workq : 16; /**< 16 work queue interrupts */ 2381#else 2382 uint64_t workq : 16; 2383 uint64_t gpio : 16; 2384 uint64_t mbox : 2; 2385 uint64_t uart : 2; 2386 uint64_t pci_int : 4; 2387 uint64_t pci_msi : 4; 2388 uint64_t reserved_44_44 : 1; 2389 uint64_t twsi : 1; 2390 uint64_t rml : 1; 2391 uint64_t reserved_47_47 : 1; 2392 uint64_t gmx_drp : 1; 2393 uint64_t reserved_49_49 : 1; 2394 uint64_t ipd_drp : 1; 2395 uint64_t reserved_51_51 : 1; 2396 uint64_t timer : 4; 2397 uint64_t usb : 1; 2398 uint64_t pcm : 1; 2399 uint64_t mpi : 1; 2400 uint64_t reserved_59_63 : 5; 2401#endif 2402 } cn30xx; 2403 struct cvmx_ciu_intx_en0_cn31xx { 2404#ifdef __BIG_ENDIAN_BITFIELD 2405 uint64_t reserved_59_63 : 5; 2406 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 2407 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 2408 uint64_t usb : 1; /**< USB interrupt */ 2409 uint64_t timer : 4; /**< General timer interrupts */ 2410 uint64_t reserved_51_51 : 1; 2411 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2412 uint64_t reserved_49_49 : 1; 2413 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2414 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2415 uint64_t rml : 1; /**< RML Interrupt */ 2416 uint64_t twsi : 1; /**< TWSI Interrupt */ 2417 uint64_t reserved_44_44 : 1; 2418 uint64_t pci_msi : 4; /**< PCI MSI */ 2419 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2420 uint64_t uart : 2; /**< Two UART interrupts */ 2421 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2422 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2423 uint64_t workq : 16; /**< 16 work queue interrupts */ 2424#else 2425 uint64_t workq : 16; 2426 uint64_t gpio : 16; 2427 uint64_t mbox : 2; 2428 uint64_t uart : 2; 2429 uint64_t pci_int : 4; 2430 uint64_t pci_msi : 4; 2431 uint64_t reserved_44_44 : 1; 2432 uint64_t twsi : 1; 2433 uint64_t rml : 1; 2434 uint64_t trace : 1; 2435 uint64_t gmx_drp : 1; 2436 uint64_t reserved_49_49 : 1; 2437 uint64_t ipd_drp : 1; 2438 uint64_t reserved_51_51 : 1; 2439 uint64_t timer : 4; 2440 uint64_t usb : 1; 2441 uint64_t pcm : 1; 2442 uint64_t mpi : 1; 2443 uint64_t reserved_59_63 : 5; 2444#endif 2445 } cn31xx; 2446 struct cvmx_ciu_intx_en0_cn38xx { 2447#ifdef __BIG_ENDIAN_BITFIELD 2448 uint64_t reserved_56_63 : 8; 2449 uint64_t timer : 4; /**< General timer interrupts */ 2450 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2451 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2452 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2453 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2454 uint64_t rml : 1; /**< RML Interrupt */ 2455 uint64_t twsi : 1; /**< TWSI Interrupt */ 2456 uint64_t reserved_44_44 : 1; 2457 uint64_t pci_msi : 4; /**< PCI MSI */ 2458 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2459 uint64_t uart : 2; /**< Two UART interrupts */ 2460 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2461 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2462 uint64_t workq : 16; /**< 16 work queue interrupts */ 2463#else 2464 uint64_t workq : 16; 2465 uint64_t gpio : 16; 2466 uint64_t mbox : 2; 2467 uint64_t uart : 2; 2468 uint64_t pci_int : 4; 2469 uint64_t pci_msi : 4; 2470 uint64_t reserved_44_44 : 1; 2471 uint64_t twsi : 1; 2472 uint64_t rml : 1; 2473 uint64_t trace : 1; 2474 uint64_t gmx_drp : 2; 2475 uint64_t ipd_drp : 1; 2476 uint64_t key_zero : 1; 2477 uint64_t timer : 4; 2478 uint64_t reserved_56_63 : 8; 2479#endif 2480 } cn38xx; 2481 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; 2482 struct cvmx_ciu_intx_en0_cn30xx cn50xx; 2483 struct cvmx_ciu_intx_en0_cn52xx { 2484#ifdef __BIG_ENDIAN_BITFIELD 2485 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2486 uint64_t mii : 1; /**< MII Interface Interrupt */ 2487 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2488 uint64_t powiq : 1; /**< POW IQ interrupt */ 2489 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2490 uint64_t reserved_57_58 : 2; 2491 uint64_t usb : 1; /**< USB Interrupt */ 2492 uint64_t timer : 4; /**< General timer interrupts */ 2493 uint64_t reserved_51_51 : 1; 2494 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2495 uint64_t reserved_49_49 : 1; 2496 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2497 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2498 uint64_t rml : 1; /**< RML Interrupt */ 2499 uint64_t twsi : 1; /**< TWSI Interrupt */ 2500 uint64_t reserved_44_44 : 1; 2501 uint64_t pci_msi : 4; /**< PCI MSI */ 2502 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2503 uint64_t uart : 2; /**< Two UART interrupts */ 2504 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2505 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2506 uint64_t workq : 16; /**< 16 work queue interrupts */ 2507#else 2508 uint64_t workq : 16; 2509 uint64_t gpio : 16; 2510 uint64_t mbox : 2; 2511 uint64_t uart : 2; 2512 uint64_t pci_int : 4; 2513 uint64_t pci_msi : 4; 2514 uint64_t reserved_44_44 : 1; 2515 uint64_t twsi : 1; 2516 uint64_t rml : 1; 2517 uint64_t trace : 1; 2518 uint64_t gmx_drp : 1; 2519 uint64_t reserved_49_49 : 1; 2520 uint64_t ipd_drp : 1; 2521 uint64_t reserved_51_51 : 1; 2522 uint64_t timer : 4; 2523 uint64_t usb : 1; 2524 uint64_t reserved_57_58 : 2; 2525 uint64_t twsi2 : 1; 2526 uint64_t powiq : 1; 2527 uint64_t ipdppthr : 1; 2528 uint64_t mii : 1; 2529 uint64_t bootdma : 1; 2530#endif 2531 } cn52xx; 2532 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; 2533 struct cvmx_ciu_intx_en0_cn56xx { 2534#ifdef __BIG_ENDIAN_BITFIELD 2535 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2536 uint64_t mii : 1; /**< MII Interface Interrupt */ 2537 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2538 uint64_t powiq : 1; /**< POW IQ interrupt */ 2539 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2540 uint64_t reserved_57_58 : 2; 2541 uint64_t usb : 1; /**< USB Interrupt */ 2542 uint64_t timer : 4; /**< General timer interrupts */ 2543 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2544 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2545 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2546 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2547 uint64_t rml : 1; /**< RML Interrupt */ 2548 uint64_t twsi : 1; /**< TWSI Interrupt */ 2549 uint64_t reserved_44_44 : 1; 2550 uint64_t pci_msi : 4; /**< PCI MSI */ 2551 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2552 uint64_t uart : 2; /**< Two UART interrupts */ 2553 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2554 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2555 uint64_t workq : 16; /**< 16 work queue interrupts */ 2556#else 2557 uint64_t workq : 16; 2558 uint64_t gpio : 16; 2559 uint64_t mbox : 2; 2560 uint64_t uart : 2; 2561 uint64_t pci_int : 4; 2562 uint64_t pci_msi : 4; 2563 uint64_t reserved_44_44 : 1; 2564 uint64_t twsi : 1; 2565 uint64_t rml : 1; 2566 uint64_t trace : 1; 2567 uint64_t gmx_drp : 2; 2568 uint64_t ipd_drp : 1; 2569 uint64_t key_zero : 1; 2570 uint64_t timer : 4; 2571 uint64_t usb : 1; 2572 uint64_t reserved_57_58 : 2; 2573 uint64_t twsi2 : 1; 2574 uint64_t powiq : 1; 2575 uint64_t ipdppthr : 1; 2576 uint64_t mii : 1; 2577 uint64_t bootdma : 1; 2578#endif 2579 } cn56xx; 2580 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; 2581 struct cvmx_ciu_intx_en0_cn38xx cn58xx; 2582 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; 2583 struct cvmx_ciu_intx_en0_cn61xx { 2584#ifdef __BIG_ENDIAN_BITFIELD 2585 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 2586 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */ 2587 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 2588 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 2589 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 2590 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 2591 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 2592 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 2593 uint64_t timer : 4; /**< General timer interrupt enables */ 2594 uint64_t reserved_51_51 : 1; 2595 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 2596 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 2597 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 2598 uint64_t rml : 1; /**< RML Interrupt enable */ 2599 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 2600 uint64_t reserved_44_44 : 1; 2601 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 2602 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 2603 uint64_t uart : 2; /**< Two UART interrupt enables */ 2604 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */ 2605 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 2606 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 2607#else 2608 uint64_t workq : 16; 2609 uint64_t gpio : 16; 2610 uint64_t mbox : 2; 2611 uint64_t uart : 2; 2612 uint64_t pci_int : 4; 2613 uint64_t pci_msi : 4; 2614 uint64_t reserved_44_44 : 1; 2615 uint64_t twsi : 1; 2616 uint64_t rml : 1; 2617 uint64_t trace : 1; 2618 uint64_t gmx_drp : 2; 2619 uint64_t ipd_drp : 1; 2620 uint64_t reserved_51_51 : 1; 2621 uint64_t timer : 4; 2622 uint64_t usb : 1; 2623 uint64_t pcm : 1; 2624 uint64_t mpi : 1; 2625 uint64_t twsi2 : 1; 2626 uint64_t powiq : 1; 2627 uint64_t ipdppthr : 1; 2628 uint64_t mii : 1; 2629 uint64_t bootdma : 1; 2630#endif 2631 } cn61xx; 2632 struct cvmx_ciu_intx_en0_cn52xx cn63xx; 2633 struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; 2634 struct cvmx_ciu_intx_en0_cn66xx { 2635#ifdef __BIG_ENDIAN_BITFIELD 2636 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 2637 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 2638 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 2639 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 2640 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 2641 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 2642 uint64_t reserved_57_57 : 1; 2643 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 2644 uint64_t timer : 4; /**< General timer interrupt enables */ 2645 uint64_t reserved_51_51 : 1; 2646 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 2647 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 2648 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 2649 uint64_t rml : 1; /**< RML Interrupt enable */ 2650 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 2651 uint64_t reserved_44_44 : 1; 2652 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */ 2653 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 2654 uint64_t uart : 2; /**< Two UART interrupt enables */ 2655 uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */ 2656 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 2657 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 2658#else 2659 uint64_t workq : 16; 2660 uint64_t gpio : 16; 2661 uint64_t mbox : 2; 2662 uint64_t uart : 2; 2663 uint64_t pci_int : 4; 2664 uint64_t pci_msi : 4; 2665 uint64_t reserved_44_44 : 1; 2666 uint64_t twsi : 1; 2667 uint64_t rml : 1; 2668 uint64_t trace : 1; 2669 uint64_t gmx_drp : 2; 2670 uint64_t ipd_drp : 1; 2671 uint64_t reserved_51_51 : 1; 2672 uint64_t timer : 4; 2673 uint64_t usb : 1; 2674 uint64_t reserved_57_57 : 1; 2675 uint64_t mpi : 1; 2676 uint64_t twsi2 : 1; 2677 uint64_t powiq : 1; 2678 uint64_t ipdppthr : 1; 2679 uint64_t mii : 1; 2680 uint64_t bootdma : 1; 2681#endif 2682 } cn66xx; 2683 struct cvmx_ciu_intx_en0_cnf71xx { 2684#ifdef __BIG_ENDIAN_BITFIELD 2685 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 2686 uint64_t reserved_62_62 : 1; 2687 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 2688 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 2689 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 2690 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 2691 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 2692 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 2693 uint64_t timer : 4; /**< General timer interrupt enables */ 2694 uint64_t reserved_51_51 : 1; 2695 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 2696 uint64_t reserved_49_49 : 1; 2697 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */ 2698 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 2699 uint64_t rml : 1; /**< RML Interrupt enable */ 2700 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 2701 uint64_t reserved_44_44 : 1; 2702 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 2703 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 2704 uint64_t uart : 2; /**< Two UART interrupt enables */ 2705 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */ 2706 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 2707 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 2708#else 2709 uint64_t workq : 16; 2710 uint64_t gpio : 16; 2711 uint64_t mbox : 2; 2712 uint64_t uart : 2; 2713 uint64_t pci_int : 4; 2714 uint64_t pci_msi : 4; 2715 uint64_t reserved_44_44 : 1; 2716 uint64_t twsi : 1; 2717 uint64_t rml : 1; 2718 uint64_t trace : 1; 2719 uint64_t gmx_drp : 1; 2720 uint64_t reserved_49_49 : 1; 2721 uint64_t ipd_drp : 1; 2722 uint64_t reserved_51_51 : 1; 2723 uint64_t timer : 4; 2724 uint64_t usb : 1; 2725 uint64_t pcm : 1; 2726 uint64_t mpi : 1; 2727 uint64_t twsi2 : 1; 2728 uint64_t powiq : 1; 2729 uint64_t ipdppthr : 1; 2730 uint64_t reserved_62_62 : 1; 2731 uint64_t bootdma : 1; 2732#endif 2733 } cnf71xx; 2734}; 2735typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t; 2736 2737/** 2738 * cvmx_ciu_int#_en0_w1c 2739 * 2740 * Notes: 2741 * Write-1-to-clear version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value. 2742 * 2743 */ 2744union cvmx_ciu_intx_en0_w1c { 2745 uint64_t u64; 2746 struct cvmx_ciu_intx_en0_w1c_s { 2747#ifdef __BIG_ENDIAN_BITFIELD 2748 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 2749 enable */ 2750 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 2751 enable */ 2752 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 2753 interrupt enable */ 2754 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 2755 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 2756 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 2757 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 2758 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 2759 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 2760 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2761 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 2762 enable */ 2763 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 2764 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 2765 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 2766 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 2767 uint64_t reserved_44_44 : 1; 2768 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 2769 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 2770 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 2771 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt 2772 enables */ 2773 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 2774 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 2775#else 2776 uint64_t workq : 16; 2777 uint64_t gpio : 16; 2778 uint64_t mbox : 2; 2779 uint64_t uart : 2; 2780 uint64_t pci_int : 4; 2781 uint64_t pci_msi : 4; 2782 uint64_t reserved_44_44 : 1; 2783 uint64_t twsi : 1; 2784 uint64_t rml : 1; 2785 uint64_t trace : 1; 2786 uint64_t gmx_drp : 2; 2787 uint64_t ipd_drp : 1; 2788 uint64_t key_zero : 1; 2789 uint64_t timer : 4; 2790 uint64_t usb : 1; 2791 uint64_t pcm : 1; 2792 uint64_t mpi : 1; 2793 uint64_t twsi2 : 1; 2794 uint64_t powiq : 1; 2795 uint64_t ipdppthr : 1; 2796 uint64_t mii : 1; 2797 uint64_t bootdma : 1; 2798#endif 2799 } s; 2800 struct cvmx_ciu_intx_en0_w1c_cn52xx { 2801#ifdef __BIG_ENDIAN_BITFIELD 2802 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2803 uint64_t mii : 1; /**< MII Interface Interrupt */ 2804 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2805 uint64_t powiq : 1; /**< POW IQ interrupt */ 2806 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2807 uint64_t reserved_57_58 : 2; 2808 uint64_t usb : 1; /**< USB Interrupt */ 2809 uint64_t timer : 4; /**< General timer interrupts */ 2810 uint64_t reserved_51_51 : 1; 2811 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2812 uint64_t reserved_49_49 : 1; 2813 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2814 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2815 uint64_t rml : 1; /**< RML Interrupt */ 2816 uint64_t twsi : 1; /**< TWSI Interrupt */ 2817 uint64_t reserved_44_44 : 1; 2818 uint64_t pci_msi : 4; /**< PCI MSI */ 2819 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2820 uint64_t uart : 2; /**< Two UART interrupts */ 2821 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2822 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2823 uint64_t workq : 16; /**< 16 work queue interrupts */ 2824#else 2825 uint64_t workq : 16; 2826 uint64_t gpio : 16; 2827 uint64_t mbox : 2; 2828 uint64_t uart : 2; 2829 uint64_t pci_int : 4; 2830 uint64_t pci_msi : 4; 2831 uint64_t reserved_44_44 : 1; 2832 uint64_t twsi : 1; 2833 uint64_t rml : 1; 2834 uint64_t trace : 1; 2835 uint64_t gmx_drp : 1; 2836 uint64_t reserved_49_49 : 1; 2837 uint64_t ipd_drp : 1; 2838 uint64_t reserved_51_51 : 1; 2839 uint64_t timer : 4; 2840 uint64_t usb : 1; 2841 uint64_t reserved_57_58 : 2; 2842 uint64_t twsi2 : 1; 2843 uint64_t powiq : 1; 2844 uint64_t ipdppthr : 1; 2845 uint64_t mii : 1; 2846 uint64_t bootdma : 1; 2847#endif 2848 } cn52xx; 2849 struct cvmx_ciu_intx_en0_w1c_cn56xx { 2850#ifdef __BIG_ENDIAN_BITFIELD 2851 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2852 uint64_t mii : 1; /**< MII Interface Interrupt */ 2853 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2854 uint64_t powiq : 1; /**< POW IQ interrupt */ 2855 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2856 uint64_t reserved_57_58 : 2; 2857 uint64_t usb : 1; /**< USB Interrupt */ 2858 uint64_t timer : 4; /**< General timer interrupts */ 2859 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2860 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2861 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2862 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2863 uint64_t rml : 1; /**< RML Interrupt */ 2864 uint64_t twsi : 1; /**< TWSI Interrupt */ 2865 uint64_t reserved_44_44 : 1; 2866 uint64_t pci_msi : 4; /**< PCI MSI */ 2867 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2868 uint64_t uart : 2; /**< Two UART interrupts */ 2869 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2870 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2871 uint64_t workq : 16; /**< 16 work queue interrupts */ 2872#else 2873 uint64_t workq : 16; 2874 uint64_t gpio : 16; 2875 uint64_t mbox : 2; 2876 uint64_t uart : 2; 2877 uint64_t pci_int : 4; 2878 uint64_t pci_msi : 4; 2879 uint64_t reserved_44_44 : 1; 2880 uint64_t twsi : 1; 2881 uint64_t rml : 1; 2882 uint64_t trace : 1; 2883 uint64_t gmx_drp : 2; 2884 uint64_t ipd_drp : 1; 2885 uint64_t key_zero : 1; 2886 uint64_t timer : 4; 2887 uint64_t usb : 1; 2888 uint64_t reserved_57_58 : 2; 2889 uint64_t twsi2 : 1; 2890 uint64_t powiq : 1; 2891 uint64_t ipdppthr : 1; 2892 uint64_t mii : 1; 2893 uint64_t bootdma : 1; 2894#endif 2895 } cn56xx; 2896 struct cvmx_ciu_intx_en0_w1c_cn58xx { 2897#ifdef __BIG_ENDIAN_BITFIELD 2898 uint64_t reserved_56_63 : 8; 2899 uint64_t timer : 4; /**< General timer interrupts */ 2900 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2901 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2902 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2903 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2904 uint64_t rml : 1; /**< RML Interrupt */ 2905 uint64_t twsi : 1; /**< TWSI Interrupt */ 2906 uint64_t reserved_44_44 : 1; 2907 uint64_t pci_msi : 4; /**< PCI MSI */ 2908 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2909 uint64_t uart : 2; /**< Two UART interrupts */ 2910 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2911 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2912 uint64_t workq : 16; /**< 16 work queue interrupts */ 2913#else 2914 uint64_t workq : 16; 2915 uint64_t gpio : 16; 2916 uint64_t mbox : 2; 2917 uint64_t uart : 2; 2918 uint64_t pci_int : 4; 2919 uint64_t pci_msi : 4; 2920 uint64_t reserved_44_44 : 1; 2921 uint64_t twsi : 1; 2922 uint64_t rml : 1; 2923 uint64_t trace : 1; 2924 uint64_t gmx_drp : 2; 2925 uint64_t ipd_drp : 1; 2926 uint64_t key_zero : 1; 2927 uint64_t timer : 4; 2928 uint64_t reserved_56_63 : 8; 2929#endif 2930 } cn58xx; 2931 struct cvmx_ciu_intx_en0_w1c_cn61xx { 2932#ifdef __BIG_ENDIAN_BITFIELD 2933 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 2934 enable */ 2935 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt 2936 enable */ 2937 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 2938 interrupt enable */ 2939 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 2940 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 2941 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 2942 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 2943 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 2944 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 2945 uint64_t reserved_51_51 : 1; 2946 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 2947 enable */ 2948 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 2949 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 2950 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 2951 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 2952 uint64_t reserved_44_44 : 1; 2953 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 2954 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 2955 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 2956 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt 2957 enables */ 2958 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 2959 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 2960#else 2961 uint64_t workq : 16; 2962 uint64_t gpio : 16; 2963 uint64_t mbox : 2; 2964 uint64_t uart : 2; 2965 uint64_t pci_int : 4; 2966 uint64_t pci_msi : 4; 2967 uint64_t reserved_44_44 : 1; 2968 uint64_t twsi : 1; 2969 uint64_t rml : 1; 2970 uint64_t trace : 1; 2971 uint64_t gmx_drp : 2; 2972 uint64_t ipd_drp : 1; 2973 uint64_t reserved_51_51 : 1; 2974 uint64_t timer : 4; 2975 uint64_t usb : 1; 2976 uint64_t pcm : 1; 2977 uint64_t mpi : 1; 2978 uint64_t twsi2 : 1; 2979 uint64_t powiq : 1; 2980 uint64_t ipdppthr : 1; 2981 uint64_t mii : 1; 2982 uint64_t bootdma : 1; 2983#endif 2984 } cn61xx; 2985 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; 2986 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; 2987 struct cvmx_ciu_intx_en0_w1c_cn66xx { 2988#ifdef __BIG_ENDIAN_BITFIELD 2989 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 2990 enable */ 2991 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 2992 enable */ 2993 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 2994 interrupt enable */ 2995 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */ 2996 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */ 2997 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */ 2998 uint64_t reserved_57_57 : 1; 2999 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */ 3000 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */ 3001 uint64_t reserved_51_51 : 1; 3002 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 3003 enable */ 3004 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 3005 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 3006 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 3007 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 3008 uint64_t reserved_44_44 : 1; 3009 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */ 3010 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 3011 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 3012 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt 3013 enables */ 3014 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 3015 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 3016#else 3017 uint64_t workq : 16; 3018 uint64_t gpio : 16; 3019 uint64_t mbox : 2; 3020 uint64_t uart : 2; 3021 uint64_t pci_int : 4; 3022 uint64_t pci_msi : 4; 3023 uint64_t reserved_44_44 : 1; 3024 uint64_t twsi : 1; 3025 uint64_t rml : 1; 3026 uint64_t trace : 1; 3027 uint64_t gmx_drp : 2; 3028 uint64_t ipd_drp : 1; 3029 uint64_t reserved_51_51 : 1; 3030 uint64_t timer : 4; 3031 uint64_t usb : 1; 3032 uint64_t reserved_57_57 : 1; 3033 uint64_t mpi : 1; 3034 uint64_t twsi2 : 1; 3035 uint64_t powiq : 1; 3036 uint64_t ipdppthr : 1; 3037 uint64_t mii : 1; 3038 uint64_t bootdma : 1; 3039#endif 3040 } cn66xx; 3041 struct cvmx_ciu_intx_en0_w1c_cnf71xx { 3042#ifdef __BIG_ENDIAN_BITFIELD 3043 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 3044 enable */ 3045 uint64_t reserved_62_62 : 1; 3046 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 3047 interrupt enable */ 3048 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 3049 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 3050 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 3051 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 3052 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 3053 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 3054 uint64_t reserved_51_51 : 1; 3055 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 3056 enable */ 3057 uint64_t reserved_49_49 : 1; 3058 uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */ 3059 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 3060 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 3061 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 3062 uint64_t reserved_44_44 : 1; 3063 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 3064 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 3065 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 3066 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt 3067 enables */ 3068 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 3069 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 3070#else 3071 uint64_t workq : 16; 3072 uint64_t gpio : 16; 3073 uint64_t mbox : 2; 3074 uint64_t uart : 2; 3075 uint64_t pci_int : 4; 3076 uint64_t pci_msi : 4; 3077 uint64_t reserved_44_44 : 1; 3078 uint64_t twsi : 1; 3079 uint64_t rml : 1; 3080 uint64_t trace : 1; 3081 uint64_t gmx_drp : 1; 3082 uint64_t reserved_49_49 : 1; 3083 uint64_t ipd_drp : 1; 3084 uint64_t reserved_51_51 : 1; 3085 uint64_t timer : 4; 3086 uint64_t usb : 1; 3087 uint64_t pcm : 1; 3088 uint64_t mpi : 1; 3089 uint64_t twsi2 : 1; 3090 uint64_t powiq : 1; 3091 uint64_t ipdppthr : 1; 3092 uint64_t reserved_62_62 : 1; 3093 uint64_t bootdma : 1; 3094#endif 3095 } cnf71xx; 3096}; 3097typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t; 3098 3099/** 3100 * cvmx_ciu_int#_en0_w1s 3101 * 3102 * Notes: 3103 * Write-1-to-set version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value. 3104 * 3105 */ 3106union cvmx_ciu_intx_en0_w1s { 3107 uint64_t u64; 3108 struct cvmx_ciu_intx_en0_w1s_s { 3109#ifdef __BIG_ENDIAN_BITFIELD 3110 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 3111 enable */ 3112 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 3113 enable */ 3114 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 3115 interrupt enable */ 3116 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 3117 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 3118 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 3119 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 3120 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 3121 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 3122 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 3123 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 3124 enable */ 3125 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 3126 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 3127 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 3128 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 3129 uint64_t reserved_44_44 : 1; 3130 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 3131 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 3132 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 3133 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt 3134 enables */ 3135 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 3136 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 3137#else 3138 uint64_t workq : 16; 3139 uint64_t gpio : 16; 3140 uint64_t mbox : 2; 3141 uint64_t uart : 2; 3142 uint64_t pci_int : 4; 3143 uint64_t pci_msi : 4; 3144 uint64_t reserved_44_44 : 1; 3145 uint64_t twsi : 1; 3146 uint64_t rml : 1; 3147 uint64_t trace : 1; 3148 uint64_t gmx_drp : 2; 3149 uint64_t ipd_drp : 1; 3150 uint64_t key_zero : 1; 3151 uint64_t timer : 4; 3152 uint64_t usb : 1; 3153 uint64_t pcm : 1; 3154 uint64_t mpi : 1; 3155 uint64_t twsi2 : 1; 3156 uint64_t powiq : 1; 3157 uint64_t ipdppthr : 1; 3158 uint64_t mii : 1; 3159 uint64_t bootdma : 1; 3160#endif 3161 } s; 3162 struct cvmx_ciu_intx_en0_w1s_cn52xx { 3163#ifdef __BIG_ENDIAN_BITFIELD 3164 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3165 uint64_t mii : 1; /**< MII Interface Interrupt */ 3166 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3167 uint64_t powiq : 1; /**< POW IQ interrupt */ 3168 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3169 uint64_t reserved_57_58 : 2; 3170 uint64_t usb : 1; /**< USB Interrupt */ 3171 uint64_t timer : 4; /**< General timer interrupts */ 3172 uint64_t reserved_51_51 : 1; 3173 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3174 uint64_t reserved_49_49 : 1; 3175 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3176 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3177 uint64_t rml : 1; /**< RML Interrupt */ 3178 uint64_t twsi : 1; /**< TWSI Interrupt */ 3179 uint64_t reserved_44_44 : 1; 3180 uint64_t pci_msi : 4; /**< PCI MSI */ 3181 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3182 uint64_t uart : 2; /**< Two UART interrupts */ 3183 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 3184 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3185 uint64_t workq : 16; /**< 16 work queue interrupts */ 3186#else 3187 uint64_t workq : 16; 3188 uint64_t gpio : 16; 3189 uint64_t mbox : 2; 3190 uint64_t uart : 2; 3191 uint64_t pci_int : 4; 3192 uint64_t pci_msi : 4; 3193 uint64_t reserved_44_44 : 1; 3194 uint64_t twsi : 1; 3195 uint64_t rml : 1; 3196 uint64_t trace : 1; 3197 uint64_t gmx_drp : 1; 3198 uint64_t reserved_49_49 : 1; 3199 uint64_t ipd_drp : 1; 3200 uint64_t reserved_51_51 : 1; 3201 uint64_t timer : 4; 3202 uint64_t usb : 1; 3203 uint64_t reserved_57_58 : 2; 3204 uint64_t twsi2 : 1; 3205 uint64_t powiq : 1; 3206 uint64_t ipdppthr : 1; 3207 uint64_t mii : 1; 3208 uint64_t bootdma : 1; 3209#endif 3210 } cn52xx; 3211 struct cvmx_ciu_intx_en0_w1s_cn56xx { 3212#ifdef __BIG_ENDIAN_BITFIELD 3213 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3214 uint64_t mii : 1; /**< MII Interface Interrupt */ 3215 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3216 uint64_t powiq : 1; /**< POW IQ interrupt */ 3217 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3218 uint64_t reserved_57_58 : 2; 3219 uint64_t usb : 1; /**< USB Interrupt */ 3220 uint64_t timer : 4; /**< General timer interrupts */ 3221 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 3222 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3223 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3224 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3225 uint64_t rml : 1; /**< RML Interrupt */ 3226 uint64_t twsi : 1; /**< TWSI Interrupt */ 3227 uint64_t reserved_44_44 : 1; 3228 uint64_t pci_msi : 4; /**< PCI MSI */ 3229 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3230 uint64_t uart : 2; /**< Two UART interrupts */ 3231 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 3232 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3233 uint64_t workq : 16; /**< 16 work queue interrupts */ 3234#else 3235 uint64_t workq : 16; 3236 uint64_t gpio : 16; 3237 uint64_t mbox : 2; 3238 uint64_t uart : 2; 3239 uint64_t pci_int : 4; 3240 uint64_t pci_msi : 4; 3241 uint64_t reserved_44_44 : 1; 3242 uint64_t twsi : 1; 3243 uint64_t rml : 1; 3244 uint64_t trace : 1; 3245 uint64_t gmx_drp : 2; 3246 uint64_t ipd_drp : 1; 3247 uint64_t key_zero : 1; 3248 uint64_t timer : 4; 3249 uint64_t usb : 1; 3250 uint64_t reserved_57_58 : 2; 3251 uint64_t twsi2 : 1; 3252 uint64_t powiq : 1; 3253 uint64_t ipdppthr : 1; 3254 uint64_t mii : 1; 3255 uint64_t bootdma : 1; 3256#endif 3257 } cn56xx; 3258 struct cvmx_ciu_intx_en0_w1s_cn58xx { 3259#ifdef __BIG_ENDIAN_BITFIELD 3260 uint64_t reserved_56_63 : 8; 3261 uint64_t timer : 4; /**< General timer interrupts */ 3262 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 3263 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3264 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3265 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3266 uint64_t rml : 1; /**< RML Interrupt */ 3267 uint64_t twsi : 1; /**< TWSI Interrupt */ 3268 uint64_t reserved_44_44 : 1; 3269 uint64_t pci_msi : 4; /**< PCI MSI */ 3270 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3271 uint64_t uart : 2; /**< Two UART interrupts */ 3272 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 3273 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3274 uint64_t workq : 16; /**< 16 work queue interrupts */ 3275#else 3276 uint64_t workq : 16; 3277 uint64_t gpio : 16; 3278 uint64_t mbox : 2; 3279 uint64_t uart : 2; 3280 uint64_t pci_int : 4; 3281 uint64_t pci_msi : 4; 3282 uint64_t reserved_44_44 : 1; 3283 uint64_t twsi : 1; 3284 uint64_t rml : 1; 3285 uint64_t trace : 1; 3286 uint64_t gmx_drp : 2; 3287 uint64_t ipd_drp : 1; 3288 uint64_t key_zero : 1; 3289 uint64_t timer : 4; 3290 uint64_t reserved_56_63 : 8; 3291#endif 3292 } cn58xx; 3293 struct cvmx_ciu_intx_en0_w1s_cn61xx { 3294#ifdef __BIG_ENDIAN_BITFIELD 3295 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 3296 enable */ 3297 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt 3298 enable */ 3299 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 3300 interrupt enable */ 3301 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 3302 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 3303 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 3304 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 3305 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 3306 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 3307 uint64_t reserved_51_51 : 1; 3308 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 3309 enable */ 3310 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 3311 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 3312 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 3313 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 3314 uint64_t reserved_44_44 : 1; 3315 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 3316 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 3317 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 3318 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt 3319 enables */ 3320 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 3321 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 3322#else 3323 uint64_t workq : 16; 3324 uint64_t gpio : 16; 3325 uint64_t mbox : 2; 3326 uint64_t uart : 2; 3327 uint64_t pci_int : 4; 3328 uint64_t pci_msi : 4; 3329 uint64_t reserved_44_44 : 1; 3330 uint64_t twsi : 1; 3331 uint64_t rml : 1; 3332 uint64_t trace : 1; 3333 uint64_t gmx_drp : 2; 3334 uint64_t ipd_drp : 1; 3335 uint64_t reserved_51_51 : 1; 3336 uint64_t timer : 4; 3337 uint64_t usb : 1; 3338 uint64_t pcm : 1; 3339 uint64_t mpi : 1; 3340 uint64_t twsi2 : 1; 3341 uint64_t powiq : 1; 3342 uint64_t ipdppthr : 1; 3343 uint64_t mii : 1; 3344 uint64_t bootdma : 1; 3345#endif 3346 } cn61xx; 3347 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; 3348 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; 3349 struct cvmx_ciu_intx_en0_w1s_cn66xx { 3350#ifdef __BIG_ENDIAN_BITFIELD 3351 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 3352 enable */ 3353 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 3354 enable */ 3355 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 3356 interrupt enable */ 3357 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */ 3358 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */ 3359 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */ 3360 uint64_t reserved_57_57 : 1; 3361 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */ 3362 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */ 3363 uint64_t reserved_51_51 : 1; 3364 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 3365 enable */ 3366 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 3367 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 3368 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 3369 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 3370 uint64_t reserved_44_44 : 1; 3371 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */ 3372 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 3373 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 3374 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt 3375 enables */ 3376 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 3377 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 3378#else 3379 uint64_t workq : 16; 3380 uint64_t gpio : 16; 3381 uint64_t mbox : 2; 3382 uint64_t uart : 2; 3383 uint64_t pci_int : 4; 3384 uint64_t pci_msi : 4; 3385 uint64_t reserved_44_44 : 1; 3386 uint64_t twsi : 1; 3387 uint64_t rml : 1; 3388 uint64_t trace : 1; 3389 uint64_t gmx_drp : 2; 3390 uint64_t ipd_drp : 1; 3391 uint64_t reserved_51_51 : 1; 3392 uint64_t timer : 4; 3393 uint64_t usb : 1; 3394 uint64_t reserved_57_57 : 1; 3395 uint64_t mpi : 1; 3396 uint64_t twsi2 : 1; 3397 uint64_t powiq : 1; 3398 uint64_t ipdppthr : 1; 3399 uint64_t mii : 1; 3400 uint64_t bootdma : 1; 3401#endif 3402 } cn66xx; 3403 struct cvmx_ciu_intx_en0_w1s_cnf71xx { 3404#ifdef __BIG_ENDIAN_BITFIELD 3405 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 3406 enable */ 3407 uint64_t reserved_62_62 : 1; 3408 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 3409 interrupt enable */ 3410 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 3411 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 3412 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 3413 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 3414 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 3415 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 3416 uint64_t reserved_51_51 : 1; 3417 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 3418 enable */ 3419 uint64_t reserved_49_49 : 1; 3420 uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */ 3421 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 3422 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 3423 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 3424 uint64_t reserved_44_44 : 1; 3425 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 3426 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 3427 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 3428 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt 3429 enables */ 3430 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 3431 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 3432#else 3433 uint64_t workq : 16; 3434 uint64_t gpio : 16; 3435 uint64_t mbox : 2; 3436 uint64_t uart : 2; 3437 uint64_t pci_int : 4; 3438 uint64_t pci_msi : 4; 3439 uint64_t reserved_44_44 : 1; 3440 uint64_t twsi : 1; 3441 uint64_t rml : 1; 3442 uint64_t trace : 1; 3443 uint64_t gmx_drp : 1; 3444 uint64_t reserved_49_49 : 1; 3445 uint64_t ipd_drp : 1; 3446 uint64_t reserved_51_51 : 1; 3447 uint64_t timer : 4; 3448 uint64_t usb : 1; 3449 uint64_t pcm : 1; 3450 uint64_t mpi : 1; 3451 uint64_t twsi2 : 1; 3452 uint64_t powiq : 1; 3453 uint64_t ipdppthr : 1; 3454 uint64_t reserved_62_62 : 1; 3455 uint64_t bootdma : 1; 3456#endif 3457 } cnf71xx; 3458}; 3459typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t; 3460 3461/** 3462 * cvmx_ciu_int#_en1 3463 * 3464 * Notes: 3465 * Enables for CIU_SUM1_PPX_IPx or CIU_SUM1_IOX_INT 3466 * CIU_INT0_EN1: PP0/IP2 3467 * CIU_INT1_EN1: PP0/IP3 3468 * CIU_INT2_EN1: PP1/IP2 3469 * CIU_INT3_EN1: PP1/IP3 3470 * CIU_INT4_EN1: PP2/IP2 3471 * CIU_INT5_EN1: PP2/IP3 3472 * CIU_INT6_EN1: PP3/IP2 3473 * CIU_INT7_EN1: PP3/IP3 3474 * ..... 3475 * 3476 * (hole) 3477 * CIU_INT32_EN1: IO0 3478 * CIU_INT33_EN1: IO1 3479 * 3480 * @verbatim 3481 * PPx/IP2 will be raised when... 3482 * 3483 * n = x*2 3484 * PPx/IP2 = |([CIU_SUM2_PPx_IP2,CIU_SUM1_PPx_IP2, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP2,CIU_INTn_EN1, CIU_INTn_EN0]) 3485 * 3486 * PPx/IP3 will be raised when... 3487 * 3488 * n = x*2 + 1 3489 * PPx/IP3 = |([CIU_SUM2_PPx_IP3,CIU_SUM1_PPx_IP3, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP3,CIU_INTn_EN1, CIU_INTn_EN0]) 3490 * 3491 * PCI/INT will be raised when... 3492 * 3493 * PCI/INT = |([CIU_SUM2_IO0_INT,CIU_SUM1_IO0_INT, CIU_INT32_SUM0] & [CIU_EN2_IO0_INT,CIU_INT32_EN1, CIU_INT32_EN0]) 3494 * PCI/INT = |([CIU_SUM2_IO1_INT,CIU_SUM1_IO1_INT, CIU_INT33_SUM0] & [CIU_EN2_IO1_INT,CIU_INT33_EN1, CIU_INT33_EN0]) 3495 * @endverbatim 3496 */ 3497union cvmx_ciu_intx_en1 { 3498 uint64_t u64; 3499 struct cvmx_ciu_intx_en1_s { 3500#ifdef __BIG_ENDIAN_BITFIELD 3501 uint64_t rst : 1; /**< MIO RST interrupt enable */ 3502 uint64_t reserved_62_62 : 1; 3503 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */ 3504 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */ 3505 uint64_t reserved_57_59 : 3; 3506 uint64_t dfm : 1; /**< DFM interrupt enable */ 3507 uint64_t reserved_53_55 : 3; 3508 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 3509 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 3510 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 3511 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 3512 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 3513 uint64_t ptp : 1; /**< PTP interrupt enable */ 3514 uint64_t agl : 1; /**< AGL interrupt enable */ 3515 uint64_t reserved_41_45 : 5; 3516 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 3517 uint64_t reserved_38_39 : 2; 3518 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 3519 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 3520 uint64_t dpi : 1; /**< DPI interrupt enable */ 3521 uint64_t sli : 1; /**< SLI interrupt enable */ 3522 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 3523 uint64_t dfa : 1; /**< DFA interrupt enable */ 3524 uint64_t key : 1; /**< KEY interrupt enable */ 3525 uint64_t rad : 1; /**< RAD interrupt enable */ 3526 uint64_t tim : 1; /**< TIM interrupt enable */ 3527 uint64_t zip : 1; /**< ZIP interrupt enable */ 3528 uint64_t pko : 1; /**< PKO interrupt enable */ 3529 uint64_t pip : 1; /**< PIP interrupt enable */ 3530 uint64_t ipd : 1; /**< IPD interrupt enable */ 3531 uint64_t l2c : 1; /**< L2C interrupt enable */ 3532 uint64_t pow : 1; /**< POW err interrupt enable */ 3533 uint64_t fpa : 1; /**< FPA interrupt enable */ 3534 uint64_t iob : 1; /**< IOB interrupt enable */ 3535 uint64_t mio : 1; /**< MIO boot interrupt enable */ 3536 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 3537 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 3538 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3539 uint64_t uart2 : 1; /**< Third UART interrupt */ 3540 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */ 3541#else 3542 uint64_t wdog : 16; 3543 uint64_t uart2 : 1; 3544 uint64_t usb1 : 1; 3545 uint64_t mii1 : 1; 3546 uint64_t nand : 1; 3547 uint64_t mio : 1; 3548 uint64_t iob : 1; 3549 uint64_t fpa : 1; 3550 uint64_t pow : 1; 3551 uint64_t l2c : 1; 3552 uint64_t ipd : 1; 3553 uint64_t pip : 1; 3554 uint64_t pko : 1; 3555 uint64_t zip : 1; 3556 uint64_t tim : 1; 3557 uint64_t rad : 1; 3558 uint64_t key : 1; 3559 uint64_t dfa : 1; 3560 uint64_t usb : 1; 3561 uint64_t sli : 1; 3562 uint64_t dpi : 1; 3563 uint64_t agx0 : 1; 3564 uint64_t agx1 : 1; 3565 uint64_t reserved_38_39 : 2; 3566 uint64_t dpi_dma : 1; 3567 uint64_t reserved_41_45 : 5; 3568 uint64_t agl : 1; 3569 uint64_t ptp : 1; 3570 uint64_t pem0 : 1; 3571 uint64_t pem1 : 1; 3572 uint64_t srio0 : 1; 3573 uint64_t srio1 : 1; 3574 uint64_t lmc0 : 1; 3575 uint64_t reserved_53_55 : 3; 3576 uint64_t dfm : 1; 3577 uint64_t reserved_57_59 : 3; 3578 uint64_t srio2 : 1; 3579 uint64_t srio3 : 1; 3580 uint64_t reserved_62_62 : 1; 3581 uint64_t rst : 1; 3582#endif 3583 } s; 3584 struct cvmx_ciu_intx_en1_cn30xx { 3585#ifdef __BIG_ENDIAN_BITFIELD 3586 uint64_t reserved_1_63 : 63; 3587 uint64_t wdog : 1; /**< Watchdog summary interrupt enable vector */ 3588#else 3589 uint64_t wdog : 1; 3590 uint64_t reserved_1_63 : 63; 3591#endif 3592 } cn30xx; 3593 struct cvmx_ciu_intx_en1_cn31xx { 3594#ifdef __BIG_ENDIAN_BITFIELD 3595 uint64_t reserved_2_63 : 62; 3596 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */ 3597#else 3598 uint64_t wdog : 2; 3599 uint64_t reserved_2_63 : 62; 3600#endif 3601 } cn31xx; 3602 struct cvmx_ciu_intx_en1_cn38xx { 3603#ifdef __BIG_ENDIAN_BITFIELD 3604 uint64_t reserved_16_63 : 48; 3605 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 3606#else 3607 uint64_t wdog : 16; 3608 uint64_t reserved_16_63 : 48; 3609#endif 3610 } cn38xx; 3611 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; 3612 struct cvmx_ciu_intx_en1_cn31xx cn50xx; 3613 struct cvmx_ciu_intx_en1_cn52xx { 3614#ifdef __BIG_ENDIAN_BITFIELD 3615 uint64_t reserved_20_63 : 44; 3616 uint64_t nand : 1; /**< NAND Flash Controller */ 3617 uint64_t mii1 : 1; /**< Second MII Interrupt */ 3618 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3619 uint64_t uart2 : 1; /**< Third UART interrupt */ 3620 uint64_t reserved_4_15 : 12; 3621 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3622#else 3623 uint64_t wdog : 4; 3624 uint64_t reserved_4_15 : 12; 3625 uint64_t uart2 : 1; 3626 uint64_t usb1 : 1; 3627 uint64_t mii1 : 1; 3628 uint64_t nand : 1; 3629 uint64_t reserved_20_63 : 44; 3630#endif 3631 } cn52xx; 3632 struct cvmx_ciu_intx_en1_cn52xxp1 { 3633#ifdef __BIG_ENDIAN_BITFIELD 3634 uint64_t reserved_19_63 : 45; 3635 uint64_t mii1 : 1; /**< Second MII Interrupt */ 3636 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3637 uint64_t uart2 : 1; /**< Third UART interrupt */ 3638 uint64_t reserved_4_15 : 12; 3639 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3640#else 3641 uint64_t wdog : 4; 3642 uint64_t reserved_4_15 : 12; 3643 uint64_t uart2 : 1; 3644 uint64_t usb1 : 1; 3645 uint64_t mii1 : 1; 3646 uint64_t reserved_19_63 : 45; 3647#endif 3648 } cn52xxp1; 3649 struct cvmx_ciu_intx_en1_cn56xx { 3650#ifdef __BIG_ENDIAN_BITFIELD 3651 uint64_t reserved_12_63 : 52; 3652 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 3653#else 3654 uint64_t wdog : 12; 3655 uint64_t reserved_12_63 : 52; 3656#endif 3657 } cn56xx; 3658 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; 3659 struct cvmx_ciu_intx_en1_cn38xx cn58xx; 3660 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; 3661 struct cvmx_ciu_intx_en1_cn61xx { 3662#ifdef __BIG_ENDIAN_BITFIELD 3663 uint64_t rst : 1; /**< MIO RST interrupt enable */ 3664 uint64_t reserved_53_62 : 10; 3665 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 3666 uint64_t reserved_50_51 : 2; 3667 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 3668 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 3669 uint64_t ptp : 1; /**< PTP interrupt enable */ 3670 uint64_t agl : 1; /**< AGL interrupt enable */ 3671 uint64_t reserved_41_45 : 5; 3672 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 3673 uint64_t reserved_38_39 : 2; 3674 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 3675 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 3676 uint64_t dpi : 1; /**< DPI interrupt enable */ 3677 uint64_t sli : 1; /**< SLI interrupt enable */ 3678 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 3679 uint64_t dfa : 1; /**< DFA interrupt enable */ 3680 uint64_t key : 1; /**< KEY interrupt enable */ 3681 uint64_t rad : 1; /**< RAD interrupt enable */ 3682 uint64_t tim : 1; /**< TIM interrupt enable */ 3683 uint64_t zip : 1; /**< ZIP interrupt enable */ 3684 uint64_t pko : 1; /**< PKO interrupt enable */ 3685 uint64_t pip : 1; /**< PIP interrupt enable */ 3686 uint64_t ipd : 1; /**< IPD interrupt enable */ 3687 uint64_t l2c : 1; /**< L2C interrupt enable */ 3688 uint64_t pow : 1; /**< POW err interrupt enable */ 3689 uint64_t fpa : 1; /**< FPA interrupt enable */ 3690 uint64_t iob : 1; /**< IOB interrupt enable */ 3691 uint64_t mio : 1; /**< MIO boot interrupt enable */ 3692 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 3693 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */ 3694 uint64_t reserved_4_17 : 14; 3695 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3696#else 3697 uint64_t wdog : 4; 3698 uint64_t reserved_4_17 : 14; 3699 uint64_t mii1 : 1; 3700 uint64_t nand : 1; 3701 uint64_t mio : 1; 3702 uint64_t iob : 1; 3703 uint64_t fpa : 1; 3704 uint64_t pow : 1; 3705 uint64_t l2c : 1; 3706 uint64_t ipd : 1; 3707 uint64_t pip : 1; 3708 uint64_t pko : 1; 3709 uint64_t zip : 1; 3710 uint64_t tim : 1; 3711 uint64_t rad : 1; 3712 uint64_t key : 1; 3713 uint64_t dfa : 1; 3714 uint64_t usb : 1; 3715 uint64_t sli : 1; 3716 uint64_t dpi : 1; 3717 uint64_t agx0 : 1; 3718 uint64_t agx1 : 1; 3719 uint64_t reserved_38_39 : 2; 3720 uint64_t dpi_dma : 1; 3721 uint64_t reserved_41_45 : 5; 3722 uint64_t agl : 1; 3723 uint64_t ptp : 1; 3724 uint64_t pem0 : 1; 3725 uint64_t pem1 : 1; 3726 uint64_t reserved_50_51 : 2; 3727 uint64_t lmc0 : 1; 3728 uint64_t reserved_53_62 : 10; 3729 uint64_t rst : 1; 3730#endif 3731 } cn61xx; 3732 struct cvmx_ciu_intx_en1_cn63xx { 3733#ifdef __BIG_ENDIAN_BITFIELD 3734 uint64_t rst : 1; /**< MIO RST interrupt enable */ 3735 uint64_t reserved_57_62 : 6; 3736 uint64_t dfm : 1; /**< DFM interrupt enable */ 3737 uint64_t reserved_53_55 : 3; 3738 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 3739 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 3740 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 3741 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 3742 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 3743 uint64_t ptp : 1; /**< PTP interrupt enable */ 3744 uint64_t agl : 1; /**< AGL interrupt enable */ 3745 uint64_t reserved_37_45 : 9; 3746 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 3747 uint64_t dpi : 1; /**< DPI interrupt enable */ 3748 uint64_t sli : 1; /**< SLI interrupt enable */ 3749 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 3750 uint64_t dfa : 1; /**< DFA interrupt enable */ 3751 uint64_t key : 1; /**< KEY interrupt enable */ 3752 uint64_t rad : 1; /**< RAD interrupt enable */ 3753 uint64_t tim : 1; /**< TIM interrupt enable */ 3754 uint64_t zip : 1; /**< ZIP interrupt enable */ 3755 uint64_t pko : 1; /**< PKO interrupt enable */ 3756 uint64_t pip : 1; /**< PIP interrupt enable */ 3757 uint64_t ipd : 1; /**< IPD interrupt enable */ 3758 uint64_t l2c : 1; /**< L2C interrupt enable */ 3759 uint64_t pow : 1; /**< POW err interrupt enable */ 3760 uint64_t fpa : 1; /**< FPA interrupt enable */ 3761 uint64_t iob : 1; /**< IOB interrupt enable */ 3762 uint64_t mio : 1; /**< MIO boot interrupt enable */ 3763 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 3764 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 3765 uint64_t reserved_6_17 : 12; 3766 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */ 3767#else 3768 uint64_t wdog : 6; 3769 uint64_t reserved_6_17 : 12; 3770 uint64_t mii1 : 1; 3771 uint64_t nand : 1; 3772 uint64_t mio : 1; 3773 uint64_t iob : 1; 3774 uint64_t fpa : 1; 3775 uint64_t pow : 1; 3776 uint64_t l2c : 1; 3777 uint64_t ipd : 1; 3778 uint64_t pip : 1; 3779 uint64_t pko : 1; 3780 uint64_t zip : 1; 3781 uint64_t tim : 1; 3782 uint64_t rad : 1; 3783 uint64_t key : 1; 3784 uint64_t dfa : 1; 3785 uint64_t usb : 1; 3786 uint64_t sli : 1; 3787 uint64_t dpi : 1; 3788 uint64_t agx0 : 1; 3789 uint64_t reserved_37_45 : 9; 3790 uint64_t agl : 1; 3791 uint64_t ptp : 1; 3792 uint64_t pem0 : 1; 3793 uint64_t pem1 : 1; 3794 uint64_t srio0 : 1; 3795 uint64_t srio1 : 1; 3796 uint64_t lmc0 : 1; 3797 uint64_t reserved_53_55 : 3; 3798 uint64_t dfm : 1; 3799 uint64_t reserved_57_62 : 6; 3800 uint64_t rst : 1; 3801#endif 3802 } cn63xx; 3803 struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; 3804 struct cvmx_ciu_intx_en1_cn66xx { 3805#ifdef __BIG_ENDIAN_BITFIELD 3806 uint64_t rst : 1; /**< MIO RST interrupt enable */ 3807 uint64_t reserved_62_62 : 1; 3808 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */ 3809 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */ 3810 uint64_t reserved_57_59 : 3; 3811 uint64_t dfm : 1; /**< DFM interrupt enable */ 3812 uint64_t reserved_53_55 : 3; 3813 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 3814 uint64_t reserved_51_51 : 1; 3815 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 3816 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 3817 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 3818 uint64_t ptp : 1; /**< PTP interrupt enable */ 3819 uint64_t agl : 1; /**< AGL interrupt enable */ 3820 uint64_t reserved_38_45 : 8; 3821 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 3822 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 3823 uint64_t dpi : 1; /**< DPI interrupt enable */ 3824 uint64_t sli : 1; /**< SLI interrupt enable */ 3825 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 3826 uint64_t dfa : 1; /**< DFA interrupt enable */ 3827 uint64_t key : 1; /**< KEY interrupt enable */ 3828 uint64_t rad : 1; /**< RAD interrupt enable */ 3829 uint64_t tim : 1; /**< TIM interrupt enable */ 3830 uint64_t zip : 1; /**< ZIP interrupt enable */ 3831 uint64_t pko : 1; /**< PKO interrupt enable */ 3832 uint64_t pip : 1; /**< PIP interrupt enable */ 3833 uint64_t ipd : 1; /**< IPD interrupt enable */ 3834 uint64_t l2c : 1; /**< L2C interrupt enable */ 3835 uint64_t pow : 1; /**< POW err interrupt enable */ 3836 uint64_t fpa : 1; /**< FPA interrupt enable */ 3837 uint64_t iob : 1; /**< IOB interrupt enable */ 3838 uint64_t mio : 1; /**< MIO boot interrupt enable */ 3839 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 3840 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 3841 uint64_t reserved_10_17 : 8; 3842 uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */ 3843#else 3844 uint64_t wdog : 10; 3845 uint64_t reserved_10_17 : 8; 3846 uint64_t mii1 : 1; 3847 uint64_t nand : 1; 3848 uint64_t mio : 1; 3849 uint64_t iob : 1; 3850 uint64_t fpa : 1; 3851 uint64_t pow : 1; 3852 uint64_t l2c : 1; 3853 uint64_t ipd : 1; 3854 uint64_t pip : 1; 3855 uint64_t pko : 1; 3856 uint64_t zip : 1; 3857 uint64_t tim : 1; 3858 uint64_t rad : 1; 3859 uint64_t key : 1; 3860 uint64_t dfa : 1; 3861 uint64_t usb : 1; 3862 uint64_t sli : 1; 3863 uint64_t dpi : 1; 3864 uint64_t agx0 : 1; 3865 uint64_t agx1 : 1; 3866 uint64_t reserved_38_45 : 8; 3867 uint64_t agl : 1; 3868 uint64_t ptp : 1; 3869 uint64_t pem0 : 1; 3870 uint64_t pem1 : 1; 3871 uint64_t srio0 : 1; 3872 uint64_t reserved_51_51 : 1; 3873 uint64_t lmc0 : 1; 3874 uint64_t reserved_53_55 : 3; 3875 uint64_t dfm : 1; 3876 uint64_t reserved_57_59 : 3; 3877 uint64_t srio2 : 1; 3878 uint64_t srio3 : 1; 3879 uint64_t reserved_62_62 : 1; 3880 uint64_t rst : 1; 3881#endif 3882 } cn66xx; 3883 struct cvmx_ciu_intx_en1_cnf71xx { 3884#ifdef __BIG_ENDIAN_BITFIELD 3885 uint64_t rst : 1; /**< MIO RST interrupt enable */ 3886 uint64_t reserved_53_62 : 10; 3887 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 3888 uint64_t reserved_50_51 : 2; 3889 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 3890 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 3891 uint64_t ptp : 1; /**< PTP interrupt enable */ 3892 uint64_t reserved_41_46 : 6; 3893 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 3894 uint64_t reserved_37_39 : 3; 3895 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 3896 uint64_t dpi : 1; /**< DPI interrupt enable */ 3897 uint64_t sli : 1; /**< SLI interrupt enable */ 3898 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 3899 uint64_t reserved_32_32 : 1; 3900 uint64_t key : 1; /**< KEY interrupt enable */ 3901 uint64_t rad : 1; /**< RAD interrupt enable */ 3902 uint64_t tim : 1; /**< TIM interrupt enable */ 3903 uint64_t reserved_28_28 : 1; 3904 uint64_t pko : 1; /**< PKO interrupt enable */ 3905 uint64_t pip : 1; /**< PIP interrupt enable */ 3906 uint64_t ipd : 1; /**< IPD interrupt enable */ 3907 uint64_t l2c : 1; /**< L2C interrupt enable */ 3908 uint64_t pow : 1; /**< POW err interrupt enable */ 3909 uint64_t fpa : 1; /**< FPA interrupt enable */ 3910 uint64_t iob : 1; /**< IOB interrupt enable */ 3911 uint64_t mio : 1; /**< MIO boot interrupt enable */ 3912 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 3913 uint64_t reserved_4_18 : 15; 3914 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3915#else 3916 uint64_t wdog : 4; 3917 uint64_t reserved_4_18 : 15; 3918 uint64_t nand : 1; 3919 uint64_t mio : 1; 3920 uint64_t iob : 1; 3921 uint64_t fpa : 1; 3922 uint64_t pow : 1; 3923 uint64_t l2c : 1; 3924 uint64_t ipd : 1; 3925 uint64_t pip : 1; 3926 uint64_t pko : 1; 3927 uint64_t reserved_28_28 : 1; 3928 uint64_t tim : 1; 3929 uint64_t rad : 1; 3930 uint64_t key : 1; 3931 uint64_t reserved_32_32 : 1; 3932 uint64_t usb : 1; 3933 uint64_t sli : 1; 3934 uint64_t dpi : 1; 3935 uint64_t agx0 : 1; 3936 uint64_t reserved_37_39 : 3; 3937 uint64_t dpi_dma : 1; 3938 uint64_t reserved_41_46 : 6; 3939 uint64_t ptp : 1; 3940 uint64_t pem0 : 1; 3941 uint64_t pem1 : 1; 3942 uint64_t reserved_50_51 : 2; 3943 uint64_t lmc0 : 1; 3944 uint64_t reserved_53_62 : 10; 3945 uint64_t rst : 1; 3946#endif 3947 } cnf71xx; 3948}; 3949typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t; 3950 3951/** 3952 * cvmx_ciu_int#_en1_w1c 3953 * 3954 * Notes: 3955 * Write-1-to-clear version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value. 3956 * 3957 */ 3958union cvmx_ciu_intx_en1_w1c { 3959 uint64_t u64; 3960 struct cvmx_ciu_intx_en1_w1c_s { 3961#ifdef __BIG_ENDIAN_BITFIELD 3962 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 3963 uint64_t reserved_62_62 : 1; 3964 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */ 3965 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */ 3966 uint64_t reserved_57_59 : 3; 3967 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 3968 uint64_t reserved_53_55 : 3; 3969 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 3970 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 3971 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 3972 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 3973 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 3974 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 3975 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 3976 uint64_t reserved_41_45 : 5; 3977 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 3978 uint64_t reserved_38_39 : 2; 3979 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 3980 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 3981 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 3982 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 3983 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 3984 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 3985 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 3986 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 3987 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 3988 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 3989 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 3990 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 3991 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 3992 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 3993 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 3994 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 3995 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 3996 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 3997 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 3998 enable */ 3999 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 4000 Interrupt enable */ 4001 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4002 uint64_t uart2 : 1; /**< Third UART interrupt */ 4003 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */ 4004#else 4005 uint64_t wdog : 16; 4006 uint64_t uart2 : 1; 4007 uint64_t usb1 : 1; 4008 uint64_t mii1 : 1; 4009 uint64_t nand : 1; 4010 uint64_t mio : 1; 4011 uint64_t iob : 1; 4012 uint64_t fpa : 1; 4013 uint64_t pow : 1; 4014 uint64_t l2c : 1; 4015 uint64_t ipd : 1; 4016 uint64_t pip : 1; 4017 uint64_t pko : 1; 4018 uint64_t zip : 1; 4019 uint64_t tim : 1; 4020 uint64_t rad : 1; 4021 uint64_t key : 1; 4022 uint64_t dfa : 1; 4023 uint64_t usb : 1; 4024 uint64_t sli : 1; 4025 uint64_t dpi : 1; 4026 uint64_t agx0 : 1; 4027 uint64_t agx1 : 1; 4028 uint64_t reserved_38_39 : 2; 4029 uint64_t dpi_dma : 1; 4030 uint64_t reserved_41_45 : 5; 4031 uint64_t agl : 1; 4032 uint64_t ptp : 1; 4033 uint64_t pem0 : 1; 4034 uint64_t pem1 : 1; 4035 uint64_t srio0 : 1; 4036 uint64_t srio1 : 1; 4037 uint64_t lmc0 : 1; 4038 uint64_t reserved_53_55 : 3; 4039 uint64_t dfm : 1; 4040 uint64_t reserved_57_59 : 3; 4041 uint64_t srio2 : 1; 4042 uint64_t srio3 : 1; 4043 uint64_t reserved_62_62 : 1; 4044 uint64_t rst : 1; 4045#endif 4046 } s; 4047 struct cvmx_ciu_intx_en1_w1c_cn52xx { 4048#ifdef __BIG_ENDIAN_BITFIELD 4049 uint64_t reserved_20_63 : 44; 4050 uint64_t nand : 1; /**< NAND Flash Controller */ 4051 uint64_t mii1 : 1; /**< Second MII Interrupt */ 4052 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4053 uint64_t uart2 : 1; /**< Third UART interrupt */ 4054 uint64_t reserved_4_15 : 12; 4055 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 4056#else 4057 uint64_t wdog : 4; 4058 uint64_t reserved_4_15 : 12; 4059 uint64_t uart2 : 1; 4060 uint64_t usb1 : 1; 4061 uint64_t mii1 : 1; 4062 uint64_t nand : 1; 4063 uint64_t reserved_20_63 : 44; 4064#endif 4065 } cn52xx; 4066 struct cvmx_ciu_intx_en1_w1c_cn56xx { 4067#ifdef __BIG_ENDIAN_BITFIELD 4068 uint64_t reserved_12_63 : 52; 4069 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 4070#else 4071 uint64_t wdog : 12; 4072 uint64_t reserved_12_63 : 52; 4073#endif 4074 } cn56xx; 4075 struct cvmx_ciu_intx_en1_w1c_cn58xx { 4076#ifdef __BIG_ENDIAN_BITFIELD 4077 uint64_t reserved_16_63 : 48; 4078 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 4079#else 4080 uint64_t wdog : 16; 4081 uint64_t reserved_16_63 : 48; 4082#endif 4083 } cn58xx; 4084 struct cvmx_ciu_intx_en1_w1c_cn61xx { 4085#ifdef __BIG_ENDIAN_BITFIELD 4086 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 4087 uint64_t reserved_53_62 : 10; 4088 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 4089 uint64_t reserved_50_51 : 2; 4090 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 4091 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 4092 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 4093 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 4094 uint64_t reserved_41_45 : 5; 4095 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 4096 uint64_t reserved_38_39 : 2; 4097 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 4098 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 4099 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 4100 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 4101 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 4102 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 4103 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 4104 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 4105 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 4106 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 4107 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 4108 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 4109 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 4110 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 4111 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 4112 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 4113 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 4114 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 4115 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 4116 enable */ 4117 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1 4118 Interrupt enable */ 4119 uint64_t reserved_4_17 : 14; 4120 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */ 4121#else 4122 uint64_t wdog : 4; 4123 uint64_t reserved_4_17 : 14; 4124 uint64_t mii1 : 1; 4125 uint64_t nand : 1; 4126 uint64_t mio : 1; 4127 uint64_t iob : 1; 4128 uint64_t fpa : 1; 4129 uint64_t pow : 1; 4130 uint64_t l2c : 1; 4131 uint64_t ipd : 1; 4132 uint64_t pip : 1; 4133 uint64_t pko : 1; 4134 uint64_t zip : 1; 4135 uint64_t tim : 1; 4136 uint64_t rad : 1; 4137 uint64_t key : 1; 4138 uint64_t dfa : 1; 4139 uint64_t usb : 1; 4140 uint64_t sli : 1; 4141 uint64_t dpi : 1; 4142 uint64_t agx0 : 1; 4143 uint64_t agx1 : 1; 4144 uint64_t reserved_38_39 : 2; 4145 uint64_t dpi_dma : 1; 4146 uint64_t reserved_41_45 : 5; 4147 uint64_t agl : 1; 4148 uint64_t ptp : 1; 4149 uint64_t pem0 : 1; 4150 uint64_t pem1 : 1; 4151 uint64_t reserved_50_51 : 2; 4152 uint64_t lmc0 : 1; 4153 uint64_t reserved_53_62 : 10; 4154 uint64_t rst : 1; 4155#endif 4156 } cn61xx; 4157 struct cvmx_ciu_intx_en1_w1c_cn63xx { 4158#ifdef __BIG_ENDIAN_BITFIELD 4159 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 4160 uint64_t reserved_57_62 : 6; 4161 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 4162 uint64_t reserved_53_55 : 3; 4163 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 4164 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 4165 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 4166 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 4167 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 4168 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 4169 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 4170 uint64_t reserved_37_45 : 9; 4171 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 4172 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 4173 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 4174 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 4175 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 4176 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 4177 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 4178 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 4179 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 4180 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 4181 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 4182 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 4183 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 4184 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 4185 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 4186 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 4187 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 4188 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 4189 enable */ 4190 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 4191 Interrupt enable */ 4192 uint64_t reserved_6_17 : 12; 4193 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */ 4194#else 4195 uint64_t wdog : 6; 4196 uint64_t reserved_6_17 : 12; 4197 uint64_t mii1 : 1; 4198 uint64_t nand : 1; 4199 uint64_t mio : 1; 4200 uint64_t iob : 1; 4201 uint64_t fpa : 1; 4202 uint64_t pow : 1; 4203 uint64_t l2c : 1; 4204 uint64_t ipd : 1; 4205 uint64_t pip : 1; 4206 uint64_t pko : 1; 4207 uint64_t zip : 1; 4208 uint64_t tim : 1; 4209 uint64_t rad : 1; 4210 uint64_t key : 1; 4211 uint64_t dfa : 1; 4212 uint64_t usb : 1; 4213 uint64_t sli : 1; 4214 uint64_t dpi : 1; 4215 uint64_t agx0 : 1; 4216 uint64_t reserved_37_45 : 9; 4217 uint64_t agl : 1; 4218 uint64_t ptp : 1; 4219 uint64_t pem0 : 1; 4220 uint64_t pem1 : 1; 4221 uint64_t srio0 : 1; 4222 uint64_t srio1 : 1; 4223 uint64_t lmc0 : 1; 4224 uint64_t reserved_53_55 : 3; 4225 uint64_t dfm : 1; 4226 uint64_t reserved_57_62 : 6; 4227 uint64_t rst : 1; 4228#endif 4229 } cn63xx; 4230 struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; 4231 struct cvmx_ciu_intx_en1_w1c_cn66xx { 4232#ifdef __BIG_ENDIAN_BITFIELD 4233 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 4234 uint64_t reserved_62_62 : 1; 4235 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */ 4236 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */ 4237 uint64_t reserved_57_59 : 3; 4238 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 4239 uint64_t reserved_53_55 : 3; 4240 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 4241 uint64_t reserved_51_51 : 1; 4242 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 4243 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 4244 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 4245 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 4246 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 4247 uint64_t reserved_38_45 : 8; 4248 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 4249 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 4250 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 4251 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 4252 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 4253 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 4254 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 4255 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 4256 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 4257 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 4258 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 4259 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 4260 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 4261 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 4262 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 4263 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 4264 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 4265 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 4266 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 4267 enable */ 4268 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 4269 Interrupt enable */ 4270 uint64_t reserved_10_17 : 8; 4271 uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */ 4272#else 4273 uint64_t wdog : 10; 4274 uint64_t reserved_10_17 : 8; 4275 uint64_t mii1 : 1; 4276 uint64_t nand : 1; 4277 uint64_t mio : 1; 4278 uint64_t iob : 1; 4279 uint64_t fpa : 1; 4280 uint64_t pow : 1; 4281 uint64_t l2c : 1; 4282 uint64_t ipd : 1; 4283 uint64_t pip : 1; 4284 uint64_t pko : 1; 4285 uint64_t zip : 1; 4286 uint64_t tim : 1; 4287 uint64_t rad : 1; 4288 uint64_t key : 1; 4289 uint64_t dfa : 1; 4290 uint64_t usb : 1; 4291 uint64_t sli : 1; 4292 uint64_t dpi : 1; 4293 uint64_t agx0 : 1; 4294 uint64_t agx1 : 1; 4295 uint64_t reserved_38_45 : 8; 4296 uint64_t agl : 1; 4297 uint64_t ptp : 1; 4298 uint64_t pem0 : 1; 4299 uint64_t pem1 : 1; 4300 uint64_t srio0 : 1; 4301 uint64_t reserved_51_51 : 1; 4302 uint64_t lmc0 : 1; 4303 uint64_t reserved_53_55 : 3; 4304 uint64_t dfm : 1; 4305 uint64_t reserved_57_59 : 3; 4306 uint64_t srio2 : 1; 4307 uint64_t srio3 : 1; 4308 uint64_t reserved_62_62 : 1; 4309 uint64_t rst : 1; 4310#endif 4311 } cn66xx; 4312 struct cvmx_ciu_intx_en1_w1c_cnf71xx { 4313#ifdef __BIG_ENDIAN_BITFIELD 4314 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 4315 uint64_t reserved_53_62 : 10; 4316 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 4317 uint64_t reserved_50_51 : 2; 4318 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 4319 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 4320 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 4321 uint64_t reserved_41_46 : 6; 4322 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 4323 uint64_t reserved_37_39 : 3; 4324 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 4325 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 4326 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 4327 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 4328 uint64_t reserved_32_32 : 1; 4329 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 4330 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 4331 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 4332 uint64_t reserved_28_28 : 1; 4333 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 4334 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 4335 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 4336 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 4337 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 4338 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 4339 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 4340 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 4341 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 4342 enable */ 4343 uint64_t reserved_4_18 : 15; 4344 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */ 4345#else 4346 uint64_t wdog : 4; 4347 uint64_t reserved_4_18 : 15; 4348 uint64_t nand : 1; 4349 uint64_t mio : 1; 4350 uint64_t iob : 1; 4351 uint64_t fpa : 1; 4352 uint64_t pow : 1; 4353 uint64_t l2c : 1; 4354 uint64_t ipd : 1; 4355 uint64_t pip : 1; 4356 uint64_t pko : 1; 4357 uint64_t reserved_28_28 : 1; 4358 uint64_t tim : 1; 4359 uint64_t rad : 1; 4360 uint64_t key : 1; 4361 uint64_t reserved_32_32 : 1; 4362 uint64_t usb : 1; 4363 uint64_t sli : 1; 4364 uint64_t dpi : 1; 4365 uint64_t agx0 : 1; 4366 uint64_t reserved_37_39 : 3; 4367 uint64_t dpi_dma : 1; 4368 uint64_t reserved_41_46 : 6; 4369 uint64_t ptp : 1; 4370 uint64_t pem0 : 1; 4371 uint64_t pem1 : 1; 4372 uint64_t reserved_50_51 : 2; 4373 uint64_t lmc0 : 1; 4374 uint64_t reserved_53_62 : 10; 4375 uint64_t rst : 1; 4376#endif 4377 } cnf71xx; 4378}; 4379typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t; 4380 4381/** 4382 * cvmx_ciu_int#_en1_w1s 4383 * 4384 * Notes: 4385 * Write-1-to-set version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value. 4386 * 4387 */ 4388union cvmx_ciu_intx_en1_w1s { 4389 uint64_t u64; 4390 struct cvmx_ciu_intx_en1_w1s_s { 4391#ifdef __BIG_ENDIAN_BITFIELD 4392 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 4393 uint64_t reserved_62_62 : 1; 4394 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */ 4395 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */ 4396 uint64_t reserved_57_59 : 3; 4397 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 4398 uint64_t reserved_53_55 : 3; 4399 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 4400 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 4401 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 4402 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 4403 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 4404 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 4405 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 4406 uint64_t reserved_41_45 : 5; 4407 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 4408 uint64_t reserved_38_39 : 2; 4409 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 4410 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 4411 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 4412 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 4413 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 4414 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 4415 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 4416 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 4417 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 4418 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 4419 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 4420 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 4421 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 4422 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 4423 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 4424 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 4425 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 4426 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 4427 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 4428 enable */ 4429 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 4430 enable */ 4431 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4432 uint64_t uart2 : 1; /**< Third UART interrupt */ 4433 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */ 4434#else 4435 uint64_t wdog : 16; 4436 uint64_t uart2 : 1; 4437 uint64_t usb1 : 1; 4438 uint64_t mii1 : 1; 4439 uint64_t nand : 1; 4440 uint64_t mio : 1; 4441 uint64_t iob : 1; 4442 uint64_t fpa : 1; 4443 uint64_t pow : 1; 4444 uint64_t l2c : 1; 4445 uint64_t ipd : 1; 4446 uint64_t pip : 1; 4447 uint64_t pko : 1; 4448 uint64_t zip : 1; 4449 uint64_t tim : 1; 4450 uint64_t rad : 1; 4451 uint64_t key : 1; 4452 uint64_t dfa : 1; 4453 uint64_t usb : 1; 4454 uint64_t sli : 1; 4455 uint64_t dpi : 1; 4456 uint64_t agx0 : 1; 4457 uint64_t agx1 : 1; 4458 uint64_t reserved_38_39 : 2; 4459 uint64_t dpi_dma : 1; 4460 uint64_t reserved_41_45 : 5; 4461 uint64_t agl : 1; 4462 uint64_t ptp : 1; 4463 uint64_t pem0 : 1; 4464 uint64_t pem1 : 1; 4465 uint64_t srio0 : 1; 4466 uint64_t srio1 : 1; 4467 uint64_t lmc0 : 1; 4468 uint64_t reserved_53_55 : 3; 4469 uint64_t dfm : 1; 4470 uint64_t reserved_57_59 : 3; 4471 uint64_t srio2 : 1; 4472 uint64_t srio3 : 1; 4473 uint64_t reserved_62_62 : 1; 4474 uint64_t rst : 1; 4475#endif 4476 } s; 4477 struct cvmx_ciu_intx_en1_w1s_cn52xx { 4478#ifdef __BIG_ENDIAN_BITFIELD 4479 uint64_t reserved_20_63 : 44; 4480 uint64_t nand : 1; /**< NAND Flash Controller */ 4481 uint64_t mii1 : 1; /**< Second MII Interrupt */ 4482 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4483 uint64_t uart2 : 1; /**< Third UART interrupt */ 4484 uint64_t reserved_4_15 : 12; 4485 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 4486#else 4487 uint64_t wdog : 4; 4488 uint64_t reserved_4_15 : 12; 4489 uint64_t uart2 : 1; 4490 uint64_t usb1 : 1; 4491 uint64_t mii1 : 1; 4492 uint64_t nand : 1; 4493 uint64_t reserved_20_63 : 44; 4494#endif 4495 } cn52xx; 4496 struct cvmx_ciu_intx_en1_w1s_cn56xx { 4497#ifdef __BIG_ENDIAN_BITFIELD 4498 uint64_t reserved_12_63 : 52; 4499 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 4500#else 4501 uint64_t wdog : 12; 4502 uint64_t reserved_12_63 : 52; 4503#endif 4504 } cn56xx; 4505 struct cvmx_ciu_intx_en1_w1s_cn58xx { 4506#ifdef __BIG_ENDIAN_BITFIELD 4507 uint64_t reserved_16_63 : 48; 4508 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 4509#else 4510 uint64_t wdog : 16; 4511 uint64_t reserved_16_63 : 48; 4512#endif 4513 } cn58xx; 4514 struct cvmx_ciu_intx_en1_w1s_cn61xx { 4515#ifdef __BIG_ENDIAN_BITFIELD 4516 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 4517 uint64_t reserved_53_62 : 10; 4518 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 4519 uint64_t reserved_50_51 : 2; 4520 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 4521 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 4522 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 4523 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 4524 uint64_t reserved_41_45 : 5; 4525 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 4526 uint64_t reserved_38_39 : 2; 4527 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 4528 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 4529 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 4530 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 4531 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 4532 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 4533 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 4534 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 4535 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 4536 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 4537 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 4538 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 4539 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 4540 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 4541 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 4542 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 4543 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 4544 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 4545 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 4546 enable */ 4547 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt 4548 enable */ 4549 uint64_t reserved_4_17 : 14; 4550 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */ 4551#else 4552 uint64_t wdog : 4; 4553 uint64_t reserved_4_17 : 14; 4554 uint64_t mii1 : 1; 4555 uint64_t nand : 1; 4556 uint64_t mio : 1; 4557 uint64_t iob : 1; 4558 uint64_t fpa : 1; 4559 uint64_t pow : 1; 4560 uint64_t l2c : 1; 4561 uint64_t ipd : 1; 4562 uint64_t pip : 1; 4563 uint64_t pko : 1; 4564 uint64_t zip : 1; 4565 uint64_t tim : 1; 4566 uint64_t rad : 1; 4567 uint64_t key : 1; 4568 uint64_t dfa : 1; 4569 uint64_t usb : 1; 4570 uint64_t sli : 1; 4571 uint64_t dpi : 1; 4572 uint64_t agx0 : 1; 4573 uint64_t agx1 : 1; 4574 uint64_t reserved_38_39 : 2; 4575 uint64_t dpi_dma : 1; 4576 uint64_t reserved_41_45 : 5; 4577 uint64_t agl : 1; 4578 uint64_t ptp : 1; 4579 uint64_t pem0 : 1; 4580 uint64_t pem1 : 1; 4581 uint64_t reserved_50_51 : 2; 4582 uint64_t lmc0 : 1; 4583 uint64_t reserved_53_62 : 10; 4584 uint64_t rst : 1; 4585#endif 4586 } cn61xx; 4587 struct cvmx_ciu_intx_en1_w1s_cn63xx { 4588#ifdef __BIG_ENDIAN_BITFIELD 4589 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 4590 uint64_t reserved_57_62 : 6; 4591 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 4592 uint64_t reserved_53_55 : 3; 4593 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 4594 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 4595 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 4596 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 4597 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 4598 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 4599 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 4600 uint64_t reserved_37_45 : 9; 4601 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 4602 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 4603 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 4604 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 4605 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 4606 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 4607 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 4608 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 4609 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 4610 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 4611 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 4612 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 4613 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 4614 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 4615 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 4616 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 4617 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 4618 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 4619 enable */ 4620 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 4621 enable */ 4622 uint64_t reserved_6_17 : 12; 4623 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */ 4624#else 4625 uint64_t wdog : 6; 4626 uint64_t reserved_6_17 : 12; 4627 uint64_t mii1 : 1; 4628 uint64_t nand : 1; 4629 uint64_t mio : 1; 4630 uint64_t iob : 1; 4631 uint64_t fpa : 1; 4632 uint64_t pow : 1; 4633 uint64_t l2c : 1; 4634 uint64_t ipd : 1; 4635 uint64_t pip : 1; 4636 uint64_t pko : 1; 4637 uint64_t zip : 1; 4638 uint64_t tim : 1; 4639 uint64_t rad : 1; 4640 uint64_t key : 1; 4641 uint64_t dfa : 1; 4642 uint64_t usb : 1; 4643 uint64_t sli : 1; 4644 uint64_t dpi : 1; 4645 uint64_t agx0 : 1; 4646 uint64_t reserved_37_45 : 9; 4647 uint64_t agl : 1; 4648 uint64_t ptp : 1; 4649 uint64_t pem0 : 1; 4650 uint64_t pem1 : 1; 4651 uint64_t srio0 : 1; 4652 uint64_t srio1 : 1; 4653 uint64_t lmc0 : 1; 4654 uint64_t reserved_53_55 : 3; 4655 uint64_t dfm : 1; 4656 uint64_t reserved_57_62 : 6; 4657 uint64_t rst : 1; 4658#endif 4659 } cn63xx; 4660 struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; 4661 struct cvmx_ciu_intx_en1_w1s_cn66xx { 4662#ifdef __BIG_ENDIAN_BITFIELD 4663 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 4664 uint64_t reserved_62_62 : 1; 4665 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */ 4666 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */ 4667 uint64_t reserved_57_59 : 3; 4668 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 4669 uint64_t reserved_53_55 : 3; 4670 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 4671 uint64_t reserved_51_51 : 1; 4672 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 4673 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 4674 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 4675 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 4676 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 4677 uint64_t reserved_38_45 : 8; 4678 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 4679 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 4680 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 4681 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 4682 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 4683 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 4684 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 4685 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 4686 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 4687 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 4688 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 4689 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 4690 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 4691 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 4692 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 4693 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 4694 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 4695 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 4696 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 4697 enable */ 4698 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 4699 enable */ 4700 uint64_t reserved_10_17 : 8; 4701 uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */ 4702#else 4703 uint64_t wdog : 10; 4704 uint64_t reserved_10_17 : 8; 4705 uint64_t mii1 : 1; 4706 uint64_t nand : 1; 4707 uint64_t mio : 1; 4708 uint64_t iob : 1; 4709 uint64_t fpa : 1; 4710 uint64_t pow : 1; 4711 uint64_t l2c : 1; 4712 uint64_t ipd : 1; 4713 uint64_t pip : 1; 4714 uint64_t pko : 1; 4715 uint64_t zip : 1; 4716 uint64_t tim : 1; 4717 uint64_t rad : 1; 4718 uint64_t key : 1; 4719 uint64_t dfa : 1; 4720 uint64_t usb : 1; 4721 uint64_t sli : 1; 4722 uint64_t dpi : 1; 4723 uint64_t agx0 : 1; 4724 uint64_t agx1 : 1; 4725 uint64_t reserved_38_45 : 8; 4726 uint64_t agl : 1; 4727 uint64_t ptp : 1; 4728 uint64_t pem0 : 1; 4729 uint64_t pem1 : 1; 4730 uint64_t srio0 : 1; 4731 uint64_t reserved_51_51 : 1; 4732 uint64_t lmc0 : 1; 4733 uint64_t reserved_53_55 : 3; 4734 uint64_t dfm : 1; 4735 uint64_t reserved_57_59 : 3; 4736 uint64_t srio2 : 1; 4737 uint64_t srio3 : 1; 4738 uint64_t reserved_62_62 : 1; 4739 uint64_t rst : 1; 4740#endif 4741 } cn66xx; 4742 struct cvmx_ciu_intx_en1_w1s_cnf71xx { 4743#ifdef __BIG_ENDIAN_BITFIELD 4744 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 4745 uint64_t reserved_53_62 : 10; 4746 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 4747 uint64_t reserved_50_51 : 2; 4748 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 4749 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 4750 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 4751 uint64_t reserved_41_46 : 6; 4752 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 4753 uint64_t reserved_37_39 : 3; 4754 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 4755 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 4756 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 4757 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 4758 uint64_t reserved_32_32 : 1; 4759 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 4760 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 4761 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 4762 uint64_t reserved_28_28 : 1; 4763 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 4764 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 4765 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 4766 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 4767 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 4768 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 4769 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 4770 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 4771 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 4772 enable */ 4773 uint64_t reserved_4_18 : 15; 4774 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */ 4775#else 4776 uint64_t wdog : 4; 4777 uint64_t reserved_4_18 : 15; 4778 uint64_t nand : 1; 4779 uint64_t mio : 1; 4780 uint64_t iob : 1; 4781 uint64_t fpa : 1; 4782 uint64_t pow : 1; 4783 uint64_t l2c : 1; 4784 uint64_t ipd : 1; 4785 uint64_t pip : 1; 4786 uint64_t pko : 1; 4787 uint64_t reserved_28_28 : 1; 4788 uint64_t tim : 1; 4789 uint64_t rad : 1; 4790 uint64_t key : 1; 4791 uint64_t reserved_32_32 : 1; 4792 uint64_t usb : 1; 4793 uint64_t sli : 1; 4794 uint64_t dpi : 1; 4795 uint64_t agx0 : 1; 4796 uint64_t reserved_37_39 : 3; 4797 uint64_t dpi_dma : 1; 4798 uint64_t reserved_41_46 : 6; 4799 uint64_t ptp : 1; 4800 uint64_t pem0 : 1; 4801 uint64_t pem1 : 1; 4802 uint64_t reserved_50_51 : 2; 4803 uint64_t lmc0 : 1; 4804 uint64_t reserved_53_62 : 10; 4805 uint64_t rst : 1; 4806#endif 4807 } cnf71xx; 4808}; 4809typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t; 4810 4811/** 4812 * cvmx_ciu_int#_en4_0 4813 * 4814 * Notes: 4815 * CIU_INT0_EN4_0: PP0 /IP4 4816 * CIU_INT1_EN4_0: PP1 /IP4 4817 * ... 4818 * CIU_INT3_EN4_0: PP3 /IP4 4819 */ 4820union cvmx_ciu_intx_en4_0 { 4821 uint64_t u64; 4822 struct cvmx_ciu_intx_en4_0_s { 4823#ifdef __BIG_ENDIAN_BITFIELD 4824 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 4825 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 4826 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 4827 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 4828 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 4829 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 4830 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 4831 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 4832 uint64_t timer : 4; /**< General timer interrupt enables */ 4833 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 4834 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 4835 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 4836 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 4837 uint64_t rml : 1; /**< RML Interrupt enable */ 4838 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 4839 uint64_t reserved_44_44 : 1; 4840 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 4841 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 4842 uint64_t uart : 2; /**< Two UART interrupt enables */ 4843 uint64_t mbox : 2; /**< Two mailbox interrupt enables */ 4844 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 4845 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 4846#else 4847 uint64_t workq : 16; 4848 uint64_t gpio : 16; 4849 uint64_t mbox : 2; 4850 uint64_t uart : 2; 4851 uint64_t pci_int : 4; 4852 uint64_t pci_msi : 4; 4853 uint64_t reserved_44_44 : 1; 4854 uint64_t twsi : 1; 4855 uint64_t rml : 1; 4856 uint64_t trace : 1; 4857 uint64_t gmx_drp : 2; 4858 uint64_t ipd_drp : 1; 4859 uint64_t key_zero : 1; 4860 uint64_t timer : 4; 4861 uint64_t usb : 1; 4862 uint64_t pcm : 1; 4863 uint64_t mpi : 1; 4864 uint64_t twsi2 : 1; 4865 uint64_t powiq : 1; 4866 uint64_t ipdppthr : 1; 4867 uint64_t mii : 1; 4868 uint64_t bootdma : 1; 4869#endif 4870 } s; 4871 struct cvmx_ciu_intx_en4_0_cn50xx { 4872#ifdef __BIG_ENDIAN_BITFIELD 4873 uint64_t reserved_59_63 : 5; 4874 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 4875 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 4876 uint64_t usb : 1; /**< USB interrupt */ 4877 uint64_t timer : 4; /**< General timer interrupts */ 4878 uint64_t reserved_51_51 : 1; 4879 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 4880 uint64_t reserved_49_49 : 1; 4881 uint64_t gmx_drp : 1; /**< GMX packet drop */ 4882 uint64_t reserved_47_47 : 1; 4883 uint64_t rml : 1; /**< RML Interrupt */ 4884 uint64_t twsi : 1; /**< TWSI Interrupt */ 4885 uint64_t reserved_44_44 : 1; 4886 uint64_t pci_msi : 4; /**< PCI MSI */ 4887 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 4888 uint64_t uart : 2; /**< Two UART interrupts */ 4889 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 4890 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 4891 uint64_t workq : 16; /**< 16 work queue interrupts */ 4892#else 4893 uint64_t workq : 16; 4894 uint64_t gpio : 16; 4895 uint64_t mbox : 2; 4896 uint64_t uart : 2; 4897 uint64_t pci_int : 4; 4898 uint64_t pci_msi : 4; 4899 uint64_t reserved_44_44 : 1; 4900 uint64_t twsi : 1; 4901 uint64_t rml : 1; 4902 uint64_t reserved_47_47 : 1; 4903 uint64_t gmx_drp : 1; 4904 uint64_t reserved_49_49 : 1; 4905 uint64_t ipd_drp : 1; 4906 uint64_t reserved_51_51 : 1; 4907 uint64_t timer : 4; 4908 uint64_t usb : 1; 4909 uint64_t pcm : 1; 4910 uint64_t mpi : 1; 4911 uint64_t reserved_59_63 : 5; 4912#endif 4913 } cn50xx; 4914 struct cvmx_ciu_intx_en4_0_cn52xx { 4915#ifdef __BIG_ENDIAN_BITFIELD 4916 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 4917 uint64_t mii : 1; /**< MII Interface Interrupt */ 4918 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 4919 uint64_t powiq : 1; /**< POW IQ interrupt */ 4920 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 4921 uint64_t reserved_57_58 : 2; 4922 uint64_t usb : 1; /**< USB Interrupt */ 4923 uint64_t timer : 4; /**< General timer interrupts */ 4924 uint64_t reserved_51_51 : 1; 4925 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 4926 uint64_t reserved_49_49 : 1; 4927 uint64_t gmx_drp : 1; /**< GMX packet drop */ 4928 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 4929 uint64_t rml : 1; /**< RML Interrupt */ 4930 uint64_t twsi : 1; /**< TWSI Interrupt */ 4931 uint64_t reserved_44_44 : 1; 4932 uint64_t pci_msi : 4; /**< PCI MSI */ 4933 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 4934 uint64_t uart : 2; /**< Two UART interrupts */ 4935 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 4936 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 4937 uint64_t workq : 16; /**< 16 work queue interrupts */ 4938#else 4939 uint64_t workq : 16; 4940 uint64_t gpio : 16; 4941 uint64_t mbox : 2; 4942 uint64_t uart : 2; 4943 uint64_t pci_int : 4; 4944 uint64_t pci_msi : 4; 4945 uint64_t reserved_44_44 : 1; 4946 uint64_t twsi : 1; 4947 uint64_t rml : 1; 4948 uint64_t trace : 1; 4949 uint64_t gmx_drp : 1; 4950 uint64_t reserved_49_49 : 1; 4951 uint64_t ipd_drp : 1; 4952 uint64_t reserved_51_51 : 1; 4953 uint64_t timer : 4; 4954 uint64_t usb : 1; 4955 uint64_t reserved_57_58 : 2; 4956 uint64_t twsi2 : 1; 4957 uint64_t powiq : 1; 4958 uint64_t ipdppthr : 1; 4959 uint64_t mii : 1; 4960 uint64_t bootdma : 1; 4961#endif 4962 } cn52xx; 4963 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; 4964 struct cvmx_ciu_intx_en4_0_cn56xx { 4965#ifdef __BIG_ENDIAN_BITFIELD 4966 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 4967 uint64_t mii : 1; /**< MII Interface Interrupt */ 4968 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 4969 uint64_t powiq : 1; /**< POW IQ interrupt */ 4970 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 4971 uint64_t reserved_57_58 : 2; 4972 uint64_t usb : 1; /**< USB Interrupt */ 4973 uint64_t timer : 4; /**< General timer interrupts */ 4974 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 4975 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 4976 uint64_t gmx_drp : 2; /**< GMX packet drop */ 4977 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 4978 uint64_t rml : 1; /**< RML Interrupt */ 4979 uint64_t twsi : 1; /**< TWSI Interrupt */ 4980 uint64_t reserved_44_44 : 1; 4981 uint64_t pci_msi : 4; /**< PCI MSI */ 4982 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 4983 uint64_t uart : 2; /**< Two UART interrupts */ 4984 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 4985 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 4986 uint64_t workq : 16; /**< 16 work queue interrupts */ 4987#else 4988 uint64_t workq : 16; 4989 uint64_t gpio : 16; 4990 uint64_t mbox : 2; 4991 uint64_t uart : 2; 4992 uint64_t pci_int : 4; 4993 uint64_t pci_msi : 4; 4994 uint64_t reserved_44_44 : 1; 4995 uint64_t twsi : 1; 4996 uint64_t rml : 1; 4997 uint64_t trace : 1; 4998 uint64_t gmx_drp : 2; 4999 uint64_t ipd_drp : 1; 5000 uint64_t key_zero : 1; 5001 uint64_t timer : 4; 5002 uint64_t usb : 1; 5003 uint64_t reserved_57_58 : 2; 5004 uint64_t twsi2 : 1; 5005 uint64_t powiq : 1; 5006 uint64_t ipdppthr : 1; 5007 uint64_t mii : 1; 5008 uint64_t bootdma : 1; 5009#endif 5010 } cn56xx; 5011 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; 5012 struct cvmx_ciu_intx_en4_0_cn58xx { 5013#ifdef __BIG_ENDIAN_BITFIELD 5014 uint64_t reserved_56_63 : 8; 5015 uint64_t timer : 4; /**< General timer interrupts */ 5016 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5017 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5018 uint64_t gmx_drp : 2; /**< GMX packet drop */ 5019 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5020 uint64_t rml : 1; /**< RML Interrupt */ 5021 uint64_t twsi : 1; /**< TWSI Interrupt */ 5022 uint64_t reserved_44_44 : 1; 5023 uint64_t pci_msi : 4; /**< PCI MSI */ 5024 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5025 uint64_t uart : 2; /**< Two UART interrupts */ 5026 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5027 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5028 uint64_t workq : 16; /**< 16 work queue interrupts */ 5029#else 5030 uint64_t workq : 16; 5031 uint64_t gpio : 16; 5032 uint64_t mbox : 2; 5033 uint64_t uart : 2; 5034 uint64_t pci_int : 4; 5035 uint64_t pci_msi : 4; 5036 uint64_t reserved_44_44 : 1; 5037 uint64_t twsi : 1; 5038 uint64_t rml : 1; 5039 uint64_t trace : 1; 5040 uint64_t gmx_drp : 2; 5041 uint64_t ipd_drp : 1; 5042 uint64_t key_zero : 1; 5043 uint64_t timer : 4; 5044 uint64_t reserved_56_63 : 8; 5045#endif 5046 } cn58xx; 5047 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; 5048 struct cvmx_ciu_intx_en4_0_cn61xx { 5049#ifdef __BIG_ENDIAN_BITFIELD 5050 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 5051 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */ 5052 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 5053 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 5054 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 5055 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 5056 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 5057 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 5058 uint64_t timer : 4; /**< General timer interrupt enables */ 5059 uint64_t reserved_51_51 : 1; 5060 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 5061 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 5062 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 5063 uint64_t rml : 1; /**< RML Interrupt enable */ 5064 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 5065 uint64_t reserved_44_44 : 1; 5066 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 5067 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 5068 uint64_t uart : 2; /**< Two UART interrupt enables */ 5069 uint64_t mbox : 2; /**< Two mailbox interrupt enables */ 5070 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 5071 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 5072#else 5073 uint64_t workq : 16; 5074 uint64_t gpio : 16; 5075 uint64_t mbox : 2; 5076 uint64_t uart : 2; 5077 uint64_t pci_int : 4; 5078 uint64_t pci_msi : 4; 5079 uint64_t reserved_44_44 : 1; 5080 uint64_t twsi : 1; 5081 uint64_t rml : 1; 5082 uint64_t trace : 1; 5083 uint64_t gmx_drp : 2; 5084 uint64_t ipd_drp : 1; 5085 uint64_t reserved_51_51 : 1; 5086 uint64_t timer : 4; 5087 uint64_t usb : 1; 5088 uint64_t pcm : 1; 5089 uint64_t mpi : 1; 5090 uint64_t twsi2 : 1; 5091 uint64_t powiq : 1; 5092 uint64_t ipdppthr : 1; 5093 uint64_t mii : 1; 5094 uint64_t bootdma : 1; 5095#endif 5096 } cn61xx; 5097 struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; 5098 struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; 5099 struct cvmx_ciu_intx_en4_0_cn66xx { 5100#ifdef __BIG_ENDIAN_BITFIELD 5101 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 5102 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 5103 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 5104 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 5105 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 5106 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 5107 uint64_t reserved_57_57 : 1; 5108 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 5109 uint64_t timer : 4; /**< General timer interrupt enables */ 5110 uint64_t reserved_51_51 : 1; 5111 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 5112 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 5113 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 5114 uint64_t rml : 1; /**< RML Interrupt enable */ 5115 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 5116 uint64_t reserved_44_44 : 1; 5117 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */ 5118 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 5119 uint64_t uart : 2; /**< Two UART interrupt enables */ 5120 uint64_t mbox : 2; /**< Two mailbox interrupt enables */ 5121 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 5122 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 5123#else 5124 uint64_t workq : 16; 5125 uint64_t gpio : 16; 5126 uint64_t mbox : 2; 5127 uint64_t uart : 2; 5128 uint64_t pci_int : 4; 5129 uint64_t pci_msi : 4; 5130 uint64_t reserved_44_44 : 1; 5131 uint64_t twsi : 1; 5132 uint64_t rml : 1; 5133 uint64_t trace : 1; 5134 uint64_t gmx_drp : 2; 5135 uint64_t ipd_drp : 1; 5136 uint64_t reserved_51_51 : 1; 5137 uint64_t timer : 4; 5138 uint64_t usb : 1; 5139 uint64_t reserved_57_57 : 1; 5140 uint64_t mpi : 1; 5141 uint64_t twsi2 : 1; 5142 uint64_t powiq : 1; 5143 uint64_t ipdppthr : 1; 5144 uint64_t mii : 1; 5145 uint64_t bootdma : 1; 5146#endif 5147 } cn66xx; 5148 struct cvmx_ciu_intx_en4_0_cnf71xx { 5149#ifdef __BIG_ENDIAN_BITFIELD 5150 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 5151 uint64_t reserved_62_62 : 1; 5152 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 5153 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 5154 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 5155 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */ 5156 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */ 5157 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 5158 uint64_t timer : 4; /**< General timer interrupt enables */ 5159 uint64_t reserved_51_51 : 1; 5160 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 5161 uint64_t reserved_49_49 : 1; 5162 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */ 5163 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 5164 uint64_t rml : 1; /**< RML Interrupt enable */ 5165 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 5166 uint64_t reserved_44_44 : 1; 5167 uint64_t pci_msi : 4; /**< PCIe MSI enables */ 5168 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 5169 uint64_t uart : 2; /**< Two UART interrupt enables */ 5170 uint64_t mbox : 2; /**< Two mailbox interrupt enables */ 5171 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 5172 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 5173#else 5174 uint64_t workq : 16; 5175 uint64_t gpio : 16; 5176 uint64_t mbox : 2; 5177 uint64_t uart : 2; 5178 uint64_t pci_int : 4; 5179 uint64_t pci_msi : 4; 5180 uint64_t reserved_44_44 : 1; 5181 uint64_t twsi : 1; 5182 uint64_t rml : 1; 5183 uint64_t trace : 1; 5184 uint64_t gmx_drp : 1; 5185 uint64_t reserved_49_49 : 1; 5186 uint64_t ipd_drp : 1; 5187 uint64_t reserved_51_51 : 1; 5188 uint64_t timer : 4; 5189 uint64_t usb : 1; 5190 uint64_t pcm : 1; 5191 uint64_t mpi : 1; 5192 uint64_t twsi2 : 1; 5193 uint64_t powiq : 1; 5194 uint64_t ipdppthr : 1; 5195 uint64_t reserved_62_62 : 1; 5196 uint64_t bootdma : 1; 5197#endif 5198 } cnf71xx; 5199}; 5200typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t; 5201 5202/** 5203 * cvmx_ciu_int#_en4_0_w1c 5204 * 5205 * Notes: 5206 * Write-1-to-clear version of the CIU_INTx_EN4_0 register, read back corresponding CIU_INTx_EN4_0 value. 5207 * 5208 */ 5209union cvmx_ciu_intx_en4_0_w1c { 5210 uint64_t u64; 5211 struct cvmx_ciu_intx_en4_0_w1c_s { 5212#ifdef __BIG_ENDIAN_BITFIELD 5213 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 5214 enable */ 5215 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 5216 enable */ 5217 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 5218 interrupt enable */ 5219 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 5220 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 5221 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 5222 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 5223 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 5224 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 5225 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5226 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 5227 enable */ 5228 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 5229 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 5230 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 5231 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 5232 uint64_t reserved_44_44 : 1; 5233 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 5234 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 5235 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 5236 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */ 5237 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 5238 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 5239#else 5240 uint64_t workq : 16; 5241 uint64_t gpio : 16; 5242 uint64_t mbox : 2; 5243 uint64_t uart : 2; 5244 uint64_t pci_int : 4; 5245 uint64_t pci_msi : 4; 5246 uint64_t reserved_44_44 : 1; 5247 uint64_t twsi : 1; 5248 uint64_t rml : 1; 5249 uint64_t trace : 1; 5250 uint64_t gmx_drp : 2; 5251 uint64_t ipd_drp : 1; 5252 uint64_t key_zero : 1; 5253 uint64_t timer : 4; 5254 uint64_t usb : 1; 5255 uint64_t pcm : 1; 5256 uint64_t mpi : 1; 5257 uint64_t twsi2 : 1; 5258 uint64_t powiq : 1; 5259 uint64_t ipdppthr : 1; 5260 uint64_t mii : 1; 5261 uint64_t bootdma : 1; 5262#endif 5263 } s; 5264 struct cvmx_ciu_intx_en4_0_w1c_cn52xx { 5265#ifdef __BIG_ENDIAN_BITFIELD 5266 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 5267 uint64_t mii : 1; /**< MII Interface Interrupt */ 5268 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 5269 uint64_t powiq : 1; /**< POW IQ interrupt */ 5270 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 5271 uint64_t reserved_57_58 : 2; 5272 uint64_t usb : 1; /**< USB Interrupt */ 5273 uint64_t timer : 4; /**< General timer interrupts */ 5274 uint64_t reserved_51_51 : 1; 5275 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5276 uint64_t reserved_49_49 : 1; 5277 uint64_t gmx_drp : 1; /**< GMX packet drop */ 5278 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5279 uint64_t rml : 1; /**< RML Interrupt */ 5280 uint64_t twsi : 1; /**< TWSI Interrupt */ 5281 uint64_t reserved_44_44 : 1; 5282 uint64_t pci_msi : 4; /**< PCI MSI */ 5283 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5284 uint64_t uart : 2; /**< Two UART interrupts */ 5285 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5286 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5287 uint64_t workq : 16; /**< 16 work queue interrupts */ 5288#else 5289 uint64_t workq : 16; 5290 uint64_t gpio : 16; 5291 uint64_t mbox : 2; 5292 uint64_t uart : 2; 5293 uint64_t pci_int : 4; 5294 uint64_t pci_msi : 4; 5295 uint64_t reserved_44_44 : 1; 5296 uint64_t twsi : 1; 5297 uint64_t rml : 1; 5298 uint64_t trace : 1; 5299 uint64_t gmx_drp : 1; 5300 uint64_t reserved_49_49 : 1; 5301 uint64_t ipd_drp : 1; 5302 uint64_t reserved_51_51 : 1; 5303 uint64_t timer : 4; 5304 uint64_t usb : 1; 5305 uint64_t reserved_57_58 : 2; 5306 uint64_t twsi2 : 1; 5307 uint64_t powiq : 1; 5308 uint64_t ipdppthr : 1; 5309 uint64_t mii : 1; 5310 uint64_t bootdma : 1; 5311#endif 5312 } cn52xx; 5313 struct cvmx_ciu_intx_en4_0_w1c_cn56xx { 5314#ifdef __BIG_ENDIAN_BITFIELD 5315 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 5316 uint64_t mii : 1; /**< MII Interface Interrupt */ 5317 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 5318 uint64_t powiq : 1; /**< POW IQ interrupt */ 5319 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 5320 uint64_t reserved_57_58 : 2; 5321 uint64_t usb : 1; /**< USB Interrupt */ 5322 uint64_t timer : 4; /**< General timer interrupts */ 5323 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5324 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5325 uint64_t gmx_drp : 2; /**< GMX packet drop */ 5326 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5327 uint64_t rml : 1; /**< RML Interrupt */ 5328 uint64_t twsi : 1; /**< TWSI Interrupt */ 5329 uint64_t reserved_44_44 : 1; 5330 uint64_t pci_msi : 4; /**< PCI MSI */ 5331 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5332 uint64_t uart : 2; /**< Two UART interrupts */ 5333 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5334 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5335 uint64_t workq : 16; /**< 16 work queue interrupts */ 5336#else 5337 uint64_t workq : 16; 5338 uint64_t gpio : 16; 5339 uint64_t mbox : 2; 5340 uint64_t uart : 2; 5341 uint64_t pci_int : 4; 5342 uint64_t pci_msi : 4; 5343 uint64_t reserved_44_44 : 1; 5344 uint64_t twsi : 1; 5345 uint64_t rml : 1; 5346 uint64_t trace : 1; 5347 uint64_t gmx_drp : 2; 5348 uint64_t ipd_drp : 1; 5349 uint64_t key_zero : 1; 5350 uint64_t timer : 4; 5351 uint64_t usb : 1; 5352 uint64_t reserved_57_58 : 2; 5353 uint64_t twsi2 : 1; 5354 uint64_t powiq : 1; 5355 uint64_t ipdppthr : 1; 5356 uint64_t mii : 1; 5357 uint64_t bootdma : 1; 5358#endif 5359 } cn56xx; 5360 struct cvmx_ciu_intx_en4_0_w1c_cn58xx { 5361#ifdef __BIG_ENDIAN_BITFIELD 5362 uint64_t reserved_56_63 : 8; 5363 uint64_t timer : 4; /**< General timer interrupts */ 5364 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5365 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5366 uint64_t gmx_drp : 2; /**< GMX packet drop */ 5367 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5368 uint64_t rml : 1; /**< RML Interrupt */ 5369 uint64_t twsi : 1; /**< TWSI Interrupt */ 5370 uint64_t reserved_44_44 : 1; 5371 uint64_t pci_msi : 4; /**< PCI MSI */ 5372 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5373 uint64_t uart : 2; /**< Two UART interrupts */ 5374 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5375 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5376 uint64_t workq : 16; /**< 16 work queue interrupts */ 5377#else 5378 uint64_t workq : 16; 5379 uint64_t gpio : 16; 5380 uint64_t mbox : 2; 5381 uint64_t uart : 2; 5382 uint64_t pci_int : 4; 5383 uint64_t pci_msi : 4; 5384 uint64_t reserved_44_44 : 1; 5385 uint64_t twsi : 1; 5386 uint64_t rml : 1; 5387 uint64_t trace : 1; 5388 uint64_t gmx_drp : 2; 5389 uint64_t ipd_drp : 1; 5390 uint64_t key_zero : 1; 5391 uint64_t timer : 4; 5392 uint64_t reserved_56_63 : 8; 5393#endif 5394 } cn58xx; 5395 struct cvmx_ciu_intx_en4_0_w1c_cn61xx { 5396#ifdef __BIG_ENDIAN_BITFIELD 5397 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 5398 enable */ 5399 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt 5400 enable */ 5401 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 5402 interrupt enable */ 5403 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 5404 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 5405 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 5406 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 5407 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 5408 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 5409 uint64_t reserved_51_51 : 1; 5410 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 5411 enable */ 5412 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 5413 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 5414 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 5415 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 5416 uint64_t reserved_44_44 : 1; 5417 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 5418 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 5419 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 5420 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */ 5421 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 5422 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 5423#else 5424 uint64_t workq : 16; 5425 uint64_t gpio : 16; 5426 uint64_t mbox : 2; 5427 uint64_t uart : 2; 5428 uint64_t pci_int : 4; 5429 uint64_t pci_msi : 4; 5430 uint64_t reserved_44_44 : 1; 5431 uint64_t twsi : 1; 5432 uint64_t rml : 1; 5433 uint64_t trace : 1; 5434 uint64_t gmx_drp : 2; 5435 uint64_t ipd_drp : 1; 5436 uint64_t reserved_51_51 : 1; 5437 uint64_t timer : 4; 5438 uint64_t usb : 1; 5439 uint64_t pcm : 1; 5440 uint64_t mpi : 1; 5441 uint64_t twsi2 : 1; 5442 uint64_t powiq : 1; 5443 uint64_t ipdppthr : 1; 5444 uint64_t mii : 1; 5445 uint64_t bootdma : 1; 5446#endif 5447 } cn61xx; 5448 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; 5449 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; 5450 struct cvmx_ciu_intx_en4_0_w1c_cn66xx { 5451#ifdef __BIG_ENDIAN_BITFIELD 5452 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 5453 enable */ 5454 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 5455 enable */ 5456 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 5457 interrupt enable */ 5458 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */ 5459 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */ 5460 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */ 5461 uint64_t reserved_57_57 : 1; 5462 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */ 5463 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */ 5464 uint64_t reserved_51_51 : 1; 5465 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 5466 enable */ 5467 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 5468 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 5469 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 5470 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 5471 uint64_t reserved_44_44 : 1; 5472 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */ 5473 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 5474 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 5475 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */ 5476 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 5477 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 5478#else 5479 uint64_t workq : 16; 5480 uint64_t gpio : 16; 5481 uint64_t mbox : 2; 5482 uint64_t uart : 2; 5483 uint64_t pci_int : 4; 5484 uint64_t pci_msi : 4; 5485 uint64_t reserved_44_44 : 1; 5486 uint64_t twsi : 1; 5487 uint64_t rml : 1; 5488 uint64_t trace : 1; 5489 uint64_t gmx_drp : 2; 5490 uint64_t ipd_drp : 1; 5491 uint64_t reserved_51_51 : 1; 5492 uint64_t timer : 4; 5493 uint64_t usb : 1; 5494 uint64_t reserved_57_57 : 1; 5495 uint64_t mpi : 1; 5496 uint64_t twsi2 : 1; 5497 uint64_t powiq : 1; 5498 uint64_t ipdppthr : 1; 5499 uint64_t mii : 1; 5500 uint64_t bootdma : 1; 5501#endif 5502 } cn66xx; 5503 struct cvmx_ciu_intx_en4_0_w1c_cnf71xx { 5504#ifdef __BIG_ENDIAN_BITFIELD 5505 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 5506 enable */ 5507 uint64_t reserved_62_62 : 1; 5508 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 5509 interrupt enable */ 5510 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */ 5511 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */ 5512 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */ 5513 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */ 5514 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */ 5515 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */ 5516 uint64_t reserved_51_51 : 1; 5517 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 5518 enable */ 5519 uint64_t reserved_49_49 : 1; 5520 uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */ 5521 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 5522 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 5523 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 5524 uint64_t reserved_44_44 : 1; 5525 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */ 5526 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 5527 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 5528 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */ 5529 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 5530 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 5531#else 5532 uint64_t workq : 16; 5533 uint64_t gpio : 16; 5534 uint64_t mbox : 2; 5535 uint64_t uart : 2; 5536 uint64_t pci_int : 4; 5537 uint64_t pci_msi : 4; 5538 uint64_t reserved_44_44 : 1; 5539 uint64_t twsi : 1; 5540 uint64_t rml : 1; 5541 uint64_t trace : 1; 5542 uint64_t gmx_drp : 1; 5543 uint64_t reserved_49_49 : 1; 5544 uint64_t ipd_drp : 1; 5545 uint64_t reserved_51_51 : 1; 5546 uint64_t timer : 4; 5547 uint64_t usb : 1; 5548 uint64_t pcm : 1; 5549 uint64_t mpi : 1; 5550 uint64_t twsi2 : 1; 5551 uint64_t powiq : 1; 5552 uint64_t ipdppthr : 1; 5553 uint64_t reserved_62_62 : 1; 5554 uint64_t bootdma : 1; 5555#endif 5556 } cnf71xx; 5557}; 5558typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t; 5559 5560/** 5561 * cvmx_ciu_int#_en4_0_w1s 5562 * 5563 * Notes: 5564 * Write-1-to-set version of the CIU_INTX_EN4_0 register, read back corresponding CIU_INTX_EN4_0 value. 5565 * 5566 */ 5567union cvmx_ciu_intx_en4_0_w1s { 5568 uint64_t u64; 5569 struct cvmx_ciu_intx_en4_0_w1s_s { 5570#ifdef __BIG_ENDIAN_BITFIELD 5571 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 5572 enable */ 5573 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 5574 enable */ 5575 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 5576 interrupt enable */ 5577 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 5578 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 5579 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 5580 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 5581 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 5582 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 5583 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5584 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 5585 enable */ 5586 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 5587 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 5588 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 5589 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 5590 uint64_t reserved_44_44 : 1; 5591 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 5592 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 5593 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 5594 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */ 5595 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 5596 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 5597#else 5598 uint64_t workq : 16; 5599 uint64_t gpio : 16; 5600 uint64_t mbox : 2; 5601 uint64_t uart : 2; 5602 uint64_t pci_int : 4; 5603 uint64_t pci_msi : 4; 5604 uint64_t reserved_44_44 : 1; 5605 uint64_t twsi : 1; 5606 uint64_t rml : 1; 5607 uint64_t trace : 1; 5608 uint64_t gmx_drp : 2; 5609 uint64_t ipd_drp : 1; 5610 uint64_t key_zero : 1; 5611 uint64_t timer : 4; 5612 uint64_t usb : 1; 5613 uint64_t pcm : 1; 5614 uint64_t mpi : 1; 5615 uint64_t twsi2 : 1; 5616 uint64_t powiq : 1; 5617 uint64_t ipdppthr : 1; 5618 uint64_t mii : 1; 5619 uint64_t bootdma : 1; 5620#endif 5621 } s; 5622 struct cvmx_ciu_intx_en4_0_w1s_cn52xx { 5623#ifdef __BIG_ENDIAN_BITFIELD 5624 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 5625 uint64_t mii : 1; /**< MII Interface Interrupt */ 5626 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 5627 uint64_t powiq : 1; /**< POW IQ interrupt */ 5628 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 5629 uint64_t reserved_57_58 : 2; 5630 uint64_t usb : 1; /**< USB Interrupt */ 5631 uint64_t timer : 4; /**< General timer interrupts */ 5632 uint64_t reserved_51_51 : 1; 5633 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5634 uint64_t reserved_49_49 : 1; 5635 uint64_t gmx_drp : 1; /**< GMX packet drop */ 5636 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5637 uint64_t rml : 1; /**< RML Interrupt */ 5638 uint64_t twsi : 1; /**< TWSI Interrupt */ 5639 uint64_t reserved_44_44 : 1; 5640 uint64_t pci_msi : 4; /**< PCI MSI */ 5641 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5642 uint64_t uart : 2; /**< Two UART interrupts */ 5643 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5644 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5645 uint64_t workq : 16; /**< 16 work queue interrupts */ 5646#else 5647 uint64_t workq : 16; 5648 uint64_t gpio : 16; 5649 uint64_t mbox : 2; 5650 uint64_t uart : 2; 5651 uint64_t pci_int : 4; 5652 uint64_t pci_msi : 4; 5653 uint64_t reserved_44_44 : 1; 5654 uint64_t twsi : 1; 5655 uint64_t rml : 1; 5656 uint64_t trace : 1; 5657 uint64_t gmx_drp : 1; 5658 uint64_t reserved_49_49 : 1; 5659 uint64_t ipd_drp : 1; 5660 uint64_t reserved_51_51 : 1; 5661 uint64_t timer : 4; 5662 uint64_t usb : 1; 5663 uint64_t reserved_57_58 : 2; 5664 uint64_t twsi2 : 1; 5665 uint64_t powiq : 1; 5666 uint64_t ipdppthr : 1; 5667 uint64_t mii : 1; 5668 uint64_t bootdma : 1; 5669#endif 5670 } cn52xx; 5671 struct cvmx_ciu_intx_en4_0_w1s_cn56xx { 5672#ifdef __BIG_ENDIAN_BITFIELD 5673 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 5674 uint64_t mii : 1; /**< MII Interface Interrupt */ 5675 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 5676 uint64_t powiq : 1; /**< POW IQ interrupt */ 5677 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 5678 uint64_t reserved_57_58 : 2; 5679 uint64_t usb : 1; /**< USB Interrupt */ 5680 uint64_t timer : 4; /**< General timer interrupts */ 5681 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5682 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5683 uint64_t gmx_drp : 2; /**< GMX packet drop */ 5684 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5685 uint64_t rml : 1; /**< RML Interrupt */ 5686 uint64_t twsi : 1; /**< TWSI Interrupt */ 5687 uint64_t reserved_44_44 : 1; 5688 uint64_t pci_msi : 4; /**< PCI MSI */ 5689 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5690 uint64_t uart : 2; /**< Two UART interrupts */ 5691 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5692 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5693 uint64_t workq : 16; /**< 16 work queue interrupts */ 5694#else 5695 uint64_t workq : 16; 5696 uint64_t gpio : 16; 5697 uint64_t mbox : 2; 5698 uint64_t uart : 2; 5699 uint64_t pci_int : 4; 5700 uint64_t pci_msi : 4; 5701 uint64_t reserved_44_44 : 1; 5702 uint64_t twsi : 1; 5703 uint64_t rml : 1; 5704 uint64_t trace : 1; 5705 uint64_t gmx_drp : 2; 5706 uint64_t ipd_drp : 1; 5707 uint64_t key_zero : 1; 5708 uint64_t timer : 4; 5709 uint64_t usb : 1; 5710 uint64_t reserved_57_58 : 2; 5711 uint64_t twsi2 : 1; 5712 uint64_t powiq : 1; 5713 uint64_t ipdppthr : 1; 5714 uint64_t mii : 1; 5715 uint64_t bootdma : 1; 5716#endif 5717 } cn56xx; 5718 struct cvmx_ciu_intx_en4_0_w1s_cn58xx { 5719#ifdef __BIG_ENDIAN_BITFIELD 5720 uint64_t reserved_56_63 : 8; 5721 uint64_t timer : 4; /**< General timer interrupts */ 5722 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 5723 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 5724 uint64_t gmx_drp : 2; /**< GMX packet drop */ 5725 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 5726 uint64_t rml : 1; /**< RML Interrupt */ 5727 uint64_t twsi : 1; /**< TWSI Interrupt */ 5728 uint64_t reserved_44_44 : 1; 5729 uint64_t pci_msi : 4; /**< PCI MSI */ 5730 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 5731 uint64_t uart : 2; /**< Two UART interrupts */ 5732 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 5733 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 5734 uint64_t workq : 16; /**< 16 work queue interrupts */ 5735#else 5736 uint64_t workq : 16; 5737 uint64_t gpio : 16; 5738 uint64_t mbox : 2; 5739 uint64_t uart : 2; 5740 uint64_t pci_int : 4; 5741 uint64_t pci_msi : 4; 5742 uint64_t reserved_44_44 : 1; 5743 uint64_t twsi : 1; 5744 uint64_t rml : 1; 5745 uint64_t trace : 1; 5746 uint64_t gmx_drp : 2; 5747 uint64_t ipd_drp : 1; 5748 uint64_t key_zero : 1; 5749 uint64_t timer : 4; 5750 uint64_t reserved_56_63 : 8; 5751#endif 5752 } cn58xx; 5753 struct cvmx_ciu_intx_en4_0_w1s_cn61xx { 5754#ifdef __BIG_ENDIAN_BITFIELD 5755 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 5756 enable */ 5757 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt 5758 enable */ 5759 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 5760 interrupt enable */ 5761 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 5762 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 5763 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 5764 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 5765 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 5766 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 5767 uint64_t reserved_51_51 : 1; 5768 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 5769 enable */ 5770 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 5771 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 5772 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 5773 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 5774 uint64_t reserved_44_44 : 1; 5775 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 5776 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 5777 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 5778 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */ 5779 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 5780 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 5781#else 5782 uint64_t workq : 16; 5783 uint64_t gpio : 16; 5784 uint64_t mbox : 2; 5785 uint64_t uart : 2; 5786 uint64_t pci_int : 4; 5787 uint64_t pci_msi : 4; 5788 uint64_t reserved_44_44 : 1; 5789 uint64_t twsi : 1; 5790 uint64_t rml : 1; 5791 uint64_t trace : 1; 5792 uint64_t gmx_drp : 2; 5793 uint64_t ipd_drp : 1; 5794 uint64_t reserved_51_51 : 1; 5795 uint64_t timer : 4; 5796 uint64_t usb : 1; 5797 uint64_t pcm : 1; 5798 uint64_t mpi : 1; 5799 uint64_t twsi2 : 1; 5800 uint64_t powiq : 1; 5801 uint64_t ipdppthr : 1; 5802 uint64_t mii : 1; 5803 uint64_t bootdma : 1; 5804#endif 5805 } cn61xx; 5806 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; 5807 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; 5808 struct cvmx_ciu_intx_en4_0_w1s_cn66xx { 5809#ifdef __BIG_ENDIAN_BITFIELD 5810 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 5811 enable */ 5812 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 5813 enable */ 5814 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 5815 interrupt enable */ 5816 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */ 5817 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */ 5818 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */ 5819 uint64_t reserved_57_57 : 1; 5820 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */ 5821 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */ 5822 uint64_t reserved_51_51 : 1; 5823 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 5824 enable */ 5825 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 5826 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 5827 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 5828 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 5829 uint64_t reserved_44_44 : 1; 5830 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */ 5831 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 5832 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 5833 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */ 5834 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 5835 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 5836#else 5837 uint64_t workq : 16; 5838 uint64_t gpio : 16; 5839 uint64_t mbox : 2; 5840 uint64_t uart : 2; 5841 uint64_t pci_int : 4; 5842 uint64_t pci_msi : 4; 5843 uint64_t reserved_44_44 : 1; 5844 uint64_t twsi : 1; 5845 uint64_t rml : 1; 5846 uint64_t trace : 1; 5847 uint64_t gmx_drp : 2; 5848 uint64_t ipd_drp : 1; 5849 uint64_t reserved_51_51 : 1; 5850 uint64_t timer : 4; 5851 uint64_t usb : 1; 5852 uint64_t reserved_57_57 : 1; 5853 uint64_t mpi : 1; 5854 uint64_t twsi2 : 1; 5855 uint64_t powiq : 1; 5856 uint64_t ipdppthr : 1; 5857 uint64_t mii : 1; 5858 uint64_t bootdma : 1; 5859#endif 5860 } cn66xx; 5861 struct cvmx_ciu_intx_en4_0_w1s_cnf71xx { 5862#ifdef __BIG_ENDIAN_BITFIELD 5863 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 5864 enable */ 5865 uint64_t reserved_62_62 : 1; 5866 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 5867 interrupt enable */ 5868 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */ 5869 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */ 5870 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */ 5871 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */ 5872 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */ 5873 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */ 5874 uint64_t reserved_51_51 : 1; 5875 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 5876 enable */ 5877 uint64_t reserved_49_49 : 1; 5878 uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */ 5879 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 5880 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 5881 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 5882 uint64_t reserved_44_44 : 1; 5883 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */ 5884 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 5885 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 5886 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */ 5887 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 5888 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 5889#else 5890 uint64_t workq : 16; 5891 uint64_t gpio : 16; 5892 uint64_t mbox : 2; 5893 uint64_t uart : 2; 5894 uint64_t pci_int : 4; 5895 uint64_t pci_msi : 4; 5896 uint64_t reserved_44_44 : 1; 5897 uint64_t twsi : 1; 5898 uint64_t rml : 1; 5899 uint64_t trace : 1; 5900 uint64_t gmx_drp : 1; 5901 uint64_t reserved_49_49 : 1; 5902 uint64_t ipd_drp : 1; 5903 uint64_t reserved_51_51 : 1; 5904 uint64_t timer : 4; 5905 uint64_t usb : 1; 5906 uint64_t pcm : 1; 5907 uint64_t mpi : 1; 5908 uint64_t twsi2 : 1; 5909 uint64_t powiq : 1; 5910 uint64_t ipdppthr : 1; 5911 uint64_t reserved_62_62 : 1; 5912 uint64_t bootdma : 1; 5913#endif 5914 } cnf71xx; 5915}; 5916typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t; 5917 5918/** 5919 * cvmx_ciu_int#_en4_1 5920 * 5921 * Notes: 5922 * PPx/IP4 will be raised when... 5923 * PPx/IP4 = |([CIU_SUM1_PPx_IP4, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0]) 5924 */ 5925union cvmx_ciu_intx_en4_1 { 5926 uint64_t u64; 5927 struct cvmx_ciu_intx_en4_1_s { 5928#ifdef __BIG_ENDIAN_BITFIELD 5929 uint64_t rst : 1; /**< MIO RST interrupt enable */ 5930 uint64_t reserved_62_62 : 1; 5931 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */ 5932 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */ 5933 uint64_t reserved_57_59 : 3; 5934 uint64_t dfm : 1; /**< DFM interrupt enable */ 5935 uint64_t reserved_53_55 : 3; 5936 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 5937 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 5938 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 5939 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 5940 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 5941 uint64_t ptp : 1; /**< PTP interrupt enable */ 5942 uint64_t agl : 1; /**< AGL interrupt enable */ 5943 uint64_t reserved_41_45 : 5; 5944 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 5945 uint64_t reserved_38_39 : 2; 5946 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 5947 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 5948 uint64_t dpi : 1; /**< DPI interrupt enable */ 5949 uint64_t sli : 1; /**< SLI interrupt enable */ 5950 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 5951 uint64_t dfa : 1; /**< DFA interrupt enable */ 5952 uint64_t key : 1; /**< KEY interrupt enable */ 5953 uint64_t rad : 1; /**< RAD interrupt enable */ 5954 uint64_t tim : 1; /**< TIM interrupt enable */ 5955 uint64_t zip : 1; /**< ZIP interrupt enable */ 5956 uint64_t pko : 1; /**< PKO interrupt enable */ 5957 uint64_t pip : 1; /**< PIP interrupt enable */ 5958 uint64_t ipd : 1; /**< IPD interrupt enable */ 5959 uint64_t l2c : 1; /**< L2C interrupt enable */ 5960 uint64_t pow : 1; /**< POW err interrupt enable */ 5961 uint64_t fpa : 1; /**< FPA interrupt enable */ 5962 uint64_t iob : 1; /**< IOB interrupt enable */ 5963 uint64_t mio : 1; /**< MIO boot interrupt enable */ 5964 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 5965 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 5966 uint64_t usb1 : 1; /**< Second USB Interrupt */ 5967 uint64_t uart2 : 1; /**< Third UART interrupt */ 5968 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */ 5969#else 5970 uint64_t wdog : 16; 5971 uint64_t uart2 : 1; 5972 uint64_t usb1 : 1; 5973 uint64_t mii1 : 1; 5974 uint64_t nand : 1; 5975 uint64_t mio : 1; 5976 uint64_t iob : 1; 5977 uint64_t fpa : 1; 5978 uint64_t pow : 1; 5979 uint64_t l2c : 1; 5980 uint64_t ipd : 1; 5981 uint64_t pip : 1; 5982 uint64_t pko : 1; 5983 uint64_t zip : 1; 5984 uint64_t tim : 1; 5985 uint64_t rad : 1; 5986 uint64_t key : 1; 5987 uint64_t dfa : 1; 5988 uint64_t usb : 1; 5989 uint64_t sli : 1; 5990 uint64_t dpi : 1; 5991 uint64_t agx0 : 1; 5992 uint64_t agx1 : 1; 5993 uint64_t reserved_38_39 : 2; 5994 uint64_t dpi_dma : 1; 5995 uint64_t reserved_41_45 : 5; 5996 uint64_t agl : 1; 5997 uint64_t ptp : 1; 5998 uint64_t pem0 : 1; 5999 uint64_t pem1 : 1; 6000 uint64_t srio0 : 1; 6001 uint64_t srio1 : 1; 6002 uint64_t lmc0 : 1; 6003 uint64_t reserved_53_55 : 3; 6004 uint64_t dfm : 1; 6005 uint64_t reserved_57_59 : 3; 6006 uint64_t srio2 : 1; 6007 uint64_t srio3 : 1; 6008 uint64_t reserved_62_62 : 1; 6009 uint64_t rst : 1; 6010#endif 6011 } s; 6012 struct cvmx_ciu_intx_en4_1_cn50xx { 6013#ifdef __BIG_ENDIAN_BITFIELD 6014 uint64_t reserved_2_63 : 62; 6015 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */ 6016#else 6017 uint64_t wdog : 2; 6018 uint64_t reserved_2_63 : 62; 6019#endif 6020 } cn50xx; 6021 struct cvmx_ciu_intx_en4_1_cn52xx { 6022#ifdef __BIG_ENDIAN_BITFIELD 6023 uint64_t reserved_20_63 : 44; 6024 uint64_t nand : 1; /**< NAND Flash Controller */ 6025 uint64_t mii1 : 1; /**< Second MII Interrupt */ 6026 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6027 uint64_t uart2 : 1; /**< Third UART interrupt */ 6028 uint64_t reserved_4_15 : 12; 6029 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6030#else 6031 uint64_t wdog : 4; 6032 uint64_t reserved_4_15 : 12; 6033 uint64_t uart2 : 1; 6034 uint64_t usb1 : 1; 6035 uint64_t mii1 : 1; 6036 uint64_t nand : 1; 6037 uint64_t reserved_20_63 : 44; 6038#endif 6039 } cn52xx; 6040 struct cvmx_ciu_intx_en4_1_cn52xxp1 { 6041#ifdef __BIG_ENDIAN_BITFIELD 6042 uint64_t reserved_19_63 : 45; 6043 uint64_t mii1 : 1; /**< Second MII Interrupt */ 6044 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6045 uint64_t uart2 : 1; /**< Third UART interrupt */ 6046 uint64_t reserved_4_15 : 12; 6047 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6048#else 6049 uint64_t wdog : 4; 6050 uint64_t reserved_4_15 : 12; 6051 uint64_t uart2 : 1; 6052 uint64_t usb1 : 1; 6053 uint64_t mii1 : 1; 6054 uint64_t reserved_19_63 : 45; 6055#endif 6056 } cn52xxp1; 6057 struct cvmx_ciu_intx_en4_1_cn56xx { 6058#ifdef __BIG_ENDIAN_BITFIELD 6059 uint64_t reserved_12_63 : 52; 6060 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 6061#else 6062 uint64_t wdog : 12; 6063 uint64_t reserved_12_63 : 52; 6064#endif 6065 } cn56xx; 6066 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; 6067 struct cvmx_ciu_intx_en4_1_cn58xx { 6068#ifdef __BIG_ENDIAN_BITFIELD 6069 uint64_t reserved_16_63 : 48; 6070 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 6071#else 6072 uint64_t wdog : 16; 6073 uint64_t reserved_16_63 : 48; 6074#endif 6075 } cn58xx; 6076 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; 6077 struct cvmx_ciu_intx_en4_1_cn61xx { 6078#ifdef __BIG_ENDIAN_BITFIELD 6079 uint64_t rst : 1; /**< MIO RST interrupt enable */ 6080 uint64_t reserved_53_62 : 10; 6081 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 6082 uint64_t reserved_50_51 : 2; 6083 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 6084 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 6085 uint64_t ptp : 1; /**< PTP interrupt enable */ 6086 uint64_t agl : 1; /**< AGL interrupt enable */ 6087 uint64_t reserved_41_45 : 5; 6088 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 6089 uint64_t reserved_38_39 : 2; 6090 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 6091 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 6092 uint64_t dpi : 1; /**< DPI interrupt enable */ 6093 uint64_t sli : 1; /**< SLI interrupt enable */ 6094 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 6095 uint64_t dfa : 1; /**< DFA interrupt enable */ 6096 uint64_t key : 1; /**< KEY interrupt enable */ 6097 uint64_t rad : 1; /**< RAD interrupt enable */ 6098 uint64_t tim : 1; /**< TIM interrupt enable */ 6099 uint64_t zip : 1; /**< ZIP interrupt enable */ 6100 uint64_t pko : 1; /**< PKO interrupt enable */ 6101 uint64_t pip : 1; /**< PIP interrupt enable */ 6102 uint64_t ipd : 1; /**< IPD interrupt enable */ 6103 uint64_t l2c : 1; /**< L2C interrupt enable */ 6104 uint64_t pow : 1; /**< POW err interrupt enable */ 6105 uint64_t fpa : 1; /**< FPA interrupt enable */ 6106 uint64_t iob : 1; /**< IOB interrupt enable */ 6107 uint64_t mio : 1; /**< MIO boot interrupt enable */ 6108 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 6109 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */ 6110 uint64_t reserved_4_17 : 14; 6111 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6112#else 6113 uint64_t wdog : 4; 6114 uint64_t reserved_4_17 : 14; 6115 uint64_t mii1 : 1; 6116 uint64_t nand : 1; 6117 uint64_t mio : 1; 6118 uint64_t iob : 1; 6119 uint64_t fpa : 1; 6120 uint64_t pow : 1; 6121 uint64_t l2c : 1; 6122 uint64_t ipd : 1; 6123 uint64_t pip : 1; 6124 uint64_t pko : 1; 6125 uint64_t zip : 1; 6126 uint64_t tim : 1; 6127 uint64_t rad : 1; 6128 uint64_t key : 1; 6129 uint64_t dfa : 1; 6130 uint64_t usb : 1; 6131 uint64_t sli : 1; 6132 uint64_t dpi : 1; 6133 uint64_t agx0 : 1; 6134 uint64_t agx1 : 1; 6135 uint64_t reserved_38_39 : 2; 6136 uint64_t dpi_dma : 1; 6137 uint64_t reserved_41_45 : 5; 6138 uint64_t agl : 1; 6139 uint64_t ptp : 1; 6140 uint64_t pem0 : 1; 6141 uint64_t pem1 : 1; 6142 uint64_t reserved_50_51 : 2; 6143 uint64_t lmc0 : 1; 6144 uint64_t reserved_53_62 : 10; 6145 uint64_t rst : 1; 6146#endif 6147 } cn61xx; 6148 struct cvmx_ciu_intx_en4_1_cn63xx { 6149#ifdef __BIG_ENDIAN_BITFIELD 6150 uint64_t rst : 1; /**< MIO RST interrupt enable */ 6151 uint64_t reserved_57_62 : 6; 6152 uint64_t dfm : 1; /**< DFM interrupt enable */ 6153 uint64_t reserved_53_55 : 3; 6154 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 6155 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 6156 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 6157 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 6158 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 6159 uint64_t ptp : 1; /**< PTP interrupt enable */ 6160 uint64_t agl : 1; /**< AGL interrupt enable */ 6161 uint64_t reserved_37_45 : 9; 6162 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 6163 uint64_t dpi : 1; /**< DPI interrupt enable */ 6164 uint64_t sli : 1; /**< SLI interrupt enable */ 6165 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 6166 uint64_t dfa : 1; /**< DFA interrupt enable */ 6167 uint64_t key : 1; /**< KEY interrupt enable */ 6168 uint64_t rad : 1; /**< RAD interrupt enable */ 6169 uint64_t tim : 1; /**< TIM interrupt enable */ 6170 uint64_t zip : 1; /**< ZIP interrupt enable */ 6171 uint64_t pko : 1; /**< PKO interrupt enable */ 6172 uint64_t pip : 1; /**< PIP interrupt enable */ 6173 uint64_t ipd : 1; /**< IPD interrupt enable */ 6174 uint64_t l2c : 1; /**< L2C interrupt enable */ 6175 uint64_t pow : 1; /**< POW err interrupt enable */ 6176 uint64_t fpa : 1; /**< FPA interrupt enable */ 6177 uint64_t iob : 1; /**< IOB interrupt enable */ 6178 uint64_t mio : 1; /**< MIO boot interrupt enable */ 6179 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 6180 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 6181 uint64_t reserved_6_17 : 12; 6182 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */ 6183#else 6184 uint64_t wdog : 6; 6185 uint64_t reserved_6_17 : 12; 6186 uint64_t mii1 : 1; 6187 uint64_t nand : 1; 6188 uint64_t mio : 1; 6189 uint64_t iob : 1; 6190 uint64_t fpa : 1; 6191 uint64_t pow : 1; 6192 uint64_t l2c : 1; 6193 uint64_t ipd : 1; 6194 uint64_t pip : 1; 6195 uint64_t pko : 1; 6196 uint64_t zip : 1; 6197 uint64_t tim : 1; 6198 uint64_t rad : 1; 6199 uint64_t key : 1; 6200 uint64_t dfa : 1; 6201 uint64_t usb : 1; 6202 uint64_t sli : 1; 6203 uint64_t dpi : 1; 6204 uint64_t agx0 : 1; 6205 uint64_t reserved_37_45 : 9; 6206 uint64_t agl : 1; 6207 uint64_t ptp : 1; 6208 uint64_t pem0 : 1; 6209 uint64_t pem1 : 1; 6210 uint64_t srio0 : 1; 6211 uint64_t srio1 : 1; 6212 uint64_t lmc0 : 1; 6213 uint64_t reserved_53_55 : 3; 6214 uint64_t dfm : 1; 6215 uint64_t reserved_57_62 : 6; 6216 uint64_t rst : 1; 6217#endif 6218 } cn63xx; 6219 struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; 6220 struct cvmx_ciu_intx_en4_1_cn66xx { 6221#ifdef __BIG_ENDIAN_BITFIELD 6222 uint64_t rst : 1; /**< MIO RST interrupt enable */ 6223 uint64_t reserved_62_62 : 1; 6224 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */ 6225 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */ 6226 uint64_t reserved_57_59 : 3; 6227 uint64_t dfm : 1; /**< DFM interrupt enable */ 6228 uint64_t reserved_53_55 : 3; 6229 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 6230 uint64_t reserved_51_51 : 1; 6231 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 6232 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 6233 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 6234 uint64_t ptp : 1; /**< PTP interrupt enable */ 6235 uint64_t agl : 1; /**< AGL interrupt enable */ 6236 uint64_t reserved_38_45 : 8; 6237 uint64_t agx1 : 1; /**< GMX1 interrupt enable */ 6238 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 6239 uint64_t dpi : 1; /**< DPI interrupt enable */ 6240 uint64_t sli : 1; /**< SLI interrupt enable */ 6241 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 6242 uint64_t dfa : 1; /**< DFA interrupt enable */ 6243 uint64_t key : 1; /**< KEY interrupt enable */ 6244 uint64_t rad : 1; /**< RAD interrupt enable */ 6245 uint64_t tim : 1; /**< TIM interrupt enable */ 6246 uint64_t zip : 1; /**< ZIP interrupt enable */ 6247 uint64_t pko : 1; /**< PKO interrupt enable */ 6248 uint64_t pip : 1; /**< PIP interrupt enable */ 6249 uint64_t ipd : 1; /**< IPD interrupt enable */ 6250 uint64_t l2c : 1; /**< L2C interrupt enable */ 6251 uint64_t pow : 1; /**< POW err interrupt enable */ 6252 uint64_t fpa : 1; /**< FPA interrupt enable */ 6253 uint64_t iob : 1; /**< IOB interrupt enable */ 6254 uint64_t mio : 1; /**< MIO boot interrupt enable */ 6255 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 6256 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 6257 uint64_t reserved_10_17 : 8; 6258 uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */ 6259#else 6260 uint64_t wdog : 10; 6261 uint64_t reserved_10_17 : 8; 6262 uint64_t mii1 : 1; 6263 uint64_t nand : 1; 6264 uint64_t mio : 1; 6265 uint64_t iob : 1; 6266 uint64_t fpa : 1; 6267 uint64_t pow : 1; 6268 uint64_t l2c : 1; 6269 uint64_t ipd : 1; 6270 uint64_t pip : 1; 6271 uint64_t pko : 1; 6272 uint64_t zip : 1; 6273 uint64_t tim : 1; 6274 uint64_t rad : 1; 6275 uint64_t key : 1; 6276 uint64_t dfa : 1; 6277 uint64_t usb : 1; 6278 uint64_t sli : 1; 6279 uint64_t dpi : 1; 6280 uint64_t agx0 : 1; 6281 uint64_t agx1 : 1; 6282 uint64_t reserved_38_45 : 8; 6283 uint64_t agl : 1; 6284 uint64_t ptp : 1; 6285 uint64_t pem0 : 1; 6286 uint64_t pem1 : 1; 6287 uint64_t srio0 : 1; 6288 uint64_t reserved_51_51 : 1; 6289 uint64_t lmc0 : 1; 6290 uint64_t reserved_53_55 : 3; 6291 uint64_t dfm : 1; 6292 uint64_t reserved_57_59 : 3; 6293 uint64_t srio2 : 1; 6294 uint64_t srio3 : 1; 6295 uint64_t reserved_62_62 : 1; 6296 uint64_t rst : 1; 6297#endif 6298 } cn66xx; 6299 struct cvmx_ciu_intx_en4_1_cnf71xx { 6300#ifdef __BIG_ENDIAN_BITFIELD 6301 uint64_t rst : 1; /**< MIO RST interrupt enable */ 6302 uint64_t reserved_53_62 : 10; 6303 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 6304 uint64_t reserved_50_51 : 2; 6305 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 6306 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 6307 uint64_t ptp : 1; /**< PTP interrupt enable */ 6308 uint64_t reserved_41_46 : 6; 6309 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */ 6310 uint64_t reserved_37_39 : 3; 6311 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 6312 uint64_t dpi : 1; /**< DPI interrupt enable */ 6313 uint64_t sli : 1; /**< SLI interrupt enable */ 6314 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 6315 uint64_t reserved_32_32 : 1; 6316 uint64_t key : 1; /**< KEY interrupt enable */ 6317 uint64_t rad : 1; /**< RAD interrupt enable */ 6318 uint64_t tim : 1; /**< TIM interrupt enable */ 6319 uint64_t reserved_28_28 : 1; 6320 uint64_t pko : 1; /**< PKO interrupt enable */ 6321 uint64_t pip : 1; /**< PIP interrupt enable */ 6322 uint64_t ipd : 1; /**< IPD interrupt enable */ 6323 uint64_t l2c : 1; /**< L2C interrupt enable */ 6324 uint64_t pow : 1; /**< POW err interrupt enable */ 6325 uint64_t fpa : 1; /**< FPA interrupt enable */ 6326 uint64_t iob : 1; /**< IOB interrupt enable */ 6327 uint64_t mio : 1; /**< MIO boot interrupt enable */ 6328 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */ 6329 uint64_t reserved_4_18 : 15; 6330 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6331#else 6332 uint64_t wdog : 4; 6333 uint64_t reserved_4_18 : 15; 6334 uint64_t nand : 1; 6335 uint64_t mio : 1; 6336 uint64_t iob : 1; 6337 uint64_t fpa : 1; 6338 uint64_t pow : 1; 6339 uint64_t l2c : 1; 6340 uint64_t ipd : 1; 6341 uint64_t pip : 1; 6342 uint64_t pko : 1; 6343 uint64_t reserved_28_28 : 1; 6344 uint64_t tim : 1; 6345 uint64_t rad : 1; 6346 uint64_t key : 1; 6347 uint64_t reserved_32_32 : 1; 6348 uint64_t usb : 1; 6349 uint64_t sli : 1; 6350 uint64_t dpi : 1; 6351 uint64_t agx0 : 1; 6352 uint64_t reserved_37_39 : 3; 6353 uint64_t dpi_dma : 1; 6354 uint64_t reserved_41_46 : 6; 6355 uint64_t ptp : 1; 6356 uint64_t pem0 : 1; 6357 uint64_t pem1 : 1; 6358 uint64_t reserved_50_51 : 2; 6359 uint64_t lmc0 : 1; 6360 uint64_t reserved_53_62 : 10; 6361 uint64_t rst : 1; 6362#endif 6363 } cnf71xx; 6364}; 6365typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t; 6366 6367/** 6368 * cvmx_ciu_int#_en4_1_w1c 6369 * 6370 * Notes: 6371 * Write-1-to-clear version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value. 6372 * 6373 */ 6374union cvmx_ciu_intx_en4_1_w1c { 6375 uint64_t u64; 6376 struct cvmx_ciu_intx_en4_1_w1c_s { 6377#ifdef __BIG_ENDIAN_BITFIELD 6378 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 6379 uint64_t reserved_62_62 : 1; 6380 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */ 6381 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */ 6382 uint64_t reserved_57_59 : 3; 6383 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 6384 uint64_t reserved_53_55 : 3; 6385 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 6386 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 6387 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 6388 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 6389 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 6390 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 6391 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 6392 uint64_t reserved_41_45 : 5; 6393 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 6394 uint64_t reserved_38_39 : 2; 6395 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 6396 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 6397 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 6398 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 6399 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 6400 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 6401 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 6402 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 6403 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 6404 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 6405 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 6406 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 6407 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 6408 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 6409 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 6410 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 6411 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 6412 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 6413 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 6414 enable */ 6415 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 6416 Interrupt enable */ 6417 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6418 uint64_t uart2 : 1; /**< Third UART interrupt */ 6419 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */ 6420#else 6421 uint64_t wdog : 16; 6422 uint64_t uart2 : 1; 6423 uint64_t usb1 : 1; 6424 uint64_t mii1 : 1; 6425 uint64_t nand : 1; 6426 uint64_t mio : 1; 6427 uint64_t iob : 1; 6428 uint64_t fpa : 1; 6429 uint64_t pow : 1; 6430 uint64_t l2c : 1; 6431 uint64_t ipd : 1; 6432 uint64_t pip : 1; 6433 uint64_t pko : 1; 6434 uint64_t zip : 1; 6435 uint64_t tim : 1; 6436 uint64_t rad : 1; 6437 uint64_t key : 1; 6438 uint64_t dfa : 1; 6439 uint64_t usb : 1; 6440 uint64_t sli : 1; 6441 uint64_t dpi : 1; 6442 uint64_t agx0 : 1; 6443 uint64_t agx1 : 1; 6444 uint64_t reserved_38_39 : 2; 6445 uint64_t dpi_dma : 1; 6446 uint64_t reserved_41_45 : 5; 6447 uint64_t agl : 1; 6448 uint64_t ptp : 1; 6449 uint64_t pem0 : 1; 6450 uint64_t pem1 : 1; 6451 uint64_t srio0 : 1; 6452 uint64_t srio1 : 1; 6453 uint64_t lmc0 : 1; 6454 uint64_t reserved_53_55 : 3; 6455 uint64_t dfm : 1; 6456 uint64_t reserved_57_59 : 3; 6457 uint64_t srio2 : 1; 6458 uint64_t srio3 : 1; 6459 uint64_t reserved_62_62 : 1; 6460 uint64_t rst : 1; 6461#endif 6462 } s; 6463 struct cvmx_ciu_intx_en4_1_w1c_cn52xx { 6464#ifdef __BIG_ENDIAN_BITFIELD 6465 uint64_t reserved_20_63 : 44; 6466 uint64_t nand : 1; /**< NAND Flash Controller */ 6467 uint64_t mii1 : 1; /**< Second MII Interrupt */ 6468 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6469 uint64_t uart2 : 1; /**< Third UART interrupt */ 6470 uint64_t reserved_4_15 : 12; 6471 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6472#else 6473 uint64_t wdog : 4; 6474 uint64_t reserved_4_15 : 12; 6475 uint64_t uart2 : 1; 6476 uint64_t usb1 : 1; 6477 uint64_t mii1 : 1; 6478 uint64_t nand : 1; 6479 uint64_t reserved_20_63 : 44; 6480#endif 6481 } cn52xx; 6482 struct cvmx_ciu_intx_en4_1_w1c_cn56xx { 6483#ifdef __BIG_ENDIAN_BITFIELD 6484 uint64_t reserved_12_63 : 52; 6485 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 6486#else 6487 uint64_t wdog : 12; 6488 uint64_t reserved_12_63 : 52; 6489#endif 6490 } cn56xx; 6491 struct cvmx_ciu_intx_en4_1_w1c_cn58xx { 6492#ifdef __BIG_ENDIAN_BITFIELD 6493 uint64_t reserved_16_63 : 48; 6494 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 6495#else 6496 uint64_t wdog : 16; 6497 uint64_t reserved_16_63 : 48; 6498#endif 6499 } cn58xx; 6500 struct cvmx_ciu_intx_en4_1_w1c_cn61xx { 6501#ifdef __BIG_ENDIAN_BITFIELD 6502 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 6503 uint64_t reserved_53_62 : 10; 6504 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 6505 uint64_t reserved_50_51 : 2; 6506 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 6507 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 6508 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 6509 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 6510 uint64_t reserved_41_45 : 5; 6511 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 6512 uint64_t reserved_38_39 : 2; 6513 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 6514 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 6515 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 6516 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 6517 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 6518 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 6519 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 6520 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 6521 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 6522 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 6523 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 6524 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 6525 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 6526 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 6527 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 6528 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 6529 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 6530 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 6531 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 6532 enable */ 6533 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1 6534 Interrupt enable */ 6535 uint64_t reserved_4_17 : 14; 6536 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */ 6537#else 6538 uint64_t wdog : 4; 6539 uint64_t reserved_4_17 : 14; 6540 uint64_t mii1 : 1; 6541 uint64_t nand : 1; 6542 uint64_t mio : 1; 6543 uint64_t iob : 1; 6544 uint64_t fpa : 1; 6545 uint64_t pow : 1; 6546 uint64_t l2c : 1; 6547 uint64_t ipd : 1; 6548 uint64_t pip : 1; 6549 uint64_t pko : 1; 6550 uint64_t zip : 1; 6551 uint64_t tim : 1; 6552 uint64_t rad : 1; 6553 uint64_t key : 1; 6554 uint64_t dfa : 1; 6555 uint64_t usb : 1; 6556 uint64_t sli : 1; 6557 uint64_t dpi : 1; 6558 uint64_t agx0 : 1; 6559 uint64_t agx1 : 1; 6560 uint64_t reserved_38_39 : 2; 6561 uint64_t dpi_dma : 1; 6562 uint64_t reserved_41_45 : 5; 6563 uint64_t agl : 1; 6564 uint64_t ptp : 1; 6565 uint64_t pem0 : 1; 6566 uint64_t pem1 : 1; 6567 uint64_t reserved_50_51 : 2; 6568 uint64_t lmc0 : 1; 6569 uint64_t reserved_53_62 : 10; 6570 uint64_t rst : 1; 6571#endif 6572 } cn61xx; 6573 struct cvmx_ciu_intx_en4_1_w1c_cn63xx { 6574#ifdef __BIG_ENDIAN_BITFIELD 6575 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 6576 uint64_t reserved_57_62 : 6; 6577 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 6578 uint64_t reserved_53_55 : 3; 6579 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 6580 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 6581 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 6582 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 6583 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 6584 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 6585 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 6586 uint64_t reserved_37_45 : 9; 6587 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 6588 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 6589 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 6590 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 6591 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 6592 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 6593 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 6594 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 6595 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 6596 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 6597 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 6598 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 6599 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 6600 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 6601 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 6602 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 6603 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 6604 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 6605 enable */ 6606 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 6607 Interrupt enable */ 6608 uint64_t reserved_6_17 : 12; 6609 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */ 6610#else 6611 uint64_t wdog : 6; 6612 uint64_t reserved_6_17 : 12; 6613 uint64_t mii1 : 1; 6614 uint64_t nand : 1; 6615 uint64_t mio : 1; 6616 uint64_t iob : 1; 6617 uint64_t fpa : 1; 6618 uint64_t pow : 1; 6619 uint64_t l2c : 1; 6620 uint64_t ipd : 1; 6621 uint64_t pip : 1; 6622 uint64_t pko : 1; 6623 uint64_t zip : 1; 6624 uint64_t tim : 1; 6625 uint64_t rad : 1; 6626 uint64_t key : 1; 6627 uint64_t dfa : 1; 6628 uint64_t usb : 1; 6629 uint64_t sli : 1; 6630 uint64_t dpi : 1; 6631 uint64_t agx0 : 1; 6632 uint64_t reserved_37_45 : 9; 6633 uint64_t agl : 1; 6634 uint64_t ptp : 1; 6635 uint64_t pem0 : 1; 6636 uint64_t pem1 : 1; 6637 uint64_t srio0 : 1; 6638 uint64_t srio1 : 1; 6639 uint64_t lmc0 : 1; 6640 uint64_t reserved_53_55 : 3; 6641 uint64_t dfm : 1; 6642 uint64_t reserved_57_62 : 6; 6643 uint64_t rst : 1; 6644#endif 6645 } cn63xx; 6646 struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; 6647 struct cvmx_ciu_intx_en4_1_w1c_cn66xx { 6648#ifdef __BIG_ENDIAN_BITFIELD 6649 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 6650 uint64_t reserved_62_62 : 1; 6651 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */ 6652 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */ 6653 uint64_t reserved_57_59 : 3; 6654 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 6655 uint64_t reserved_53_55 : 3; 6656 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 6657 uint64_t reserved_51_51 : 1; 6658 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 6659 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 6660 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 6661 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 6662 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 6663 uint64_t reserved_38_45 : 8; 6664 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */ 6665 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 6666 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 6667 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 6668 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 6669 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 6670 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 6671 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 6672 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 6673 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 6674 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 6675 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 6676 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 6677 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 6678 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 6679 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 6680 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 6681 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 6682 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 6683 enable */ 6684 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 6685 Interrupt enable */ 6686 uint64_t reserved_10_17 : 8; 6687 uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */ 6688#else 6689 uint64_t wdog : 10; 6690 uint64_t reserved_10_17 : 8; 6691 uint64_t mii1 : 1; 6692 uint64_t nand : 1; 6693 uint64_t mio : 1; 6694 uint64_t iob : 1; 6695 uint64_t fpa : 1; 6696 uint64_t pow : 1; 6697 uint64_t l2c : 1; 6698 uint64_t ipd : 1; 6699 uint64_t pip : 1; 6700 uint64_t pko : 1; 6701 uint64_t zip : 1; 6702 uint64_t tim : 1; 6703 uint64_t rad : 1; 6704 uint64_t key : 1; 6705 uint64_t dfa : 1; 6706 uint64_t usb : 1; 6707 uint64_t sli : 1; 6708 uint64_t dpi : 1; 6709 uint64_t agx0 : 1; 6710 uint64_t agx1 : 1; 6711 uint64_t reserved_38_45 : 8; 6712 uint64_t agl : 1; 6713 uint64_t ptp : 1; 6714 uint64_t pem0 : 1; 6715 uint64_t pem1 : 1; 6716 uint64_t srio0 : 1; 6717 uint64_t reserved_51_51 : 1; 6718 uint64_t lmc0 : 1; 6719 uint64_t reserved_53_55 : 3; 6720 uint64_t dfm : 1; 6721 uint64_t reserved_57_59 : 3; 6722 uint64_t srio2 : 1; 6723 uint64_t srio3 : 1; 6724 uint64_t reserved_62_62 : 1; 6725 uint64_t rst : 1; 6726#endif 6727 } cn66xx; 6728 struct cvmx_ciu_intx_en4_1_w1c_cnf71xx { 6729#ifdef __BIG_ENDIAN_BITFIELD 6730 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 6731 uint64_t reserved_53_62 : 10; 6732 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 6733 uint64_t reserved_50_51 : 2; 6734 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 6735 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 6736 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 6737 uint64_t reserved_41_46 : 6; 6738 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */ 6739 uint64_t reserved_37_39 : 3; 6740 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 6741 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 6742 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 6743 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 6744 uint64_t reserved_32_32 : 1; 6745 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 6746 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 6747 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 6748 uint64_t reserved_28_28 : 1; 6749 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 6750 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 6751 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 6752 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 6753 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 6754 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 6755 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 6756 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 6757 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt 6758 enable */ 6759 uint64_t reserved_4_18 : 15; 6760 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */ 6761#else 6762 uint64_t wdog : 4; 6763 uint64_t reserved_4_18 : 15; 6764 uint64_t nand : 1; 6765 uint64_t mio : 1; 6766 uint64_t iob : 1; 6767 uint64_t fpa : 1; 6768 uint64_t pow : 1; 6769 uint64_t l2c : 1; 6770 uint64_t ipd : 1; 6771 uint64_t pip : 1; 6772 uint64_t pko : 1; 6773 uint64_t reserved_28_28 : 1; 6774 uint64_t tim : 1; 6775 uint64_t rad : 1; 6776 uint64_t key : 1; 6777 uint64_t reserved_32_32 : 1; 6778 uint64_t usb : 1; 6779 uint64_t sli : 1; 6780 uint64_t dpi : 1; 6781 uint64_t agx0 : 1; 6782 uint64_t reserved_37_39 : 3; 6783 uint64_t dpi_dma : 1; 6784 uint64_t reserved_41_46 : 6; 6785 uint64_t ptp : 1; 6786 uint64_t pem0 : 1; 6787 uint64_t pem1 : 1; 6788 uint64_t reserved_50_51 : 2; 6789 uint64_t lmc0 : 1; 6790 uint64_t reserved_53_62 : 10; 6791 uint64_t rst : 1; 6792#endif 6793 } cnf71xx; 6794}; 6795typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t; 6796 6797/** 6798 * cvmx_ciu_int#_en4_1_w1s 6799 * 6800 * Notes: 6801 * Write-1-to-set version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value. 6802 * 6803 */ 6804union cvmx_ciu_intx_en4_1_w1s { 6805 uint64_t u64; 6806 struct cvmx_ciu_intx_en4_1_w1s_s { 6807#ifdef __BIG_ENDIAN_BITFIELD 6808 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 6809 uint64_t reserved_62_62 : 1; 6810 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */ 6811 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */ 6812 uint64_t reserved_57_59 : 3; 6813 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 6814 uint64_t reserved_53_55 : 3; 6815 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 6816 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 6817 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 6818 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 6819 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 6820 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 6821 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 6822 uint64_t reserved_41_45 : 5; 6823 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 6824 uint64_t reserved_38_39 : 2; 6825 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 6826 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 6827 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 6828 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 6829 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 6830 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 6831 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 6832 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 6833 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 6834 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 6835 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 6836 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 6837 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 6838 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 6839 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 6840 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 6841 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 6842 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 6843 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 6844 enable */ 6845 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 6846 enable */ 6847 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6848 uint64_t uart2 : 1; /**< Third UART interrupt */ 6849 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */ 6850#else 6851 uint64_t wdog : 16; 6852 uint64_t uart2 : 1; 6853 uint64_t usb1 : 1; 6854 uint64_t mii1 : 1; 6855 uint64_t nand : 1; 6856 uint64_t mio : 1; 6857 uint64_t iob : 1; 6858 uint64_t fpa : 1; 6859 uint64_t pow : 1; 6860 uint64_t l2c : 1; 6861 uint64_t ipd : 1; 6862 uint64_t pip : 1; 6863 uint64_t pko : 1; 6864 uint64_t zip : 1; 6865 uint64_t tim : 1; 6866 uint64_t rad : 1; 6867 uint64_t key : 1; 6868 uint64_t dfa : 1; 6869 uint64_t usb : 1; 6870 uint64_t sli : 1; 6871 uint64_t dpi : 1; 6872 uint64_t agx0 : 1; 6873 uint64_t agx1 : 1; 6874 uint64_t reserved_38_39 : 2; 6875 uint64_t dpi_dma : 1; 6876 uint64_t reserved_41_45 : 5; 6877 uint64_t agl : 1; 6878 uint64_t ptp : 1; 6879 uint64_t pem0 : 1; 6880 uint64_t pem1 : 1; 6881 uint64_t srio0 : 1; 6882 uint64_t srio1 : 1; 6883 uint64_t lmc0 : 1; 6884 uint64_t reserved_53_55 : 3; 6885 uint64_t dfm : 1; 6886 uint64_t reserved_57_59 : 3; 6887 uint64_t srio2 : 1; 6888 uint64_t srio3 : 1; 6889 uint64_t reserved_62_62 : 1; 6890 uint64_t rst : 1; 6891#endif 6892 } s; 6893 struct cvmx_ciu_intx_en4_1_w1s_cn52xx { 6894#ifdef __BIG_ENDIAN_BITFIELD 6895 uint64_t reserved_20_63 : 44; 6896 uint64_t nand : 1; /**< NAND Flash Controller */ 6897 uint64_t mii1 : 1; /**< Second MII Interrupt */ 6898 uint64_t usb1 : 1; /**< Second USB Interrupt */ 6899 uint64_t uart2 : 1; /**< Third UART interrupt */ 6900 uint64_t reserved_4_15 : 12; 6901 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 6902#else 6903 uint64_t wdog : 4; 6904 uint64_t reserved_4_15 : 12; 6905 uint64_t uart2 : 1; 6906 uint64_t usb1 : 1; 6907 uint64_t mii1 : 1; 6908 uint64_t nand : 1; 6909 uint64_t reserved_20_63 : 44; 6910#endif 6911 } cn52xx; 6912 struct cvmx_ciu_intx_en4_1_w1s_cn56xx { 6913#ifdef __BIG_ENDIAN_BITFIELD 6914 uint64_t reserved_12_63 : 52; 6915 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 6916#else 6917 uint64_t wdog : 12; 6918 uint64_t reserved_12_63 : 52; 6919#endif 6920 } cn56xx; 6921 struct cvmx_ciu_intx_en4_1_w1s_cn58xx { 6922#ifdef __BIG_ENDIAN_BITFIELD 6923 uint64_t reserved_16_63 : 48; 6924 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 6925#else 6926 uint64_t wdog : 16; 6927 uint64_t reserved_16_63 : 48; 6928#endif 6929 } cn58xx; 6930 struct cvmx_ciu_intx_en4_1_w1s_cn61xx { 6931#ifdef __BIG_ENDIAN_BITFIELD 6932 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 6933 uint64_t reserved_53_62 : 10; 6934 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 6935 uint64_t reserved_50_51 : 2; 6936 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 6937 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 6938 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 6939 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 6940 uint64_t reserved_41_45 : 5; 6941 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 6942 uint64_t reserved_38_39 : 2; 6943 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 6944 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 6945 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 6946 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 6947 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 6948 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 6949 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 6950 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 6951 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 6952 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 6953 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 6954 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 6955 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 6956 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 6957 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 6958 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 6959 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 6960 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 6961 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 6962 enable */ 6963 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt 6964 enable */ 6965 uint64_t reserved_4_17 : 14; 6966 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */ 6967#else 6968 uint64_t wdog : 4; 6969 uint64_t reserved_4_17 : 14; 6970 uint64_t mii1 : 1; 6971 uint64_t nand : 1; 6972 uint64_t mio : 1; 6973 uint64_t iob : 1; 6974 uint64_t fpa : 1; 6975 uint64_t pow : 1; 6976 uint64_t l2c : 1; 6977 uint64_t ipd : 1; 6978 uint64_t pip : 1; 6979 uint64_t pko : 1; 6980 uint64_t zip : 1; 6981 uint64_t tim : 1; 6982 uint64_t rad : 1; 6983 uint64_t key : 1; 6984 uint64_t dfa : 1; 6985 uint64_t usb : 1; 6986 uint64_t sli : 1; 6987 uint64_t dpi : 1; 6988 uint64_t agx0 : 1; 6989 uint64_t agx1 : 1; 6990 uint64_t reserved_38_39 : 2; 6991 uint64_t dpi_dma : 1; 6992 uint64_t reserved_41_45 : 5; 6993 uint64_t agl : 1; 6994 uint64_t ptp : 1; 6995 uint64_t pem0 : 1; 6996 uint64_t pem1 : 1; 6997 uint64_t reserved_50_51 : 2; 6998 uint64_t lmc0 : 1; 6999 uint64_t reserved_53_62 : 10; 7000 uint64_t rst : 1; 7001#endif 7002 } cn61xx; 7003 struct cvmx_ciu_intx_en4_1_w1s_cn63xx { 7004#ifdef __BIG_ENDIAN_BITFIELD 7005 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 7006 uint64_t reserved_57_62 : 6; 7007 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 7008 uint64_t reserved_53_55 : 3; 7009 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 7010 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 7011 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 7012 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 7013 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 7014 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 7015 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 7016 uint64_t reserved_37_45 : 9; 7017 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 7018 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 7019 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 7020 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 7021 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 7022 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 7023 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 7024 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 7025 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 7026 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 7027 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 7028 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 7029 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 7030 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 7031 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 7032 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 7033 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 7034 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 7035 enable */ 7036 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 7037 enable */ 7038 uint64_t reserved_6_17 : 12; 7039 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */ 7040#else 7041 uint64_t wdog : 6; 7042 uint64_t reserved_6_17 : 12; 7043 uint64_t mii1 : 1; 7044 uint64_t nand : 1; 7045 uint64_t mio : 1; 7046 uint64_t iob : 1; 7047 uint64_t fpa : 1; 7048 uint64_t pow : 1; 7049 uint64_t l2c : 1; 7050 uint64_t ipd : 1; 7051 uint64_t pip : 1; 7052 uint64_t pko : 1; 7053 uint64_t zip : 1; 7054 uint64_t tim : 1; 7055 uint64_t rad : 1; 7056 uint64_t key : 1; 7057 uint64_t dfa : 1; 7058 uint64_t usb : 1; 7059 uint64_t sli : 1; 7060 uint64_t dpi : 1; 7061 uint64_t agx0 : 1; 7062 uint64_t reserved_37_45 : 9; 7063 uint64_t agl : 1; 7064 uint64_t ptp : 1; 7065 uint64_t pem0 : 1; 7066 uint64_t pem1 : 1; 7067 uint64_t srio0 : 1; 7068 uint64_t srio1 : 1; 7069 uint64_t lmc0 : 1; 7070 uint64_t reserved_53_55 : 3; 7071 uint64_t dfm : 1; 7072 uint64_t reserved_57_62 : 6; 7073 uint64_t rst : 1; 7074#endif 7075 } cn63xx; 7076 struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; 7077 struct cvmx_ciu_intx_en4_1_w1s_cn66xx { 7078#ifdef __BIG_ENDIAN_BITFIELD 7079 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 7080 uint64_t reserved_62_62 : 1; 7081 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */ 7082 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */ 7083 uint64_t reserved_57_59 : 3; 7084 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 7085 uint64_t reserved_53_55 : 3; 7086 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 7087 uint64_t reserved_51_51 : 1; 7088 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 7089 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 7090 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 7091 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 7092 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 7093 uint64_t reserved_38_45 : 8; 7094 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */ 7095 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 7096 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 7097 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 7098 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 7099 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 7100 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 7101 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 7102 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 7103 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 7104 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 7105 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 7106 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 7107 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 7108 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 7109 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 7110 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 7111 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 7112 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 7113 enable */ 7114 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 7115 enable */ 7116 uint64_t reserved_10_17 : 8; 7117 uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */ 7118#else 7119 uint64_t wdog : 10; 7120 uint64_t reserved_10_17 : 8; 7121 uint64_t mii1 : 1; 7122 uint64_t nand : 1; 7123 uint64_t mio : 1; 7124 uint64_t iob : 1; 7125 uint64_t fpa : 1; 7126 uint64_t pow : 1; 7127 uint64_t l2c : 1; 7128 uint64_t ipd : 1; 7129 uint64_t pip : 1; 7130 uint64_t pko : 1; 7131 uint64_t zip : 1; 7132 uint64_t tim : 1; 7133 uint64_t rad : 1; 7134 uint64_t key : 1; 7135 uint64_t dfa : 1; 7136 uint64_t usb : 1; 7137 uint64_t sli : 1; 7138 uint64_t dpi : 1; 7139 uint64_t agx0 : 1; 7140 uint64_t agx1 : 1; 7141 uint64_t reserved_38_45 : 8; 7142 uint64_t agl : 1; 7143 uint64_t ptp : 1; 7144 uint64_t pem0 : 1; 7145 uint64_t pem1 : 1; 7146 uint64_t srio0 : 1; 7147 uint64_t reserved_51_51 : 1; 7148 uint64_t lmc0 : 1; 7149 uint64_t reserved_53_55 : 3; 7150 uint64_t dfm : 1; 7151 uint64_t reserved_57_59 : 3; 7152 uint64_t srio2 : 1; 7153 uint64_t srio3 : 1; 7154 uint64_t reserved_62_62 : 1; 7155 uint64_t rst : 1; 7156#endif 7157 } cn66xx; 7158 struct cvmx_ciu_intx_en4_1_w1s_cnf71xx { 7159#ifdef __BIG_ENDIAN_BITFIELD 7160 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 7161 uint64_t reserved_53_62 : 10; 7162 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 7163 uint64_t reserved_50_51 : 2; 7164 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 7165 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 7166 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 7167 uint64_t reserved_41_46 : 6; 7168 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */ 7169 uint64_t reserved_37_39 : 3; 7170 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 7171 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 7172 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 7173 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 7174 uint64_t reserved_32_32 : 1; 7175 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 7176 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 7177 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 7178 uint64_t reserved_28_28 : 1; 7179 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 7180 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 7181 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 7182 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 7183 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 7184 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 7185 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 7186 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 7187 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt 7188 enable */ 7189 uint64_t reserved_4_18 : 15; 7190 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */ 7191#else 7192 uint64_t wdog : 4; 7193 uint64_t reserved_4_18 : 15; 7194 uint64_t nand : 1; 7195 uint64_t mio : 1; 7196 uint64_t iob : 1; 7197 uint64_t fpa : 1; 7198 uint64_t pow : 1; 7199 uint64_t l2c : 1; 7200 uint64_t ipd : 1; 7201 uint64_t pip : 1; 7202 uint64_t pko : 1; 7203 uint64_t reserved_28_28 : 1; 7204 uint64_t tim : 1; 7205 uint64_t rad : 1; 7206 uint64_t key : 1; 7207 uint64_t reserved_32_32 : 1; 7208 uint64_t usb : 1; 7209 uint64_t sli : 1; 7210 uint64_t dpi : 1; 7211 uint64_t agx0 : 1; 7212 uint64_t reserved_37_39 : 3; 7213 uint64_t dpi_dma : 1; 7214 uint64_t reserved_41_46 : 6; 7215 uint64_t ptp : 1; 7216 uint64_t pem0 : 1; 7217 uint64_t pem1 : 1; 7218 uint64_t reserved_50_51 : 2; 7219 uint64_t lmc0 : 1; 7220 uint64_t reserved_53_62 : 10; 7221 uint64_t rst : 1; 7222#endif 7223 } cnf71xx; 7224}; 7225typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t; 7226 7227/** 7228 * cvmx_ciu_int#_sum0 7229 */ 7230union cvmx_ciu_intx_sum0 { 7231 uint64_t u64; 7232 struct cvmx_ciu_intx_sum0_s { 7233#ifdef __BIG_ENDIAN_BITFIELD 7234 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7235 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7236 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 7237 See MIX0_ISR */ 7238 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7239 See IPD_PORT_QOS_INT* */ 7240 uint64_t powiq : 1; /**< POW IQ interrupt 7241 See POW_IQ_INT */ 7242 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 7243 See MIO_TWS1_INT */ 7244 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction 7245 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */ 7246 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7247 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 7248 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7249 uint64_t timer : 4; /**< General timer 0-3 interrupts. 7250 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 7251 common for all PP/IRQs, writing '1' to any PP/IRQ 7252 will clear all TIMERx(x=0..9) interrupts. 7253 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 7254 are set at the same time, but clearing are based on 7255 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 7256 The combination of this field and the 7257 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 7258 interrupts. */ 7259 uint64_t reserved_51_51 : 1; 7260 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7261 Set any time PIP/IPD drops a packet */ 7262 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt 7263 Set any time corresponding GMX0/1 drops a packet */ 7264 uint64_t trace : 1; /**< Trace buffer interrupt 7265 See TRA_INT_STATUS */ 7266 uint64_t rml : 1; /**< RML Interrupt 7267 This interrupt will assert if any bit within 7268 CIU_BLOCK_INT is asserted. */ 7269 uint64_t twsi : 1; /**< TWSI Interrupt 7270 See MIO_TWS0_INT */ 7271 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 7272 This read-only bit reads as a one whenever any 7273 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 7274 and corresponding enable bit in CIU_INTx_EN is set 7275 PPs use CIU_INTx_SUM0 where x=0-7 7276 PCIe uses the CIU_INTx_SUM0 where x=32-33. 7277 Note that WDOG_SUM only summarizes the SUM1/EN1 7278 result and does not have a corresponding enable 7279 bit, so does not directly contribute to 7280 interrupts. */ 7281 uint64_t pci_msi : 4; /**< PCIe MSI 7282 See SLI_MSI_RCVn for bit <40+n> */ 7283 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 7284 Refer to "Receiving Emulated INTA/INTB/ 7285 INTC/INTD" in the SLI chapter of the spec 7286 PCI_INT<3> = INTD 7287 PCI_INT<2> = INTC 7288 PCI_INT<1> = INTB 7289 PCI_INT<0> = INTA */ 7290 uint64_t uart : 2; /**< Two UART interrupts 7291 See MIO_UARTn_IIR[IID] for bit <34+n> */ 7292 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 7293 [33] is the or of <31:16> 7294 [32] is the or of <15:0> 7295 Two PCIe internal interrupts for entries 32-33 7296 which equal CIU_PCI_INTA[INT] */ 7297 uint64_t gpio : 16; /**< 16 GPIO interrupts 7298 When GPIO_MULTI_CAST[EN] == 1 7299 Write 1 to clear either the per PP or common GPIO 7300 edge-triggered interrupts,depending on mode. 7301 See GPIO_MULTI_CAST for all details. 7302 When GPIO_MULTI_CAST[EN] == 0 7303 Read Only, retain the same behavior as o63. */ 7304 uint64_t workq : 16; /**< 16 work queue interrupts 7305 See POW_WQ_INT[WQ_INT] 7306 1 bit/group. A copy of the R/W1C bit in the POW. */ 7307#else 7308 uint64_t workq : 16; 7309 uint64_t gpio : 16; 7310 uint64_t mbox : 2; 7311 uint64_t uart : 2; 7312 uint64_t pci_int : 4; 7313 uint64_t pci_msi : 4; 7314 uint64_t wdog_sum : 1; 7315 uint64_t twsi : 1; 7316 uint64_t rml : 1; 7317 uint64_t trace : 1; 7318 uint64_t gmx_drp : 2; 7319 uint64_t ipd_drp : 1; 7320 uint64_t reserved_51_51 : 1; 7321 uint64_t timer : 4; 7322 uint64_t usb : 1; 7323 uint64_t pcm : 1; 7324 uint64_t mpi : 1; 7325 uint64_t twsi2 : 1; 7326 uint64_t powiq : 1; 7327 uint64_t ipdppthr : 1; 7328 uint64_t mii : 1; 7329 uint64_t bootdma : 1; 7330#endif 7331 } s; 7332 struct cvmx_ciu_intx_sum0_cn30xx { 7333#ifdef __BIG_ENDIAN_BITFIELD 7334 uint64_t reserved_59_63 : 5; 7335 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 7336 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7337 uint64_t usb : 1; /**< USB interrupt */ 7338 uint64_t timer : 4; /**< General timer interrupts */ 7339 uint64_t reserved_51_51 : 1; 7340 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 7341 uint64_t reserved_49_49 : 1; 7342 uint64_t gmx_drp : 1; /**< GMX packet drop */ 7343 uint64_t reserved_47_47 : 1; 7344 uint64_t rml : 1; /**< RML Interrupt */ 7345 uint64_t twsi : 1; /**< TWSI Interrupt */ 7346 uint64_t wdog_sum : 1; /**< Watchdog summary 7347 PPs use CIU_INTx_SUM0 where x=0-1. 7348 PCI uses the CIU_INTx_SUM0 where x=32. 7349 Even INTx registers report WDOG to IP2 7350 Odd INTx registers report WDOG to IP3 */ 7351 uint64_t pci_msi : 4; /**< PCI MSI 7352 [43] is the or of <63:48> 7353 [42] is the or of <47:32> 7354 [41] is the or of <31:16> 7355 [40] is the or of <15:0> */ 7356 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 7357 uint64_t uart : 2; /**< Two UART interrupts */ 7358 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 7359 [33] is the or of <31:16> 7360 [32] is the or of <15:0> 7361 Two PCI internal interrupts for entry 32 7362 CIU_PCI_INTA */ 7363 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7364 uint64_t workq : 16; /**< 16 work queue interrupts 7365 1 bit/group. A copy of the R/W1C bit in the POW. */ 7366#else 7367 uint64_t workq : 16; 7368 uint64_t gpio : 16; 7369 uint64_t mbox : 2; 7370 uint64_t uart : 2; 7371 uint64_t pci_int : 4; 7372 uint64_t pci_msi : 4; 7373 uint64_t wdog_sum : 1; 7374 uint64_t twsi : 1; 7375 uint64_t rml : 1; 7376 uint64_t reserved_47_47 : 1; 7377 uint64_t gmx_drp : 1; 7378 uint64_t reserved_49_49 : 1; 7379 uint64_t ipd_drp : 1; 7380 uint64_t reserved_51_51 : 1; 7381 uint64_t timer : 4; 7382 uint64_t usb : 1; 7383 uint64_t pcm : 1; 7384 uint64_t mpi : 1; 7385 uint64_t reserved_59_63 : 5; 7386#endif 7387 } cn30xx; 7388 struct cvmx_ciu_intx_sum0_cn31xx { 7389#ifdef __BIG_ENDIAN_BITFIELD 7390 uint64_t reserved_59_63 : 5; 7391 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 7392 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7393 uint64_t usb : 1; /**< USB interrupt */ 7394 uint64_t timer : 4; /**< General timer interrupts */ 7395 uint64_t reserved_51_51 : 1; 7396 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 7397 uint64_t reserved_49_49 : 1; 7398 uint64_t gmx_drp : 1; /**< GMX packet drop */ 7399 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 7400 uint64_t rml : 1; /**< RML Interrupt */ 7401 uint64_t twsi : 1; /**< TWSI Interrupt */ 7402 uint64_t wdog_sum : 1; /**< Watchdog summary 7403 PPs use CIU_INTx_SUM0 where x=0-3. 7404 PCI uses the CIU_INTx_SUM0 where x=32. 7405 Even INTx registers report WDOG to IP2 7406 Odd INTx registers report WDOG to IP3 */ 7407 uint64_t pci_msi : 4; /**< PCI MSI 7408 [43] is the or of <63:48> 7409 [42] is the or of <47:32> 7410 [41] is the or of <31:16> 7411 [40] is the or of <15:0> */ 7412 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 7413 uint64_t uart : 2; /**< Two UART interrupts */ 7414 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 7415 [33] is the or of <31:16> 7416 [32] is the or of <15:0> 7417 Two PCI internal interrupts for entry 32 7418 CIU_PCI_INTA */ 7419 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7420 uint64_t workq : 16; /**< 16 work queue interrupts 7421 1 bit/group. A copy of the R/W1C bit in the POW. */ 7422#else 7423 uint64_t workq : 16; 7424 uint64_t gpio : 16; 7425 uint64_t mbox : 2; 7426 uint64_t uart : 2; 7427 uint64_t pci_int : 4; 7428 uint64_t pci_msi : 4; 7429 uint64_t wdog_sum : 1; 7430 uint64_t twsi : 1; 7431 uint64_t rml : 1; 7432 uint64_t trace : 1; 7433 uint64_t gmx_drp : 1; 7434 uint64_t reserved_49_49 : 1; 7435 uint64_t ipd_drp : 1; 7436 uint64_t reserved_51_51 : 1; 7437 uint64_t timer : 4; 7438 uint64_t usb : 1; 7439 uint64_t pcm : 1; 7440 uint64_t mpi : 1; 7441 uint64_t reserved_59_63 : 5; 7442#endif 7443 } cn31xx; 7444 struct cvmx_ciu_intx_sum0_cn38xx { 7445#ifdef __BIG_ENDIAN_BITFIELD 7446 uint64_t reserved_56_63 : 8; 7447 uint64_t timer : 4; /**< General timer interrupts */ 7448 uint64_t key_zero : 1; /**< Key Zeroization interrupt 7449 KEY_ZERO will be set when the external ZERO_KEYS 7450 pin is sampled high. KEY_ZERO is cleared by SW */ 7451 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 7452 uint64_t gmx_drp : 2; /**< GMX packet drop */ 7453 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 7454 uint64_t rml : 1; /**< RML Interrupt */ 7455 uint64_t twsi : 1; /**< TWSI Interrupt */ 7456 uint64_t wdog_sum : 1; /**< Watchdog summary 7457 PPs use CIU_INTx_SUM0 where x=0-31. 7458 PCI uses the CIU_INTx_SUM0 where x=32. 7459 Even INTx registers report WDOG to IP2 7460 Odd INTx registers report WDOG to IP3 */ 7461 uint64_t pci_msi : 4; /**< PCI MSI 7462 [43] is the or of <63:48> 7463 [42] is the or of <47:32> 7464 [41] is the or of <31:16> 7465 [40] is the or of <15:0> */ 7466 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 7467 uint64_t uart : 2; /**< Two UART interrupts */ 7468 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 7469 [33] is the or of <31:16> 7470 [32] is the or of <15:0> 7471 Two PCI internal interrupts for entry 32 7472 CIU_PCI_INTA */ 7473 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7474 uint64_t workq : 16; /**< 16 work queue interrupts 7475 1 bit/group. A copy of the R/W1C bit in the POW. */ 7476#else 7477 uint64_t workq : 16; 7478 uint64_t gpio : 16; 7479 uint64_t mbox : 2; 7480 uint64_t uart : 2; 7481 uint64_t pci_int : 4; 7482 uint64_t pci_msi : 4; 7483 uint64_t wdog_sum : 1; 7484 uint64_t twsi : 1; 7485 uint64_t rml : 1; 7486 uint64_t trace : 1; 7487 uint64_t gmx_drp : 2; 7488 uint64_t ipd_drp : 1; 7489 uint64_t key_zero : 1; 7490 uint64_t timer : 4; 7491 uint64_t reserved_56_63 : 8; 7492#endif 7493 } cn38xx; 7494 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; 7495 struct cvmx_ciu_intx_sum0_cn30xx cn50xx; 7496 struct cvmx_ciu_intx_sum0_cn52xx { 7497#ifdef __BIG_ENDIAN_BITFIELD 7498 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 7499 uint64_t mii : 1; /**< MII Interface Interrupt */ 7500 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 7501 uint64_t powiq : 1; /**< POW IQ interrupt */ 7502 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 7503 uint64_t reserved_57_58 : 2; 7504 uint64_t usb : 1; /**< USB Interrupt */ 7505 uint64_t timer : 4; /**< General timer interrupts */ 7506 uint64_t reserved_51_51 : 1; 7507 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 7508 uint64_t reserved_49_49 : 1; 7509 uint64_t gmx_drp : 1; /**< GMX packet drop */ 7510 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 7511 uint64_t rml : 1; /**< RML Interrupt */ 7512 uint64_t twsi : 1; /**< TWSI Interrupt */ 7513 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 7514 This read-only bit reads as a one whenever any 7515 CIU_INT_SUM1 bit is set and corresponding 7516 enable bit in CIU_INTx_EN is set, where x 7517 is the same as x in this CIU_INTx_SUM0. 7518 PPs use CIU_INTx_SUM0 where x=0-7. 7519 PCI uses the CIU_INTx_SUM0 where x=32. 7520 Even INTx registers report WDOG to IP2 7521 Odd INTx registers report WDOG to IP3 7522 Note that WDOG_SUM only summarizes the SUM/EN1 7523 result and does not have a corresponding enable 7524 bit, so does not directly contribute to 7525 interrupts. */ 7526 uint64_t pci_msi : 4; /**< PCI MSI 7527 Refer to "Receiving Message-Signalled 7528 Interrupts" in the PCIe chapter of the spec */ 7529 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 7530 Refer to "Receiving Emulated INTA/INTB/ 7531 INTC/INTD" in the PCIe chapter of the spec */ 7532 uint64_t uart : 2; /**< Two UART interrupts */ 7533 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-7 7534 [33] is the or of <31:16> 7535 [32] is the or of <15:0> 7536 Two PCI internal interrupts for entry 32 7537 CIU_PCI_INTA */ 7538 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7539 uint64_t workq : 16; /**< 16 work queue interrupts 7540 1 bit/group. A copy of the R/W1C bit in the POW. */ 7541#else 7542 uint64_t workq : 16; 7543 uint64_t gpio : 16; 7544 uint64_t mbox : 2; 7545 uint64_t uart : 2; 7546 uint64_t pci_int : 4; 7547 uint64_t pci_msi : 4; 7548 uint64_t wdog_sum : 1; 7549 uint64_t twsi : 1; 7550 uint64_t rml : 1; 7551 uint64_t trace : 1; 7552 uint64_t gmx_drp : 1; 7553 uint64_t reserved_49_49 : 1; 7554 uint64_t ipd_drp : 1; 7555 uint64_t reserved_51_51 : 1; 7556 uint64_t timer : 4; 7557 uint64_t usb : 1; 7558 uint64_t reserved_57_58 : 2; 7559 uint64_t twsi2 : 1; 7560 uint64_t powiq : 1; 7561 uint64_t ipdppthr : 1; 7562 uint64_t mii : 1; 7563 uint64_t bootdma : 1; 7564#endif 7565 } cn52xx; 7566 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; 7567 struct cvmx_ciu_intx_sum0_cn56xx { 7568#ifdef __BIG_ENDIAN_BITFIELD 7569 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 7570 uint64_t mii : 1; /**< MII Interface Interrupt */ 7571 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 7572 uint64_t powiq : 1; /**< POW IQ interrupt */ 7573 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 7574 uint64_t reserved_57_58 : 2; 7575 uint64_t usb : 1; /**< USB Interrupt */ 7576 uint64_t timer : 4; /**< General timer interrupts */ 7577 uint64_t key_zero : 1; /**< Key Zeroization interrupt 7578 KEY_ZERO will be set when the external ZERO_KEYS 7579 pin is sampled high. KEY_ZERO is cleared by SW */ 7580 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 7581 uint64_t gmx_drp : 2; /**< GMX packet drop */ 7582 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 7583 uint64_t rml : 1; /**< RML Interrupt */ 7584 uint64_t twsi : 1; /**< TWSI Interrupt */ 7585 uint64_t wdog_sum : 1; /**< Watchdog summary 7586 PPs use CIU_INTx_SUM0 where x=0-23. 7587 PCI uses the CIU_INTx_SUM0 where x=32. 7588 Even INTx registers report WDOG to IP2 7589 Odd INTx registers report WDOG to IP3 */ 7590 uint64_t pci_msi : 4; /**< PCI MSI 7591 Refer to "Receiving Message-Signalled 7592 Interrupts" in the PCIe chapter of the spec */ 7593 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 7594 Refer to "Receiving Emulated INTA/INTB/ 7595 INTC/INTD" in the PCIe chapter of the spec */ 7596 uint64_t uart : 2; /**< Two UART interrupts */ 7597 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-23 7598 [33] is the or of <31:16> 7599 [32] is the or of <15:0> 7600 Two PCI internal interrupts for entry 32 7601 CIU_PCI_INTA */ 7602 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7603 uint64_t workq : 16; /**< 16 work queue interrupts 7604 1 bit/group. A copy of the R/W1C bit in the POW. */ 7605#else 7606 uint64_t workq : 16; 7607 uint64_t gpio : 16; 7608 uint64_t mbox : 2; 7609 uint64_t uart : 2; 7610 uint64_t pci_int : 4; 7611 uint64_t pci_msi : 4; 7612 uint64_t wdog_sum : 1; 7613 uint64_t twsi : 1; 7614 uint64_t rml : 1; 7615 uint64_t trace : 1; 7616 uint64_t gmx_drp : 2; 7617 uint64_t ipd_drp : 1; 7618 uint64_t key_zero : 1; 7619 uint64_t timer : 4; 7620 uint64_t usb : 1; 7621 uint64_t reserved_57_58 : 2; 7622 uint64_t twsi2 : 1; 7623 uint64_t powiq : 1; 7624 uint64_t ipdppthr : 1; 7625 uint64_t mii : 1; 7626 uint64_t bootdma : 1; 7627#endif 7628 } cn56xx; 7629 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; 7630 struct cvmx_ciu_intx_sum0_cn38xx cn58xx; 7631 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; 7632 struct cvmx_ciu_intx_sum0_cn61xx { 7633#ifdef __BIG_ENDIAN_BITFIELD 7634 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7635 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7636 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt 7637 See MIX0_ISR */ 7638 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7639 See IPD_PORT_QOS_INT* */ 7640 uint64_t powiq : 1; /**< POW IQ interrupt 7641 See POW_IQ_INT */ 7642 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 7643 See MIO_TWS1_INT */ 7644 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction 7645 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */ 7646 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7647 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 7648 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7649 uint64_t timer : 4; /**< General timer 0-3 interrupts. 7650 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 7651 common for all PP/IRQs, writing '1' to any PP/IRQ 7652 will clear all TIMERx(x=0..9) interrupts. 7653 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 7654 are set at the same time, but clearing are based on 7655 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 7656 The combination of this field and the 7657 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 7658 interrupts. */ 7659 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 7660 This read-only bit reads as a one whenever any 7661 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 7662 and corresponding enable bit in CIU_EN2_PPX_IPx 7663 (CIU_EN2_IOX_INT) is set. 7664 Note that SUM2 only summarizes the SUM2/EN2 7665 result and does not have a corresponding enable 7666 bit, so does not directly contribute to 7667 interrupts. */ 7668 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7669 Set any time PIP/IPD drops a packet */ 7670 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt 7671 Set any time corresponding GMX0/1 drops a packet */ 7672 uint64_t trace : 1; /**< Trace buffer interrupt 7673 See TRA_INT_STATUS */ 7674 uint64_t rml : 1; /**< RML Interrupt 7675 This interrupt will assert if any bit within 7676 CIU_BLOCK_INT is asserted. */ 7677 uint64_t twsi : 1; /**< TWSI Interrupt 7678 See MIO_TWS0_INT */ 7679 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 7680 This read-only bit reads as a one whenever any 7681 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 7682 and corresponding enable bit in CIU_INTx_EN is set 7683 PPs use CIU_INTx_SUM0 where x=0-7 7684 PCIe uses the CIU_INTx_SUM0 where x=32-33. 7685 Note that WDOG_SUM only summarizes the SUM1/EN1 7686 result and does not have a corresponding enable 7687 bit, so does not directly contribute to 7688 interrupts. */ 7689 uint64_t pci_msi : 4; /**< PCIe MSI 7690 See SLI_MSI_RCVn for bit <40+n> */ 7691 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 7692 Refer to "Receiving Emulated INTA/INTB/ 7693 INTC/INTD" in the SLI chapter of the spec 7694 PCI_INT<3> = INTD 7695 PCI_INT<2> = INTC 7696 PCI_INT<1> = INTB 7697 PCI_INT<0> = INTA */ 7698 uint64_t uart : 2; /**< Two UART interrupts 7699 See MIO_UARTn_IIR[IID] for bit <34+n> */ 7700 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 7701 [33] is the or of <31:16> 7702 [32] is the or of <15:0> 7703 Two PCIe internal interrupts for entries 32-33 7704 which equal CIU_PCI_INTA[INT] */ 7705 uint64_t gpio : 16; /**< 16 GPIO interrupts 7706 When GPIO_MULTI_CAST[EN] == 1 7707 Write 1 to clear either the per PP or common GPIO 7708 edge-triggered interrupts,depending on mode. 7709 See GPIO_MULTI_CAST for all details. 7710 When GPIO_MULTI_CAST[EN] == 0 7711 Read Only, retain the same behavior as o63. */ 7712 uint64_t workq : 16; /**< 16 work queue interrupts 7713 See POW_WQ_INT[WQ_INT] 7714 1 bit/group. A copy of the R/W1C bit in the POW. */ 7715#else 7716 uint64_t workq : 16; 7717 uint64_t gpio : 16; 7718 uint64_t mbox : 2; 7719 uint64_t uart : 2; 7720 uint64_t pci_int : 4; 7721 uint64_t pci_msi : 4; 7722 uint64_t wdog_sum : 1; 7723 uint64_t twsi : 1; 7724 uint64_t rml : 1; 7725 uint64_t trace : 1; 7726 uint64_t gmx_drp : 2; 7727 uint64_t ipd_drp : 1; 7728 uint64_t sum2 : 1; 7729 uint64_t timer : 4; 7730 uint64_t usb : 1; 7731 uint64_t pcm : 1; 7732 uint64_t mpi : 1; 7733 uint64_t twsi2 : 1; 7734 uint64_t powiq : 1; 7735 uint64_t ipdppthr : 1; 7736 uint64_t mii : 1; 7737 uint64_t bootdma : 1; 7738#endif 7739 } cn61xx; 7740 struct cvmx_ciu_intx_sum0_cn52xx cn63xx; 7741 struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; 7742 struct cvmx_ciu_intx_sum0_cn66xx { 7743#ifdef __BIG_ENDIAN_BITFIELD 7744 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7745 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7746 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 7747 See MIX0_ISR */ 7748 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7749 See IPD_PORT_QOS_INT* */ 7750 uint64_t powiq : 1; /**< POW IQ interrupt 7751 See POW_IQ_INT */ 7752 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 7753 See MIO_TWS1_INT */ 7754 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction 7755 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */ 7756 uint64_t reserved_57_57 : 1; 7757 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 7758 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7759 uint64_t timer : 4; /**< General timer 0-3 interrupts. 7760 Prior to pass 1.2 or 7761 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is 7762 common for all PP/IRQs, writing '1' to any PP/IRQ 7763 will clear all TIMERx(x=0..9) interrupts. 7764 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 7765 are set at the same time, but clearing is per 7766 cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 7767 The combination of this field and the 7768 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 7769 interrupts. */ 7770 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 7771 In pass 1.2 and subsequent passes, 7772 this read-only bit reads as a one whenever any 7773 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 7774 and corresponding enable bit in CIU_EN2_PPX_IPx 7775 (CIU_EN2_IOX_INT) is set. 7776 Note that SUM2 only summarizes the SUM2/EN2 7777 result and does not have a corresponding enable 7778 bit, so does not directly contribute to 7779 interrupts. 7780 Prior to pass 1.2, SUM2 did not exist and this 7781 bit reads as zero. */ 7782 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7783 Set any time PIP/IPD drops a packet */ 7784 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt 7785 Set any time corresponding GMX0/1 drops a packet */ 7786 uint64_t trace : 1; /**< Trace buffer interrupt 7787 See TRA_INT_STATUS */ 7788 uint64_t rml : 1; /**< RML Interrupt 7789 This interrupt will assert if any bit within 7790 CIU_BLOCK_INT is asserted. */ 7791 uint64_t twsi : 1; /**< TWSI Interrupt 7792 See MIO_TWS0_INT */ 7793 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 7794 This read-only bit reads as a one whenever any 7795 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 7796 and corresponding enable bit in CIU_INTx_EN is set 7797 PPs use CIU_INTx_SUM0 where x=0-19 7798 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 7799 Note that WDOG_SUM only summarizes the SUM1/EN1 7800 result and does not have a corresponding enable 7801 bit, so does not directly contribute to 7802 interrupts. */ 7803 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 7804 See SLI_MSI_RCVn for bit <40+n> */ 7805 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 7806 Refer to "Receiving Emulated INTA/INTB/ 7807 INTC/INTD" in the SLI chapter of the spec 7808 PCI_INT<3> = INTD 7809 PCI_INT<2> = INTC 7810 PCI_INT<1> = INTB 7811 PCI_INT<0> = INTA */ 7812 uint64_t uart : 2; /**< Two UART interrupts 7813 See MIO_UARTn_IIR[IID] for bit <34+n> */ 7814 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 7815 [33] is the or of <31:16> 7816 [32] is the or of <15:0> 7817 Two PCIe/sRIO internal interrupts for entries 32-33 7818 which equal CIU_PCI_INTA[INT] */ 7819 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 7820 uint64_t workq : 16; /**< 16 work queue interrupts 7821 See POW_WQ_INT[WQ_INT] 7822 1 bit/group. A copy of the R/W1C bit in the POW. */ 7823#else 7824 uint64_t workq : 16; 7825 uint64_t gpio : 16; 7826 uint64_t mbox : 2; 7827 uint64_t uart : 2; 7828 uint64_t pci_int : 4; 7829 uint64_t pci_msi : 4; 7830 uint64_t wdog_sum : 1; 7831 uint64_t twsi : 1; 7832 uint64_t rml : 1; 7833 uint64_t trace : 1; 7834 uint64_t gmx_drp : 2; 7835 uint64_t ipd_drp : 1; 7836 uint64_t sum2 : 1; 7837 uint64_t timer : 4; 7838 uint64_t usb : 1; 7839 uint64_t reserved_57_57 : 1; 7840 uint64_t mpi : 1; 7841 uint64_t twsi2 : 1; 7842 uint64_t powiq : 1; 7843 uint64_t ipdppthr : 1; 7844 uint64_t mii : 1; 7845 uint64_t bootdma : 1; 7846#endif 7847 } cn66xx; 7848 struct cvmx_ciu_intx_sum0_cnf71xx { 7849#ifdef __BIG_ENDIAN_BITFIELD 7850 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7851 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7852 uint64_t reserved_62_62 : 1; 7853 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7854 See IPD_PORT_QOS_INT* */ 7855 uint64_t powiq : 1; /**< POW IQ interrupt 7856 See POW_IQ_INT */ 7857 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 7858 See MIO_TWS1_INT */ 7859 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction 7860 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */ 7861 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7862 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 7863 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7864 uint64_t timer : 4; /**< General timer 0-3 interrupts. 7865 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 7866 common for all PP/IRQs, writing '1' to any PP/IRQ 7867 will clear all TIMERx(x=0..9) interrupts. 7868 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 7869 are set at the same time, but clearing are based on 7870 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 7871 The combination of this field and the 7872 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 7873 interrupts. */ 7874 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 7875 This read-only bit reads as a one whenever any 7876 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 7877 and corresponding enable bit in CIU_EN2_PPX_IPx 7878 (CIU_EN2_IOX_INT) is set. 7879 Note that SUM2 only summarizes the SUM2/EN2 7880 result and does not have a corresponding enable 7881 bit, so does not directly contribute to 7882 interrupts. */ 7883 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7884 Set any time PIP/IPD drops a packet */ 7885 uint64_t reserved_49_49 : 1; 7886 uint64_t gmx_drp : 1; /**< GMX0/1 packet drop interrupt 7887 Set any time corresponding GMX0/1 drops a packet */ 7888 uint64_t trace : 1; /**< Trace buffer interrupt 7889 See TRA_INT_STATUS */ 7890 uint64_t rml : 1; /**< RML Interrupt 7891 This interrupt will assert if any bit within 7892 CIU_BLOCK_INT is asserted. */ 7893 uint64_t twsi : 1; /**< TWSI Interrupt 7894 See MIO_TWS0_INT */ 7895 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 7896 This read-only bit reads as a one whenever any 7897 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 7898 and corresponding enable bit in CIU_INTx_EN is set 7899 PPs use CIU_INTx_SUM0 where x=0-7 7900 PCIe uses the CIU_INTx_SUM0 where x=32-33. 7901 Note that WDOG_SUM only summarizes the SUM1/EN1 7902 result and does not have a corresponding enable 7903 bit, so does not directly contribute to 7904 interrupts. */ 7905 uint64_t pci_msi : 4; /**< PCIe MSI 7906 See SLI_MSI_RCVn for bit <40+n> */ 7907 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 7908 Refer to "Receiving Emulated INTA/INTB/ 7909 INTC/INTD" in the SLI chapter of the spec 7910 PCI_INT<3> = INTD 7911 PCI_INT<2> = INTC 7912 PCI_INT<1> = INTB 7913 PCI_INT<0> = INTA */ 7914 uint64_t uart : 2; /**< Two UART interrupts 7915 See MIO_UARTn_IIR[IID] for bit <34+n> */ 7916 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 7917 [33] is the or of <31:16> 7918 [32] is the or of <15:0> 7919 Two PCIe internal interrupts for entries 32-33 7920 which equal CIU_PCI_INTA[INT] */ 7921 uint64_t gpio : 16; /**< 16 GPIO interrupts 7922 When GPIO_MULTI_CAST[EN] == 1 7923 Write 1 to clear either the per PP or common GPIO 7924 edge-triggered interrupts,depending on mode. 7925 See GPIO_MULTI_CAST for all details. 7926 When GPIO_MULTI_CAST[EN] == 0 7927 Read Only, retain the same behavior as o63. */ 7928 uint64_t workq : 16; /**< 16 work queue interrupts 7929 See POW_WQ_INT[WQ_INT] 7930 1 bit/group. A copy of the R/W1C bit in the POW. */ 7931#else 7932 uint64_t workq : 16; 7933 uint64_t gpio : 16; 7934 uint64_t mbox : 2; 7935 uint64_t uart : 2; 7936 uint64_t pci_int : 4; 7937 uint64_t pci_msi : 4; 7938 uint64_t wdog_sum : 1; 7939 uint64_t twsi : 1; 7940 uint64_t rml : 1; 7941 uint64_t trace : 1; 7942 uint64_t gmx_drp : 1; 7943 uint64_t reserved_49_49 : 1; 7944 uint64_t ipd_drp : 1; 7945 uint64_t sum2 : 1; 7946 uint64_t timer : 4; 7947 uint64_t usb : 1; 7948 uint64_t pcm : 1; 7949 uint64_t mpi : 1; 7950 uint64_t twsi2 : 1; 7951 uint64_t powiq : 1; 7952 uint64_t ipdppthr : 1; 7953 uint64_t reserved_62_62 : 1; 7954 uint64_t bootdma : 1; 7955#endif 7956 } cnf71xx; 7957}; 7958typedef union cvmx_ciu_intx_sum0 cvmx_ciu_intx_sum0_t; 7959 7960/** 7961 * cvmx_ciu_int#_sum4 7962 */ 7963union cvmx_ciu_intx_sum4 { 7964 uint64_t u64; 7965 struct cvmx_ciu_intx_sum4_s { 7966#ifdef __BIG_ENDIAN_BITFIELD 7967 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 7968 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 7969 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 7970 See MIX0_ISR */ 7971 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 7972 See IPD_PORT_QOS_INT* */ 7973 uint64_t powiq : 1; /**< POW IQ interrupt 7974 See POW_IQ_INT */ 7975 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 7976 See MIO_TWS1_INT */ 7977 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 7978 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 7979 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 7980 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 7981 uint64_t timer : 4; /**< General timer 0-3 interrupts 7982 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 7983 common for all PP/IRQs, writing '1' to any PP/IRQ 7984 will clear all TIMERx(x=0..9) interrupts. 7985 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 7986 are set at the same time, but clearing are based on 7987 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 7988 The combination of this field and the 7989 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 7990 interrupts. */ 7991 uint64_t reserved_51_51 : 1; 7992 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 7993 Set any time PIP/IPD drops a packet */ 7994 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 7995 Set any time corresponding GMX drops a packet */ 7996 uint64_t trace : 1; /**< Trace buffer interrupt 7997 See TRA_INT_STATUS */ 7998 uint64_t rml : 1; /**< RML Interrupt 7999 This bit is set when any bit is set in 8000 CIU_BLOCK_INT. */ 8001 uint64_t twsi : 1; /**< TWSI Interrupt 8002 See MIO_TWS0_INT */ 8003 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8004 This read-only bit reads as a one whenever any 8005 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 8006 and corresponding enable bit in CIU_INTx_EN is set 8007 PPs use CIU_INTx_SUM0 where x=0-19 8008 PCIe uses the CIU_INTx_SUM0 where x=32-33. 8009 Note that WDOG_SUM only summarizes the SUM1/EN1 8010 result and does not have a corresponding enable 8011 bit, so does not directly contribute to 8012 interrupts. */ 8013 uint64_t pci_msi : 4; /**< PCIe MSI 8014 See SLI_MSI_RCVn for bit <40+n> */ 8015 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8016 Refer to "Receiving Emulated INTA/INTB/ 8017 INTC/INTD" in the SLI chapter of the spec 8018 PCI_INT<3> = INTD 8019 PCI_INT<2> = INTC 8020 PCI_INT<1> = INTB 8021 PCI_INT<0> = INTA */ 8022 uint64_t uart : 2; /**< Two UART interrupts 8023 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8024 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5 8025 [33] is the or of <31:16> 8026 [32] is the or of <15:0> */ 8027 uint64_t gpio : 16; /**< 16 GPIO interrupts 8028 When GPIO_MULTI_CAST[EN] == 1 8029 Write 1 to clear either the per PP interrupt or 8030 common GPIO interrupt for all PP/IOs,depending 8031 on mode setting. This will apply to all 16 GPIOs. 8032 See GPIO_MULTI_CAST for all details 8033 When GPIO_MULTI_CAST[EN] == 0 8034 Read Only, retain the same behavior as o63. */ 8035 uint64_t workq : 16; /**< 16 work queue interrupts 8036 See POW_WQ_INT[WQ_INT] 8037 1 bit/group. A copy of the R/W1C bit in the POW. */ 8038#else 8039 uint64_t workq : 16; 8040 uint64_t gpio : 16; 8041 uint64_t mbox : 2; 8042 uint64_t uart : 2; 8043 uint64_t pci_int : 4; 8044 uint64_t pci_msi : 4; 8045 uint64_t wdog_sum : 1; 8046 uint64_t twsi : 1; 8047 uint64_t rml : 1; 8048 uint64_t trace : 1; 8049 uint64_t gmx_drp : 2; 8050 uint64_t ipd_drp : 1; 8051 uint64_t reserved_51_51 : 1; 8052 uint64_t timer : 4; 8053 uint64_t usb : 1; 8054 uint64_t pcm : 1; 8055 uint64_t mpi : 1; 8056 uint64_t twsi2 : 1; 8057 uint64_t powiq : 1; 8058 uint64_t ipdppthr : 1; 8059 uint64_t mii : 1; 8060 uint64_t bootdma : 1; 8061#endif 8062 } s; 8063 struct cvmx_ciu_intx_sum4_cn50xx { 8064#ifdef __BIG_ENDIAN_BITFIELD 8065 uint64_t reserved_59_63 : 5; 8066 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8067 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 8068 uint64_t usb : 1; /**< USB interrupt */ 8069 uint64_t timer : 4; /**< General timer interrupts */ 8070 uint64_t reserved_51_51 : 1; 8071 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 8072 uint64_t reserved_49_49 : 1; 8073 uint64_t gmx_drp : 1; /**< GMX packet drop */ 8074 uint64_t reserved_47_47 : 1; 8075 uint64_t rml : 1; /**< RML Interrupt */ 8076 uint64_t twsi : 1; /**< TWSI Interrupt */ 8077 uint64_t wdog_sum : 1; /**< Watchdog summary 8078 PPs use CIU_INTx_SUM4 where x=0-1. */ 8079 uint64_t pci_msi : 4; /**< PCI MSI 8080 [43] is the or of <63:48> 8081 [42] is the or of <47:32> 8082 [41] is the or of <31:16> 8083 [40] is the or of <15:0> */ 8084 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 8085 uint64_t uart : 2; /**< Two UART interrupts */ 8086 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 8087 [33] is the or of <31:16> 8088 [32] is the or of <15:0> 8089 Two PCI internal interrupts for entry 32 8090 CIU_PCI_INTA */ 8091 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8092 uint64_t workq : 16; /**< 16 work queue interrupts 8093 1 bit/group. A copy of the R/W1C bit in the POW. */ 8094#else 8095 uint64_t workq : 16; 8096 uint64_t gpio : 16; 8097 uint64_t mbox : 2; 8098 uint64_t uart : 2; 8099 uint64_t pci_int : 4; 8100 uint64_t pci_msi : 4; 8101 uint64_t wdog_sum : 1; 8102 uint64_t twsi : 1; 8103 uint64_t rml : 1; 8104 uint64_t reserved_47_47 : 1; 8105 uint64_t gmx_drp : 1; 8106 uint64_t reserved_49_49 : 1; 8107 uint64_t ipd_drp : 1; 8108 uint64_t reserved_51_51 : 1; 8109 uint64_t timer : 4; 8110 uint64_t usb : 1; 8111 uint64_t pcm : 1; 8112 uint64_t mpi : 1; 8113 uint64_t reserved_59_63 : 5; 8114#endif 8115 } cn50xx; 8116 struct cvmx_ciu_intx_sum4_cn52xx { 8117#ifdef __BIG_ENDIAN_BITFIELD 8118 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 8119 uint64_t mii : 1; /**< MII Interface Interrupt */ 8120 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 8121 uint64_t powiq : 1; /**< POW IQ interrupt */ 8122 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 8123 uint64_t reserved_57_58 : 2; 8124 uint64_t usb : 1; /**< USB Interrupt */ 8125 uint64_t timer : 4; /**< General timer interrupts */ 8126 uint64_t reserved_51_51 : 1; 8127 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 8128 uint64_t reserved_49_49 : 1; 8129 uint64_t gmx_drp : 1; /**< GMX packet drop */ 8130 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 8131 uint64_t rml : 1; /**< RML Interrupt */ 8132 uint64_t twsi : 1; /**< TWSI Interrupt */ 8133 uint64_t wdog_sum : 1; /**< SUM1&EN4_1 summary bit 8134 This read-only bit reads as a one whenever any 8135 CIU_INT_SUM1 bit is set and corresponding 8136 enable bit in CIU_INTx_EN4_1 is set, where x 8137 is the same as x in this CIU_INTx_SUM4. 8138 PPs use CIU_INTx_SUM4 for IP4, where x=PPid. 8139 Note that WDOG_SUM only summarizes the SUM/EN4_1 8140 result and does not have a corresponding enable 8141 bit, so does not directly contribute to 8142 interrupts. */ 8143 uint64_t pci_msi : 4; /**< PCI MSI 8144 Refer to "Receiving Message-Signalled 8145 Interrupts" in the PCIe chapter of the spec */ 8146 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 8147 Refer to "Receiving Emulated INTA/INTB/ 8148 INTC/INTD" in the PCIe chapter of the spec */ 8149 uint64_t uart : 2; /**< Two UART interrupts */ 8150 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-3 8151 [33] is the or of <31:16> 8152 [32] is the or of <15:0> */ 8153 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8154 uint64_t workq : 16; /**< 16 work queue interrupts 8155 1 bit/group. A copy of the R/W1C bit in the POW. */ 8156#else 8157 uint64_t workq : 16; 8158 uint64_t gpio : 16; 8159 uint64_t mbox : 2; 8160 uint64_t uart : 2; 8161 uint64_t pci_int : 4; 8162 uint64_t pci_msi : 4; 8163 uint64_t wdog_sum : 1; 8164 uint64_t twsi : 1; 8165 uint64_t rml : 1; 8166 uint64_t trace : 1; 8167 uint64_t gmx_drp : 1; 8168 uint64_t reserved_49_49 : 1; 8169 uint64_t ipd_drp : 1; 8170 uint64_t reserved_51_51 : 1; 8171 uint64_t timer : 4; 8172 uint64_t usb : 1; 8173 uint64_t reserved_57_58 : 2; 8174 uint64_t twsi2 : 1; 8175 uint64_t powiq : 1; 8176 uint64_t ipdppthr : 1; 8177 uint64_t mii : 1; 8178 uint64_t bootdma : 1; 8179#endif 8180 } cn52xx; 8181 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; 8182 struct cvmx_ciu_intx_sum4_cn56xx { 8183#ifdef __BIG_ENDIAN_BITFIELD 8184 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 8185 uint64_t mii : 1; /**< MII Interface Interrupt */ 8186 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 8187 uint64_t powiq : 1; /**< POW IQ interrupt */ 8188 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 8189 uint64_t reserved_57_58 : 2; 8190 uint64_t usb : 1; /**< USB Interrupt */ 8191 uint64_t timer : 4; /**< General timer interrupts */ 8192 uint64_t key_zero : 1; /**< Key Zeroization interrupt 8193 KEY_ZERO will be set when the external ZERO_KEYS 8194 pin is sampled high. KEY_ZERO is cleared by SW */ 8195 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 8196 uint64_t gmx_drp : 2; /**< GMX packet drop */ 8197 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 8198 uint64_t rml : 1; /**< RML Interrupt */ 8199 uint64_t twsi : 1; /**< TWSI Interrupt */ 8200 uint64_t wdog_sum : 1; /**< Watchdog summary 8201 These registers report WDOG to IP4 */ 8202 uint64_t pci_msi : 4; /**< PCI MSI 8203 Refer to "Receiving Message-Signalled 8204 Interrupts" in the PCIe chapter of the spec */ 8205 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 8206 Refer to "Receiving Emulated INTA/INTB/ 8207 INTC/INTD" in the PCIe chapter of the spec */ 8208 uint64_t uart : 2; /**< Two UART interrupts */ 8209 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 8210 [33] is the or of <31:16> 8211 [32] is the or of <15:0> */ 8212 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8213 uint64_t workq : 16; /**< 16 work queue interrupts 8214 1 bit/group. A copy of the R/W1C bit in the POW. */ 8215#else 8216 uint64_t workq : 16; 8217 uint64_t gpio : 16; 8218 uint64_t mbox : 2; 8219 uint64_t uart : 2; 8220 uint64_t pci_int : 4; 8221 uint64_t pci_msi : 4; 8222 uint64_t wdog_sum : 1; 8223 uint64_t twsi : 1; 8224 uint64_t rml : 1; 8225 uint64_t trace : 1; 8226 uint64_t gmx_drp : 2; 8227 uint64_t ipd_drp : 1; 8228 uint64_t key_zero : 1; 8229 uint64_t timer : 4; 8230 uint64_t usb : 1; 8231 uint64_t reserved_57_58 : 2; 8232 uint64_t twsi2 : 1; 8233 uint64_t powiq : 1; 8234 uint64_t ipdppthr : 1; 8235 uint64_t mii : 1; 8236 uint64_t bootdma : 1; 8237#endif 8238 } cn56xx; 8239 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; 8240 struct cvmx_ciu_intx_sum4_cn58xx { 8241#ifdef __BIG_ENDIAN_BITFIELD 8242 uint64_t reserved_56_63 : 8; 8243 uint64_t timer : 4; /**< General timer interrupts */ 8244 uint64_t key_zero : 1; /**< Key Zeroization interrupt 8245 KEY_ZERO will be set when the external ZERO_KEYS 8246 pin is sampled high. KEY_ZERO is cleared by SW */ 8247 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 8248 uint64_t gmx_drp : 2; /**< GMX packet drop */ 8249 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 8250 uint64_t rml : 1; /**< RML Interrupt */ 8251 uint64_t twsi : 1; /**< TWSI Interrupt */ 8252 uint64_t wdog_sum : 1; /**< Watchdog summary 8253 These registers report WDOG to IP4 */ 8254 uint64_t pci_msi : 4; /**< PCI MSI 8255 [43] is the or of <63:48> 8256 [42] is the or of <47:32> 8257 [41] is the or of <31:16> 8258 [40] is the or of <15:0> */ 8259 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 8260 uint64_t uart : 2; /**< Two UART interrupts */ 8261 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 8262 [33] is the or of <31:16> 8263 [32] is the or of <15:0> 8264 Two PCI internal interrupts for entry 32 8265 CIU_PCI_INTA */ 8266 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8267 uint64_t workq : 16; /**< 16 work queue interrupts 8268 1 bit/group. A copy of the R/W1C bit in the POW. */ 8269#else 8270 uint64_t workq : 16; 8271 uint64_t gpio : 16; 8272 uint64_t mbox : 2; 8273 uint64_t uart : 2; 8274 uint64_t pci_int : 4; 8275 uint64_t pci_msi : 4; 8276 uint64_t wdog_sum : 1; 8277 uint64_t twsi : 1; 8278 uint64_t rml : 1; 8279 uint64_t trace : 1; 8280 uint64_t gmx_drp : 2; 8281 uint64_t ipd_drp : 1; 8282 uint64_t key_zero : 1; 8283 uint64_t timer : 4; 8284 uint64_t reserved_56_63 : 8; 8285#endif 8286 } cn58xx; 8287 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; 8288 struct cvmx_ciu_intx_sum4_cn61xx { 8289#ifdef __BIG_ENDIAN_BITFIELD 8290 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8291 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8292 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt 8293 See MIX0_ISR */ 8294 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8295 See IPD_PORT_QOS_INT* */ 8296 uint64_t powiq : 1; /**< POW IQ interrupt 8297 See POW_IQ_INT */ 8298 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8299 See MIO_TWS1_INT */ 8300 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8301 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 8302 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8303 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8304 uint64_t timer : 4; /**< General timer 0-3 interrupts 8305 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 8306 common for all PP/IRQs, writing '1' to any PP/IRQ 8307 will clear all TIMERx(x=0..9) interrupts. 8308 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8309 are set at the same time, but clearing are based on 8310 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8311 The combination of this field and the 8312 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8313 interrupts. */ 8314 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8315 This read-only bit reads as a one whenever any 8316 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8317 and corresponding enable bit in CIU_EN2_PPX_IPx 8318 (CIU_EN2_IOX_INT) is set. 8319 Note that WDOG_SUM only summarizes the SUM2/EN2 8320 result and does not have a corresponding enable 8321 bit, so does not directly contribute to 8322 interrupts. */ 8323 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8324 Set any time PIP/IPD drops a packet */ 8325 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 8326 Set any time corresponding GMX drops a packet */ 8327 uint64_t trace : 1; /**< Trace buffer interrupt 8328 See TRA_INT_STATUS */ 8329 uint64_t rml : 1; /**< RML Interrupt 8330 This bit is set when any bit is set in 8331 CIU_BLOCK_INT. */ 8332 uint64_t twsi : 1; /**< TWSI Interrupt 8333 See MIO_TWS0_INT */ 8334 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8335 This read-only bit reads as a one whenever any 8336 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 8337 and corresponding enable bit in CIU_INTx_EN is set 8338 PPs use CIU_INTx_SUM0 where x=0-19 8339 PCIe uses the CIU_INTx_SUM0 where x=32-33. 8340 Note that WDOG_SUM only summarizes the SUM1/EN1 8341 result and does not have a corresponding enable 8342 bit, so does not directly contribute to 8343 interrupts. */ 8344 uint64_t pci_msi : 4; /**< PCIe MSI 8345 See SLI_MSI_RCVn for bit <40+n> */ 8346 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8347 Refer to "Receiving Emulated INTA/INTB/ 8348 INTC/INTD" in the SLI chapter of the spec 8349 PCI_INT<3> = INTD 8350 PCI_INT<2> = INTC 8351 PCI_INT<1> = INTB 8352 PCI_INT<0> = INTA */ 8353 uint64_t uart : 2; /**< Two UART interrupts 8354 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8355 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5 8356 [33] is the or of <31:16> 8357 [32] is the or of <15:0> */ 8358 uint64_t gpio : 16; /**< 16 GPIO interrupts 8359 When GPIO_MULTI_CAST[EN] == 1 8360 Write 1 to clear either the per PP interrupt or 8361 common GPIO interrupt for all PP/IOs,depending 8362 on mode setting. This will apply to all 16 GPIOs. 8363 See GPIO_MULTI_CAST for all details 8364 When GPIO_MULTI_CAST[EN] == 0 8365 Read Only, retain the same behavior as o63. */ 8366 uint64_t workq : 16; /**< 16 work queue interrupts 8367 See POW_WQ_INT[WQ_INT] 8368 1 bit/group. A copy of the R/W1C bit in the POW. */ 8369#else 8370 uint64_t workq : 16; 8371 uint64_t gpio : 16; 8372 uint64_t mbox : 2; 8373 uint64_t uart : 2; 8374 uint64_t pci_int : 4; 8375 uint64_t pci_msi : 4; 8376 uint64_t wdog_sum : 1; 8377 uint64_t twsi : 1; 8378 uint64_t rml : 1; 8379 uint64_t trace : 1; 8380 uint64_t gmx_drp : 2; 8381 uint64_t ipd_drp : 1; 8382 uint64_t sum2 : 1; 8383 uint64_t timer : 4; 8384 uint64_t usb : 1; 8385 uint64_t pcm : 1; 8386 uint64_t mpi : 1; 8387 uint64_t twsi2 : 1; 8388 uint64_t powiq : 1; 8389 uint64_t ipdppthr : 1; 8390 uint64_t mii : 1; 8391 uint64_t bootdma : 1; 8392#endif 8393 } cn61xx; 8394 struct cvmx_ciu_intx_sum4_cn52xx cn63xx; 8395 struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; 8396 struct cvmx_ciu_intx_sum4_cn66xx { 8397#ifdef __BIG_ENDIAN_BITFIELD 8398 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8399 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8400 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 8401 See MIX0_ISR */ 8402 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8403 See IPD_PORT_QOS_INT* */ 8404 uint64_t powiq : 1; /**< POW IQ interrupt 8405 See POW_IQ_INT */ 8406 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8407 See MIO_TWS1_INT */ 8408 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8409 uint64_t reserved_57_57 : 1; 8410 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8411 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8412 uint64_t timer : 4; /**< General timer 0-3 interrupts. 8413 Prior to pass 1.2 or 8414 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is 8415 common for all PP/IRQs, writing '1' to any PP/IRQ 8416 will clear all TIMERx(x=0..9) interrupts. 8417 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8418 are set at the same time, but clearing is per 8419 cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8420 The combination of this field and the 8421 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8422 interrupts. */ 8423 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8424 In pass 1.2 and subsequent passes, 8425 this read-only bit reads as a one whenever any 8426 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8427 and corresponding enable bit in CIU_EN2_PPX_IPx 8428 (CIU_EN2_IOX_INT) is set. 8429 Note that WDOG_SUM only summarizes the SUM2/EN2 8430 result and does not have a corresponding enable 8431 bit, so does not directly contribute to 8432 interrupts. 8433 Prior to pass 1.2, SUM2 did not exist and this 8434 bit reads as zero. */ 8435 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8436 Set any time PIP/IPD drops a packet */ 8437 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 8438 Set any time corresponding GMX drops a packet */ 8439 uint64_t trace : 1; /**< Trace buffer interrupt 8440 See TRA_INT_STATUS */ 8441 uint64_t rml : 1; /**< RML Interrupt 8442 This bit is set when any bit is set in 8443 CIU_BLOCK_INT. */ 8444 uint64_t twsi : 1; /**< TWSI Interrupt 8445 See MIO_TWS0_INT */ 8446 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8447 This read-only bit reads as a one whenever any 8448 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 8449 and corresponding enable bit in CIU_INTx_EN is set 8450 PPs use CIU_INTx_SUM0 where x=0-19 8451 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 8452 Note that WDOG_SUM only summarizes the SUM1/EN1 8453 result and does not have a corresponding enable 8454 bit, so does not directly contribute to 8455 interrupts. */ 8456 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 8457 See SLI_MSI_RCVn for bit <40+n> */ 8458 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8459 Refer to "Receiving Emulated INTA/INTB/ 8460 INTC/INTD" in the SLI chapter of the spec 8461 PCI_INT<3> = INTD 8462 PCI_INT<2> = INTC 8463 PCI_INT<1> = INTB 8464 PCI_INT<0> = INTA */ 8465 uint64_t uart : 2; /**< Two UART interrupts 8466 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8467 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5 8468 [33] is the or of <31:16> 8469 [32] is the or of <15:0> */ 8470 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8471 uint64_t workq : 16; /**< 16 work queue interrupts 8472 See POW_WQ_INT[WQ_INT] 8473 1 bit/group. A copy of the R/W1C bit in the POW. */ 8474#else 8475 uint64_t workq : 16; 8476 uint64_t gpio : 16; 8477 uint64_t mbox : 2; 8478 uint64_t uart : 2; 8479 uint64_t pci_int : 4; 8480 uint64_t pci_msi : 4; 8481 uint64_t wdog_sum : 1; 8482 uint64_t twsi : 1; 8483 uint64_t rml : 1; 8484 uint64_t trace : 1; 8485 uint64_t gmx_drp : 2; 8486 uint64_t ipd_drp : 1; 8487 uint64_t sum2 : 1; 8488 uint64_t timer : 4; 8489 uint64_t usb : 1; 8490 uint64_t reserved_57_57 : 1; 8491 uint64_t mpi : 1; 8492 uint64_t twsi2 : 1; 8493 uint64_t powiq : 1; 8494 uint64_t ipdppthr : 1; 8495 uint64_t mii : 1; 8496 uint64_t bootdma : 1; 8497#endif 8498 } cn66xx; 8499 struct cvmx_ciu_intx_sum4_cnf71xx { 8500#ifdef __BIG_ENDIAN_BITFIELD 8501 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8502 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8503 uint64_t reserved_62_62 : 1; 8504 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8505 See IPD_PORT_QOS_INT* */ 8506 uint64_t powiq : 1; /**< POW IQ interrupt 8507 See POW_IQ_INT */ 8508 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8509 See MIO_TWS1_INT */ 8510 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8511 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 8512 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8513 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8514 uint64_t timer : 4; /**< General timer 0-3 interrupts 8515 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 8516 common for all PP/IRQs, writing '1' to any PP/IRQ 8517 will clear all TIMERx(x=0..9) interrupts. 8518 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8519 are set at the same time, but clearing are based on 8520 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8521 The combination of this field and the 8522 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8523 interrupts. */ 8524 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8525 This read-only bit reads as a one whenever any 8526 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8527 and corresponding enable bit in CIU_EN2_PPX_IPx 8528 (CIU_EN2_IOX_INT) is set. 8529 Note that WDOG_SUM only summarizes the SUM2/EN2 8530 result and does not have a corresponding enable 8531 bit, so does not directly contribute to 8532 interrupts. */ 8533 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8534 Set any time PIP/IPD drops a packet */ 8535 uint64_t reserved_49_49 : 1; 8536 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt 8537 Set any time corresponding GMX drops a packet */ 8538 uint64_t trace : 1; /**< Trace buffer interrupt 8539 See TRA_INT_STATUS */ 8540 uint64_t rml : 1; /**< RML Interrupt 8541 This bit is set when any bit is set in 8542 CIU_BLOCK_INT. */ 8543 uint64_t twsi : 1; /**< TWSI Interrupt 8544 See MIO_TWS0_INT */ 8545 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8546 This read-only bit reads as a one whenever any 8547 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 8548 and corresponding enable bit in CIU_INTx_EN is set 8549 PPs use CIU_INTx_SUM0 where x=0-19 8550 PCIe uses the CIU_INTx_SUM0 where x=32-33. 8551 Note that WDOG_SUM only summarizes the SUM1/EN1 8552 result and does not have a corresponding enable 8553 bit, so does not directly contribute to 8554 interrupts. */ 8555 uint64_t pci_msi : 4; /**< PCIe MSI 8556 See SLI_MSI_RCVn for bit <40+n> */ 8557 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8558 Refer to "Receiving Emulated INTA/INTB/ 8559 INTC/INTD" in the SLI chapter of the spec 8560 PCI_INT<3> = INTD 8561 PCI_INT<2> = INTC 8562 PCI_INT<1> = INTB 8563 PCI_INT<0> = INTA */ 8564 uint64_t uart : 2; /**< Two UART interrupts 8565 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8566 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5 8567 [33] is the or of <31:16> 8568 [32] is the or of <15:0> */ 8569 uint64_t gpio : 16; /**< 16 GPIO interrupts 8570 When GPIO_MULTI_CAST[EN] == 1 8571 Write 1 to clear either the per PP interrupt or 8572 common GPIO interrupt for all PP/IOs,depending 8573 on mode setting. This will apply to all 16 GPIOs. 8574 See GPIO_MULTI_CAST for all details 8575 When GPIO_MULTI_CAST[EN] == 0 8576 Read Only, retain the same behavior as o63. */ 8577 uint64_t workq : 16; /**< 16 work queue interrupts 8578 See POW_WQ_INT[WQ_INT] 8579 1 bit/group. A copy of the R/W1C bit in the POW. */ 8580#else 8581 uint64_t workq : 16; 8582 uint64_t gpio : 16; 8583 uint64_t mbox : 2; 8584 uint64_t uart : 2; 8585 uint64_t pci_int : 4; 8586 uint64_t pci_msi : 4; 8587 uint64_t wdog_sum : 1; 8588 uint64_t twsi : 1; 8589 uint64_t rml : 1; 8590 uint64_t trace : 1; 8591 uint64_t gmx_drp : 1; 8592 uint64_t reserved_49_49 : 1; 8593 uint64_t ipd_drp : 1; 8594 uint64_t sum2 : 1; 8595 uint64_t timer : 4; 8596 uint64_t usb : 1; 8597 uint64_t pcm : 1; 8598 uint64_t mpi : 1; 8599 uint64_t twsi2 : 1; 8600 uint64_t powiq : 1; 8601 uint64_t ipdppthr : 1; 8602 uint64_t reserved_62_62 : 1; 8603 uint64_t bootdma : 1; 8604#endif 8605 } cnf71xx; 8606}; 8607typedef union cvmx_ciu_intx_sum4 cvmx_ciu_intx_sum4_t; 8608 8609/** 8610 * cvmx_ciu_int33_sum0 8611 */ 8612union cvmx_ciu_int33_sum0 { 8613 uint64_t u64; 8614 struct cvmx_ciu_int33_sum0_s { 8615#ifdef __BIG_ENDIAN_BITFIELD 8616 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8617 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8618 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 8619 See MIX0_ISR */ 8620 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8621 See IPD_PORT_QOS_INT* */ 8622 uint64_t powiq : 1; /**< POW IQ interrupt 8623 See POW_IQ_INT */ 8624 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8625 See MIO_TWS1_INT */ 8626 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8627 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 8628 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8629 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8630 uint64_t timer : 4; /**< General timer 0-3 interrupts. 8631 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 8632 common for all PP/IRQs, writing '1' to any PP/IRQ 8633 will clear all TIMERx(x=0..9) interrupts. 8634 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8635 are set at the same time, but clearing are based on 8636 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8637 The combination of this field and the 8638 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8639 interrupts. */ 8640 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8641 This read-only bit reads as a one whenever any 8642 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8643 and corresponding enable bit in CIU_EN2_PPX_IPx 8644 (CIU_EN2_IOX_INT) is set. 8645 Note that SUM2 only summarizes the SUM2/EN2 8646 result and does not have a corresponding enable 8647 bit, so does not directly contribute to 8648 interrupts. */ 8649 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8650 Set any time PIP/IPD drops a packet */ 8651 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 8652 Set any time corresponding GMX drops a packet */ 8653 uint64_t trace : 1; /**< Trace buffer interrupt 8654 See TRA_INT_STATUS */ 8655 uint64_t rml : 1; /**< RML Interrupt 8656 This interrupt will assert if any bit within 8657 CIU_BLOCK_INT is asserted. */ 8658 uint64_t twsi : 1; /**< TWSI Interrupt 8659 See MIO_TWS0_INT */ 8660 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8661 This read-only bit reads as a one whenever any 8662 CIU_SUM1_PPX_IPx bit is set and corresponding 8663 enable bit in CIU_INTx_EN is set, where x 8664 is the same as x in this CIU_INTx_SUM0. 8665 PPs use CIU_INTx_SUM0 where x=0-7. 8666 PCIe uses the CIU_INTx_SUM0 where x=32-33. 8667 Note that WDOG_SUM only summarizes the SUM1/EN1 8668 result and does not have a corresponding enable 8669 bit, so does not directly contribute to 8670 interrupts. */ 8671 uint64_t pci_msi : 4; /**< PCIe MSI 8672 See SLI_MSI_RCVn for bit <40+n> */ 8673 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8674 Refer to "Receiving Emulated INTA/INTB/ 8675 INTC/INTD" in the SLI chapter of the spec 8676 PCI_INT<3> = INTD 8677 PCI_INT<2> = INTC 8678 PCI_INT<1> = INTB 8679 PCI_INT<0> = INTA */ 8680 uint64_t uart : 2; /**< Two UART interrupts 8681 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8682 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */ 8683 uint64_t gpio : 16; /**< 16 GPIO interrupts 8684 When GPIO_MULTI_CAST[EN] == 1 8685 Write 1 to clear either the per PP or common GPIO 8686 edge-triggered interrupts,depending on mode. 8687 See GPIO_MULTI_CAST for all details. 8688 When GPIO_MULTI_CAST[EN] == 0 8689 Read Only, retain the same behavior as o63. */ 8690 uint64_t workq : 16; /**< 16 work queue interrupts 8691 See POW_WQ_INT[WQ_INT] 8692 1 bit/group. A copy of the R/W1C bit in the POW. */ 8693#else 8694 uint64_t workq : 16; 8695 uint64_t gpio : 16; 8696 uint64_t mbox : 2; 8697 uint64_t uart : 2; 8698 uint64_t pci_int : 4; 8699 uint64_t pci_msi : 4; 8700 uint64_t wdog_sum : 1; 8701 uint64_t twsi : 1; 8702 uint64_t rml : 1; 8703 uint64_t trace : 1; 8704 uint64_t gmx_drp : 2; 8705 uint64_t ipd_drp : 1; 8706 uint64_t sum2 : 1; 8707 uint64_t timer : 4; 8708 uint64_t usb : 1; 8709 uint64_t pcm : 1; 8710 uint64_t mpi : 1; 8711 uint64_t twsi2 : 1; 8712 uint64_t powiq : 1; 8713 uint64_t ipdppthr : 1; 8714 uint64_t mii : 1; 8715 uint64_t bootdma : 1; 8716#endif 8717 } s; 8718 struct cvmx_ciu_int33_sum0_s cn61xx; 8719 struct cvmx_ciu_int33_sum0_cn63xx { 8720#ifdef __BIG_ENDIAN_BITFIELD 8721 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8722 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8723 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 8724 See MIX0_ISR */ 8725 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8726 See IPD_PORT_QOS_INT* */ 8727 uint64_t powiq : 1; /**< POW IQ interrupt 8728 See POW_IQ_INT */ 8729 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8730 See MIO_TWS1_INT */ 8731 uint64_t reserved_57_58 : 2; 8732 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8733 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8734 uint64_t timer : 4; /**< General timer interrupts 8735 Set any time the corresponding CIU timer expires */ 8736 uint64_t reserved_51_51 : 1; 8737 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8738 Set any time PIP/IPD drops a packet */ 8739 uint64_t reserved_49_49 : 1; 8740 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt 8741 Set any time corresponding GMX drops a packet */ 8742 uint64_t trace : 1; /**< Trace buffer interrupt 8743 See TRA_INT_STATUS */ 8744 uint64_t rml : 1; /**< RML Interrupt 8745 This interrupt will assert if any bit within 8746 CIU_BLOCK_INT is asserted. */ 8747 uint64_t twsi : 1; /**< TWSI Interrupt 8748 See MIO_TWS0_INT */ 8749 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8750 This read-only bit reads as a one whenever any 8751 CIU_INT_SUM1 bit is set and corresponding 8752 enable bit in CIU_INTx_EN is set, where x 8753 is the same as x in this CIU_INTx_SUM0. 8754 PPs use CIU_INTx_SUM0 where x=0-11. 8755 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 8756 Even INTx registers report WDOG to IP2 8757 Odd INTx registers report WDOG to IP3 8758 Note that WDOG_SUM only summarizes the SUM/EN1 8759 result and does not have a corresponding enable 8760 bit, so does not directly contribute to 8761 interrupts. */ 8762 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 8763 See SLI_MSI_RCVn for bit <40+n> */ 8764 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8765 Refer to "Receiving Emulated INTA/INTB/ 8766 INTC/INTD" in the SLI chapter of the spec 8767 PCI_INT<3> = INTD 8768 PCI_INT<2> = INTC 8769 PCI_INT<1> = INTB 8770 PCI_INT<0> = INTA */ 8771 uint64_t uart : 2; /**< Two UART interrupts 8772 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8773 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */ 8774 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8775 uint64_t workq : 16; /**< 16 work queue interrupts 8776 See POW_WQ_INT[WQ_INT] 8777 1 bit/group. A copy of the R/W1C bit in the POW. */ 8778#else 8779 uint64_t workq : 16; 8780 uint64_t gpio : 16; 8781 uint64_t mbox : 2; 8782 uint64_t uart : 2; 8783 uint64_t pci_int : 4; 8784 uint64_t pci_msi : 4; 8785 uint64_t wdog_sum : 1; 8786 uint64_t twsi : 1; 8787 uint64_t rml : 1; 8788 uint64_t trace : 1; 8789 uint64_t gmx_drp : 1; 8790 uint64_t reserved_49_49 : 1; 8791 uint64_t ipd_drp : 1; 8792 uint64_t reserved_51_51 : 1; 8793 uint64_t timer : 4; 8794 uint64_t usb : 1; 8795 uint64_t reserved_57_58 : 2; 8796 uint64_t twsi2 : 1; 8797 uint64_t powiq : 1; 8798 uint64_t ipdppthr : 1; 8799 uint64_t mii : 1; 8800 uint64_t bootdma : 1; 8801#endif 8802 } cn63xx; 8803 struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1; 8804 struct cvmx_ciu_int33_sum0_cn66xx { 8805#ifdef __BIG_ENDIAN_BITFIELD 8806 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8807 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8808 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 8809 See MIX0_ISR */ 8810 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8811 See IPD_PORT_QOS_INT* */ 8812 uint64_t powiq : 1; /**< POW IQ interrupt 8813 See POW_IQ_INT */ 8814 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8815 See MIO_TWS1_INT */ 8816 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8817 uint64_t reserved_57_57 : 1; 8818 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8819 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8820 uint64_t timer : 4; /**< General timer 0-3 interrupts. 8821 Prior to pass 1.2 or 8822 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is 8823 common for all PP/IRQs, writing '1' to any PP/IRQ 8824 will clear all TIMERx(x=0..9) interrupts. 8825 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8826 are set at the same time, but clearing is per 8827 cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8828 The combination of this field and the 8829 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8830 interrupts. */ 8831 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8832 In pass 1.2 and subsequent passes, 8833 this read-only bit reads as a one whenever any 8834 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8835 and corresponding enable bit in CIU_EN2_PPX_IPx 8836 (CIU_EN2_IOX_INT) is set. 8837 Note that SUM2 only summarizes the SUM2/EN2 8838 result and does not have a corresponding enable 8839 bit, so does not directly contribute to 8840 interrupts. 8841 Prior to pass 1.2, SUM2 did not exist and this 8842 bit reads as zero. */ 8843 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8844 Set any time PIP/IPD drops a packet */ 8845 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 8846 Set any time corresponding GMX drops a packet */ 8847 uint64_t trace : 1; /**< Trace buffer interrupt 8848 See TRA_INT_STATUS */ 8849 uint64_t rml : 1; /**< RML Interrupt 8850 This interrupt will assert if any bit within 8851 CIU_BLOCK_INT is asserted. */ 8852 uint64_t twsi : 1; /**< TWSI Interrupt 8853 See MIO_TWS0_INT */ 8854 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8855 This read-only bit reads as a one whenever any 8856 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set 8857 and corresponding enable bit in CIU_INTx_EN is set 8858 PPs use CIU_INTx_SUM0 where x=0-19 8859 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 8860 Note that WDOG_SUM only summarizes the SUM1/EN1 8861 result and does not have a corresponding enable 8862 bit, so does not directly contribute to 8863 interrupts. */ 8864 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 8865 See SLI_MSI_RCVn for bit <40+n> */ 8866 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8867 Refer to "Receiving Emulated INTA/INTB/ 8868 INTC/INTD" in the SLI chapter of the spec 8869 PCI_INT<3> = INTD 8870 PCI_INT<2> = INTC 8871 PCI_INT<1> = INTB 8872 PCI_INT<0> = INTA */ 8873 uint64_t uart : 2; /**< Two UART interrupts 8874 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8875 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */ 8876 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 8877 uint64_t workq : 16; /**< 16 work queue interrupts 8878 See POW_WQ_INT[WQ_INT] 8879 1 bit/group. A copy of the R/W1C bit in the POW. */ 8880#else 8881 uint64_t workq : 16; 8882 uint64_t gpio : 16; 8883 uint64_t mbox : 2; 8884 uint64_t uart : 2; 8885 uint64_t pci_int : 4; 8886 uint64_t pci_msi : 4; 8887 uint64_t wdog_sum : 1; 8888 uint64_t twsi : 1; 8889 uint64_t rml : 1; 8890 uint64_t trace : 1; 8891 uint64_t gmx_drp : 2; 8892 uint64_t ipd_drp : 1; 8893 uint64_t sum2 : 1; 8894 uint64_t timer : 4; 8895 uint64_t usb : 1; 8896 uint64_t reserved_57_57 : 1; 8897 uint64_t mpi : 1; 8898 uint64_t twsi2 : 1; 8899 uint64_t powiq : 1; 8900 uint64_t ipdppthr : 1; 8901 uint64_t mii : 1; 8902 uint64_t bootdma : 1; 8903#endif 8904 } cn66xx; 8905 struct cvmx_ciu_int33_sum0_cnf71xx { 8906#ifdef __BIG_ENDIAN_BITFIELD 8907 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 8908 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 8909 uint64_t reserved_62_62 : 1; 8910 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 8911 See IPD_PORT_QOS_INT* */ 8912 uint64_t powiq : 1; /**< POW IQ interrupt 8913 See POW_IQ_INT */ 8914 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 8915 See MIO_TWS1_INT */ 8916 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 8917 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 8918 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 8919 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 8920 uint64_t timer : 4; /**< General timer 0-3 interrupts. 8921 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 8922 common for all PP/IRQs, writing '1' to any PP/IRQ 8923 will clear all TIMERx(x=0..9) interrupts. 8924 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 8925 are set at the same time, but clearing are based on 8926 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 8927 The combination of this field and the 8928 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM* 8929 interrupts. */ 8930 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit 8931 This read-only bit reads as a one whenever any 8932 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set 8933 and corresponding enable bit in CIU_EN2_PPX_IPx 8934 (CIU_EN2_IOX_INT) is set. 8935 Note that SUM2 only summarizes the SUM2/EN2 8936 result and does not have a corresponding enable 8937 bit, so does not directly contribute to 8938 interrupts. */ 8939 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 8940 Set any time PIP/IPD drops a packet */ 8941 uint64_t reserved_49_49 : 1; 8942 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt 8943 Set any time corresponding GMX drops a packet */ 8944 uint64_t trace : 1; /**< Trace buffer interrupt 8945 See TRA_INT_STATUS */ 8946 uint64_t rml : 1; /**< RML Interrupt 8947 This interrupt will assert if any bit within 8948 CIU_BLOCK_INT is asserted. */ 8949 uint64_t twsi : 1; /**< TWSI Interrupt 8950 See MIO_TWS0_INT */ 8951 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 8952 This read-only bit reads as a one whenever any 8953 CIU_SUM1_PPX_IPx bit is set and corresponding 8954 enable bit in CIU_INTx_EN is set, where x 8955 is the same as x in this CIU_INTx_SUM0. 8956 PPs use CIU_INTx_SUM0 where x=0-7. 8957 PCIe uses the CIU_INTx_SUM0 where x=32-33. 8958 Note that WDOG_SUM only summarizes the SUM1/EN1 8959 result and does not have a corresponding enable 8960 bit, so does not directly contribute to 8961 interrupts. */ 8962 uint64_t pci_msi : 4; /**< PCIe MSI 8963 See SLI_MSI_RCVn for bit <40+n> */ 8964 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 8965 Refer to "Receiving Emulated INTA/INTB/ 8966 INTC/INTD" in the SLI chapter of the spec 8967 PCI_INT<3> = INTD 8968 PCI_INT<2> = INTC 8969 PCI_INT<1> = INTB 8970 PCI_INT<0> = INTA */ 8971 uint64_t uart : 2; /**< Two UART interrupts 8972 See MIO_UARTn_IIR[IID] for bit <34+n> */ 8973 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */ 8974 uint64_t gpio : 16; /**< 16 GPIO interrupts 8975 When GPIO_MULTI_CAST[EN] == 1 8976 Write 1 to clear either the per PP or common GPIO 8977 edge-triggered interrupts,depending on mode. 8978 See GPIO_MULTI_CAST for all details. 8979 When GPIO_MULTI_CAST[EN] == 0 8980 Read Only, retain the same behavior as o63. */ 8981 uint64_t workq : 16; /**< 16 work queue interrupts 8982 See POW_WQ_INT[WQ_INT] 8983 1 bit/group. A copy of the R/W1C bit in the POW. */ 8984#else 8985 uint64_t workq : 16; 8986 uint64_t gpio : 16; 8987 uint64_t mbox : 2; 8988 uint64_t uart : 2; 8989 uint64_t pci_int : 4; 8990 uint64_t pci_msi : 4; 8991 uint64_t wdog_sum : 1; 8992 uint64_t twsi : 1; 8993 uint64_t rml : 1; 8994 uint64_t trace : 1; 8995 uint64_t gmx_drp : 1; 8996 uint64_t reserved_49_49 : 1; 8997 uint64_t ipd_drp : 1; 8998 uint64_t sum2 : 1; 8999 uint64_t timer : 4; 9000 uint64_t usb : 1; 9001 uint64_t pcm : 1; 9002 uint64_t mpi : 1; 9003 uint64_t twsi2 : 1; 9004 uint64_t powiq : 1; 9005 uint64_t ipdppthr : 1; 9006 uint64_t reserved_62_62 : 1; 9007 uint64_t bootdma : 1; 9008#endif 9009 } cnf71xx; 9010}; 9011typedef union cvmx_ciu_int33_sum0 cvmx_ciu_int33_sum0_t; 9012 9013/** 9014 * cvmx_ciu_int_dbg_sel 9015 */ 9016union cvmx_ciu_int_dbg_sel { 9017 uint64_t u64; 9018 struct cvmx_ciu_int_dbg_sel_s { 9019#ifdef __BIG_ENDIAN_BITFIELD 9020 uint64_t reserved_19_63 : 45; 9021 uint64_t sel : 3; /**< Selects if all or the specific interrupt is 9022 presented on the debug port. 9023 0=erst_n 9024 1=start_bist 9025 2=toggle at sclk/2 freq 9026 3=All PP interrupt bits are ORed together 9027 4=Only the selected virtual PP/IRQ is selected */ 9028 uint64_t reserved_10_15 : 6; 9029 uint64_t irq : 2; /**< Which IRQ to select 9030 0=IRQ2 9031 1=IRQ3 9032 2=IRQ4 */ 9033 uint64_t reserved_5_7 : 3; 9034 uint64_t pp : 5; /**< Which PP to select */ 9035#else 9036 uint64_t pp : 5; 9037 uint64_t reserved_5_7 : 3; 9038 uint64_t irq : 2; 9039 uint64_t reserved_10_15 : 6; 9040 uint64_t sel : 3; 9041 uint64_t reserved_19_63 : 45; 9042#endif 9043 } s; 9044 struct cvmx_ciu_int_dbg_sel_cn61xx { 9045#ifdef __BIG_ENDIAN_BITFIELD 9046 uint64_t reserved_19_63 : 45; 9047 uint64_t sel : 3; /**< Selects if all or the specific interrupt is 9048 presented on the debug port. 9049 0=erst_n 9050 1=start_bist 9051 2=toggle at sclk/2 freq 9052 3=All PP interrupt bits are ORed together 9053 4=Only the selected virtual PP/IRQ is selected */ 9054 uint64_t reserved_10_15 : 6; 9055 uint64_t irq : 2; /**< Which IRQ to select 9056 0=IRQ2 9057 1=IRQ3 9058 2=IRQ4 */ 9059 uint64_t reserved_4_7 : 4; 9060 uint64_t pp : 4; /**< Which PP to select */ 9061#else 9062 uint64_t pp : 4; 9063 uint64_t reserved_4_7 : 4; 9064 uint64_t irq : 2; 9065 uint64_t reserved_10_15 : 6; 9066 uint64_t sel : 3; 9067 uint64_t reserved_19_63 : 45; 9068#endif 9069 } cn61xx; 9070 struct cvmx_ciu_int_dbg_sel_cn63xx { 9071#ifdef __BIG_ENDIAN_BITFIELD 9072 uint64_t reserved_19_63 : 45; 9073 uint64_t sel : 3; /**< Selects if all or the specific interrupt is 9074 presented on the debug port. 9075 0=erst_n 9076 1=start_bist 9077 2=toggle at sclk/2 freq 9078 3=All PP interrupt bits are ORed together 9079 4=Only the selected physical PP/IRQ is selected */ 9080 uint64_t reserved_10_15 : 6; 9081 uint64_t irq : 2; /**< Which IRQ to select 9082 0=IRQ2 9083 1=IRQ3 9084 2=IRQ4 */ 9085 uint64_t reserved_3_7 : 5; 9086 uint64_t pp : 3; /**< Which PP to select */ 9087#else 9088 uint64_t pp : 3; 9089 uint64_t reserved_3_7 : 5; 9090 uint64_t irq : 2; 9091 uint64_t reserved_10_15 : 6; 9092 uint64_t sel : 3; 9093 uint64_t reserved_19_63 : 45; 9094#endif 9095 } cn63xx; 9096 struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx; 9097 struct cvmx_ciu_int_dbg_sel_s cn68xx; 9098 struct cvmx_ciu_int_dbg_sel_s cn68xxp1; 9099 struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx; 9100}; 9101typedef union cvmx_ciu_int_dbg_sel cvmx_ciu_int_dbg_sel_t; 9102 9103/** 9104 * cvmx_ciu_int_sum1 9105 */ 9106union cvmx_ciu_int_sum1 { 9107 uint64_t u64; 9108 struct cvmx_ciu_int_sum1_s { 9109#ifdef __BIG_ENDIAN_BITFIELD 9110 uint64_t rst : 1; /**< MIO RST interrupt 9111 See MIO_RST_INT */ 9112 uint64_t reserved_62_62 : 1; 9113 uint64_t srio3 : 1; /**< SRIO3 interrupt 9114 See SRIO3_INT_REG, SRIO3_INT2_REG */ 9115 uint64_t srio2 : 1; /**< SRIO2 interrupt 9116 See SRIO2_INT_REG, SRIO2_INT2_REG */ 9117 uint64_t reserved_57_59 : 3; 9118 uint64_t dfm : 1; /**< DFM Interrupt 9119 See DFM_FNT_STAT */ 9120 uint64_t reserved_53_55 : 3; 9121 uint64_t lmc0 : 1; /**< LMC0 interrupt 9122 See LMC0_INT */ 9123 uint64_t srio1 : 1; /**< SRIO1 interrupt 9124 See SRIO1_INT_REG */ 9125 uint64_t srio0 : 1; /**< SRIO0 interrupt 9126 See SRIO0_INT_REG, SRIO0_INT2_REG */ 9127 uint64_t pem1 : 1; /**< PEM1 interrupt 9128 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 9129 uint64_t pem0 : 1; /**< PEM0 interrupt 9130 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 9131 uint64_t ptp : 1; /**< PTP interrupt 9132 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 9133 uint64_t agl : 1; /**< AGL interrupt 9134 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 9135 uint64_t reserved_38_45 : 8; 9136 uint64_t agx1 : 1; /**< GMX1 interrupt 9137 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 9138 PCS1_INT*_REG, PCSX1_INT_REG */ 9139 uint64_t agx0 : 1; /**< GMX0 interrupt 9140 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 9141 PCS0_INT*_REG, PCSX0_INT_REG */ 9142 uint64_t dpi : 1; /**< DPI interrupt 9143 See DPI_INT_REG */ 9144 uint64_t sli : 1; /**< SLI interrupt 9145 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 9146 uint64_t usb : 1; /**< USB UCTL0 interrupt 9147 See UCTL0_INT_REG */ 9148 uint64_t dfa : 1; /**< DFA interrupt 9149 See DFA_ERROR */ 9150 uint64_t key : 1; /**< KEY interrupt 9151 See KEY_INT_SUM */ 9152 uint64_t rad : 1; /**< RAD interrupt 9153 See RAD_REG_ERROR */ 9154 uint64_t tim : 1; /**< TIM interrupt 9155 See TIM_REG_ERROR */ 9156 uint64_t zip : 1; /**< ZIP interrupt 9157 See ZIP_ERROR */ 9158 uint64_t pko : 1; /**< PKO interrupt 9159 See PKO_REG_ERROR */ 9160 uint64_t pip : 1; /**< PIP interrupt 9161 See PIP_INT_REG */ 9162 uint64_t ipd : 1; /**< IPD interrupt 9163 See IPD_INT_SUM */ 9164 uint64_t l2c : 1; /**< L2C interrupt 9165 See L2C_INT_REG */ 9166 uint64_t pow : 1; /**< POW err interrupt 9167 See POW_ECC_ERR */ 9168 uint64_t fpa : 1; /**< FPA interrupt 9169 See FPA_INT_SUM */ 9170 uint64_t iob : 1; /**< IOB interrupt 9171 See IOB_INT_SUM */ 9172 uint64_t mio : 1; /**< MIO boot interrupt 9173 See MIO_BOOT_ERR */ 9174 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 9175 See EMMC interrupt */ 9176 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 9177 See MIX1_ISR */ 9178 uint64_t usb1 : 1; /**< Second USB Interrupt */ 9179 uint64_t uart2 : 1; /**< Third UART interrupt */ 9180 uint64_t wdog : 16; /**< Per PP watchdog interrupts */ 9181#else 9182 uint64_t wdog : 16; 9183 uint64_t uart2 : 1; 9184 uint64_t usb1 : 1; 9185 uint64_t mii1 : 1; 9186 uint64_t nand : 1; 9187 uint64_t mio : 1; 9188 uint64_t iob : 1; 9189 uint64_t fpa : 1; 9190 uint64_t pow : 1; 9191 uint64_t l2c : 1; 9192 uint64_t ipd : 1; 9193 uint64_t pip : 1; 9194 uint64_t pko : 1; 9195 uint64_t zip : 1; 9196 uint64_t tim : 1; 9197 uint64_t rad : 1; 9198 uint64_t key : 1; 9199 uint64_t dfa : 1; 9200 uint64_t usb : 1; 9201 uint64_t sli : 1; 9202 uint64_t dpi : 1; 9203 uint64_t agx0 : 1; 9204 uint64_t agx1 : 1; 9205 uint64_t reserved_38_45 : 8; 9206 uint64_t agl : 1; 9207 uint64_t ptp : 1; 9208 uint64_t pem0 : 1; 9209 uint64_t pem1 : 1; 9210 uint64_t srio0 : 1; 9211 uint64_t srio1 : 1; 9212 uint64_t lmc0 : 1; 9213 uint64_t reserved_53_55 : 3; 9214 uint64_t dfm : 1; 9215 uint64_t reserved_57_59 : 3; 9216 uint64_t srio2 : 1; 9217 uint64_t srio3 : 1; 9218 uint64_t reserved_62_62 : 1; 9219 uint64_t rst : 1; 9220#endif 9221 } s; 9222 struct cvmx_ciu_int_sum1_cn30xx { 9223#ifdef __BIG_ENDIAN_BITFIELD 9224 uint64_t reserved_1_63 : 63; 9225 uint64_t wdog : 1; /**< 1 watchdog interrupt */ 9226#else 9227 uint64_t wdog : 1; 9228 uint64_t reserved_1_63 : 63; 9229#endif 9230 } cn30xx; 9231 struct cvmx_ciu_int_sum1_cn31xx { 9232#ifdef __BIG_ENDIAN_BITFIELD 9233 uint64_t reserved_2_63 : 62; 9234 uint64_t wdog : 2; /**< 2 watchdog interrupts */ 9235#else 9236 uint64_t wdog : 2; 9237 uint64_t reserved_2_63 : 62; 9238#endif 9239 } cn31xx; 9240 struct cvmx_ciu_int_sum1_cn38xx { 9241#ifdef __BIG_ENDIAN_BITFIELD 9242 uint64_t reserved_16_63 : 48; 9243 uint64_t wdog : 16; /**< 16 watchdog interrupts */ 9244#else 9245 uint64_t wdog : 16; 9246 uint64_t reserved_16_63 : 48; 9247#endif 9248 } cn38xx; 9249 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; 9250 struct cvmx_ciu_int_sum1_cn31xx cn50xx; 9251 struct cvmx_ciu_int_sum1_cn52xx { 9252#ifdef __BIG_ENDIAN_BITFIELD 9253 uint64_t reserved_20_63 : 44; 9254 uint64_t nand : 1; /**< NAND Flash Controller */ 9255 uint64_t mii1 : 1; /**< Second MII Interrupt */ 9256 uint64_t usb1 : 1; /**< Second USB Interrupt */ 9257 uint64_t uart2 : 1; /**< Third UART interrupt */ 9258 uint64_t reserved_4_15 : 12; 9259 uint64_t wdog : 4; /**< 4 watchdog interrupts */ 9260#else 9261 uint64_t wdog : 4; 9262 uint64_t reserved_4_15 : 12; 9263 uint64_t uart2 : 1; 9264 uint64_t usb1 : 1; 9265 uint64_t mii1 : 1; 9266 uint64_t nand : 1; 9267 uint64_t reserved_20_63 : 44; 9268#endif 9269 } cn52xx; 9270 struct cvmx_ciu_int_sum1_cn52xxp1 { 9271#ifdef __BIG_ENDIAN_BITFIELD 9272 uint64_t reserved_19_63 : 45; 9273 uint64_t mii1 : 1; /**< Second MII Interrupt */ 9274 uint64_t usb1 : 1; /**< Second USB Interrupt */ 9275 uint64_t uart2 : 1; /**< Third UART interrupt */ 9276 uint64_t reserved_4_15 : 12; 9277 uint64_t wdog : 4; /**< 4 watchdog interrupts */ 9278#else 9279 uint64_t wdog : 4; 9280 uint64_t reserved_4_15 : 12; 9281 uint64_t uart2 : 1; 9282 uint64_t usb1 : 1; 9283 uint64_t mii1 : 1; 9284 uint64_t reserved_19_63 : 45; 9285#endif 9286 } cn52xxp1; 9287 struct cvmx_ciu_int_sum1_cn56xx { 9288#ifdef __BIG_ENDIAN_BITFIELD 9289 uint64_t reserved_12_63 : 52; 9290 uint64_t wdog : 12; /**< 12 watchdog interrupts */ 9291#else 9292 uint64_t wdog : 12; 9293 uint64_t reserved_12_63 : 52; 9294#endif 9295 } cn56xx; 9296 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; 9297 struct cvmx_ciu_int_sum1_cn38xx cn58xx; 9298 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; 9299 struct cvmx_ciu_int_sum1_cn61xx { 9300#ifdef __BIG_ENDIAN_BITFIELD 9301 uint64_t rst : 1; /**< MIO RST interrupt 9302 See MIO_RST_INT */ 9303 uint64_t reserved_53_62 : 10; 9304 uint64_t lmc0 : 1; /**< LMC0 interrupt 9305 See LMC0_INT */ 9306 uint64_t reserved_50_51 : 2; 9307 uint64_t pem1 : 1; /**< PEM1 interrupt 9308 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 9309 uint64_t pem0 : 1; /**< PEM0 interrupt 9310 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 9311 uint64_t ptp : 1; /**< PTP interrupt 9312 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 9313 uint64_t agl : 1; /**< AGL interrupt 9314 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 9315 uint64_t reserved_38_45 : 8; 9316 uint64_t agx1 : 1; /**< GMX1 interrupt 9317 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 9318 PCS1_INT*_REG, PCSX1_INT_REG */ 9319 uint64_t agx0 : 1; /**< GMX0 interrupt 9320 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 9321 PCS0_INT*_REG, PCSX0_INT_REG */ 9322 uint64_t dpi : 1; /**< DPI interrupt 9323 See DPI_INT_REG */ 9324 uint64_t sli : 1; /**< SLI interrupt 9325 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 9326 uint64_t usb : 1; /**< USB UCTL0 interrupt 9327 See UCTL0_INT_REG */ 9328 uint64_t dfa : 1; /**< DFA interrupt 9329 See DFA_ERROR */ 9330 uint64_t key : 1; /**< KEY interrupt 9331 See KEY_INT_SUM */ 9332 uint64_t rad : 1; /**< RAD interrupt 9333 See RAD_REG_ERROR */ 9334 uint64_t tim : 1; /**< TIM interrupt 9335 See TIM_REG_ERROR */ 9336 uint64_t zip : 1; /**< ZIP interrupt 9337 See ZIP_ERROR */ 9338 uint64_t pko : 1; /**< PKO interrupt 9339 See PKO_REG_ERROR */ 9340 uint64_t pip : 1; /**< PIP interrupt 9341 See PIP_INT_REG */ 9342 uint64_t ipd : 1; /**< IPD interrupt 9343 See IPD_INT_SUM */ 9344 uint64_t l2c : 1; /**< L2C interrupt 9345 See L2C_INT_REG */ 9346 uint64_t pow : 1; /**< POW err interrupt 9347 See POW_ECC_ERR */ 9348 uint64_t fpa : 1; /**< FPA interrupt 9349 See FPA_INT_SUM */ 9350 uint64_t iob : 1; /**< IOB interrupt 9351 See IOB_INT_SUM */ 9352 uint64_t mio : 1; /**< MIO boot interrupt 9353 See MIO_BOOT_ERR */ 9354 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 9355 See EMMC interrupt */ 9356 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt 9357 See MIX1_ISR */ 9358 uint64_t reserved_4_17 : 14; 9359 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 9360#else 9361 uint64_t wdog : 4; 9362 uint64_t reserved_4_17 : 14; 9363 uint64_t mii1 : 1; 9364 uint64_t nand : 1; 9365 uint64_t mio : 1; 9366 uint64_t iob : 1; 9367 uint64_t fpa : 1; 9368 uint64_t pow : 1; 9369 uint64_t l2c : 1; 9370 uint64_t ipd : 1; 9371 uint64_t pip : 1; 9372 uint64_t pko : 1; 9373 uint64_t zip : 1; 9374 uint64_t tim : 1; 9375 uint64_t rad : 1; 9376 uint64_t key : 1; 9377 uint64_t dfa : 1; 9378 uint64_t usb : 1; 9379 uint64_t sli : 1; 9380 uint64_t dpi : 1; 9381 uint64_t agx0 : 1; 9382 uint64_t agx1 : 1; 9383 uint64_t reserved_38_45 : 8; 9384 uint64_t agl : 1; 9385 uint64_t ptp : 1; 9386 uint64_t pem0 : 1; 9387 uint64_t pem1 : 1; 9388 uint64_t reserved_50_51 : 2; 9389 uint64_t lmc0 : 1; 9390 uint64_t reserved_53_62 : 10; 9391 uint64_t rst : 1; 9392#endif 9393 } cn61xx; 9394 struct cvmx_ciu_int_sum1_cn63xx { 9395#ifdef __BIG_ENDIAN_BITFIELD 9396 uint64_t rst : 1; /**< MIO RST interrupt 9397 See MIO_RST_INT */ 9398 uint64_t reserved_57_62 : 6; 9399 uint64_t dfm : 1; /**< DFM Interrupt 9400 See DFM_FNT_STAT */ 9401 uint64_t reserved_53_55 : 3; 9402 uint64_t lmc0 : 1; /**< LMC0 interrupt 9403 See LMC0_INT */ 9404 uint64_t srio1 : 1; /**< SRIO1 interrupt 9405 See SRIO1_INT_REG, SRIO1_INT2_REG */ 9406 uint64_t srio0 : 1; /**< SRIO0 interrupt 9407 See SRIO0_INT_REG, SRIO0_INT2_REG */ 9408 uint64_t pem1 : 1; /**< PEM1 interrupt 9409 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 9410 uint64_t pem0 : 1; /**< PEM0 interrupt 9411 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 9412 uint64_t ptp : 1; /**< PTP interrupt 9413 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 9414 uint64_t agl : 1; /**< AGL interrupt 9415 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 9416 uint64_t reserved_37_45 : 9; 9417 uint64_t agx0 : 1; /**< GMX0 interrupt 9418 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 9419 PCS0_INT*_REG, PCSX0_INT_REG */ 9420 uint64_t dpi : 1; /**< DPI interrupt 9421 See DPI_INT_REG */ 9422 uint64_t sli : 1; /**< SLI interrupt 9423 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 9424 uint64_t usb : 1; /**< USB UCTL0 interrupt 9425 See UCTL0_INT_REG */ 9426 uint64_t dfa : 1; /**< DFA interrupt 9427 See DFA_ERROR */ 9428 uint64_t key : 1; /**< KEY interrupt 9429 See KEY_INT_SUM */ 9430 uint64_t rad : 1; /**< RAD interrupt 9431 See RAD_REG_ERROR */ 9432 uint64_t tim : 1; /**< TIM interrupt 9433 See TIM_REG_ERROR */ 9434 uint64_t zip : 1; /**< ZIP interrupt 9435 See ZIP_ERROR */ 9436 uint64_t pko : 1; /**< PKO interrupt 9437 See PKO_REG_ERROR */ 9438 uint64_t pip : 1; /**< PIP interrupt 9439 See PIP_INT_REG */ 9440 uint64_t ipd : 1; /**< IPD interrupt 9441 See IPD_INT_SUM */ 9442 uint64_t l2c : 1; /**< L2C interrupt 9443 See L2C_INT_REG */ 9444 uint64_t pow : 1; /**< POW err interrupt 9445 See POW_ECC_ERR */ 9446 uint64_t fpa : 1; /**< FPA interrupt 9447 See FPA_INT_SUM */ 9448 uint64_t iob : 1; /**< IOB interrupt 9449 See IOB_INT_SUM */ 9450 uint64_t mio : 1; /**< MIO boot interrupt 9451 See MIO_BOOT_ERR */ 9452 uint64_t nand : 1; /**< NAND Flash Controller interrupt 9453 See NDF_INT */ 9454 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 9455 See MIX1_ISR */ 9456 uint64_t reserved_6_17 : 12; 9457 uint64_t wdog : 6; /**< 6 watchdog interrupts */ 9458#else 9459 uint64_t wdog : 6; 9460 uint64_t reserved_6_17 : 12; 9461 uint64_t mii1 : 1; 9462 uint64_t nand : 1; 9463 uint64_t mio : 1; 9464 uint64_t iob : 1; 9465 uint64_t fpa : 1; 9466 uint64_t pow : 1; 9467 uint64_t l2c : 1; 9468 uint64_t ipd : 1; 9469 uint64_t pip : 1; 9470 uint64_t pko : 1; 9471 uint64_t zip : 1; 9472 uint64_t tim : 1; 9473 uint64_t rad : 1; 9474 uint64_t key : 1; 9475 uint64_t dfa : 1; 9476 uint64_t usb : 1; 9477 uint64_t sli : 1; 9478 uint64_t dpi : 1; 9479 uint64_t agx0 : 1; 9480 uint64_t reserved_37_45 : 9; 9481 uint64_t agl : 1; 9482 uint64_t ptp : 1; 9483 uint64_t pem0 : 1; 9484 uint64_t pem1 : 1; 9485 uint64_t srio0 : 1; 9486 uint64_t srio1 : 1; 9487 uint64_t lmc0 : 1; 9488 uint64_t reserved_53_55 : 3; 9489 uint64_t dfm : 1; 9490 uint64_t reserved_57_62 : 6; 9491 uint64_t rst : 1; 9492#endif 9493 } cn63xx; 9494 struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; 9495 struct cvmx_ciu_int_sum1_cn66xx { 9496#ifdef __BIG_ENDIAN_BITFIELD 9497 uint64_t rst : 1; /**< MIO RST interrupt 9498 See MIO_RST_INT */ 9499 uint64_t reserved_62_62 : 1; 9500 uint64_t srio3 : 1; /**< SRIO3 interrupt 9501 See SRIO3_INT_REG, SRIO3_INT2_REG */ 9502 uint64_t srio2 : 1; /**< SRIO2 interrupt 9503 See SRIO2_INT_REG, SRIO2_INT2_REG */ 9504 uint64_t reserved_57_59 : 3; 9505 uint64_t dfm : 1; /**< DFM Interrupt 9506 See DFM_FNT_STAT */ 9507 uint64_t reserved_53_55 : 3; 9508 uint64_t lmc0 : 1; /**< LMC0 interrupt 9509 See LMC0_INT */ 9510 uint64_t reserved_51_51 : 1; 9511 uint64_t srio0 : 1; /**< SRIO0 interrupt 9512 See SRIO0_INT_REG, SRIO0_INT2_REG */ 9513 uint64_t pem1 : 1; /**< PEM1 interrupt 9514 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 9515 uint64_t pem0 : 1; /**< PEM0 interrupt 9516 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 9517 uint64_t ptp : 1; /**< PTP interrupt 9518 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 9519 uint64_t agl : 1; /**< AGL interrupt 9520 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 9521 uint64_t reserved_38_45 : 8; 9522 uint64_t agx1 : 1; /**< GMX1 interrupt 9523 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 9524 PCS1_INT*_REG, PCSX1_INT_REG */ 9525 uint64_t agx0 : 1; /**< GMX0 interrupt 9526 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 9527 PCS0_INT*_REG, PCSX0_INT_REG */ 9528 uint64_t dpi : 1; /**< DPI interrupt 9529 See DPI_INT_REG */ 9530 uint64_t sli : 1; /**< SLI interrupt 9531 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 9532 uint64_t usb : 1; /**< USB UCTL0 interrupt 9533 See UCTL0_INT_REG */ 9534 uint64_t dfa : 1; /**< DFA interrupt 9535 See DFA_ERROR */ 9536 uint64_t key : 1; /**< KEY interrupt 9537 See KEY_INT_SUM */ 9538 uint64_t rad : 1; /**< RAD interrupt 9539 See RAD_REG_ERROR */ 9540 uint64_t tim : 1; /**< TIM interrupt 9541 See TIM_REG_ERROR */ 9542 uint64_t zip : 1; /**< ZIP interrupt 9543 See ZIP_ERROR */ 9544 uint64_t pko : 1; /**< PKO interrupt 9545 See PKO_REG_ERROR */ 9546 uint64_t pip : 1; /**< PIP interrupt 9547 See PIP_INT_REG */ 9548 uint64_t ipd : 1; /**< IPD interrupt 9549 See IPD_INT_SUM */ 9550 uint64_t l2c : 1; /**< L2C interrupt 9551 See L2C_INT_REG */ 9552 uint64_t pow : 1; /**< POW err interrupt 9553 See POW_ECC_ERR */ 9554 uint64_t fpa : 1; /**< FPA interrupt 9555 See FPA_INT_SUM */ 9556 uint64_t iob : 1; /**< IOB interrupt 9557 See IOB_INT_SUM */ 9558 uint64_t mio : 1; /**< MIO boot interrupt 9559 See MIO_BOOT_ERR */ 9560 uint64_t nand : 1; /**< NAND Flash Controller interrupt 9561 See NDF_INT */ 9562 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 9563 See MIX1_ISR */ 9564 uint64_t reserved_10_17 : 8; 9565 uint64_t wdog : 10; /**< 10 watchdog interrupts */ 9566#else 9567 uint64_t wdog : 10; 9568 uint64_t reserved_10_17 : 8; 9569 uint64_t mii1 : 1; 9570 uint64_t nand : 1; 9571 uint64_t mio : 1; 9572 uint64_t iob : 1; 9573 uint64_t fpa : 1; 9574 uint64_t pow : 1; 9575 uint64_t l2c : 1; 9576 uint64_t ipd : 1; 9577 uint64_t pip : 1; 9578 uint64_t pko : 1; 9579 uint64_t zip : 1; 9580 uint64_t tim : 1; 9581 uint64_t rad : 1; 9582 uint64_t key : 1; 9583 uint64_t dfa : 1; 9584 uint64_t usb : 1; 9585 uint64_t sli : 1; 9586 uint64_t dpi : 1; 9587 uint64_t agx0 : 1; 9588 uint64_t agx1 : 1; 9589 uint64_t reserved_38_45 : 8; 9590 uint64_t agl : 1; 9591 uint64_t ptp : 1; 9592 uint64_t pem0 : 1; 9593 uint64_t pem1 : 1; 9594 uint64_t srio0 : 1; 9595 uint64_t reserved_51_51 : 1; 9596 uint64_t lmc0 : 1; 9597 uint64_t reserved_53_55 : 3; 9598 uint64_t dfm : 1; 9599 uint64_t reserved_57_59 : 3; 9600 uint64_t srio2 : 1; 9601 uint64_t srio3 : 1; 9602 uint64_t reserved_62_62 : 1; 9603 uint64_t rst : 1; 9604#endif 9605 } cn66xx; 9606 struct cvmx_ciu_int_sum1_cnf71xx { 9607#ifdef __BIG_ENDIAN_BITFIELD 9608 uint64_t rst : 1; /**< MIO RST interrupt 9609 See MIO_RST_INT */ 9610 uint64_t reserved_53_62 : 10; 9611 uint64_t lmc0 : 1; /**< LMC0 interrupt 9612 See LMC0_INT */ 9613 uint64_t reserved_50_51 : 2; 9614 uint64_t pem1 : 1; /**< PEM1 interrupt 9615 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 9616 uint64_t pem0 : 1; /**< PEM0 interrupt 9617 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 9618 uint64_t ptp : 1; /**< PTP interrupt 9619 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 9620 uint64_t reserved_37_46 : 10; 9621 uint64_t agx0 : 1; /**< GMX0 interrupt 9622 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 9623 PCS0_INT*_REG, PCSX0_INT_REG */ 9624 uint64_t dpi : 1; /**< DPI interrupt 9625 See DPI_INT_REG */ 9626 uint64_t sli : 1; /**< SLI interrupt 9627 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 9628 uint64_t usb : 1; /**< USB UCTL0 interrupt 9629 See UCTL0_INT_REG */ 9630 uint64_t reserved_32_32 : 1; 9631 uint64_t key : 1; /**< KEY interrupt 9632 See KEY_INT_SUM */ 9633 uint64_t rad : 1; /**< RAD interrupt 9634 See RAD_REG_ERROR */ 9635 uint64_t tim : 1; /**< TIM interrupt 9636 See TIM_REG_ERROR */ 9637 uint64_t reserved_28_28 : 1; 9638 uint64_t pko : 1; /**< PKO interrupt 9639 See PKO_REG_ERROR */ 9640 uint64_t pip : 1; /**< PIP interrupt 9641 See PIP_INT_REG */ 9642 uint64_t ipd : 1; /**< IPD interrupt 9643 See IPD_INT_SUM */ 9644 uint64_t l2c : 1; /**< L2C interrupt 9645 See L2C_INT_REG */ 9646 uint64_t pow : 1; /**< POW err interrupt 9647 See POW_ECC_ERR */ 9648 uint64_t fpa : 1; /**< FPA interrupt 9649 See FPA_INT_SUM */ 9650 uint64_t iob : 1; /**< IOB interrupt 9651 See IOB_INT_SUM */ 9652 uint64_t mio : 1; /**< MIO boot interrupt 9653 See MIO_BOOT_ERR */ 9654 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 9655 See EMMC interrupt */ 9656 uint64_t reserved_4_18 : 15; 9657 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 9658#else 9659 uint64_t wdog : 4; 9660 uint64_t reserved_4_18 : 15; 9661 uint64_t nand : 1; 9662 uint64_t mio : 1; 9663 uint64_t iob : 1; 9664 uint64_t fpa : 1; 9665 uint64_t pow : 1; 9666 uint64_t l2c : 1; 9667 uint64_t ipd : 1; 9668 uint64_t pip : 1; 9669 uint64_t pko : 1; 9670 uint64_t reserved_28_28 : 1; 9671 uint64_t tim : 1; 9672 uint64_t rad : 1; 9673 uint64_t key : 1; 9674 uint64_t reserved_32_32 : 1; 9675 uint64_t usb : 1; 9676 uint64_t sli : 1; 9677 uint64_t dpi : 1; 9678 uint64_t agx0 : 1; 9679 uint64_t reserved_37_46 : 10; 9680 uint64_t ptp : 1; 9681 uint64_t pem0 : 1; 9682 uint64_t pem1 : 1; 9683 uint64_t reserved_50_51 : 2; 9684 uint64_t lmc0 : 1; 9685 uint64_t reserved_53_62 : 10; 9686 uint64_t rst : 1; 9687#endif 9688 } cnf71xx; 9689}; 9690typedef union cvmx_ciu_int_sum1 cvmx_ciu_int_sum1_t; 9691 9692/** 9693 * cvmx_ciu_mbox_clr# 9694 */ 9695union cvmx_ciu_mbox_clrx { 9696 uint64_t u64; 9697 struct cvmx_ciu_mbox_clrx_s { 9698#ifdef __BIG_ENDIAN_BITFIELD 9699 uint64_t reserved_32_63 : 32; 9700 uint64_t bits : 32; /**< On writes, clr corresponding bit in MBOX register 9701 on reads, return the MBOX register */ 9702#else 9703 uint64_t bits : 32; 9704 uint64_t reserved_32_63 : 32; 9705#endif 9706 } s; 9707 struct cvmx_ciu_mbox_clrx_s cn30xx; 9708 struct cvmx_ciu_mbox_clrx_s cn31xx; 9709 struct cvmx_ciu_mbox_clrx_s cn38xx; 9710 struct cvmx_ciu_mbox_clrx_s cn38xxp2; 9711 struct cvmx_ciu_mbox_clrx_s cn50xx; 9712 struct cvmx_ciu_mbox_clrx_s cn52xx; 9713 struct cvmx_ciu_mbox_clrx_s cn52xxp1; 9714 struct cvmx_ciu_mbox_clrx_s cn56xx; 9715 struct cvmx_ciu_mbox_clrx_s cn56xxp1; 9716 struct cvmx_ciu_mbox_clrx_s cn58xx; 9717 struct cvmx_ciu_mbox_clrx_s cn58xxp1; 9718 struct cvmx_ciu_mbox_clrx_s cn61xx; 9719 struct cvmx_ciu_mbox_clrx_s cn63xx; 9720 struct cvmx_ciu_mbox_clrx_s cn63xxp1; 9721 struct cvmx_ciu_mbox_clrx_s cn66xx; 9722 struct cvmx_ciu_mbox_clrx_s cn68xx; 9723 struct cvmx_ciu_mbox_clrx_s cn68xxp1; 9724 struct cvmx_ciu_mbox_clrx_s cnf71xx; 9725}; 9726typedef union cvmx_ciu_mbox_clrx cvmx_ciu_mbox_clrx_t; 9727 9728/** 9729 * cvmx_ciu_mbox_set# 9730 */ 9731union cvmx_ciu_mbox_setx { 9732 uint64_t u64; 9733 struct cvmx_ciu_mbox_setx_s { 9734#ifdef __BIG_ENDIAN_BITFIELD 9735 uint64_t reserved_32_63 : 32; 9736 uint64_t bits : 32; /**< On writes, set corresponding bit in MBOX register 9737 on reads, return the MBOX register */ 9738#else 9739 uint64_t bits : 32; 9740 uint64_t reserved_32_63 : 32; 9741#endif 9742 } s; 9743 struct cvmx_ciu_mbox_setx_s cn30xx; 9744 struct cvmx_ciu_mbox_setx_s cn31xx; 9745 struct cvmx_ciu_mbox_setx_s cn38xx; 9746 struct cvmx_ciu_mbox_setx_s cn38xxp2; 9747 struct cvmx_ciu_mbox_setx_s cn50xx; 9748 struct cvmx_ciu_mbox_setx_s cn52xx; 9749 struct cvmx_ciu_mbox_setx_s cn52xxp1; 9750 struct cvmx_ciu_mbox_setx_s cn56xx; 9751 struct cvmx_ciu_mbox_setx_s cn56xxp1; 9752 struct cvmx_ciu_mbox_setx_s cn58xx; 9753 struct cvmx_ciu_mbox_setx_s cn58xxp1; 9754 struct cvmx_ciu_mbox_setx_s cn61xx; 9755 struct cvmx_ciu_mbox_setx_s cn63xx; 9756 struct cvmx_ciu_mbox_setx_s cn63xxp1; 9757 struct cvmx_ciu_mbox_setx_s cn66xx; 9758 struct cvmx_ciu_mbox_setx_s cn68xx; 9759 struct cvmx_ciu_mbox_setx_s cn68xxp1; 9760 struct cvmx_ciu_mbox_setx_s cnf71xx; 9761}; 9762typedef union cvmx_ciu_mbox_setx cvmx_ciu_mbox_setx_t; 9763 9764/** 9765 * cvmx_ciu_nmi 9766 */ 9767union cvmx_ciu_nmi { 9768 uint64_t u64; 9769 struct cvmx_ciu_nmi_s { 9770#ifdef __BIG_ENDIAN_BITFIELD 9771 uint64_t reserved_32_63 : 32; 9772 uint64_t nmi : 32; /**< Send NMI pulse to PP vector */ 9773#else 9774 uint64_t nmi : 32; 9775 uint64_t reserved_32_63 : 32; 9776#endif 9777 } s; 9778 struct cvmx_ciu_nmi_cn30xx { 9779#ifdef __BIG_ENDIAN_BITFIELD 9780 uint64_t reserved_1_63 : 63; 9781 uint64_t nmi : 1; /**< Send NMI pulse to PP vector */ 9782#else 9783 uint64_t nmi : 1; 9784 uint64_t reserved_1_63 : 63; 9785#endif 9786 } cn30xx; 9787 struct cvmx_ciu_nmi_cn31xx { 9788#ifdef __BIG_ENDIAN_BITFIELD 9789 uint64_t reserved_2_63 : 62; 9790 uint64_t nmi : 2; /**< Send NMI pulse to PP vector */ 9791#else 9792 uint64_t nmi : 2; 9793 uint64_t reserved_2_63 : 62; 9794#endif 9795 } cn31xx; 9796 struct cvmx_ciu_nmi_cn38xx { 9797#ifdef __BIG_ENDIAN_BITFIELD 9798 uint64_t reserved_16_63 : 48; 9799 uint64_t nmi : 16; /**< Send NMI pulse to PP vector */ 9800#else 9801 uint64_t nmi : 16; 9802 uint64_t reserved_16_63 : 48; 9803#endif 9804 } cn38xx; 9805 struct cvmx_ciu_nmi_cn38xx cn38xxp2; 9806 struct cvmx_ciu_nmi_cn31xx cn50xx; 9807 struct cvmx_ciu_nmi_cn52xx { 9808#ifdef __BIG_ENDIAN_BITFIELD 9809 uint64_t reserved_4_63 : 60; 9810 uint64_t nmi : 4; /**< Send NMI pulse to PP vector */ 9811#else 9812 uint64_t nmi : 4; 9813 uint64_t reserved_4_63 : 60; 9814#endif 9815 } cn52xx; 9816 struct cvmx_ciu_nmi_cn52xx cn52xxp1; 9817 struct cvmx_ciu_nmi_cn56xx { 9818#ifdef __BIG_ENDIAN_BITFIELD 9819 uint64_t reserved_12_63 : 52; 9820 uint64_t nmi : 12; /**< Send NMI pulse to PP vector */ 9821#else 9822 uint64_t nmi : 12; 9823 uint64_t reserved_12_63 : 52; 9824#endif 9825 } cn56xx; 9826 struct cvmx_ciu_nmi_cn56xx cn56xxp1; 9827 struct cvmx_ciu_nmi_cn38xx cn58xx; 9828 struct cvmx_ciu_nmi_cn38xx cn58xxp1; 9829 struct cvmx_ciu_nmi_cn52xx cn61xx; 9830 struct cvmx_ciu_nmi_cn63xx { 9831#ifdef __BIG_ENDIAN_BITFIELD 9832 uint64_t reserved_6_63 : 58; 9833 uint64_t nmi : 6; /**< Send NMI pulse to PP vector */ 9834#else 9835 uint64_t nmi : 6; 9836 uint64_t reserved_6_63 : 58; 9837#endif 9838 } cn63xx; 9839 struct cvmx_ciu_nmi_cn63xx cn63xxp1; 9840 struct cvmx_ciu_nmi_cn66xx { 9841#ifdef __BIG_ENDIAN_BITFIELD 9842 uint64_t reserved_10_63 : 54; 9843 uint64_t nmi : 10; /**< Send NMI pulse to PP vector */ 9844#else 9845 uint64_t nmi : 10; 9846 uint64_t reserved_10_63 : 54; 9847#endif 9848 } cn66xx; 9849 struct cvmx_ciu_nmi_s cn68xx; 9850 struct cvmx_ciu_nmi_s cn68xxp1; 9851 struct cvmx_ciu_nmi_cn52xx cnf71xx; 9852}; 9853typedef union cvmx_ciu_nmi cvmx_ciu_nmi_t; 9854 9855/** 9856 * cvmx_ciu_pci_inta 9857 */ 9858union cvmx_ciu_pci_inta { 9859 uint64_t u64; 9860 struct cvmx_ciu_pci_inta_s { 9861#ifdef __BIG_ENDIAN_BITFIELD 9862 uint64_t reserved_2_63 : 62; 9863 uint64_t intr : 2; /**< PCIe interrupt 9864 These bits are observed in CIU_INTX_SUM0<33:32> 9865 where X=32-33 */ 9866#else 9867 uint64_t intr : 2; 9868 uint64_t reserved_2_63 : 62; 9869#endif 9870 } s; 9871 struct cvmx_ciu_pci_inta_s cn30xx; 9872 struct cvmx_ciu_pci_inta_s cn31xx; 9873 struct cvmx_ciu_pci_inta_s cn38xx; 9874 struct cvmx_ciu_pci_inta_s cn38xxp2; 9875 struct cvmx_ciu_pci_inta_s cn50xx; 9876 struct cvmx_ciu_pci_inta_s cn52xx; 9877 struct cvmx_ciu_pci_inta_s cn52xxp1; 9878 struct cvmx_ciu_pci_inta_s cn56xx; 9879 struct cvmx_ciu_pci_inta_s cn56xxp1; 9880 struct cvmx_ciu_pci_inta_s cn58xx; 9881 struct cvmx_ciu_pci_inta_s cn58xxp1; 9882 struct cvmx_ciu_pci_inta_s cn61xx; 9883 struct cvmx_ciu_pci_inta_s cn63xx; 9884 struct cvmx_ciu_pci_inta_s cn63xxp1; 9885 struct cvmx_ciu_pci_inta_s cn66xx; 9886 struct cvmx_ciu_pci_inta_s cn68xx; 9887 struct cvmx_ciu_pci_inta_s cn68xxp1; 9888 struct cvmx_ciu_pci_inta_s cnf71xx; 9889}; 9890typedef union cvmx_ciu_pci_inta cvmx_ciu_pci_inta_t; 9891 9892/** 9893 * cvmx_ciu_pp_bist_stat 9894 */ 9895union cvmx_ciu_pp_bist_stat { 9896 uint64_t u64; 9897 struct cvmx_ciu_pp_bist_stat_s { 9898#ifdef __BIG_ENDIAN_BITFIELD 9899 uint64_t reserved_32_63 : 32; 9900 uint64_t pp_bist : 32; /**< Physical PP BIST status */ 9901#else 9902 uint64_t pp_bist : 32; 9903 uint64_t reserved_32_63 : 32; 9904#endif 9905 } s; 9906 struct cvmx_ciu_pp_bist_stat_s cn68xx; 9907 struct cvmx_ciu_pp_bist_stat_s cn68xxp1; 9908}; 9909typedef union cvmx_ciu_pp_bist_stat cvmx_ciu_pp_bist_stat_t; 9910 9911/** 9912 * cvmx_ciu_pp_dbg 9913 */ 9914union cvmx_ciu_pp_dbg { 9915 uint64_t u64; 9916 struct cvmx_ciu_pp_dbg_s { 9917#ifdef __BIG_ENDIAN_BITFIELD 9918 uint64_t reserved_32_63 : 32; 9919 uint64_t ppdbg : 32; /**< Debug[DM] value for each PP 9920 whether the PP's are in debug mode or not */ 9921#else 9922 uint64_t ppdbg : 32; 9923 uint64_t reserved_32_63 : 32; 9924#endif 9925 } s; 9926 struct cvmx_ciu_pp_dbg_cn30xx { 9927#ifdef __BIG_ENDIAN_BITFIELD 9928 uint64_t reserved_1_63 : 63; 9929 uint64_t ppdbg : 1; /**< Debug[DM] value for each PP 9930 whether the PP's are in debug mode or not */ 9931#else 9932 uint64_t ppdbg : 1; 9933 uint64_t reserved_1_63 : 63; 9934#endif 9935 } cn30xx; 9936 struct cvmx_ciu_pp_dbg_cn31xx { 9937#ifdef __BIG_ENDIAN_BITFIELD 9938 uint64_t reserved_2_63 : 62; 9939 uint64_t ppdbg : 2; /**< Debug[DM] value for each PP 9940 whether the PP's are in debug mode or not */ 9941#else 9942 uint64_t ppdbg : 2; 9943 uint64_t reserved_2_63 : 62; 9944#endif 9945 } cn31xx; 9946 struct cvmx_ciu_pp_dbg_cn38xx { 9947#ifdef __BIG_ENDIAN_BITFIELD 9948 uint64_t reserved_16_63 : 48; 9949 uint64_t ppdbg : 16; /**< Debug[DM] value for each PP 9950 whether the PP's are in debug mode or not */ 9951#else 9952 uint64_t ppdbg : 16; 9953 uint64_t reserved_16_63 : 48; 9954#endif 9955 } cn38xx; 9956 struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2; 9957 struct cvmx_ciu_pp_dbg_cn31xx cn50xx; 9958 struct cvmx_ciu_pp_dbg_cn52xx { 9959#ifdef __BIG_ENDIAN_BITFIELD 9960 uint64_t reserved_4_63 : 60; 9961 uint64_t ppdbg : 4; /**< Debug[DM] value for each PP 9962 whether the PP's are in debug mode or not */ 9963#else 9964 uint64_t ppdbg : 4; 9965 uint64_t reserved_4_63 : 60; 9966#endif 9967 } cn52xx; 9968 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; 9969 struct cvmx_ciu_pp_dbg_cn56xx { 9970#ifdef __BIG_ENDIAN_BITFIELD 9971 uint64_t reserved_12_63 : 52; 9972 uint64_t ppdbg : 12; /**< Debug[DM] value for each PP 9973 whether the PP's are in debug mode or not */ 9974#else 9975 uint64_t ppdbg : 12; 9976 uint64_t reserved_12_63 : 52; 9977#endif 9978 } cn56xx; 9979 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; 9980 struct cvmx_ciu_pp_dbg_cn38xx cn58xx; 9981 struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1; 9982 struct cvmx_ciu_pp_dbg_cn52xx cn61xx; 9983 struct cvmx_ciu_pp_dbg_cn63xx { 9984#ifdef __BIG_ENDIAN_BITFIELD 9985 uint64_t reserved_6_63 : 58; 9986 uint64_t ppdbg : 6; /**< Debug[DM] value for each PP 9987 whether the PP's are in debug mode or not */ 9988#else 9989 uint64_t ppdbg : 6; 9990 uint64_t reserved_6_63 : 58; 9991#endif 9992 } cn63xx; 9993 struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; 9994 struct cvmx_ciu_pp_dbg_cn66xx { 9995#ifdef __BIG_ENDIAN_BITFIELD 9996 uint64_t reserved_10_63 : 54; 9997 uint64_t ppdbg : 10; /**< Debug[DM] value for each PP 9998 whether the PP's are in debug mode or not */ 9999#else 10000 uint64_t ppdbg : 10; 10001 uint64_t reserved_10_63 : 54; 10002#endif 10003 } cn66xx; 10004 struct cvmx_ciu_pp_dbg_s cn68xx; 10005 struct cvmx_ciu_pp_dbg_s cn68xxp1; 10006 struct cvmx_ciu_pp_dbg_cn52xx cnf71xx; 10007}; 10008typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t; 10009 10010/** 10011 * cvmx_ciu_pp_poke# 10012 * 10013 * Notes: 10014 * Any write to a CIU_PP_POKE register clears any pending interrupt generated 10015 * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set 10016 * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8). 10017 * 10018 * Reads to this register will return the associated CIU_WDOG register. 10019 */ 10020union cvmx_ciu_pp_pokex { 10021 uint64_t u64; 10022 struct cvmx_ciu_pp_pokex_s { 10023#ifdef __BIG_ENDIAN_BITFIELD 10024 uint64_t poke : 64; /**< Reserved */ 10025#else 10026 uint64_t poke : 64; 10027#endif 10028 } s; 10029 struct cvmx_ciu_pp_pokex_s cn30xx; 10030 struct cvmx_ciu_pp_pokex_s cn31xx; 10031 struct cvmx_ciu_pp_pokex_s cn38xx; 10032 struct cvmx_ciu_pp_pokex_s cn38xxp2; 10033 struct cvmx_ciu_pp_pokex_s cn50xx; 10034 struct cvmx_ciu_pp_pokex_s cn52xx; 10035 struct cvmx_ciu_pp_pokex_s cn52xxp1; 10036 struct cvmx_ciu_pp_pokex_s cn56xx; 10037 struct cvmx_ciu_pp_pokex_s cn56xxp1; 10038 struct cvmx_ciu_pp_pokex_s cn58xx; 10039 struct cvmx_ciu_pp_pokex_s cn58xxp1; 10040 struct cvmx_ciu_pp_pokex_s cn61xx; 10041 struct cvmx_ciu_pp_pokex_s cn63xx; 10042 struct cvmx_ciu_pp_pokex_s cn63xxp1; 10043 struct cvmx_ciu_pp_pokex_s cn66xx; 10044 struct cvmx_ciu_pp_pokex_s cn68xx; 10045 struct cvmx_ciu_pp_pokex_s cn68xxp1; 10046 struct cvmx_ciu_pp_pokex_s cnf71xx; 10047}; 10048typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t; 10049 10050/** 10051 * cvmx_ciu_pp_rst 10052 * 10053 * Contains the reset control for each PP. Value of '1' will hold a PP in reset, '0' will release. 10054 * Resets to 0xf when PCI boot is enabled, 0xe otherwise. 10055 */ 10056union cvmx_ciu_pp_rst { 10057 uint64_t u64; 10058 struct cvmx_ciu_pp_rst_s { 10059#ifdef __BIG_ENDIAN_BITFIELD 10060 uint64_t reserved_32_63 : 32; 10061 uint64_t rst : 31; /**< PP Rst for PP's 3-1 */ 10062 uint64_t rst0 : 1; /**< PP Rst for PP0 10063 depends on standalone mode */ 10064#else 10065 uint64_t rst0 : 1; 10066 uint64_t rst : 31; 10067 uint64_t reserved_32_63 : 32; 10068#endif 10069 } s; 10070 struct cvmx_ciu_pp_rst_cn30xx { 10071#ifdef __BIG_ENDIAN_BITFIELD 10072 uint64_t reserved_1_63 : 63; 10073 uint64_t rst0 : 1; /**< PP Rst for PP0 10074 depends on standalone mode */ 10075#else 10076 uint64_t rst0 : 1; 10077 uint64_t reserved_1_63 : 63; 10078#endif 10079 } cn30xx; 10080 struct cvmx_ciu_pp_rst_cn31xx { 10081#ifdef __BIG_ENDIAN_BITFIELD 10082 uint64_t reserved_2_63 : 62; 10083 uint64_t rst : 1; /**< PP Rst for PP1 */ 10084 uint64_t rst0 : 1; /**< PP Rst for PP0 10085 depends on standalone mode */ 10086#else 10087 uint64_t rst0 : 1; 10088 uint64_t rst : 1; 10089 uint64_t reserved_2_63 : 62; 10090#endif 10091 } cn31xx; 10092 struct cvmx_ciu_pp_rst_cn38xx { 10093#ifdef __BIG_ENDIAN_BITFIELD 10094 uint64_t reserved_16_63 : 48; 10095 uint64_t rst : 15; /**< PP Rst for PP's 15-1 */ 10096 uint64_t rst0 : 1; /**< PP Rst for PP0 10097 depends on standalone mode */ 10098#else 10099 uint64_t rst0 : 1; 10100 uint64_t rst : 15; 10101 uint64_t reserved_16_63 : 48; 10102#endif 10103 } cn38xx; 10104 struct cvmx_ciu_pp_rst_cn38xx cn38xxp2; 10105 struct cvmx_ciu_pp_rst_cn31xx cn50xx; 10106 struct cvmx_ciu_pp_rst_cn52xx { 10107#ifdef __BIG_ENDIAN_BITFIELD 10108 uint64_t reserved_4_63 : 60; 10109 uint64_t rst : 3; /**< PP Rst for PP's 11-1 */ 10110 uint64_t rst0 : 1; /**< PP Rst for PP0 10111 depends on standalone mode */ 10112#else 10113 uint64_t rst0 : 1; 10114 uint64_t rst : 3; 10115 uint64_t reserved_4_63 : 60; 10116#endif 10117 } cn52xx; 10118 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; 10119 struct cvmx_ciu_pp_rst_cn56xx { 10120#ifdef __BIG_ENDIAN_BITFIELD 10121 uint64_t reserved_12_63 : 52; 10122 uint64_t rst : 11; /**< PP Rst for PP's 11-1 */ 10123 uint64_t rst0 : 1; /**< PP Rst for PP0 10124 depends on standalone mode */ 10125#else 10126 uint64_t rst0 : 1; 10127 uint64_t rst : 11; 10128 uint64_t reserved_12_63 : 52; 10129#endif 10130 } cn56xx; 10131 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; 10132 struct cvmx_ciu_pp_rst_cn38xx cn58xx; 10133 struct cvmx_ciu_pp_rst_cn38xx cn58xxp1; 10134 struct cvmx_ciu_pp_rst_cn52xx cn61xx; 10135 struct cvmx_ciu_pp_rst_cn63xx { 10136#ifdef __BIG_ENDIAN_BITFIELD 10137 uint64_t reserved_6_63 : 58; 10138 uint64_t rst : 5; /**< PP Rst for PP's 5-1 */ 10139 uint64_t rst0 : 1; /**< PP Rst for PP0 10140 depends on standalone mode */ 10141#else 10142 uint64_t rst0 : 1; 10143 uint64_t rst : 5; 10144 uint64_t reserved_6_63 : 58; 10145#endif 10146 } cn63xx; 10147 struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; 10148 struct cvmx_ciu_pp_rst_cn66xx { 10149#ifdef __BIG_ENDIAN_BITFIELD 10150 uint64_t reserved_10_63 : 54; 10151 uint64_t rst : 9; /**< PP Rst for PP's 9-1 */ 10152 uint64_t rst0 : 1; /**< PP Rst for PP0 10153 depends on standalone mode */ 10154#else 10155 uint64_t rst0 : 1; 10156 uint64_t rst : 9; 10157 uint64_t reserved_10_63 : 54; 10158#endif 10159 } cn66xx; 10160 struct cvmx_ciu_pp_rst_s cn68xx; 10161 struct cvmx_ciu_pp_rst_s cn68xxp1; 10162 struct cvmx_ciu_pp_rst_cn52xx cnf71xx; 10163}; 10164typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t; 10165 10166/** 10167 * cvmx_ciu_qlm0 10168 * 10169 * Notes: 10170 * This register is only reset by cold reset. 10171 * 10172 */ 10173union cvmx_ciu_qlm0 { 10174 uint64_t u64; 10175 struct cvmx_ciu_qlm0_s { 10176#ifdef __BIG_ENDIAN_BITFIELD 10177 uint64_t g2bypass : 1; /**< QLM0 PCIE Gen2 tx bypass enable */ 10178 uint64_t reserved_53_62 : 10; 10179 uint64_t g2deemph : 5; /**< QLM0 PCIE Gen2 tx bypass de-emphasis value */ 10180 uint64_t reserved_45_47 : 3; 10181 uint64_t g2margin : 5; /**< QLM0 PCIE Gen2 tx bypass margin (amplitude) value */ 10182 uint64_t reserved_32_39 : 8; 10183 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */ 10184 uint64_t reserved_21_30 : 10; 10185 uint64_t txdeemph : 5; /**< QLM0 transmitter bypass de-emphasis value */ 10186 uint64_t reserved_13_15 : 3; 10187 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */ 10188 uint64_t reserved_4_7 : 4; 10189 uint64_t lane_en : 4; /**< QLM0 lane enable mask */ 10190#else 10191 uint64_t lane_en : 4; 10192 uint64_t reserved_4_7 : 4; 10193 uint64_t txmargin : 5; 10194 uint64_t reserved_13_15 : 3; 10195 uint64_t txdeemph : 5; 10196 uint64_t reserved_21_30 : 10; 10197 uint64_t txbypass : 1; 10198 uint64_t reserved_32_39 : 8; 10199 uint64_t g2margin : 5; 10200 uint64_t reserved_45_47 : 3; 10201 uint64_t g2deemph : 5; 10202 uint64_t reserved_53_62 : 10; 10203 uint64_t g2bypass : 1; 10204#endif 10205 } s; 10206 struct cvmx_ciu_qlm0_s cn61xx; 10207 struct cvmx_ciu_qlm0_s cn63xx; 10208 struct cvmx_ciu_qlm0_cn63xxp1 { 10209#ifdef __BIG_ENDIAN_BITFIELD 10210 uint64_t reserved_32_63 : 32; 10211 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */ 10212 uint64_t reserved_20_30 : 11; 10213 uint64_t txdeemph : 4; /**< QLM0 transmitter bypass de-emphasis value */ 10214 uint64_t reserved_13_15 : 3; 10215 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */ 10216 uint64_t reserved_4_7 : 4; 10217 uint64_t lane_en : 4; /**< QLM0 lane enable mask */ 10218#else 10219 uint64_t lane_en : 4; 10220 uint64_t reserved_4_7 : 4; 10221 uint64_t txmargin : 5; 10222 uint64_t reserved_13_15 : 3; 10223 uint64_t txdeemph : 4; 10224 uint64_t reserved_20_30 : 11; 10225 uint64_t txbypass : 1; 10226 uint64_t reserved_32_63 : 32; 10227#endif 10228 } cn63xxp1; 10229 struct cvmx_ciu_qlm0_s cn66xx; 10230 struct cvmx_ciu_qlm0_cn68xx { 10231#ifdef __BIG_ENDIAN_BITFIELD 10232 uint64_t reserved_32_63 : 32; 10233 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */ 10234 uint64_t reserved_21_30 : 10; 10235 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */ 10236 uint64_t reserved_13_15 : 3; 10237 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */ 10238 uint64_t reserved_4_7 : 4; 10239 uint64_t lane_en : 4; /**< QLMx lane enable mask */ 10240#else 10241 uint64_t lane_en : 4; 10242 uint64_t reserved_4_7 : 4; 10243 uint64_t txmargin : 5; 10244 uint64_t reserved_13_15 : 3; 10245 uint64_t txdeemph : 5; 10246 uint64_t reserved_21_30 : 10; 10247 uint64_t txbypass : 1; 10248 uint64_t reserved_32_63 : 32; 10249#endif 10250 } cn68xx; 10251 struct cvmx_ciu_qlm0_cn68xx cn68xxp1; 10252 struct cvmx_ciu_qlm0_s cnf71xx; 10253}; 10254typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t; 10255 10256/** 10257 * cvmx_ciu_qlm1 10258 * 10259 * Notes: 10260 * This register is only reset by cold reset. 10261 * 10262 */ 10263union cvmx_ciu_qlm1 { 10264 uint64_t u64; 10265 struct cvmx_ciu_qlm1_s { 10266#ifdef __BIG_ENDIAN_BITFIELD 10267 uint64_t g2bypass : 1; /**< QLM1 PCIE Gen2 tx bypass enable */ 10268 uint64_t reserved_53_62 : 10; 10269 uint64_t g2deemph : 5; /**< QLM1 PCIE Gen2 tx bypass de-emphasis value */ 10270 uint64_t reserved_45_47 : 3; 10271 uint64_t g2margin : 5; /**< QLM1 PCIE Gen2 tx bypass margin (amplitude) value */ 10272 uint64_t reserved_32_39 : 8; 10273 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */ 10274 uint64_t reserved_21_30 : 10; 10275 uint64_t txdeemph : 5; /**< QLM1 transmitter bypass de-emphasis value */ 10276 uint64_t reserved_13_15 : 3; 10277 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */ 10278 uint64_t reserved_4_7 : 4; 10279 uint64_t lane_en : 4; /**< QLM1 lane enable mask */ 10280#else 10281 uint64_t lane_en : 4; 10282 uint64_t reserved_4_7 : 4; 10283 uint64_t txmargin : 5; 10284 uint64_t reserved_13_15 : 3; 10285 uint64_t txdeemph : 5; 10286 uint64_t reserved_21_30 : 10; 10287 uint64_t txbypass : 1; 10288 uint64_t reserved_32_39 : 8; 10289 uint64_t g2margin : 5; 10290 uint64_t reserved_45_47 : 3; 10291 uint64_t g2deemph : 5; 10292 uint64_t reserved_53_62 : 10; 10293 uint64_t g2bypass : 1; 10294#endif 10295 } s; 10296 struct cvmx_ciu_qlm1_s cn61xx; 10297 struct cvmx_ciu_qlm1_s cn63xx; 10298 struct cvmx_ciu_qlm1_cn63xxp1 { 10299#ifdef __BIG_ENDIAN_BITFIELD 10300 uint64_t reserved_32_63 : 32; 10301 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */ 10302 uint64_t reserved_20_30 : 11; 10303 uint64_t txdeemph : 4; /**< QLM1 transmitter bypass de-emphasis value */ 10304 uint64_t reserved_13_15 : 3; 10305 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */ 10306 uint64_t reserved_4_7 : 4; 10307 uint64_t lane_en : 4; /**< QLM1 lane enable mask */ 10308#else 10309 uint64_t lane_en : 4; 10310 uint64_t reserved_4_7 : 4; 10311 uint64_t txmargin : 5; 10312 uint64_t reserved_13_15 : 3; 10313 uint64_t txdeemph : 4; 10314 uint64_t reserved_20_30 : 11; 10315 uint64_t txbypass : 1; 10316 uint64_t reserved_32_63 : 32; 10317#endif 10318 } cn63xxp1; 10319 struct cvmx_ciu_qlm1_s cn66xx; 10320 struct cvmx_ciu_qlm1_s cn68xx; 10321 struct cvmx_ciu_qlm1_s cn68xxp1; 10322 struct cvmx_ciu_qlm1_s cnf71xx; 10323}; 10324typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t; 10325 10326/** 10327 * cvmx_ciu_qlm2 10328 * 10329 * Notes: 10330 * This register is only reset by cold reset. 10331 * 10332 */ 10333union cvmx_ciu_qlm2 { 10334 uint64_t u64; 10335 struct cvmx_ciu_qlm2_s { 10336#ifdef __BIG_ENDIAN_BITFIELD 10337 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */ 10338 uint64_t reserved_53_62 : 10; 10339 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */ 10340 uint64_t reserved_45_47 : 3; 10341 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */ 10342 uint64_t reserved_32_39 : 8; 10343 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */ 10344 uint64_t reserved_21_30 : 10; 10345 uint64_t txdeemph : 5; /**< QLM2 transmitter bypass de-emphasis value */ 10346 uint64_t reserved_13_15 : 3; 10347 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */ 10348 uint64_t reserved_4_7 : 4; 10349 uint64_t lane_en : 4; /**< QLM2 lane enable mask */ 10350#else 10351 uint64_t lane_en : 4; 10352 uint64_t reserved_4_7 : 4; 10353 uint64_t txmargin : 5; 10354 uint64_t reserved_13_15 : 3; 10355 uint64_t txdeemph : 5; 10356 uint64_t reserved_21_30 : 10; 10357 uint64_t txbypass : 1; 10358 uint64_t reserved_32_39 : 8; 10359 uint64_t g2margin : 5; 10360 uint64_t reserved_45_47 : 3; 10361 uint64_t g2deemph : 5; 10362 uint64_t reserved_53_62 : 10; 10363 uint64_t g2bypass : 1; 10364#endif 10365 } s; 10366 struct cvmx_ciu_qlm2_cn61xx { 10367#ifdef __BIG_ENDIAN_BITFIELD 10368 uint64_t reserved_32_63 : 32; 10369 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */ 10370 uint64_t reserved_21_30 : 10; 10371 uint64_t txdeemph : 5; /**< QLM2 transmitter bypass de-emphasis value */ 10372 uint64_t reserved_13_15 : 3; 10373 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */ 10374 uint64_t reserved_4_7 : 4; 10375 uint64_t lane_en : 4; /**< QLM2 lane enable mask */ 10376#else 10377 uint64_t lane_en : 4; 10378 uint64_t reserved_4_7 : 4; 10379 uint64_t txmargin : 5; 10380 uint64_t reserved_13_15 : 3; 10381 uint64_t txdeemph : 5; 10382 uint64_t reserved_21_30 : 10; 10383 uint64_t txbypass : 1; 10384 uint64_t reserved_32_63 : 32; 10385#endif 10386 } cn61xx; 10387 struct cvmx_ciu_qlm2_cn61xx cn63xx; 10388 struct cvmx_ciu_qlm2_cn63xxp1 { 10389#ifdef __BIG_ENDIAN_BITFIELD 10390 uint64_t reserved_32_63 : 32; 10391 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */ 10392 uint64_t reserved_20_30 : 11; 10393 uint64_t txdeemph : 4; /**< QLM2 transmitter bypass de-emphasis value */ 10394 uint64_t reserved_13_15 : 3; 10395 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */ 10396 uint64_t reserved_4_7 : 4; 10397 uint64_t lane_en : 4; /**< QLM2 lane enable mask */ 10398#else 10399 uint64_t lane_en : 4; 10400 uint64_t reserved_4_7 : 4; 10401 uint64_t txmargin : 5; 10402 uint64_t reserved_13_15 : 3; 10403 uint64_t txdeemph : 4; 10404 uint64_t reserved_20_30 : 11; 10405 uint64_t txbypass : 1; 10406 uint64_t reserved_32_63 : 32; 10407#endif 10408 } cn63xxp1; 10409 struct cvmx_ciu_qlm2_cn61xx cn66xx; 10410 struct cvmx_ciu_qlm2_s cn68xx; 10411 struct cvmx_ciu_qlm2_s cn68xxp1; 10412 struct cvmx_ciu_qlm2_cn61xx cnf71xx; 10413}; 10414typedef union cvmx_ciu_qlm2 cvmx_ciu_qlm2_t; 10415 10416/** 10417 * cvmx_ciu_qlm3 10418 * 10419 * Notes: 10420 * This register is only reset by cold reset. 10421 * 10422 */ 10423union cvmx_ciu_qlm3 { 10424 uint64_t u64; 10425 struct cvmx_ciu_qlm3_s { 10426#ifdef __BIG_ENDIAN_BITFIELD 10427 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */ 10428 uint64_t reserved_53_62 : 10; 10429 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */ 10430 uint64_t reserved_45_47 : 3; 10431 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */ 10432 uint64_t reserved_32_39 : 8; 10433 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */ 10434 uint64_t reserved_21_30 : 10; 10435 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */ 10436 uint64_t reserved_13_15 : 3; 10437 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */ 10438 uint64_t reserved_4_7 : 4; 10439 uint64_t lane_en : 4; /**< QLMx lane enable mask */ 10440#else 10441 uint64_t lane_en : 4; 10442 uint64_t reserved_4_7 : 4; 10443 uint64_t txmargin : 5; 10444 uint64_t reserved_13_15 : 3; 10445 uint64_t txdeemph : 5; 10446 uint64_t reserved_21_30 : 10; 10447 uint64_t txbypass : 1; 10448 uint64_t reserved_32_39 : 8; 10449 uint64_t g2margin : 5; 10450 uint64_t reserved_45_47 : 3; 10451 uint64_t g2deemph : 5; 10452 uint64_t reserved_53_62 : 10; 10453 uint64_t g2bypass : 1; 10454#endif 10455 } s; 10456 struct cvmx_ciu_qlm3_s cn68xx; 10457 struct cvmx_ciu_qlm3_s cn68xxp1; 10458}; 10459typedef union cvmx_ciu_qlm3 cvmx_ciu_qlm3_t; 10460 10461/** 10462 * cvmx_ciu_qlm4 10463 * 10464 * Notes: 10465 * This register is only reset by cold reset. 10466 * 10467 */ 10468union cvmx_ciu_qlm4 { 10469 uint64_t u64; 10470 struct cvmx_ciu_qlm4_s { 10471#ifdef __BIG_ENDIAN_BITFIELD 10472 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */ 10473 uint64_t reserved_53_62 : 10; 10474 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */ 10475 uint64_t reserved_45_47 : 3; 10476 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */ 10477 uint64_t reserved_32_39 : 8; 10478 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */ 10479 uint64_t reserved_21_30 : 10; 10480 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */ 10481 uint64_t reserved_13_15 : 3; 10482 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */ 10483 uint64_t reserved_4_7 : 4; 10484 uint64_t lane_en : 4; /**< QLMx lane enable mask */ 10485#else 10486 uint64_t lane_en : 4; 10487 uint64_t reserved_4_7 : 4; 10488 uint64_t txmargin : 5; 10489 uint64_t reserved_13_15 : 3; 10490 uint64_t txdeemph : 5; 10491 uint64_t reserved_21_30 : 10; 10492 uint64_t txbypass : 1; 10493 uint64_t reserved_32_39 : 8; 10494 uint64_t g2margin : 5; 10495 uint64_t reserved_45_47 : 3; 10496 uint64_t g2deemph : 5; 10497 uint64_t reserved_53_62 : 10; 10498 uint64_t g2bypass : 1; 10499#endif 10500 } s; 10501 struct cvmx_ciu_qlm4_s cn68xx; 10502 struct cvmx_ciu_qlm4_s cn68xxp1; 10503}; 10504typedef union cvmx_ciu_qlm4 cvmx_ciu_qlm4_t; 10505 10506/** 10507 * cvmx_ciu_qlm_dcok 10508 */ 10509union cvmx_ciu_qlm_dcok { 10510 uint64_t u64; 10511 struct cvmx_ciu_qlm_dcok_s { 10512#ifdef __BIG_ENDIAN_BITFIELD 10513 uint64_t reserved_4_63 : 60; 10514 uint64_t qlm_dcok : 4; /**< Re-assert dcok for each QLM. The value in this 10515 field is "anded" with the pll_dcok pin and then 10516 sent to each QLM (0..3). */ 10517#else 10518 uint64_t qlm_dcok : 4; 10519 uint64_t reserved_4_63 : 60; 10520#endif 10521 } s; 10522 struct cvmx_ciu_qlm_dcok_cn52xx { 10523#ifdef __BIG_ENDIAN_BITFIELD 10524 uint64_t reserved_2_63 : 62; 10525 uint64_t qlm_dcok : 2; /**< Re-assert dcok for each QLM. The value in this 10526 field is "anded" with the pll_dcok pin and then 10527 sent to each QLM (0..3). */ 10528#else 10529 uint64_t qlm_dcok : 2; 10530 uint64_t reserved_2_63 : 62; 10531#endif 10532 } cn52xx; 10533 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; 10534 struct cvmx_ciu_qlm_dcok_s cn56xx; 10535 struct cvmx_ciu_qlm_dcok_s cn56xxp1; 10536}; 10537typedef union cvmx_ciu_qlm_dcok cvmx_ciu_qlm_dcok_t; 10538 10539/** 10540 * cvmx_ciu_qlm_jtgc 10541 */ 10542union cvmx_ciu_qlm_jtgc { 10543 uint64_t u64; 10544 struct cvmx_ciu_qlm_jtgc_s { 10545#ifdef __BIG_ENDIAN_BITFIELD 10546 uint64_t reserved_17_63 : 47; 10547 uint64_t bypass_ext : 1; /**< BYPASS Field extension to select QLM 4 10548 Selects which QLM JTAG shift chains are bypassed 10549 by the QLM JTAG data register (CIU_QLM_JTGD) (one 10550 bit per QLM) */ 10551 uint64_t reserved_11_15 : 5; 10552 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 10553 divided by 2^(CLK_DIV + 2) */ 10554 uint64_t reserved_7_7 : 1; 10555 uint64_t mux_sel : 3; /**< Selects which QLM JTAG shift out is shifted into 10556 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 10557 uint64_t bypass : 4; /**< Selects which QLM JTAG shift chains are bypassed 10558 by the QLM JTAG data register (CIU_QLM_JTGD) (one 10559 bit per QLM) */ 10560#else 10561 uint64_t bypass : 4; 10562 uint64_t mux_sel : 3; 10563 uint64_t reserved_7_7 : 1; 10564 uint64_t clk_div : 3; 10565 uint64_t reserved_11_15 : 5; 10566 uint64_t bypass_ext : 1; 10567 uint64_t reserved_17_63 : 47; 10568#endif 10569 } s; 10570 struct cvmx_ciu_qlm_jtgc_cn52xx { 10571#ifdef __BIG_ENDIAN_BITFIELD 10572 uint64_t reserved_11_63 : 53; 10573 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 10574 divided by 2^(CLK_DIV + 2) */ 10575 uint64_t reserved_5_7 : 3; 10576 uint64_t mux_sel : 1; /**< Selects which QLM JTAG shift out is shifted into 10577 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 10578 uint64_t reserved_2_3 : 2; 10579 uint64_t bypass : 2; /**< Selects which QLM JTAG shift chains are bypassed 10580 by the QLM JTAG data register (CIU_QLM_JTGD) (one 10581 bit per QLM) */ 10582#else 10583 uint64_t bypass : 2; 10584 uint64_t reserved_2_3 : 2; 10585 uint64_t mux_sel : 1; 10586 uint64_t reserved_5_7 : 3; 10587 uint64_t clk_div : 3; 10588 uint64_t reserved_11_63 : 53; 10589#endif 10590 } cn52xx; 10591 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; 10592 struct cvmx_ciu_qlm_jtgc_cn56xx { 10593#ifdef __BIG_ENDIAN_BITFIELD 10594 uint64_t reserved_11_63 : 53; 10595 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 10596 divided by 2^(CLK_DIV + 2) */ 10597 uint64_t reserved_6_7 : 2; 10598 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into 10599 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 10600 uint64_t bypass : 4; /**< Selects which QLM JTAG shift chains are bypassed 10601 by the QLM JTAG data register (CIU_QLM_JTGD) (one 10602 bit per QLM) */ 10603#else 10604 uint64_t bypass : 4; 10605 uint64_t mux_sel : 2; 10606 uint64_t reserved_6_7 : 2; 10607 uint64_t clk_div : 3; 10608 uint64_t reserved_11_63 : 53; 10609#endif 10610 } cn56xx; 10611 struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1; 10612 struct cvmx_ciu_qlm_jtgc_cn61xx { 10613#ifdef __BIG_ENDIAN_BITFIELD 10614 uint64_t reserved_11_63 : 53; 10615 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 10616 divided by 2^(CLK_DIV + 2) */ 10617 uint64_t reserved_6_7 : 2; 10618 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into 10619 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 10620 uint64_t reserved_3_3 : 1; 10621 uint64_t bypass : 3; /**< Selects which QLM JTAG shift chains are bypassed 10622 by the QLM JTAG data register (CIU_QLM_JTGD) (one 10623 bit per QLM) */ 10624#else 10625 uint64_t bypass : 3; 10626 uint64_t reserved_3_3 : 1; 10627 uint64_t mux_sel : 2; 10628 uint64_t reserved_6_7 : 2; 10629 uint64_t clk_div : 3; 10630 uint64_t reserved_11_63 : 53; 10631#endif 10632 } cn61xx; 10633 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx; 10634 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1; 10635 struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx; 10636 struct cvmx_ciu_qlm_jtgc_s cn68xx; 10637 struct cvmx_ciu_qlm_jtgc_s cn68xxp1; 10638 struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx; 10639}; 10640typedef union cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgc_t; 10641 10642/** 10643 * cvmx_ciu_qlm_jtgd 10644 */ 10645union cvmx_ciu_qlm_jtgd { 10646 uint64_t u64; 10647 struct cvmx_ciu_qlm_jtgd_s { 10648#ifdef __BIG_ENDIAN_BITFIELD 10649 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 10650 op completes) */ 10651 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 10652 op completes) */ 10653 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 10654 op completes) */ 10655 uint64_t reserved_45_60 : 16; 10656 uint64_t select : 5; /**< Selects which QLM JTAG shift chains the JTAG 10657 operations are performed on */ 10658 uint64_t reserved_37_39 : 3; 10659 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 10660 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 10661#else 10662 uint64_t shft_reg : 32; 10663 uint64_t shft_cnt : 5; 10664 uint64_t reserved_37_39 : 3; 10665 uint64_t select : 5; 10666 uint64_t reserved_45_60 : 16; 10667 uint64_t update : 1; 10668 uint64_t shift : 1; 10669 uint64_t capture : 1; 10670#endif 10671 } s; 10672 struct cvmx_ciu_qlm_jtgd_cn52xx { 10673#ifdef __BIG_ENDIAN_BITFIELD 10674 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 10675 op completes) */ 10676 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 10677 op completes) */ 10678 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 10679 op completes) */ 10680 uint64_t reserved_42_60 : 19; 10681 uint64_t select : 2; /**< Selects which QLM JTAG shift chains the JTAG 10682 operations are performed on */ 10683 uint64_t reserved_37_39 : 3; 10684 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 10685 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 10686#else 10687 uint64_t shft_reg : 32; 10688 uint64_t shft_cnt : 5; 10689 uint64_t reserved_37_39 : 3; 10690 uint64_t select : 2; 10691 uint64_t reserved_42_60 : 19; 10692 uint64_t update : 1; 10693 uint64_t shift : 1; 10694 uint64_t capture : 1; 10695#endif 10696 } cn52xx; 10697 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; 10698 struct cvmx_ciu_qlm_jtgd_cn56xx { 10699#ifdef __BIG_ENDIAN_BITFIELD 10700 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 10701 op completes) */ 10702 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 10703 op completes) */ 10704 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 10705 op completes) */ 10706 uint64_t reserved_44_60 : 17; 10707 uint64_t select : 4; /**< Selects which QLM JTAG shift chains the JTAG 10708 operations are performed on */ 10709 uint64_t reserved_37_39 : 3; 10710 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 10711 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 10712#else 10713 uint64_t shft_reg : 32; 10714 uint64_t shft_cnt : 5; 10715 uint64_t reserved_37_39 : 3; 10716 uint64_t select : 4; 10717 uint64_t reserved_44_60 : 17; 10718 uint64_t update : 1; 10719 uint64_t shift : 1; 10720 uint64_t capture : 1; 10721#endif 10722 } cn56xx; 10723 struct cvmx_ciu_qlm_jtgd_cn56xxp1 { 10724#ifdef __BIG_ENDIAN_BITFIELD 10725 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 10726 op completes) */ 10727 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 10728 op completes) */ 10729 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 10730 op completes) */ 10731 uint64_t reserved_37_60 : 24; 10732 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 10733 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 10734#else 10735 uint64_t shft_reg : 32; 10736 uint64_t shft_cnt : 5; 10737 uint64_t reserved_37_60 : 24; 10738 uint64_t update : 1; 10739 uint64_t shift : 1; 10740 uint64_t capture : 1; 10741#endif 10742 } cn56xxp1; 10743 struct cvmx_ciu_qlm_jtgd_cn61xx { 10744#ifdef __BIG_ENDIAN_BITFIELD 10745 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 10746 op completes) */ 10747 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 10748 op completes) */ 10749 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 10750 op completes) */ 10751 uint64_t reserved_43_60 : 18; 10752 uint64_t select : 3; /**< Selects which QLM JTAG shift chains the JTAG 10753 operations are performed on */ 10754 uint64_t reserved_37_39 : 3; 10755 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 10756 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 10757#else 10758 uint64_t shft_reg : 32; 10759 uint64_t shft_cnt : 5; 10760 uint64_t reserved_37_39 : 3; 10761 uint64_t select : 3; 10762 uint64_t reserved_43_60 : 18; 10763 uint64_t update : 1; 10764 uint64_t shift : 1; 10765 uint64_t capture : 1; 10766#endif 10767 } cn61xx; 10768 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx; 10769 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1; 10770 struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx; 10771 struct cvmx_ciu_qlm_jtgd_s cn68xx; 10772 struct cvmx_ciu_qlm_jtgd_s cn68xxp1; 10773 struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx; 10774}; 10775typedef union cvmx_ciu_qlm_jtgd cvmx_ciu_qlm_jtgd_t; 10776 10777/** 10778 * cvmx_ciu_soft_bist 10779 */ 10780union cvmx_ciu_soft_bist { 10781 uint64_t u64; 10782 struct cvmx_ciu_soft_bist_s { 10783#ifdef __BIG_ENDIAN_BITFIELD 10784 uint64_t reserved_1_63 : 63; 10785 uint64_t soft_bist : 1; /**< Reserved */ 10786#else 10787 uint64_t soft_bist : 1; 10788 uint64_t reserved_1_63 : 63; 10789#endif 10790 } s; 10791 struct cvmx_ciu_soft_bist_s cn30xx; 10792 struct cvmx_ciu_soft_bist_s cn31xx; 10793 struct cvmx_ciu_soft_bist_s cn38xx; 10794 struct cvmx_ciu_soft_bist_s cn38xxp2; 10795 struct cvmx_ciu_soft_bist_s cn50xx; 10796 struct cvmx_ciu_soft_bist_s cn52xx; 10797 struct cvmx_ciu_soft_bist_s cn52xxp1; 10798 struct cvmx_ciu_soft_bist_s cn56xx; 10799 struct cvmx_ciu_soft_bist_s cn56xxp1; 10800 struct cvmx_ciu_soft_bist_s cn58xx; 10801 struct cvmx_ciu_soft_bist_s cn58xxp1; 10802 struct cvmx_ciu_soft_bist_s cn61xx; 10803 struct cvmx_ciu_soft_bist_s cn63xx; 10804 struct cvmx_ciu_soft_bist_s cn63xxp1; 10805 struct cvmx_ciu_soft_bist_s cn66xx; 10806 struct cvmx_ciu_soft_bist_s cn68xx; 10807 struct cvmx_ciu_soft_bist_s cn68xxp1; 10808 struct cvmx_ciu_soft_bist_s cnf71xx; 10809}; 10810typedef union cvmx_ciu_soft_bist cvmx_ciu_soft_bist_t; 10811 10812/** 10813 * cvmx_ciu_soft_prst 10814 */ 10815union cvmx_ciu_soft_prst { 10816 uint64_t u64; 10817 struct cvmx_ciu_soft_prst_s { 10818#ifdef __BIG_ENDIAN_BITFIELD 10819 uint64_t reserved_3_63 : 61; 10820 uint64_t host64 : 1; /**< PCX Host Mode Device Capability (0=32b/1=64b) */ 10821 uint64_t npi : 1; /**< When PCI soft reset is asserted, also reset the 10822 NPI and PNI logic */ 10823 uint64_t soft_prst : 1; /**< Resets the PCIe logic in all modes, not just 10824 RC mode. The reset value is based on the 10825 corresponding MIO_RST_CTL[PRTMODE] CSR field: 10826 If PRTMODE == 0, then SOFT_PRST resets to 0 10827 If PRTMODE != 0, then SOFT_PRST resets to 1 10828 When OCTEON is configured to drive the PERST*_L 10829 chip pin (ie. MIO_RST_CTL0[RST_DRV] is set), this 10830 controls the PERST*_L chip pin. */ 10831#else 10832 uint64_t soft_prst : 1; 10833 uint64_t npi : 1; 10834 uint64_t host64 : 1; 10835 uint64_t reserved_3_63 : 61; 10836#endif 10837 } s; 10838 struct cvmx_ciu_soft_prst_s cn30xx; 10839 struct cvmx_ciu_soft_prst_s cn31xx; 10840 struct cvmx_ciu_soft_prst_s cn38xx; 10841 struct cvmx_ciu_soft_prst_s cn38xxp2; 10842 struct cvmx_ciu_soft_prst_s cn50xx; 10843 struct cvmx_ciu_soft_prst_cn52xx { 10844#ifdef __BIG_ENDIAN_BITFIELD 10845 uint64_t reserved_1_63 : 63; 10846 uint64_t soft_prst : 1; /**< Reset the PCI bus. Only works when Octane is 10847 configured as a HOST. When OCTEON is a PCI host 10848 (i.e. when PCI_HOST_MODE = 1), This controls 10849 PCI_RST_L. Refer to section 10.11.1. */ 10850#else 10851 uint64_t soft_prst : 1; 10852 uint64_t reserved_1_63 : 63; 10853#endif 10854 } cn52xx; 10855 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; 10856 struct cvmx_ciu_soft_prst_cn52xx cn56xx; 10857 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; 10858 struct cvmx_ciu_soft_prst_s cn58xx; 10859 struct cvmx_ciu_soft_prst_s cn58xxp1; 10860 struct cvmx_ciu_soft_prst_cn52xx cn61xx; 10861 struct cvmx_ciu_soft_prst_cn52xx cn63xx; 10862 struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; 10863 struct cvmx_ciu_soft_prst_cn52xx cn66xx; 10864 struct cvmx_ciu_soft_prst_cn52xx cn68xx; 10865 struct cvmx_ciu_soft_prst_cn52xx cn68xxp1; 10866 struct cvmx_ciu_soft_prst_cn52xx cnf71xx; 10867}; 10868typedef union cvmx_ciu_soft_prst cvmx_ciu_soft_prst_t; 10869 10870/** 10871 * cvmx_ciu_soft_prst1 10872 */ 10873union cvmx_ciu_soft_prst1 { 10874 uint64_t u64; 10875 struct cvmx_ciu_soft_prst1_s { 10876#ifdef __BIG_ENDIAN_BITFIELD 10877 uint64_t reserved_1_63 : 63; 10878 uint64_t soft_prst : 1; /**< Resets the PCIe logic in all modes, not just 10879 RC mode. The reset value is based on the 10880 corresponding MIO_RST_CTL[PRTMODE] CSR field: 10881 If PRTMODE == 0, then SOFT_PRST resets to 0 10882 If PRTMODE != 0, then SOFT_PRST resets to 1 10883 In o61, this PRST initial value is always '1' as 10884 PEM1 always running on host mode. */ 10885#else 10886 uint64_t soft_prst : 1; 10887 uint64_t reserved_1_63 : 63; 10888#endif 10889 } s; 10890 struct cvmx_ciu_soft_prst1_s cn52xx; 10891 struct cvmx_ciu_soft_prst1_s cn52xxp1; 10892 struct cvmx_ciu_soft_prst1_s cn56xx; 10893 struct cvmx_ciu_soft_prst1_s cn56xxp1; 10894 struct cvmx_ciu_soft_prst1_s cn61xx; 10895 struct cvmx_ciu_soft_prst1_s cn63xx; 10896 struct cvmx_ciu_soft_prst1_s cn63xxp1; 10897 struct cvmx_ciu_soft_prst1_s cn66xx; 10898 struct cvmx_ciu_soft_prst1_s cn68xx; 10899 struct cvmx_ciu_soft_prst1_s cn68xxp1; 10900 struct cvmx_ciu_soft_prst1_s cnf71xx; 10901}; 10902typedef union cvmx_ciu_soft_prst1 cvmx_ciu_soft_prst1_t; 10903 10904/** 10905 * cvmx_ciu_soft_prst2 10906 */ 10907union cvmx_ciu_soft_prst2 { 10908 uint64_t u64; 10909 struct cvmx_ciu_soft_prst2_s { 10910#ifdef __BIG_ENDIAN_BITFIELD 10911 uint64_t reserved_1_63 : 63; 10912 uint64_t soft_prst : 1; /**< Resets the sRIO logic in all modes, not just 10913 RC mode. The reset value is based on the 10914 corresponding MIO_RST_CNTL[PRTMODE] CSR field: 10915 If PRTMODE == 0, then SOFT_PRST resets to 0 10916 If PRTMODE != 0, then SOFT_PRST resets to 1 */ 10917#else 10918 uint64_t soft_prst : 1; 10919 uint64_t reserved_1_63 : 63; 10920#endif 10921 } s; 10922 struct cvmx_ciu_soft_prst2_s cn66xx; 10923}; 10924typedef union cvmx_ciu_soft_prst2 cvmx_ciu_soft_prst2_t; 10925 10926/** 10927 * cvmx_ciu_soft_prst3 10928 */ 10929union cvmx_ciu_soft_prst3 { 10930 uint64_t u64; 10931 struct cvmx_ciu_soft_prst3_s { 10932#ifdef __BIG_ENDIAN_BITFIELD 10933 uint64_t reserved_1_63 : 63; 10934 uint64_t soft_prst : 1; /**< Resets the sRIO logic in all modes, not just 10935 RC mode. The reset value is based on the 10936 corresponding MIO_RST_CNTL[PRTMODE] CSR field: 10937 If PRTMODE == 0, then SOFT_PRST resets to 0 10938 If PRTMODE != 0, then SOFT_PRST resets to 1 */ 10939#else 10940 uint64_t soft_prst : 1; 10941 uint64_t reserved_1_63 : 63; 10942#endif 10943 } s; 10944 struct cvmx_ciu_soft_prst3_s cn66xx; 10945}; 10946typedef union cvmx_ciu_soft_prst3 cvmx_ciu_soft_prst3_t; 10947 10948/** 10949 * cvmx_ciu_soft_rst 10950 */ 10951union cvmx_ciu_soft_rst { 10952 uint64_t u64; 10953 struct cvmx_ciu_soft_rst_s { 10954#ifdef __BIG_ENDIAN_BITFIELD 10955 uint64_t reserved_1_63 : 63; 10956 uint64_t soft_rst : 1; /**< Resets Octeon 10957 When soft reseting Octeon from a remote PCIe 10958 host, always read CIU_SOFT_RST (and wait for 10959 result) before writing SOFT_RST to '1'. */ 10960#else 10961 uint64_t soft_rst : 1; 10962 uint64_t reserved_1_63 : 63; 10963#endif 10964 } s; 10965 struct cvmx_ciu_soft_rst_s cn30xx; 10966 struct cvmx_ciu_soft_rst_s cn31xx; 10967 struct cvmx_ciu_soft_rst_s cn38xx; 10968 struct cvmx_ciu_soft_rst_s cn38xxp2; 10969 struct cvmx_ciu_soft_rst_s cn50xx; 10970 struct cvmx_ciu_soft_rst_s cn52xx; 10971 struct cvmx_ciu_soft_rst_s cn52xxp1; 10972 struct cvmx_ciu_soft_rst_s cn56xx; 10973 struct cvmx_ciu_soft_rst_s cn56xxp1; 10974 struct cvmx_ciu_soft_rst_s cn58xx; 10975 struct cvmx_ciu_soft_rst_s cn58xxp1; 10976 struct cvmx_ciu_soft_rst_s cn61xx; 10977 struct cvmx_ciu_soft_rst_s cn63xx; 10978 struct cvmx_ciu_soft_rst_s cn63xxp1; 10979 struct cvmx_ciu_soft_rst_s cn66xx; 10980 struct cvmx_ciu_soft_rst_s cn68xx; 10981 struct cvmx_ciu_soft_rst_s cn68xxp1; 10982 struct cvmx_ciu_soft_rst_s cnf71xx; 10983}; 10984typedef union cvmx_ciu_soft_rst cvmx_ciu_soft_rst_t; 10985 10986/** 10987 * cvmx_ciu_sum1_io#_int 10988 * 10989 * Notes: 10990 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have 10991 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always 10992 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for 10993 * different PPs, same value as $CIU_INT_SUM1. 10994 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field. 10995 */ 10996union cvmx_ciu_sum1_iox_int { 10997 uint64_t u64; 10998 struct cvmx_ciu_sum1_iox_int_s { 10999#ifdef __BIG_ENDIAN_BITFIELD 11000 uint64_t rst : 1; /**< MIO RST interrupt 11001 See MIO_RST_INT */ 11002 uint64_t reserved_62_62 : 1; 11003 uint64_t srio3 : 1; /**< SRIO3 interrupt 11004 See SRIO3_INT_REG, SRIO3_INT2_REG */ 11005 uint64_t srio2 : 1; /**< SRIO2 interrupt 11006 See SRIO2_INT_REG, SRIO2_INT2_REG */ 11007 uint64_t reserved_57_59 : 3; 11008 uint64_t dfm : 1; /**< DFM Interrupt 11009 See DFM_FNT_STAT */ 11010 uint64_t reserved_53_55 : 3; 11011 uint64_t lmc0 : 1; /**< LMC0 interrupt 11012 See LMC0_INT */ 11013 uint64_t reserved_51_51 : 1; 11014 uint64_t srio0 : 1; /**< SRIO0 interrupt 11015 See SRIO0_INT_REG, SRIO0_INT2_REG */ 11016 uint64_t pem1 : 1; /**< PEM1 interrupt 11017 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11018 uint64_t pem0 : 1; /**< PEM0 interrupt 11019 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11020 uint64_t ptp : 1; /**< PTP interrupt 11021 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11022 uint64_t agl : 1; /**< AGL interrupt 11023 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11024 uint64_t reserved_41_45 : 5; 11025 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11026 TBD, See DPI DMA instruction completion */ 11027 uint64_t reserved_38_39 : 2; 11028 uint64_t agx1 : 1; /**< GMX1 interrupt 11029 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11030 PCS1_INT*_REG, PCSX1_INT_REG */ 11031 uint64_t agx0 : 1; /**< GMX0 interrupt 11032 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11033 PCS0_INT*_REG, PCSX0_INT_REG */ 11034 uint64_t dpi : 1; /**< DPI interrupt 11035 See DPI_INT_REG */ 11036 uint64_t sli : 1; /**< SLI interrupt 11037 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11038 uint64_t usb : 1; /**< USB UCTL0 interrupt 11039 See UCTL0_INT_REG */ 11040 uint64_t dfa : 1; /**< DFA interrupt 11041 See DFA_ERROR */ 11042 uint64_t key : 1; /**< KEY interrupt 11043 See KEY_INT_SUM */ 11044 uint64_t rad : 1; /**< RAD interrupt 11045 See RAD_REG_ERROR */ 11046 uint64_t tim : 1; /**< TIM interrupt 11047 See TIM_REG_ERROR */ 11048 uint64_t zip : 1; /**< ZIP interrupt 11049 See ZIP_ERROR */ 11050 uint64_t pko : 1; /**< PKO interrupt 11051 See PKO_REG_ERROR */ 11052 uint64_t pip : 1; /**< PIP interrupt 11053 See PIP_INT_REG */ 11054 uint64_t ipd : 1; /**< IPD interrupt 11055 See IPD_INT_SUM */ 11056 uint64_t l2c : 1; /**< L2C interrupt 11057 See L2C_INT_REG */ 11058 uint64_t pow : 1; /**< POW err interrupt 11059 See POW_ECC_ERR */ 11060 uint64_t fpa : 1; /**< FPA interrupt 11061 See FPA_INT_SUM */ 11062 uint64_t iob : 1; /**< IOB interrupt 11063 See IOB_INT_SUM */ 11064 uint64_t mio : 1; /**< MIO boot interrupt 11065 See MIO_BOOT_ERR */ 11066 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11067 See EMMC interrupt */ 11068 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 11069 See MIX1_ISR */ 11070 uint64_t reserved_10_17 : 8; 11071 uint64_t wdog : 10; /**< Per PP watchdog interrupts */ 11072#else 11073 uint64_t wdog : 10; 11074 uint64_t reserved_10_17 : 8; 11075 uint64_t mii1 : 1; 11076 uint64_t nand : 1; 11077 uint64_t mio : 1; 11078 uint64_t iob : 1; 11079 uint64_t fpa : 1; 11080 uint64_t pow : 1; 11081 uint64_t l2c : 1; 11082 uint64_t ipd : 1; 11083 uint64_t pip : 1; 11084 uint64_t pko : 1; 11085 uint64_t zip : 1; 11086 uint64_t tim : 1; 11087 uint64_t rad : 1; 11088 uint64_t key : 1; 11089 uint64_t dfa : 1; 11090 uint64_t usb : 1; 11091 uint64_t sli : 1; 11092 uint64_t dpi : 1; 11093 uint64_t agx0 : 1; 11094 uint64_t agx1 : 1; 11095 uint64_t reserved_38_39 : 2; 11096 uint64_t dpi_dma : 1; 11097 uint64_t reserved_41_45 : 5; 11098 uint64_t agl : 1; 11099 uint64_t ptp : 1; 11100 uint64_t pem0 : 1; 11101 uint64_t pem1 : 1; 11102 uint64_t srio0 : 1; 11103 uint64_t reserved_51_51 : 1; 11104 uint64_t lmc0 : 1; 11105 uint64_t reserved_53_55 : 3; 11106 uint64_t dfm : 1; 11107 uint64_t reserved_57_59 : 3; 11108 uint64_t srio2 : 1; 11109 uint64_t srio3 : 1; 11110 uint64_t reserved_62_62 : 1; 11111 uint64_t rst : 1; 11112#endif 11113 } s; 11114 struct cvmx_ciu_sum1_iox_int_cn61xx { 11115#ifdef __BIG_ENDIAN_BITFIELD 11116 uint64_t rst : 1; /**< MIO RST interrupt 11117 See MIO_RST_INT */ 11118 uint64_t reserved_53_62 : 10; 11119 uint64_t lmc0 : 1; /**< LMC0 interrupt 11120 See LMC0_INT */ 11121 uint64_t reserved_50_51 : 2; 11122 uint64_t pem1 : 1; /**< PEM1 interrupt 11123 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11124 uint64_t pem0 : 1; /**< PEM0 interrupt 11125 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11126 uint64_t ptp : 1; /**< PTP interrupt 11127 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11128 uint64_t agl : 1; /**< AGL interrupt 11129 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11130 uint64_t reserved_41_45 : 5; 11131 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11132 TBD, See DPI DMA instruction completion */ 11133 uint64_t reserved_38_39 : 2; 11134 uint64_t agx1 : 1; /**< GMX1 interrupt 11135 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11136 PCS1_INT*_REG, PCSX1_INT_REG */ 11137 uint64_t agx0 : 1; /**< GMX0 interrupt 11138 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11139 PCS0_INT*_REG, PCSX0_INT_REG */ 11140 uint64_t dpi : 1; /**< DPI interrupt 11141 See DPI_INT_REG */ 11142 uint64_t sli : 1; /**< SLI interrupt 11143 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11144 uint64_t usb : 1; /**< USB UCTL0 interrupt 11145 See UCTL0_INT_REG */ 11146 uint64_t dfa : 1; /**< DFA interrupt 11147 See DFA_ERROR */ 11148 uint64_t key : 1; /**< KEY interrupt 11149 See KEY_INT_SUM */ 11150 uint64_t rad : 1; /**< RAD interrupt 11151 See RAD_REG_ERROR */ 11152 uint64_t tim : 1; /**< TIM interrupt 11153 See TIM_REG_ERROR */ 11154 uint64_t zip : 1; /**< ZIP interrupt 11155 See ZIP_ERROR */ 11156 uint64_t pko : 1; /**< PKO interrupt 11157 See PKO_REG_ERROR */ 11158 uint64_t pip : 1; /**< PIP interrupt 11159 See PIP_INT_REG */ 11160 uint64_t ipd : 1; /**< IPD interrupt 11161 See IPD_INT_SUM */ 11162 uint64_t l2c : 1; /**< L2C interrupt 11163 See L2C_INT_REG */ 11164 uint64_t pow : 1; /**< POW err interrupt 11165 See POW_ECC_ERR */ 11166 uint64_t fpa : 1; /**< FPA interrupt 11167 See FPA_INT_SUM */ 11168 uint64_t iob : 1; /**< IOB interrupt 11169 See IOB_INT_SUM */ 11170 uint64_t mio : 1; /**< MIO boot interrupt 11171 See MIO_BOOT_ERR */ 11172 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11173 See EMMC interrupt */ 11174 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt 11175 See MIX1_ISR */ 11176 uint64_t reserved_4_17 : 14; 11177 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 11178#else 11179 uint64_t wdog : 4; 11180 uint64_t reserved_4_17 : 14; 11181 uint64_t mii1 : 1; 11182 uint64_t nand : 1; 11183 uint64_t mio : 1; 11184 uint64_t iob : 1; 11185 uint64_t fpa : 1; 11186 uint64_t pow : 1; 11187 uint64_t l2c : 1; 11188 uint64_t ipd : 1; 11189 uint64_t pip : 1; 11190 uint64_t pko : 1; 11191 uint64_t zip : 1; 11192 uint64_t tim : 1; 11193 uint64_t rad : 1; 11194 uint64_t key : 1; 11195 uint64_t dfa : 1; 11196 uint64_t usb : 1; 11197 uint64_t sli : 1; 11198 uint64_t dpi : 1; 11199 uint64_t agx0 : 1; 11200 uint64_t agx1 : 1; 11201 uint64_t reserved_38_39 : 2; 11202 uint64_t dpi_dma : 1; 11203 uint64_t reserved_41_45 : 5; 11204 uint64_t agl : 1; 11205 uint64_t ptp : 1; 11206 uint64_t pem0 : 1; 11207 uint64_t pem1 : 1; 11208 uint64_t reserved_50_51 : 2; 11209 uint64_t lmc0 : 1; 11210 uint64_t reserved_53_62 : 10; 11211 uint64_t rst : 1; 11212#endif 11213 } cn61xx; 11214 struct cvmx_ciu_sum1_iox_int_cn66xx { 11215#ifdef __BIG_ENDIAN_BITFIELD 11216 uint64_t rst : 1; /**< MIO RST interrupt 11217 See MIO_RST_INT */ 11218 uint64_t reserved_62_62 : 1; 11219 uint64_t srio3 : 1; /**< SRIO3 interrupt 11220 See SRIO3_INT_REG, SRIO3_INT2_REG */ 11221 uint64_t srio2 : 1; /**< SRIO2 interrupt 11222 See SRIO2_INT_REG, SRIO2_INT2_REG */ 11223 uint64_t reserved_57_59 : 3; 11224 uint64_t dfm : 1; /**< DFM Interrupt 11225 See DFM_FNT_STAT */ 11226 uint64_t reserved_53_55 : 3; 11227 uint64_t lmc0 : 1; /**< LMC0 interrupt 11228 See LMC0_INT */ 11229 uint64_t reserved_51_51 : 1; 11230 uint64_t srio0 : 1; /**< SRIO0 interrupt 11231 See SRIO0_INT_REG, SRIO0_INT2_REG */ 11232 uint64_t pem1 : 1; /**< PEM1 interrupt 11233 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11234 uint64_t pem0 : 1; /**< PEM0 interrupt 11235 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11236 uint64_t ptp : 1; /**< PTP interrupt 11237 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11238 uint64_t agl : 1; /**< AGL interrupt 11239 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11240 uint64_t reserved_38_45 : 8; 11241 uint64_t agx1 : 1; /**< GMX1 interrupt 11242 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11243 PCS1_INT*_REG, PCSX1_INT_REG */ 11244 uint64_t agx0 : 1; /**< GMX0 interrupt 11245 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11246 PCS0_INT*_REG, PCSX0_INT_REG */ 11247 uint64_t dpi : 1; /**< DPI interrupt 11248 See DPI_INT_REG */ 11249 uint64_t sli : 1; /**< SLI interrupt 11250 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11251 uint64_t usb : 1; /**< USB UCTL0 interrupt 11252 See UCTL0_INT_REG */ 11253 uint64_t dfa : 1; /**< DFA interrupt 11254 See DFA_ERROR */ 11255 uint64_t key : 1; /**< KEY interrupt 11256 See KEY_INT_SUM */ 11257 uint64_t rad : 1; /**< RAD interrupt 11258 See RAD_REG_ERROR */ 11259 uint64_t tim : 1; /**< TIM interrupt 11260 See TIM_REG_ERROR */ 11261 uint64_t zip : 1; /**< ZIP interrupt 11262 See ZIP_ERROR */ 11263 uint64_t pko : 1; /**< PKO interrupt 11264 See PKO_REG_ERROR */ 11265 uint64_t pip : 1; /**< PIP interrupt 11266 See PIP_INT_REG */ 11267 uint64_t ipd : 1; /**< IPD interrupt 11268 See IPD_INT_SUM */ 11269 uint64_t l2c : 1; /**< L2C interrupt 11270 See L2C_INT_REG */ 11271 uint64_t pow : 1; /**< POW err interrupt 11272 See POW_ECC_ERR */ 11273 uint64_t fpa : 1; /**< FPA interrupt 11274 See FPA_INT_SUM */ 11275 uint64_t iob : 1; /**< IOB interrupt 11276 See IOB_INT_SUM */ 11277 uint64_t mio : 1; /**< MIO boot interrupt 11278 See MIO_BOOT_ERR */ 11279 uint64_t nand : 1; /**< NAND Flash Controller interrupt 11280 See NDF_INT */ 11281 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 11282 See MIX1_ISR */ 11283 uint64_t reserved_10_17 : 8; 11284 uint64_t wdog : 10; /**< 10 watchdog interrupts */ 11285#else 11286 uint64_t wdog : 10; 11287 uint64_t reserved_10_17 : 8; 11288 uint64_t mii1 : 1; 11289 uint64_t nand : 1; 11290 uint64_t mio : 1; 11291 uint64_t iob : 1; 11292 uint64_t fpa : 1; 11293 uint64_t pow : 1; 11294 uint64_t l2c : 1; 11295 uint64_t ipd : 1; 11296 uint64_t pip : 1; 11297 uint64_t pko : 1; 11298 uint64_t zip : 1; 11299 uint64_t tim : 1; 11300 uint64_t rad : 1; 11301 uint64_t key : 1; 11302 uint64_t dfa : 1; 11303 uint64_t usb : 1; 11304 uint64_t sli : 1; 11305 uint64_t dpi : 1; 11306 uint64_t agx0 : 1; 11307 uint64_t agx1 : 1; 11308 uint64_t reserved_38_45 : 8; 11309 uint64_t agl : 1; 11310 uint64_t ptp : 1; 11311 uint64_t pem0 : 1; 11312 uint64_t pem1 : 1; 11313 uint64_t srio0 : 1; 11314 uint64_t reserved_51_51 : 1; 11315 uint64_t lmc0 : 1; 11316 uint64_t reserved_53_55 : 3; 11317 uint64_t dfm : 1; 11318 uint64_t reserved_57_59 : 3; 11319 uint64_t srio2 : 1; 11320 uint64_t srio3 : 1; 11321 uint64_t reserved_62_62 : 1; 11322 uint64_t rst : 1; 11323#endif 11324 } cn66xx; 11325 struct cvmx_ciu_sum1_iox_int_cnf71xx { 11326#ifdef __BIG_ENDIAN_BITFIELD 11327 uint64_t rst : 1; /**< MIO RST interrupt 11328 See MIO_RST_INT */ 11329 uint64_t reserved_53_62 : 10; 11330 uint64_t lmc0 : 1; /**< LMC0 interrupt 11331 See LMC0_INT */ 11332 uint64_t reserved_50_51 : 2; 11333 uint64_t pem1 : 1; /**< PEM1 interrupt 11334 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11335 uint64_t pem0 : 1; /**< PEM0 interrupt 11336 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11337 uint64_t ptp : 1; /**< PTP interrupt 11338 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11339 uint64_t reserved_41_46 : 6; 11340 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11341 TBD, See DPI DMA instruction completion */ 11342 uint64_t reserved_37_39 : 3; 11343 uint64_t agx0 : 1; /**< GMX0 interrupt 11344 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11345 PCS0_INT*_REG, PCSX0_INT_REG */ 11346 uint64_t dpi : 1; /**< DPI interrupt 11347 See DPI_INT_REG */ 11348 uint64_t sli : 1; /**< SLI interrupt 11349 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11350 uint64_t usb : 1; /**< USB UCTL0 interrupt 11351 See UCTL0_INT_REG */ 11352 uint64_t reserved_32_32 : 1; 11353 uint64_t key : 1; /**< KEY interrupt 11354 See KEY_INT_SUM */ 11355 uint64_t rad : 1; /**< RAD interrupt 11356 See RAD_REG_ERROR */ 11357 uint64_t tim : 1; /**< TIM interrupt 11358 See TIM_REG_ERROR */ 11359 uint64_t reserved_28_28 : 1; 11360 uint64_t pko : 1; /**< PKO interrupt 11361 See PKO_REG_ERROR */ 11362 uint64_t pip : 1; /**< PIP interrupt 11363 See PIP_INT_REG */ 11364 uint64_t ipd : 1; /**< IPD interrupt 11365 See IPD_INT_SUM */ 11366 uint64_t l2c : 1; /**< L2C interrupt 11367 See L2C_INT_REG */ 11368 uint64_t pow : 1; /**< POW err interrupt 11369 See POW_ECC_ERR */ 11370 uint64_t fpa : 1; /**< FPA interrupt 11371 See FPA_INT_SUM */ 11372 uint64_t iob : 1; /**< IOB interrupt 11373 See IOB_INT_SUM */ 11374 uint64_t mio : 1; /**< MIO boot interrupt 11375 See MIO_BOOT_ERR */ 11376 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11377 See EMMC interrupt */ 11378 uint64_t reserved_4_18 : 15; 11379 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 11380#else 11381 uint64_t wdog : 4; 11382 uint64_t reserved_4_18 : 15; 11383 uint64_t nand : 1; 11384 uint64_t mio : 1; 11385 uint64_t iob : 1; 11386 uint64_t fpa : 1; 11387 uint64_t pow : 1; 11388 uint64_t l2c : 1; 11389 uint64_t ipd : 1; 11390 uint64_t pip : 1; 11391 uint64_t pko : 1; 11392 uint64_t reserved_28_28 : 1; 11393 uint64_t tim : 1; 11394 uint64_t rad : 1; 11395 uint64_t key : 1; 11396 uint64_t reserved_32_32 : 1; 11397 uint64_t usb : 1; 11398 uint64_t sli : 1; 11399 uint64_t dpi : 1; 11400 uint64_t agx0 : 1; 11401 uint64_t reserved_37_39 : 3; 11402 uint64_t dpi_dma : 1; 11403 uint64_t reserved_41_46 : 6; 11404 uint64_t ptp : 1; 11405 uint64_t pem0 : 1; 11406 uint64_t pem1 : 1; 11407 uint64_t reserved_50_51 : 2; 11408 uint64_t lmc0 : 1; 11409 uint64_t reserved_53_62 : 10; 11410 uint64_t rst : 1; 11411#endif 11412 } cnf71xx; 11413}; 11414typedef union cvmx_ciu_sum1_iox_int cvmx_ciu_sum1_iox_int_t; 11415 11416/** 11417 * cvmx_ciu_sum1_pp#_ip2 11418 * 11419 * Notes: 11420 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have 11421 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always 11422 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for 11423 * different PPs, same value as $CIU_INT_SUM1. 11424 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field. 11425 */ 11426union cvmx_ciu_sum1_ppx_ip2 { 11427 uint64_t u64; 11428 struct cvmx_ciu_sum1_ppx_ip2_s { 11429#ifdef __BIG_ENDIAN_BITFIELD 11430 uint64_t rst : 1; /**< MIO RST interrupt 11431 See MIO_RST_INT */ 11432 uint64_t reserved_62_62 : 1; 11433 uint64_t srio3 : 1; /**< SRIO3 interrupt 11434 See SRIO3_INT_REG, SRIO3_INT2_REG */ 11435 uint64_t srio2 : 1; /**< SRIO2 interrupt 11436 See SRIO2_INT_REG, SRIO2_INT2_REG */ 11437 uint64_t reserved_57_59 : 3; 11438 uint64_t dfm : 1; /**< DFM Interrupt 11439 See DFM_FNT_STAT */ 11440 uint64_t reserved_53_55 : 3; 11441 uint64_t lmc0 : 1; /**< LMC0 interrupt 11442 See LMC0_INT */ 11443 uint64_t reserved_51_51 : 1; 11444 uint64_t srio0 : 1; /**< SRIO0 interrupt 11445 See SRIO0_INT_REG, SRIO0_INT2_REG */ 11446 uint64_t pem1 : 1; /**< PEM1 interrupt 11447 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11448 uint64_t pem0 : 1; /**< PEM0 interrupt 11449 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11450 uint64_t ptp : 1; /**< PTP interrupt 11451 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11452 uint64_t agl : 1; /**< AGL interrupt 11453 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11454 uint64_t reserved_41_45 : 5; 11455 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11456 TBD, See DPI DMA instruction completion */ 11457 uint64_t reserved_38_39 : 2; 11458 uint64_t agx1 : 1; /**< GMX1 interrupt 11459 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11460 PCS1_INT*_REG, PCSX1_INT_REG */ 11461 uint64_t agx0 : 1; /**< GMX0 interrupt 11462 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11463 PCS0_INT*_REG, PCSX0_INT_REG */ 11464 uint64_t dpi : 1; /**< DPI interrupt 11465 See DPI_INT_REG */ 11466 uint64_t sli : 1; /**< SLI interrupt 11467 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11468 uint64_t usb : 1; /**< USB UCTL0 interrupt 11469 See UCTL0_INT_REG */ 11470 uint64_t dfa : 1; /**< DFA interrupt 11471 See DFA_ERROR */ 11472 uint64_t key : 1; /**< KEY interrupt 11473 See KEY_INT_SUM */ 11474 uint64_t rad : 1; /**< RAD interrupt 11475 See RAD_REG_ERROR */ 11476 uint64_t tim : 1; /**< TIM interrupt 11477 See TIM_REG_ERROR */ 11478 uint64_t zip : 1; /**< ZIP interrupt 11479 See ZIP_ERROR */ 11480 uint64_t pko : 1; /**< PKO interrupt 11481 See PKO_REG_ERROR */ 11482 uint64_t pip : 1; /**< PIP interrupt 11483 See PIP_INT_REG */ 11484 uint64_t ipd : 1; /**< IPD interrupt 11485 See IPD_INT_SUM */ 11486 uint64_t l2c : 1; /**< L2C interrupt 11487 See L2C_INT_REG */ 11488 uint64_t pow : 1; /**< POW err interrupt 11489 See POW_ECC_ERR */ 11490 uint64_t fpa : 1; /**< FPA interrupt 11491 See FPA_INT_SUM */ 11492 uint64_t iob : 1; /**< IOB interrupt 11493 See IOB_INT_SUM */ 11494 uint64_t mio : 1; /**< MIO boot interrupt 11495 See MIO_BOOT_ERR */ 11496 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11497 See EMMC interrupt */ 11498 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 11499 See MIX1_ISR */ 11500 uint64_t reserved_10_17 : 8; 11501 uint64_t wdog : 10; /**< Per PP watchdog interrupts */ 11502#else 11503 uint64_t wdog : 10; 11504 uint64_t reserved_10_17 : 8; 11505 uint64_t mii1 : 1; 11506 uint64_t nand : 1; 11507 uint64_t mio : 1; 11508 uint64_t iob : 1; 11509 uint64_t fpa : 1; 11510 uint64_t pow : 1; 11511 uint64_t l2c : 1; 11512 uint64_t ipd : 1; 11513 uint64_t pip : 1; 11514 uint64_t pko : 1; 11515 uint64_t zip : 1; 11516 uint64_t tim : 1; 11517 uint64_t rad : 1; 11518 uint64_t key : 1; 11519 uint64_t dfa : 1; 11520 uint64_t usb : 1; 11521 uint64_t sli : 1; 11522 uint64_t dpi : 1; 11523 uint64_t agx0 : 1; 11524 uint64_t agx1 : 1; 11525 uint64_t reserved_38_39 : 2; 11526 uint64_t dpi_dma : 1; 11527 uint64_t reserved_41_45 : 5; 11528 uint64_t agl : 1; 11529 uint64_t ptp : 1; 11530 uint64_t pem0 : 1; 11531 uint64_t pem1 : 1; 11532 uint64_t srio0 : 1; 11533 uint64_t reserved_51_51 : 1; 11534 uint64_t lmc0 : 1; 11535 uint64_t reserved_53_55 : 3; 11536 uint64_t dfm : 1; 11537 uint64_t reserved_57_59 : 3; 11538 uint64_t srio2 : 1; 11539 uint64_t srio3 : 1; 11540 uint64_t reserved_62_62 : 1; 11541 uint64_t rst : 1; 11542#endif 11543 } s; 11544 struct cvmx_ciu_sum1_ppx_ip2_cn61xx { 11545#ifdef __BIG_ENDIAN_BITFIELD 11546 uint64_t rst : 1; /**< MIO RST interrupt 11547 See MIO_RST_INT */ 11548 uint64_t reserved_53_62 : 10; 11549 uint64_t lmc0 : 1; /**< LMC0 interrupt 11550 See LMC0_INT */ 11551 uint64_t reserved_50_51 : 2; 11552 uint64_t pem1 : 1; /**< PEM1 interrupt 11553 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11554 uint64_t pem0 : 1; /**< PEM0 interrupt 11555 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11556 uint64_t ptp : 1; /**< PTP interrupt 11557 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11558 uint64_t agl : 1; /**< AGL interrupt 11559 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11560 uint64_t reserved_41_45 : 5; 11561 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11562 TBD, See DPI DMA instruction completion */ 11563 uint64_t reserved_38_39 : 2; 11564 uint64_t agx1 : 1; /**< GMX1 interrupt 11565 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11566 PCS1_INT*_REG, PCSX1_INT_REG */ 11567 uint64_t agx0 : 1; /**< GMX0 interrupt 11568 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11569 PCS0_INT*_REG, PCSX0_INT_REG */ 11570 uint64_t dpi : 1; /**< DPI interrupt 11571 See DPI_INT_REG */ 11572 uint64_t sli : 1; /**< SLI interrupt 11573 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11574 uint64_t usb : 1; /**< USB UCTL0 interrupt 11575 See UCTL0_INT_REG */ 11576 uint64_t dfa : 1; /**< DFA interrupt 11577 See DFA_ERROR */ 11578 uint64_t key : 1; /**< KEY interrupt 11579 See KEY_INT_SUM */ 11580 uint64_t rad : 1; /**< RAD interrupt 11581 See RAD_REG_ERROR */ 11582 uint64_t tim : 1; /**< TIM interrupt 11583 See TIM_REG_ERROR */ 11584 uint64_t zip : 1; /**< ZIP interrupt 11585 See ZIP_ERROR */ 11586 uint64_t pko : 1; /**< PKO interrupt 11587 See PKO_REG_ERROR */ 11588 uint64_t pip : 1; /**< PIP interrupt 11589 See PIP_INT_REG */ 11590 uint64_t ipd : 1; /**< IPD interrupt 11591 See IPD_INT_SUM */ 11592 uint64_t l2c : 1; /**< L2C interrupt 11593 See L2C_INT_REG */ 11594 uint64_t pow : 1; /**< POW err interrupt 11595 See POW_ECC_ERR */ 11596 uint64_t fpa : 1; /**< FPA interrupt 11597 See FPA_INT_SUM */ 11598 uint64_t iob : 1; /**< IOB interrupt 11599 See IOB_INT_SUM */ 11600 uint64_t mio : 1; /**< MIO boot interrupt 11601 See MIO_BOOT_ERR */ 11602 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11603 See EMMC interrupt */ 11604 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt 11605 See MIX1_ISR */ 11606 uint64_t reserved_4_17 : 14; 11607 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 11608#else 11609 uint64_t wdog : 4; 11610 uint64_t reserved_4_17 : 14; 11611 uint64_t mii1 : 1; 11612 uint64_t nand : 1; 11613 uint64_t mio : 1; 11614 uint64_t iob : 1; 11615 uint64_t fpa : 1; 11616 uint64_t pow : 1; 11617 uint64_t l2c : 1; 11618 uint64_t ipd : 1; 11619 uint64_t pip : 1; 11620 uint64_t pko : 1; 11621 uint64_t zip : 1; 11622 uint64_t tim : 1; 11623 uint64_t rad : 1; 11624 uint64_t key : 1; 11625 uint64_t dfa : 1; 11626 uint64_t usb : 1; 11627 uint64_t sli : 1; 11628 uint64_t dpi : 1; 11629 uint64_t agx0 : 1; 11630 uint64_t agx1 : 1; 11631 uint64_t reserved_38_39 : 2; 11632 uint64_t dpi_dma : 1; 11633 uint64_t reserved_41_45 : 5; 11634 uint64_t agl : 1; 11635 uint64_t ptp : 1; 11636 uint64_t pem0 : 1; 11637 uint64_t pem1 : 1; 11638 uint64_t reserved_50_51 : 2; 11639 uint64_t lmc0 : 1; 11640 uint64_t reserved_53_62 : 10; 11641 uint64_t rst : 1; 11642#endif 11643 } cn61xx; 11644 struct cvmx_ciu_sum1_ppx_ip2_cn66xx { 11645#ifdef __BIG_ENDIAN_BITFIELD 11646 uint64_t rst : 1; /**< MIO RST interrupt 11647 See MIO_RST_INT */ 11648 uint64_t reserved_62_62 : 1; 11649 uint64_t srio3 : 1; /**< SRIO3 interrupt 11650 See SRIO3_INT_REG, SRIO3_INT2_REG */ 11651 uint64_t srio2 : 1; /**< SRIO2 interrupt 11652 See SRIO2_INT_REG, SRIO2_INT2_REG */ 11653 uint64_t reserved_57_59 : 3; 11654 uint64_t dfm : 1; /**< DFM Interrupt 11655 See DFM_FNT_STAT */ 11656 uint64_t reserved_53_55 : 3; 11657 uint64_t lmc0 : 1; /**< LMC0 interrupt 11658 See LMC0_INT */ 11659 uint64_t reserved_51_51 : 1; 11660 uint64_t srio0 : 1; /**< SRIO0 interrupt 11661 See SRIO0_INT_REG, SRIO0_INT2_REG */ 11662 uint64_t pem1 : 1; /**< PEM1 interrupt 11663 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11664 uint64_t pem0 : 1; /**< PEM0 interrupt 11665 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11666 uint64_t ptp : 1; /**< PTP interrupt 11667 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11668 uint64_t agl : 1; /**< AGL interrupt 11669 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11670 uint64_t reserved_38_45 : 8; 11671 uint64_t agx1 : 1; /**< GMX1 interrupt 11672 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11673 PCS1_INT*_REG, PCSX1_INT_REG */ 11674 uint64_t agx0 : 1; /**< GMX0 interrupt 11675 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11676 PCS0_INT*_REG, PCSX0_INT_REG */ 11677 uint64_t dpi : 1; /**< DPI interrupt 11678 See DPI_INT_REG */ 11679 uint64_t sli : 1; /**< SLI interrupt 11680 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11681 uint64_t usb : 1; /**< USB UCTL0 interrupt 11682 See UCTL0_INT_REG */ 11683 uint64_t dfa : 1; /**< DFA interrupt 11684 See DFA_ERROR */ 11685 uint64_t key : 1; /**< KEY interrupt 11686 See KEY_INT_SUM */ 11687 uint64_t rad : 1; /**< RAD interrupt 11688 See RAD_REG_ERROR */ 11689 uint64_t tim : 1; /**< TIM interrupt 11690 See TIM_REG_ERROR */ 11691 uint64_t zip : 1; /**< ZIP interrupt 11692 See ZIP_ERROR */ 11693 uint64_t pko : 1; /**< PKO interrupt 11694 See PKO_REG_ERROR */ 11695 uint64_t pip : 1; /**< PIP interrupt 11696 See PIP_INT_REG */ 11697 uint64_t ipd : 1; /**< IPD interrupt 11698 See IPD_INT_SUM */ 11699 uint64_t l2c : 1; /**< L2C interrupt 11700 See L2C_INT_REG */ 11701 uint64_t pow : 1; /**< POW err interrupt 11702 See POW_ECC_ERR */ 11703 uint64_t fpa : 1; /**< FPA interrupt 11704 See FPA_INT_SUM */ 11705 uint64_t iob : 1; /**< IOB interrupt 11706 See IOB_INT_SUM */ 11707 uint64_t mio : 1; /**< MIO boot interrupt 11708 See MIO_BOOT_ERR */ 11709 uint64_t nand : 1; /**< NAND Flash Controller interrupt 11710 See NDF_INT */ 11711 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 11712 See MIX1_ISR */ 11713 uint64_t reserved_10_17 : 8; 11714 uint64_t wdog : 10; /**< 10 watchdog interrupts */ 11715#else 11716 uint64_t wdog : 10; 11717 uint64_t reserved_10_17 : 8; 11718 uint64_t mii1 : 1; 11719 uint64_t nand : 1; 11720 uint64_t mio : 1; 11721 uint64_t iob : 1; 11722 uint64_t fpa : 1; 11723 uint64_t pow : 1; 11724 uint64_t l2c : 1; 11725 uint64_t ipd : 1; 11726 uint64_t pip : 1; 11727 uint64_t pko : 1; 11728 uint64_t zip : 1; 11729 uint64_t tim : 1; 11730 uint64_t rad : 1; 11731 uint64_t key : 1; 11732 uint64_t dfa : 1; 11733 uint64_t usb : 1; 11734 uint64_t sli : 1; 11735 uint64_t dpi : 1; 11736 uint64_t agx0 : 1; 11737 uint64_t agx1 : 1; 11738 uint64_t reserved_38_45 : 8; 11739 uint64_t agl : 1; 11740 uint64_t ptp : 1; 11741 uint64_t pem0 : 1; 11742 uint64_t pem1 : 1; 11743 uint64_t srio0 : 1; 11744 uint64_t reserved_51_51 : 1; 11745 uint64_t lmc0 : 1; 11746 uint64_t reserved_53_55 : 3; 11747 uint64_t dfm : 1; 11748 uint64_t reserved_57_59 : 3; 11749 uint64_t srio2 : 1; 11750 uint64_t srio3 : 1; 11751 uint64_t reserved_62_62 : 1; 11752 uint64_t rst : 1; 11753#endif 11754 } cn66xx; 11755 struct cvmx_ciu_sum1_ppx_ip2_cnf71xx { 11756#ifdef __BIG_ENDIAN_BITFIELD 11757 uint64_t rst : 1; /**< MIO RST interrupt 11758 See MIO_RST_INT */ 11759 uint64_t reserved_53_62 : 10; 11760 uint64_t lmc0 : 1; /**< LMC0 interrupt 11761 See LMC0_INT */ 11762 uint64_t reserved_50_51 : 2; 11763 uint64_t pem1 : 1; /**< PEM1 interrupt 11764 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11765 uint64_t pem0 : 1; /**< PEM0 interrupt 11766 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11767 uint64_t ptp : 1; /**< PTP interrupt 11768 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11769 uint64_t reserved_41_46 : 6; 11770 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11771 TBD, See DPI DMA instruction completion */ 11772 uint64_t reserved_37_39 : 3; 11773 uint64_t agx0 : 1; /**< GMX0 interrupt 11774 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11775 PCS0_INT*_REG, PCSX0_INT_REG */ 11776 uint64_t dpi : 1; /**< DPI interrupt 11777 See DPI_INT_REG */ 11778 uint64_t sli : 1; /**< SLI interrupt 11779 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11780 uint64_t usb : 1; /**< USB UCTL0 interrupt 11781 See UCTL0_INT_REG */ 11782 uint64_t reserved_32_32 : 1; 11783 uint64_t key : 1; /**< KEY interrupt 11784 See KEY_INT_SUM */ 11785 uint64_t rad : 1; /**< RAD interrupt 11786 See RAD_REG_ERROR */ 11787 uint64_t tim : 1; /**< TIM interrupt 11788 See TIM_REG_ERROR */ 11789 uint64_t reserved_28_28 : 1; 11790 uint64_t pko : 1; /**< PKO interrupt 11791 See PKO_REG_ERROR */ 11792 uint64_t pip : 1; /**< PIP interrupt 11793 See PIP_INT_REG */ 11794 uint64_t ipd : 1; /**< IPD interrupt 11795 See IPD_INT_SUM */ 11796 uint64_t l2c : 1; /**< L2C interrupt 11797 See L2C_INT_REG */ 11798 uint64_t pow : 1; /**< POW err interrupt 11799 See POW_ECC_ERR */ 11800 uint64_t fpa : 1; /**< FPA interrupt 11801 See FPA_INT_SUM */ 11802 uint64_t iob : 1; /**< IOB interrupt 11803 See IOB_INT_SUM */ 11804 uint64_t mio : 1; /**< MIO boot interrupt 11805 See MIO_BOOT_ERR */ 11806 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11807 See EMMC interrupt */ 11808 uint64_t reserved_4_18 : 15; 11809 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 11810#else 11811 uint64_t wdog : 4; 11812 uint64_t reserved_4_18 : 15; 11813 uint64_t nand : 1; 11814 uint64_t mio : 1; 11815 uint64_t iob : 1; 11816 uint64_t fpa : 1; 11817 uint64_t pow : 1; 11818 uint64_t l2c : 1; 11819 uint64_t ipd : 1; 11820 uint64_t pip : 1; 11821 uint64_t pko : 1; 11822 uint64_t reserved_28_28 : 1; 11823 uint64_t tim : 1; 11824 uint64_t rad : 1; 11825 uint64_t key : 1; 11826 uint64_t reserved_32_32 : 1; 11827 uint64_t usb : 1; 11828 uint64_t sli : 1; 11829 uint64_t dpi : 1; 11830 uint64_t agx0 : 1; 11831 uint64_t reserved_37_39 : 3; 11832 uint64_t dpi_dma : 1; 11833 uint64_t reserved_41_46 : 6; 11834 uint64_t ptp : 1; 11835 uint64_t pem0 : 1; 11836 uint64_t pem1 : 1; 11837 uint64_t reserved_50_51 : 2; 11838 uint64_t lmc0 : 1; 11839 uint64_t reserved_53_62 : 10; 11840 uint64_t rst : 1; 11841#endif 11842 } cnf71xx; 11843}; 11844typedef union cvmx_ciu_sum1_ppx_ip2 cvmx_ciu_sum1_ppx_ip2_t; 11845 11846/** 11847 * cvmx_ciu_sum1_pp#_ip3 11848 * 11849 * Notes: 11850 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have 11851 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always 11852 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for 11853 * different PPs, same value as $CIU_INT_SUM1. 11854 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field. 11855 */ 11856union cvmx_ciu_sum1_ppx_ip3 { 11857 uint64_t u64; 11858 struct cvmx_ciu_sum1_ppx_ip3_s { 11859#ifdef __BIG_ENDIAN_BITFIELD 11860 uint64_t rst : 1; /**< MIO RST interrupt 11861 See MIO_RST_INT */ 11862 uint64_t reserved_62_62 : 1; 11863 uint64_t srio3 : 1; /**< SRIO3 interrupt 11864 See SRIO3_INT_REG, SRIO3_INT2_REG */ 11865 uint64_t srio2 : 1; /**< SRIO2 interrupt 11866 See SRIO2_INT_REG, SRIO2_INT2_REG */ 11867 uint64_t reserved_57_59 : 3; 11868 uint64_t dfm : 1; /**< DFM Interrupt 11869 See DFM_FNT_STAT */ 11870 uint64_t reserved_53_55 : 3; 11871 uint64_t lmc0 : 1; /**< LMC0 interrupt 11872 See LMC0_INT */ 11873 uint64_t reserved_51_51 : 1; 11874 uint64_t srio0 : 1; /**< SRIO0 interrupt 11875 See SRIO0_INT_REG, SRIO0_INT2_REG */ 11876 uint64_t pem1 : 1; /**< PEM1 interrupt 11877 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11878 uint64_t pem0 : 1; /**< PEM0 interrupt 11879 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11880 uint64_t ptp : 1; /**< PTP interrupt 11881 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11882 uint64_t agl : 1; /**< AGL interrupt 11883 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11884 uint64_t reserved_41_45 : 5; 11885 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11886 TBD, See DPI DMA instruction completion */ 11887 uint64_t reserved_38_39 : 2; 11888 uint64_t agx1 : 1; /**< GMX1 interrupt 11889 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11890 PCS1_INT*_REG, PCSX1_INT_REG */ 11891 uint64_t agx0 : 1; /**< GMX0 interrupt 11892 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11893 PCS0_INT*_REG, PCSX0_INT_REG */ 11894 uint64_t dpi : 1; /**< DPI interrupt 11895 See DPI_INT_REG */ 11896 uint64_t sli : 1; /**< SLI interrupt 11897 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 11898 uint64_t usb : 1; /**< USB UCTL0 interrupt 11899 See UCTL0_INT_REG */ 11900 uint64_t dfa : 1; /**< DFA interrupt 11901 See DFA_ERROR */ 11902 uint64_t key : 1; /**< KEY interrupt 11903 See KEY_INT_SUM */ 11904 uint64_t rad : 1; /**< RAD interrupt 11905 See RAD_REG_ERROR */ 11906 uint64_t tim : 1; /**< TIM interrupt 11907 See TIM_REG_ERROR */ 11908 uint64_t zip : 1; /**< ZIP interrupt 11909 See ZIP_ERROR */ 11910 uint64_t pko : 1; /**< PKO interrupt 11911 See PKO_REG_ERROR */ 11912 uint64_t pip : 1; /**< PIP interrupt 11913 See PIP_INT_REG */ 11914 uint64_t ipd : 1; /**< IPD interrupt 11915 See IPD_INT_SUM */ 11916 uint64_t l2c : 1; /**< L2C interrupt 11917 See L2C_INT_REG */ 11918 uint64_t pow : 1; /**< POW err interrupt 11919 See POW_ECC_ERR */ 11920 uint64_t fpa : 1; /**< FPA interrupt 11921 See FPA_INT_SUM */ 11922 uint64_t iob : 1; /**< IOB interrupt 11923 See IOB_INT_SUM */ 11924 uint64_t mio : 1; /**< MIO boot interrupt 11925 See MIO_BOOT_ERR */ 11926 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 11927 See EMMC interrupt */ 11928 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 11929 See MIX1_ISR */ 11930 uint64_t reserved_10_17 : 8; 11931 uint64_t wdog : 10; /**< Per PP watchdog interrupts */ 11932#else 11933 uint64_t wdog : 10; 11934 uint64_t reserved_10_17 : 8; 11935 uint64_t mii1 : 1; 11936 uint64_t nand : 1; 11937 uint64_t mio : 1; 11938 uint64_t iob : 1; 11939 uint64_t fpa : 1; 11940 uint64_t pow : 1; 11941 uint64_t l2c : 1; 11942 uint64_t ipd : 1; 11943 uint64_t pip : 1; 11944 uint64_t pko : 1; 11945 uint64_t zip : 1; 11946 uint64_t tim : 1; 11947 uint64_t rad : 1; 11948 uint64_t key : 1; 11949 uint64_t dfa : 1; 11950 uint64_t usb : 1; 11951 uint64_t sli : 1; 11952 uint64_t dpi : 1; 11953 uint64_t agx0 : 1; 11954 uint64_t agx1 : 1; 11955 uint64_t reserved_38_39 : 2; 11956 uint64_t dpi_dma : 1; 11957 uint64_t reserved_41_45 : 5; 11958 uint64_t agl : 1; 11959 uint64_t ptp : 1; 11960 uint64_t pem0 : 1; 11961 uint64_t pem1 : 1; 11962 uint64_t srio0 : 1; 11963 uint64_t reserved_51_51 : 1; 11964 uint64_t lmc0 : 1; 11965 uint64_t reserved_53_55 : 3; 11966 uint64_t dfm : 1; 11967 uint64_t reserved_57_59 : 3; 11968 uint64_t srio2 : 1; 11969 uint64_t srio3 : 1; 11970 uint64_t reserved_62_62 : 1; 11971 uint64_t rst : 1; 11972#endif 11973 } s; 11974 struct cvmx_ciu_sum1_ppx_ip3_cn61xx { 11975#ifdef __BIG_ENDIAN_BITFIELD 11976 uint64_t rst : 1; /**< MIO RST interrupt 11977 See MIO_RST_INT */ 11978 uint64_t reserved_53_62 : 10; 11979 uint64_t lmc0 : 1; /**< LMC0 interrupt 11980 See LMC0_INT */ 11981 uint64_t reserved_50_51 : 2; 11982 uint64_t pem1 : 1; /**< PEM1 interrupt 11983 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 11984 uint64_t pem0 : 1; /**< PEM0 interrupt 11985 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 11986 uint64_t ptp : 1; /**< PTP interrupt 11987 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 11988 uint64_t agl : 1; /**< AGL interrupt 11989 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 11990 uint64_t reserved_41_45 : 5; 11991 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 11992 TBD, See DPI DMA instruction completion */ 11993 uint64_t reserved_38_39 : 2; 11994 uint64_t agx1 : 1; /**< GMX1 interrupt 11995 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 11996 PCS1_INT*_REG, PCSX1_INT_REG */ 11997 uint64_t agx0 : 1; /**< GMX0 interrupt 11998 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 11999 PCS0_INT*_REG, PCSX0_INT_REG */ 12000 uint64_t dpi : 1; /**< DPI interrupt 12001 See DPI_INT_REG */ 12002 uint64_t sli : 1; /**< SLI interrupt 12003 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12004 uint64_t usb : 1; /**< USB UCTL0 interrupt 12005 See UCTL0_INT_REG */ 12006 uint64_t dfa : 1; /**< DFA interrupt 12007 See DFA_ERROR */ 12008 uint64_t key : 1; /**< KEY interrupt 12009 See KEY_INT_SUM */ 12010 uint64_t rad : 1; /**< RAD interrupt 12011 See RAD_REG_ERROR */ 12012 uint64_t tim : 1; /**< TIM interrupt 12013 See TIM_REG_ERROR */ 12014 uint64_t zip : 1; /**< ZIP interrupt 12015 See ZIP_ERROR */ 12016 uint64_t pko : 1; /**< PKO interrupt 12017 See PKO_REG_ERROR */ 12018 uint64_t pip : 1; /**< PIP interrupt 12019 See PIP_INT_REG */ 12020 uint64_t ipd : 1; /**< IPD interrupt 12021 See IPD_INT_SUM */ 12022 uint64_t l2c : 1; /**< L2C interrupt 12023 See L2C_INT_REG */ 12024 uint64_t pow : 1; /**< POW err interrupt 12025 See POW_ECC_ERR */ 12026 uint64_t fpa : 1; /**< FPA interrupt 12027 See FPA_INT_SUM */ 12028 uint64_t iob : 1; /**< IOB interrupt 12029 See IOB_INT_SUM */ 12030 uint64_t mio : 1; /**< MIO boot interrupt 12031 See MIO_BOOT_ERR */ 12032 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 12033 See EMMC interrupt */ 12034 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt 12035 See MIX1_ISR */ 12036 uint64_t reserved_4_17 : 14; 12037 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 12038#else 12039 uint64_t wdog : 4; 12040 uint64_t reserved_4_17 : 14; 12041 uint64_t mii1 : 1; 12042 uint64_t nand : 1; 12043 uint64_t mio : 1; 12044 uint64_t iob : 1; 12045 uint64_t fpa : 1; 12046 uint64_t pow : 1; 12047 uint64_t l2c : 1; 12048 uint64_t ipd : 1; 12049 uint64_t pip : 1; 12050 uint64_t pko : 1; 12051 uint64_t zip : 1; 12052 uint64_t tim : 1; 12053 uint64_t rad : 1; 12054 uint64_t key : 1; 12055 uint64_t dfa : 1; 12056 uint64_t usb : 1; 12057 uint64_t sli : 1; 12058 uint64_t dpi : 1; 12059 uint64_t agx0 : 1; 12060 uint64_t agx1 : 1; 12061 uint64_t reserved_38_39 : 2; 12062 uint64_t dpi_dma : 1; 12063 uint64_t reserved_41_45 : 5; 12064 uint64_t agl : 1; 12065 uint64_t ptp : 1; 12066 uint64_t pem0 : 1; 12067 uint64_t pem1 : 1; 12068 uint64_t reserved_50_51 : 2; 12069 uint64_t lmc0 : 1; 12070 uint64_t reserved_53_62 : 10; 12071 uint64_t rst : 1; 12072#endif 12073 } cn61xx; 12074 struct cvmx_ciu_sum1_ppx_ip3_cn66xx { 12075#ifdef __BIG_ENDIAN_BITFIELD 12076 uint64_t rst : 1; /**< MIO RST interrupt 12077 See MIO_RST_INT */ 12078 uint64_t reserved_62_62 : 1; 12079 uint64_t srio3 : 1; /**< SRIO3 interrupt 12080 See SRIO3_INT_REG, SRIO3_INT2_REG */ 12081 uint64_t srio2 : 1; /**< SRIO2 interrupt 12082 See SRIO2_INT_REG, SRIO2_INT2_REG */ 12083 uint64_t reserved_57_59 : 3; 12084 uint64_t dfm : 1; /**< DFM Interrupt 12085 See DFM_FNT_STAT */ 12086 uint64_t reserved_53_55 : 3; 12087 uint64_t lmc0 : 1; /**< LMC0 interrupt 12088 See LMC0_INT */ 12089 uint64_t reserved_51_51 : 1; 12090 uint64_t srio0 : 1; /**< SRIO0 interrupt 12091 See SRIO0_INT_REG, SRIO0_INT2_REG */ 12092 uint64_t pem1 : 1; /**< PEM1 interrupt 12093 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12094 uint64_t pem0 : 1; /**< PEM0 interrupt 12095 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12096 uint64_t ptp : 1; /**< PTP interrupt 12097 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12098 uint64_t agl : 1; /**< AGL interrupt 12099 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 12100 uint64_t reserved_38_45 : 8; 12101 uint64_t agx1 : 1; /**< GMX1 interrupt 12102 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 12103 PCS1_INT*_REG, PCSX1_INT_REG */ 12104 uint64_t agx0 : 1; /**< GMX0 interrupt 12105 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12106 PCS0_INT*_REG, PCSX0_INT_REG */ 12107 uint64_t dpi : 1; /**< DPI interrupt 12108 See DPI_INT_REG */ 12109 uint64_t sli : 1; /**< SLI interrupt 12110 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12111 uint64_t usb : 1; /**< USB UCTL0 interrupt 12112 See UCTL0_INT_REG */ 12113 uint64_t dfa : 1; /**< DFA interrupt 12114 See DFA_ERROR */ 12115 uint64_t key : 1; /**< KEY interrupt 12116 See KEY_INT_SUM */ 12117 uint64_t rad : 1; /**< RAD interrupt 12118 See RAD_REG_ERROR */ 12119 uint64_t tim : 1; /**< TIM interrupt 12120 See TIM_REG_ERROR */ 12121 uint64_t zip : 1; /**< ZIP interrupt 12122 See ZIP_ERROR */ 12123 uint64_t pko : 1; /**< PKO interrupt 12124 See PKO_REG_ERROR */ 12125 uint64_t pip : 1; /**< PIP interrupt 12126 See PIP_INT_REG */ 12127 uint64_t ipd : 1; /**< IPD interrupt 12128 See IPD_INT_SUM */ 12129 uint64_t l2c : 1; /**< L2C interrupt 12130 See L2C_INT_REG */ 12131 uint64_t pow : 1; /**< POW err interrupt 12132 See POW_ECC_ERR */ 12133 uint64_t fpa : 1; /**< FPA interrupt 12134 See FPA_INT_SUM */ 12135 uint64_t iob : 1; /**< IOB interrupt 12136 See IOB_INT_SUM */ 12137 uint64_t mio : 1; /**< MIO boot interrupt 12138 See MIO_BOOT_ERR */ 12139 uint64_t nand : 1; /**< NAND Flash Controller interrupt 12140 See NDF_INT */ 12141 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 12142 See MIX1_ISR */ 12143 uint64_t reserved_10_17 : 8; 12144 uint64_t wdog : 10; /**< 10 watchdog interrupts */ 12145#else 12146 uint64_t wdog : 10; 12147 uint64_t reserved_10_17 : 8; 12148 uint64_t mii1 : 1; 12149 uint64_t nand : 1; 12150 uint64_t mio : 1; 12151 uint64_t iob : 1; 12152 uint64_t fpa : 1; 12153 uint64_t pow : 1; 12154 uint64_t l2c : 1; 12155 uint64_t ipd : 1; 12156 uint64_t pip : 1; 12157 uint64_t pko : 1; 12158 uint64_t zip : 1; 12159 uint64_t tim : 1; 12160 uint64_t rad : 1; 12161 uint64_t key : 1; 12162 uint64_t dfa : 1; 12163 uint64_t usb : 1; 12164 uint64_t sli : 1; 12165 uint64_t dpi : 1; 12166 uint64_t agx0 : 1; 12167 uint64_t agx1 : 1; 12168 uint64_t reserved_38_45 : 8; 12169 uint64_t agl : 1; 12170 uint64_t ptp : 1; 12171 uint64_t pem0 : 1; 12172 uint64_t pem1 : 1; 12173 uint64_t srio0 : 1; 12174 uint64_t reserved_51_51 : 1; 12175 uint64_t lmc0 : 1; 12176 uint64_t reserved_53_55 : 3; 12177 uint64_t dfm : 1; 12178 uint64_t reserved_57_59 : 3; 12179 uint64_t srio2 : 1; 12180 uint64_t srio3 : 1; 12181 uint64_t reserved_62_62 : 1; 12182 uint64_t rst : 1; 12183#endif 12184 } cn66xx; 12185 struct cvmx_ciu_sum1_ppx_ip3_cnf71xx { 12186#ifdef __BIG_ENDIAN_BITFIELD 12187 uint64_t rst : 1; /**< MIO RST interrupt 12188 See MIO_RST_INT */ 12189 uint64_t reserved_53_62 : 10; 12190 uint64_t lmc0 : 1; /**< LMC0 interrupt 12191 See LMC0_INT */ 12192 uint64_t reserved_50_51 : 2; 12193 uint64_t pem1 : 1; /**< PEM1 interrupt 12194 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12195 uint64_t pem0 : 1; /**< PEM0 interrupt 12196 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12197 uint64_t ptp : 1; /**< PTP interrupt 12198 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12199 uint64_t reserved_41_46 : 6; 12200 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 12201 TBD, See DPI DMA instruction completion */ 12202 uint64_t reserved_37_39 : 3; 12203 uint64_t agx0 : 1; /**< GMX0 interrupt 12204 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12205 PCS0_INT*_REG, PCSX0_INT_REG */ 12206 uint64_t dpi : 1; /**< DPI interrupt 12207 See DPI_INT_REG */ 12208 uint64_t sli : 1; /**< SLI interrupt 12209 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12210 uint64_t usb : 1; /**< USB UCTL0 interrupt 12211 See UCTL0_INT_REG */ 12212 uint64_t reserved_32_32 : 1; 12213 uint64_t key : 1; /**< KEY interrupt 12214 See KEY_INT_SUM */ 12215 uint64_t rad : 1; /**< RAD interrupt 12216 See RAD_REG_ERROR */ 12217 uint64_t tim : 1; /**< TIM interrupt 12218 See TIM_REG_ERROR */ 12219 uint64_t reserved_28_28 : 1; 12220 uint64_t pko : 1; /**< PKO interrupt 12221 See PKO_REG_ERROR */ 12222 uint64_t pip : 1; /**< PIP interrupt 12223 See PIP_INT_REG */ 12224 uint64_t ipd : 1; /**< IPD interrupt 12225 See IPD_INT_SUM */ 12226 uint64_t l2c : 1; /**< L2C interrupt 12227 See L2C_INT_REG */ 12228 uint64_t pow : 1; /**< POW err interrupt 12229 See POW_ECC_ERR */ 12230 uint64_t fpa : 1; /**< FPA interrupt 12231 See FPA_INT_SUM */ 12232 uint64_t iob : 1; /**< IOB interrupt 12233 See IOB_INT_SUM */ 12234 uint64_t mio : 1; /**< MIO boot interrupt 12235 See MIO_BOOT_ERR */ 12236 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 12237 See EMMC interrupt */ 12238 uint64_t reserved_4_18 : 15; 12239 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 12240#else 12241 uint64_t wdog : 4; 12242 uint64_t reserved_4_18 : 15; 12243 uint64_t nand : 1; 12244 uint64_t mio : 1; 12245 uint64_t iob : 1; 12246 uint64_t fpa : 1; 12247 uint64_t pow : 1; 12248 uint64_t l2c : 1; 12249 uint64_t ipd : 1; 12250 uint64_t pip : 1; 12251 uint64_t pko : 1; 12252 uint64_t reserved_28_28 : 1; 12253 uint64_t tim : 1; 12254 uint64_t rad : 1; 12255 uint64_t key : 1; 12256 uint64_t reserved_32_32 : 1; 12257 uint64_t usb : 1; 12258 uint64_t sli : 1; 12259 uint64_t dpi : 1; 12260 uint64_t agx0 : 1; 12261 uint64_t reserved_37_39 : 3; 12262 uint64_t dpi_dma : 1; 12263 uint64_t reserved_41_46 : 6; 12264 uint64_t ptp : 1; 12265 uint64_t pem0 : 1; 12266 uint64_t pem1 : 1; 12267 uint64_t reserved_50_51 : 2; 12268 uint64_t lmc0 : 1; 12269 uint64_t reserved_53_62 : 10; 12270 uint64_t rst : 1; 12271#endif 12272 } cnf71xx; 12273}; 12274typedef union cvmx_ciu_sum1_ppx_ip3 cvmx_ciu_sum1_ppx_ip3_t; 12275 12276/** 12277 * cvmx_ciu_sum1_pp#_ip4 12278 * 12279 * Notes: 12280 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have 12281 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always 12282 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for 12283 * different PPs, same value as $CIU_INT_SUM1. 12284 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field. 12285 */ 12286union cvmx_ciu_sum1_ppx_ip4 { 12287 uint64_t u64; 12288 struct cvmx_ciu_sum1_ppx_ip4_s { 12289#ifdef __BIG_ENDIAN_BITFIELD 12290 uint64_t rst : 1; /**< MIO RST interrupt 12291 See MIO_RST_INT */ 12292 uint64_t reserved_62_62 : 1; 12293 uint64_t srio3 : 1; /**< SRIO3 interrupt 12294 See SRIO3_INT_REG, SRIO3_INT2_REG */ 12295 uint64_t srio2 : 1; /**< SRIO2 interrupt 12296 See SRIO2_INT_REG, SRIO2_INT2_REG */ 12297 uint64_t reserved_57_59 : 3; 12298 uint64_t dfm : 1; /**< DFM Interrupt 12299 See DFM_FNT_STAT */ 12300 uint64_t reserved_53_55 : 3; 12301 uint64_t lmc0 : 1; /**< LMC0 interrupt 12302 See LMC0_INT */ 12303 uint64_t reserved_51_51 : 1; 12304 uint64_t srio0 : 1; /**< SRIO0 interrupt 12305 See SRIO0_INT_REG, SRIO0_INT2_REG */ 12306 uint64_t pem1 : 1; /**< PEM1 interrupt 12307 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12308 uint64_t pem0 : 1; /**< PEM0 interrupt 12309 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12310 uint64_t ptp : 1; /**< PTP interrupt 12311 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12312 uint64_t agl : 1; /**< AGL interrupt 12313 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 12314 uint64_t reserved_41_45 : 5; 12315 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 12316 TBD, See DPI DMA instruction completion */ 12317 uint64_t reserved_38_39 : 2; 12318 uint64_t agx1 : 1; /**< GMX1 interrupt 12319 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 12320 PCS1_INT*_REG, PCSX1_INT_REG */ 12321 uint64_t agx0 : 1; /**< GMX0 interrupt 12322 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12323 PCS0_INT*_REG, PCSX0_INT_REG */ 12324 uint64_t dpi : 1; /**< DPI interrupt 12325 See DPI_INT_REG */ 12326 uint64_t sli : 1; /**< SLI interrupt 12327 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12328 uint64_t usb : 1; /**< USB UCTL0 interrupt 12329 See UCTL0_INT_REG */ 12330 uint64_t dfa : 1; /**< DFA interrupt 12331 See DFA_ERROR */ 12332 uint64_t key : 1; /**< KEY interrupt 12333 See KEY_INT_SUM */ 12334 uint64_t rad : 1; /**< RAD interrupt 12335 See RAD_REG_ERROR */ 12336 uint64_t tim : 1; /**< TIM interrupt 12337 See TIM_REG_ERROR */ 12338 uint64_t zip : 1; /**< ZIP interrupt 12339 See ZIP_ERROR */ 12340 uint64_t pko : 1; /**< PKO interrupt 12341 See PKO_REG_ERROR */ 12342 uint64_t pip : 1; /**< PIP interrupt 12343 See PIP_INT_REG */ 12344 uint64_t ipd : 1; /**< IPD interrupt 12345 See IPD_INT_SUM */ 12346 uint64_t l2c : 1; /**< L2C interrupt 12347 See L2C_INT_REG */ 12348 uint64_t pow : 1; /**< POW err interrupt 12349 See POW_ECC_ERR */ 12350 uint64_t fpa : 1; /**< FPA interrupt 12351 See FPA_INT_SUM */ 12352 uint64_t iob : 1; /**< IOB interrupt 12353 See IOB_INT_SUM */ 12354 uint64_t mio : 1; /**< MIO boot interrupt 12355 See MIO_BOOT_ERR */ 12356 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 12357 See EMMC interrupt */ 12358 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 12359 See MIX1_ISR */ 12360 uint64_t reserved_10_17 : 8; 12361 uint64_t wdog : 10; /**< Per PP watchdog interrupts */ 12362#else 12363 uint64_t wdog : 10; 12364 uint64_t reserved_10_17 : 8; 12365 uint64_t mii1 : 1; 12366 uint64_t nand : 1; 12367 uint64_t mio : 1; 12368 uint64_t iob : 1; 12369 uint64_t fpa : 1; 12370 uint64_t pow : 1; 12371 uint64_t l2c : 1; 12372 uint64_t ipd : 1; 12373 uint64_t pip : 1; 12374 uint64_t pko : 1; 12375 uint64_t zip : 1; 12376 uint64_t tim : 1; 12377 uint64_t rad : 1; 12378 uint64_t key : 1; 12379 uint64_t dfa : 1; 12380 uint64_t usb : 1; 12381 uint64_t sli : 1; 12382 uint64_t dpi : 1; 12383 uint64_t agx0 : 1; 12384 uint64_t agx1 : 1; 12385 uint64_t reserved_38_39 : 2; 12386 uint64_t dpi_dma : 1; 12387 uint64_t reserved_41_45 : 5; 12388 uint64_t agl : 1; 12389 uint64_t ptp : 1; 12390 uint64_t pem0 : 1; 12391 uint64_t pem1 : 1; 12392 uint64_t srio0 : 1; 12393 uint64_t reserved_51_51 : 1; 12394 uint64_t lmc0 : 1; 12395 uint64_t reserved_53_55 : 3; 12396 uint64_t dfm : 1; 12397 uint64_t reserved_57_59 : 3; 12398 uint64_t srio2 : 1; 12399 uint64_t srio3 : 1; 12400 uint64_t reserved_62_62 : 1; 12401 uint64_t rst : 1; 12402#endif 12403 } s; 12404 struct cvmx_ciu_sum1_ppx_ip4_cn61xx { 12405#ifdef __BIG_ENDIAN_BITFIELD 12406 uint64_t rst : 1; /**< MIO RST interrupt 12407 See MIO_RST_INT */ 12408 uint64_t reserved_53_62 : 10; 12409 uint64_t lmc0 : 1; /**< LMC0 interrupt 12410 See LMC0_INT */ 12411 uint64_t reserved_50_51 : 2; 12412 uint64_t pem1 : 1; /**< PEM1 interrupt 12413 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12414 uint64_t pem0 : 1; /**< PEM0 interrupt 12415 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12416 uint64_t ptp : 1; /**< PTP interrupt 12417 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12418 uint64_t agl : 1; /**< AGL interrupt 12419 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 12420 uint64_t reserved_41_45 : 5; 12421 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 12422 TBD, See DPI DMA instruction completion */ 12423 uint64_t reserved_38_39 : 2; 12424 uint64_t agx1 : 1; /**< GMX1 interrupt 12425 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 12426 PCS1_INT*_REG, PCSX1_INT_REG */ 12427 uint64_t agx0 : 1; /**< GMX0 interrupt 12428 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12429 PCS0_INT*_REG, PCSX0_INT_REG */ 12430 uint64_t dpi : 1; /**< DPI interrupt 12431 See DPI_INT_REG */ 12432 uint64_t sli : 1; /**< SLI interrupt 12433 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12434 uint64_t usb : 1; /**< USB UCTL0 interrupt 12435 See UCTL0_INT_REG */ 12436 uint64_t dfa : 1; /**< DFA interrupt 12437 See DFA_ERROR */ 12438 uint64_t key : 1; /**< KEY interrupt 12439 See KEY_INT_SUM */ 12440 uint64_t rad : 1; /**< RAD interrupt 12441 See RAD_REG_ERROR */ 12442 uint64_t tim : 1; /**< TIM interrupt 12443 See TIM_REG_ERROR */ 12444 uint64_t zip : 1; /**< ZIP interrupt 12445 See ZIP_ERROR */ 12446 uint64_t pko : 1; /**< PKO interrupt 12447 See PKO_REG_ERROR */ 12448 uint64_t pip : 1; /**< PIP interrupt 12449 See PIP_INT_REG */ 12450 uint64_t ipd : 1; /**< IPD interrupt 12451 See IPD_INT_SUM */ 12452 uint64_t l2c : 1; /**< L2C interrupt 12453 See L2C_INT_REG */ 12454 uint64_t pow : 1; /**< POW err interrupt 12455 See POW_ECC_ERR */ 12456 uint64_t fpa : 1; /**< FPA interrupt 12457 See FPA_INT_SUM */ 12458 uint64_t iob : 1; /**< IOB interrupt 12459 See IOB_INT_SUM */ 12460 uint64_t mio : 1; /**< MIO boot interrupt 12461 See MIO_BOOT_ERR */ 12462 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 12463 See EMMC interrupt */ 12464 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt 12465 See MIX1_ISR */ 12466 uint64_t reserved_4_17 : 14; 12467 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 12468#else 12469 uint64_t wdog : 4; 12470 uint64_t reserved_4_17 : 14; 12471 uint64_t mii1 : 1; 12472 uint64_t nand : 1; 12473 uint64_t mio : 1; 12474 uint64_t iob : 1; 12475 uint64_t fpa : 1; 12476 uint64_t pow : 1; 12477 uint64_t l2c : 1; 12478 uint64_t ipd : 1; 12479 uint64_t pip : 1; 12480 uint64_t pko : 1; 12481 uint64_t zip : 1; 12482 uint64_t tim : 1; 12483 uint64_t rad : 1; 12484 uint64_t key : 1; 12485 uint64_t dfa : 1; 12486 uint64_t usb : 1; 12487 uint64_t sli : 1; 12488 uint64_t dpi : 1; 12489 uint64_t agx0 : 1; 12490 uint64_t agx1 : 1; 12491 uint64_t reserved_38_39 : 2; 12492 uint64_t dpi_dma : 1; 12493 uint64_t reserved_41_45 : 5; 12494 uint64_t agl : 1; 12495 uint64_t ptp : 1; 12496 uint64_t pem0 : 1; 12497 uint64_t pem1 : 1; 12498 uint64_t reserved_50_51 : 2; 12499 uint64_t lmc0 : 1; 12500 uint64_t reserved_53_62 : 10; 12501 uint64_t rst : 1; 12502#endif 12503 } cn61xx; 12504 struct cvmx_ciu_sum1_ppx_ip4_cn66xx { 12505#ifdef __BIG_ENDIAN_BITFIELD 12506 uint64_t rst : 1; /**< MIO RST interrupt 12507 See MIO_RST_INT */ 12508 uint64_t reserved_62_62 : 1; 12509 uint64_t srio3 : 1; /**< SRIO3 interrupt 12510 See SRIO3_INT_REG, SRIO3_INT2_REG */ 12511 uint64_t srio2 : 1; /**< SRIO2 interrupt 12512 See SRIO2_INT_REG, SRIO2_INT2_REG */ 12513 uint64_t reserved_57_59 : 3; 12514 uint64_t dfm : 1; /**< DFM Interrupt 12515 See DFM_FNT_STAT */ 12516 uint64_t reserved_53_55 : 3; 12517 uint64_t lmc0 : 1; /**< LMC0 interrupt 12518 See LMC0_INT */ 12519 uint64_t reserved_51_51 : 1; 12520 uint64_t srio0 : 1; /**< SRIO0 interrupt 12521 See SRIO0_INT_REG, SRIO0_INT2_REG */ 12522 uint64_t pem1 : 1; /**< PEM1 interrupt 12523 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12524 uint64_t pem0 : 1; /**< PEM0 interrupt 12525 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12526 uint64_t ptp : 1; /**< PTP interrupt 12527 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12528 uint64_t agl : 1; /**< AGL interrupt 12529 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 12530 uint64_t reserved_38_45 : 8; 12531 uint64_t agx1 : 1; /**< GMX1 interrupt 12532 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG, 12533 PCS1_INT*_REG, PCSX1_INT_REG */ 12534 uint64_t agx0 : 1; /**< GMX0 interrupt 12535 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12536 PCS0_INT*_REG, PCSX0_INT_REG */ 12537 uint64_t dpi : 1; /**< DPI interrupt 12538 See DPI_INT_REG */ 12539 uint64_t sli : 1; /**< SLI interrupt 12540 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12541 uint64_t usb : 1; /**< USB UCTL0 interrupt 12542 See UCTL0_INT_REG */ 12543 uint64_t dfa : 1; /**< DFA interrupt 12544 See DFA_ERROR */ 12545 uint64_t key : 1; /**< KEY interrupt 12546 See KEY_INT_SUM */ 12547 uint64_t rad : 1; /**< RAD interrupt 12548 See RAD_REG_ERROR */ 12549 uint64_t tim : 1; /**< TIM interrupt 12550 See TIM_REG_ERROR */ 12551 uint64_t zip : 1; /**< ZIP interrupt 12552 See ZIP_ERROR */ 12553 uint64_t pko : 1; /**< PKO interrupt 12554 See PKO_REG_ERROR */ 12555 uint64_t pip : 1; /**< PIP interrupt 12556 See PIP_INT_REG */ 12557 uint64_t ipd : 1; /**< IPD interrupt 12558 See IPD_INT_SUM */ 12559 uint64_t l2c : 1; /**< L2C interrupt 12560 See L2C_INT_REG */ 12561 uint64_t pow : 1; /**< POW err interrupt 12562 See POW_ECC_ERR */ 12563 uint64_t fpa : 1; /**< FPA interrupt 12564 See FPA_INT_SUM */ 12565 uint64_t iob : 1; /**< IOB interrupt 12566 See IOB_INT_SUM */ 12567 uint64_t mio : 1; /**< MIO boot interrupt 12568 See MIO_BOOT_ERR */ 12569 uint64_t nand : 1; /**< NAND Flash Controller interrupt 12570 See NDF_INT */ 12571 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 12572 See MIX1_ISR */ 12573 uint64_t reserved_10_17 : 8; 12574 uint64_t wdog : 10; /**< 10 watchdog interrupts */ 12575#else 12576 uint64_t wdog : 10; 12577 uint64_t reserved_10_17 : 8; 12578 uint64_t mii1 : 1; 12579 uint64_t nand : 1; 12580 uint64_t mio : 1; 12581 uint64_t iob : 1; 12582 uint64_t fpa : 1; 12583 uint64_t pow : 1; 12584 uint64_t l2c : 1; 12585 uint64_t ipd : 1; 12586 uint64_t pip : 1; 12587 uint64_t pko : 1; 12588 uint64_t zip : 1; 12589 uint64_t tim : 1; 12590 uint64_t rad : 1; 12591 uint64_t key : 1; 12592 uint64_t dfa : 1; 12593 uint64_t usb : 1; 12594 uint64_t sli : 1; 12595 uint64_t dpi : 1; 12596 uint64_t agx0 : 1; 12597 uint64_t agx1 : 1; 12598 uint64_t reserved_38_45 : 8; 12599 uint64_t agl : 1; 12600 uint64_t ptp : 1; 12601 uint64_t pem0 : 1; 12602 uint64_t pem1 : 1; 12603 uint64_t srio0 : 1; 12604 uint64_t reserved_51_51 : 1; 12605 uint64_t lmc0 : 1; 12606 uint64_t reserved_53_55 : 3; 12607 uint64_t dfm : 1; 12608 uint64_t reserved_57_59 : 3; 12609 uint64_t srio2 : 1; 12610 uint64_t srio3 : 1; 12611 uint64_t reserved_62_62 : 1; 12612 uint64_t rst : 1; 12613#endif 12614 } cn66xx; 12615 struct cvmx_ciu_sum1_ppx_ip4_cnf71xx { 12616#ifdef __BIG_ENDIAN_BITFIELD 12617 uint64_t rst : 1; /**< MIO RST interrupt 12618 See MIO_RST_INT */ 12619 uint64_t reserved_53_62 : 10; 12620 uint64_t lmc0 : 1; /**< LMC0 interrupt 12621 See LMC0_INT */ 12622 uint64_t reserved_50_51 : 2; 12623 uint64_t pem1 : 1; /**< PEM1 interrupt 12624 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 12625 uint64_t pem0 : 1; /**< PEM0 interrupt 12626 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 12627 uint64_t ptp : 1; /**< PTP interrupt 12628 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 12629 uint64_t reserved_41_46 : 6; 12630 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt 12631 TBD, See DPI DMA instruction completion */ 12632 uint64_t reserved_37_39 : 3; 12633 uint64_t agx0 : 1; /**< GMX0 interrupt 12634 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 12635 PCS0_INT*_REG, PCSX0_INT_REG */ 12636 uint64_t dpi : 1; /**< DPI interrupt 12637 See DPI_INT_REG */ 12638 uint64_t sli : 1; /**< SLI interrupt 12639 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 12640 uint64_t usb : 1; /**< USB UCTL0 interrupt 12641 See UCTL0_INT_REG */ 12642 uint64_t reserved_32_32 : 1; 12643 uint64_t key : 1; /**< KEY interrupt 12644 See KEY_INT_SUM */ 12645 uint64_t rad : 1; /**< RAD interrupt 12646 See RAD_REG_ERROR */ 12647 uint64_t tim : 1; /**< TIM interrupt 12648 See TIM_REG_ERROR */ 12649 uint64_t reserved_28_28 : 1; 12650 uint64_t pko : 1; /**< PKO interrupt 12651 See PKO_REG_ERROR */ 12652 uint64_t pip : 1; /**< PIP interrupt 12653 See PIP_INT_REG */ 12654 uint64_t ipd : 1; /**< IPD interrupt 12655 See IPD_INT_SUM */ 12656 uint64_t l2c : 1; /**< L2C interrupt 12657 See L2C_INT_REG */ 12658 uint64_t pow : 1; /**< POW err interrupt 12659 See POW_ECC_ERR */ 12660 uint64_t fpa : 1; /**< FPA interrupt 12661 See FPA_INT_SUM */ 12662 uint64_t iob : 1; /**< IOB interrupt 12663 See IOB_INT_SUM */ 12664 uint64_t mio : 1; /**< MIO boot interrupt 12665 See MIO_BOOT_ERR */ 12666 uint64_t nand : 1; /**< EMMC Flash Controller interrupt 12667 See EMMC interrupt */ 12668 uint64_t reserved_4_18 : 15; 12669 uint64_t wdog : 4; /**< Per PP watchdog interrupts */ 12670#else 12671 uint64_t wdog : 4; 12672 uint64_t reserved_4_18 : 15; 12673 uint64_t nand : 1; 12674 uint64_t mio : 1; 12675 uint64_t iob : 1; 12676 uint64_t fpa : 1; 12677 uint64_t pow : 1; 12678 uint64_t l2c : 1; 12679 uint64_t ipd : 1; 12680 uint64_t pip : 1; 12681 uint64_t pko : 1; 12682 uint64_t reserved_28_28 : 1; 12683 uint64_t tim : 1; 12684 uint64_t rad : 1; 12685 uint64_t key : 1; 12686 uint64_t reserved_32_32 : 1; 12687 uint64_t usb : 1; 12688 uint64_t sli : 1; 12689 uint64_t dpi : 1; 12690 uint64_t agx0 : 1; 12691 uint64_t reserved_37_39 : 3; 12692 uint64_t dpi_dma : 1; 12693 uint64_t reserved_41_46 : 6; 12694 uint64_t ptp : 1; 12695 uint64_t pem0 : 1; 12696 uint64_t pem1 : 1; 12697 uint64_t reserved_50_51 : 2; 12698 uint64_t lmc0 : 1; 12699 uint64_t reserved_53_62 : 10; 12700 uint64_t rst : 1; 12701#endif 12702 } cnf71xx; 12703}; 12704typedef union cvmx_ciu_sum1_ppx_ip4 cvmx_ciu_sum1_ppx_ip4_t; 12705 12706/** 12707 * cvmx_ciu_sum2_io#_int 12708 * 12709 * Notes: 12710 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 12711 * 12712 */ 12713union cvmx_ciu_sum2_iox_int { 12714 uint64_t u64; 12715 struct cvmx_ciu_sum2_iox_int_s { 12716#ifdef __BIG_ENDIAN_BITFIELD 12717 uint64_t reserved_15_63 : 49; 12718 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status 12719 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */ 12720 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */ 12721 uint64_t reserved_10_11 : 2; 12722 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12723 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12724 common for all PP/IRQs, writing '1' to any PP/IRQ 12725 will clear all TIMERx(x=0..9) interrupts. 12726 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12727 are set at the same time, but clearing are based on 12728 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12729 The combination of this field and the 12730 CIU_INT*_SUM0/4[TIMER] field implement all 10 12731 CIU_TIM* interrupts. */ 12732 uint64_t reserved_0_3 : 4; 12733#else 12734 uint64_t reserved_0_3 : 4; 12735 uint64_t timer : 6; 12736 uint64_t reserved_10_11 : 2; 12737 uint64_t eoi : 1; 12738 uint64_t endor : 2; 12739 uint64_t reserved_15_63 : 49; 12740#endif 12741 } s; 12742 struct cvmx_ciu_sum2_iox_int_cn61xx { 12743#ifdef __BIG_ENDIAN_BITFIELD 12744 uint64_t reserved_10_63 : 54; 12745 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12746 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12747 common for all PP/IRQs, writing '1' to any PP/IRQ 12748 will clear all TIMERx(x=0..9) interrupts. 12749 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12750 are set at the same time, but clearing are based on 12751 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12752 The combination of this field and the 12753 CIU_INT*_SUM0/4[TIMER] field implement all 10 12754 CIU_TIM* interrupts. */ 12755 uint64_t reserved_0_3 : 4; 12756#else 12757 uint64_t reserved_0_3 : 4; 12758 uint64_t timer : 6; 12759 uint64_t reserved_10_63 : 54; 12760#endif 12761 } cn61xx; 12762 struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx; 12763 struct cvmx_ciu_sum2_iox_int_s cnf71xx; 12764}; 12765typedef union cvmx_ciu_sum2_iox_int cvmx_ciu_sum2_iox_int_t; 12766 12767/** 12768 * cvmx_ciu_sum2_pp#_ip2 12769 * 12770 * Notes: 12771 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 12772 * 12773 */ 12774union cvmx_ciu_sum2_ppx_ip2 { 12775 uint64_t u64; 12776 struct cvmx_ciu_sum2_ppx_ip2_s { 12777#ifdef __BIG_ENDIAN_BITFIELD 12778 uint64_t reserved_15_63 : 49; 12779 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status 12780 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */ 12781 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */ 12782 uint64_t reserved_10_11 : 2; 12783 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12784 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12785 common for all PP/IRQs, writing '1' to any PP/IRQ 12786 will clear all TIMERx(x=0..9) interrupts. 12787 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12788 are set at the same time, but clearing are based on 12789 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12790 The combination of this field and the 12791 CIU_INT*_SUM0/4[TIMER] field implement all 10 12792 CIU_TIM* interrupts. */ 12793 uint64_t reserved_0_3 : 4; 12794#else 12795 uint64_t reserved_0_3 : 4; 12796 uint64_t timer : 6; 12797 uint64_t reserved_10_11 : 2; 12798 uint64_t eoi : 1; 12799 uint64_t endor : 2; 12800 uint64_t reserved_15_63 : 49; 12801#endif 12802 } s; 12803 struct cvmx_ciu_sum2_ppx_ip2_cn61xx { 12804#ifdef __BIG_ENDIAN_BITFIELD 12805 uint64_t reserved_10_63 : 54; 12806 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12807 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12808 common for all PP/IRQs, writing '1' to any PP/IRQ 12809 will clear all TIMERx(x=0..9) interrupts. 12810 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12811 are set at the same time, but clearing are based on 12812 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12813 The combination of this field and the 12814 CIU_INT*_SUM0/4[TIMER] field implement all 10 12815 CIU_TIM* interrupts. */ 12816 uint64_t reserved_0_3 : 4; 12817#else 12818 uint64_t reserved_0_3 : 4; 12819 uint64_t timer : 6; 12820 uint64_t reserved_10_63 : 54; 12821#endif 12822 } cn61xx; 12823 struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx; 12824 struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx; 12825}; 12826typedef union cvmx_ciu_sum2_ppx_ip2 cvmx_ciu_sum2_ppx_ip2_t; 12827 12828/** 12829 * cvmx_ciu_sum2_pp#_ip3 12830 * 12831 * Notes: 12832 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 12833 * 12834 */ 12835union cvmx_ciu_sum2_ppx_ip3 { 12836 uint64_t u64; 12837 struct cvmx_ciu_sum2_ppx_ip3_s { 12838#ifdef __BIG_ENDIAN_BITFIELD 12839 uint64_t reserved_15_63 : 49; 12840 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status 12841 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */ 12842 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */ 12843 uint64_t reserved_10_11 : 2; 12844 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12845 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12846 common for all PP/IRQs, writing '1' to any PP/IRQ 12847 will clear all TIMERx(x=0..9) interrupts. 12848 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12849 are set at the same time, but clearing are based on 12850 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12851 The combination of this field and the 12852 CIU_INT*_SUM0/4[TIMER] field implement all 10 12853 CIU_TIM* interrupts. */ 12854 uint64_t reserved_0_3 : 4; 12855#else 12856 uint64_t reserved_0_3 : 4; 12857 uint64_t timer : 6; 12858 uint64_t reserved_10_11 : 2; 12859 uint64_t eoi : 1; 12860 uint64_t endor : 2; 12861 uint64_t reserved_15_63 : 49; 12862#endif 12863 } s; 12864 struct cvmx_ciu_sum2_ppx_ip3_cn61xx { 12865#ifdef __BIG_ENDIAN_BITFIELD 12866 uint64_t reserved_10_63 : 54; 12867 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12868 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12869 common for all PP/IRQs, writing '1' to any PP/IRQ 12870 will clear all TIMERx(x=0..9) interrupts. 12871 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12872 are set at the same time, but clearing are based on 12873 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12874 The combination of this field and the 12875 CIU_INT*_SUM0/4[TIMER] field implement all 10 12876 CIU_TIM* interrupts. */ 12877 uint64_t reserved_0_3 : 4; 12878#else 12879 uint64_t reserved_0_3 : 4; 12880 uint64_t timer : 6; 12881 uint64_t reserved_10_63 : 54; 12882#endif 12883 } cn61xx; 12884 struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx; 12885 struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx; 12886}; 12887typedef union cvmx_ciu_sum2_ppx_ip3 cvmx_ciu_sum2_ppx_ip3_t; 12888 12889/** 12890 * cvmx_ciu_sum2_pp#_ip4 12891 * 12892 * Notes: 12893 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2. 12894 * 12895 */ 12896union cvmx_ciu_sum2_ppx_ip4 { 12897 uint64_t u64; 12898 struct cvmx_ciu_sum2_ppx_ip4_s { 12899#ifdef __BIG_ENDIAN_BITFIELD 12900 uint64_t reserved_15_63 : 49; 12901 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status 12902 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */ 12903 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */ 12904 uint64_t reserved_10_11 : 2; 12905 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12906 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12907 common for all PP/IRQs, writing '1' to any PP/IRQ 12908 will clear all TIMERx(x=0..9) interrupts. 12909 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12910 are set at the same time, but clearing are based on 12911 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12912 The combination of this field and the 12913 CIU_INT*_SUM0/4[TIMER] field implement all 10 12914 CIU_TIM* interrupts. */ 12915 uint64_t reserved_0_3 : 4; 12916#else 12917 uint64_t reserved_0_3 : 4; 12918 uint64_t timer : 6; 12919 uint64_t reserved_10_11 : 2; 12920 uint64_t eoi : 1; 12921 uint64_t endor : 2; 12922 uint64_t reserved_15_63 : 49; 12923#endif 12924 } s; 12925 struct cvmx_ciu_sum2_ppx_ip4_cn61xx { 12926#ifdef __BIG_ENDIAN_BITFIELD 12927 uint64_t reserved_10_63 : 54; 12928 uint64_t timer : 6; /**< General timer 4-9 interrupts. 12929 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is 12930 common for all PP/IRQs, writing '1' to any PP/IRQ 12931 will clear all TIMERx(x=0..9) interrupts. 12932 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9) 12933 are set at the same time, but clearing are based on 12934 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail. 12935 The combination of this field and the 12936 CIU_INT*_SUM0/4[TIMER] field implement all 10 12937 CIU_TIM* interrupts. */ 12938 uint64_t reserved_0_3 : 4; 12939#else 12940 uint64_t reserved_0_3 : 4; 12941 uint64_t timer : 6; 12942 uint64_t reserved_10_63 : 54; 12943#endif 12944 } cn61xx; 12945 struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx; 12946 struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx; 12947}; 12948typedef union cvmx_ciu_sum2_ppx_ip4 cvmx_ciu_sum2_ppx_ip4_t; 12949 12950/** 12951 * cvmx_ciu_tim# 12952 * 12953 * Notes: 12954 * CIU_TIM4-9 did not exist prior to pass 1.2 12955 * 12956 */ 12957union cvmx_ciu_timx { 12958 uint64_t u64; 12959 struct cvmx_ciu_timx_s { 12960#ifdef __BIG_ENDIAN_BITFIELD 12961 uint64_t reserved_37_63 : 27; 12962 uint64_t one_shot : 1; /**< One-shot mode */ 12963 uint64_t len : 36; /**< Timeout length in core clock cycles 12964 Periodic interrupts will occur every LEN+1 core 12965 clock cycles when ONE_SHOT==0 12966 Timer disabled when LEN==0 */ 12967#else 12968 uint64_t len : 36; 12969 uint64_t one_shot : 1; 12970 uint64_t reserved_37_63 : 27; 12971#endif 12972 } s; 12973 struct cvmx_ciu_timx_s cn30xx; 12974 struct cvmx_ciu_timx_s cn31xx; 12975 struct cvmx_ciu_timx_s cn38xx; 12976 struct cvmx_ciu_timx_s cn38xxp2; 12977 struct cvmx_ciu_timx_s cn50xx; 12978 struct cvmx_ciu_timx_s cn52xx; 12979 struct cvmx_ciu_timx_s cn52xxp1; 12980 struct cvmx_ciu_timx_s cn56xx; 12981 struct cvmx_ciu_timx_s cn56xxp1; 12982 struct cvmx_ciu_timx_s cn58xx; 12983 struct cvmx_ciu_timx_s cn58xxp1; 12984 struct cvmx_ciu_timx_s cn61xx; 12985 struct cvmx_ciu_timx_s cn63xx; 12986 struct cvmx_ciu_timx_s cn63xxp1; 12987 struct cvmx_ciu_timx_s cn66xx; 12988 struct cvmx_ciu_timx_s cn68xx; 12989 struct cvmx_ciu_timx_s cn68xxp1; 12990 struct cvmx_ciu_timx_s cnf71xx; 12991}; 12992typedef union cvmx_ciu_timx cvmx_ciu_timx_t; 12993 12994/** 12995 * cvmx_ciu_tim_multi_cast 12996 * 12997 * Notes: 12998 * This register does not exist prior to pass 1.2 silicon. Those earlier chip passes operate as if 12999 * EN==0. 13000 */ 13001union cvmx_ciu_tim_multi_cast { 13002 uint64_t u64; 13003 struct cvmx_ciu_tim_multi_cast_s { 13004#ifdef __BIG_ENDIAN_BITFIELD 13005 uint64_t reserved_1_63 : 63; 13006 uint64_t en : 1; /**< General Timer Interrupt Mutli-Cast mode: 13007 - 0: Timer interrupt is common for all PP/IRQs. 13008 - 1: Timer interrupts are set at the same time for 13009 all PP/IRQs, but interrupt clearings can/need 13010 to be done Individually based on per cnMIPS core. 13011 Timer interrupts for IOs (X=32,33) will always use 13012 common interrupts. Clear any of the I/O interrupts 13013 will clear the common interrupt. */ 13014#else 13015 uint64_t en : 1; 13016 uint64_t reserved_1_63 : 63; 13017#endif 13018 } s; 13019 struct cvmx_ciu_tim_multi_cast_s cn61xx; 13020 struct cvmx_ciu_tim_multi_cast_s cn66xx; 13021 struct cvmx_ciu_tim_multi_cast_s cnf71xx; 13022}; 13023typedef union cvmx_ciu_tim_multi_cast cvmx_ciu_tim_multi_cast_t; 13024 13025/** 13026 * cvmx_ciu_wdog# 13027 */ 13028union cvmx_ciu_wdogx { 13029 uint64_t u64; 13030 struct cvmx_ciu_wdogx_s { 13031#ifdef __BIG_ENDIAN_BITFIELD 13032 uint64_t reserved_46_63 : 18; 13033 uint64_t gstopen : 1; /**< GSTOPEN */ 13034 uint64_t dstop : 1; /**< DSTOP */ 13035 uint64_t cnt : 24; /**< Number of 256-cycle intervals until next watchdog 13036 expiration. Cleared on write to associated 13037 CIU_PP_POKE register. */ 13038 uint64_t len : 16; /**< Watchdog time expiration length 13039 The 16 bits of LEN represent the most significant 13040 bits of a 24 bit decrementer that decrements 13041 every 256 cycles. 13042 LEN must be set > 0 */ 13043 uint64_t state : 2; /**< Watchdog state 13044 number of watchdog time expirations since last 13045 PP poke. Cleared on write to associated 13046 CIU_PP_POKE register. */ 13047 uint64_t mode : 2; /**< Watchdog mode 13048 0 = Off 13049 1 = Interrupt Only 13050 2 = Interrupt + NMI 13051 3 = Interrupt + NMI + Soft-Reset */ 13052#else 13053 uint64_t mode : 2; 13054 uint64_t state : 2; 13055 uint64_t len : 16; 13056 uint64_t cnt : 24; 13057 uint64_t dstop : 1; 13058 uint64_t gstopen : 1; 13059 uint64_t reserved_46_63 : 18; 13060#endif 13061 } s; 13062 struct cvmx_ciu_wdogx_s cn30xx; 13063 struct cvmx_ciu_wdogx_s cn31xx; 13064 struct cvmx_ciu_wdogx_s cn38xx; 13065 struct cvmx_ciu_wdogx_s cn38xxp2; 13066 struct cvmx_ciu_wdogx_s cn50xx; 13067 struct cvmx_ciu_wdogx_s cn52xx; 13068 struct cvmx_ciu_wdogx_s cn52xxp1; 13069 struct cvmx_ciu_wdogx_s cn56xx; 13070 struct cvmx_ciu_wdogx_s cn56xxp1; 13071 struct cvmx_ciu_wdogx_s cn58xx; 13072 struct cvmx_ciu_wdogx_s cn58xxp1; 13073 struct cvmx_ciu_wdogx_s cn61xx; 13074 struct cvmx_ciu_wdogx_s cn63xx; 13075 struct cvmx_ciu_wdogx_s cn63xxp1; 13076 struct cvmx_ciu_wdogx_s cn66xx; 13077 struct cvmx_ciu_wdogx_s cn68xx; 13078 struct cvmx_ciu_wdogx_s cn68xxp1; 13079 struct cvmx_ciu_wdogx_s cnf71xx; 13080}; 13081typedef union cvmx_ciu_wdogx cvmx_ciu_wdogx_t; 13082 13083#endif 13084