sheevaplug.dts revision 235778
1208561Sraj/* 2208561Sraj * Copyright (c) 2010 The FreeBSD Foundation 3208561Sraj * All rights reserved. 4208561Sraj * 5208561Sraj * This software was developed by Semihalf under sponsorship from 6208561Sraj * the FreeBSD Foundation. 7208561Sraj * 8208561Sraj * Redistribution and use in source and binary forms, with or without 9208561Sraj * modification, are permitted provided that the following conditions 10208561Sraj * are met: 11208561Sraj * 1. Redistributions of source code must retain the above copyright 12208561Sraj * notice, this list of conditions and the following disclaimer. 13208561Sraj * 2. Redistributions in binary form must reproduce the above copyright 14208561Sraj * notice, this list of conditions and the following disclaimer in the 15208561Sraj * documentation and/or other materials provided with the distribution. 16208561Sraj * 17208561Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18208561Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19208561Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20208561Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21208561Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22208561Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23208561Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24208561Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25208561Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26208561Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27208561Sraj * SUCH DAMAGE. 28208561Sraj * 29208561Sraj * Marvell SheevaPlug Device Tree Source. 30208561Sraj * 31208561Sraj * $FreeBSD: head/sys/boot/fdt/dts/sheevaplug.dts 235778 2012-05-22 08:33:14Z gber $ 32208561Sraj */ 33208561Sraj 34208561Sraj/dts-v1/; 35208561Sraj 36208561Sraj/ { 37208561Sraj model = "mrvl,SheevaPlug"; 38208561Sraj compatible = "SheevaPlug"; 39208561Sraj #address-cells = <1>; 40208561Sraj #size-cells = <1>; 41208561Sraj 42208561Sraj aliases { 43208561Sraj ethernet0 = &enet0; 44208561Sraj mpp = &MPP; 45208561Sraj serial0 = &serial0; 46208561Sraj serial1 = &serial1; 47208561Sraj soc = &SOC; 48208561Sraj sram = &SRAM; 49208561Sraj }; 50208561Sraj 51208561Sraj cpus { 52208561Sraj #address-cells = <1>; 53208561Sraj #size-cells = <0>; 54208561Sraj 55208561Sraj cpu@0 { 56208561Sraj device_type = "cpu"; 57208561Sraj compatible = "ARM,88FR131"; 58208561Sraj reg = <0x0>; 59208561Sraj d-cache-line-size = <32>; // 32 bytes 60208561Sraj i-cache-line-size = <32>; // 32 bytes 61208561Sraj d-cache-size = <0x4000>; // L1, 16K 62208561Sraj i-cache-size = <0x4000>; // L1, 16K 63208561Sraj timebase-frequency = <0>; 64208561Sraj bus-frequency = <0>; 65208561Sraj clock-frequency = <0>; 66208561Sraj }; 67208561Sraj }; 68208561Sraj 69208561Sraj memory { 70208561Sraj device_type = "memory"; 71208561Sraj reg = <0x0 0x20000000>; // 512M at 0x0 72208561Sraj }; 73208561Sraj 74235609Sgber localbus@0 { 75208561Sraj #address-cells = <2>; 76208561Sraj #size-cells = <1>; 77208561Sraj compatible = "mrvl,lbc"; 78235609Sgber bank-count = <3>; 79208561Sraj 80208561Sraj /* This reflects CPU decode windows setup. */ 81235609Sgber ranges = <0x0 0x2f 0xf9300000 0x00100000>; 82208561Sraj 83235609Sgber nand@0,0 { 84208561Sraj #address-cells = <1>; 85208561Sraj #size-cells = <1>; 86235609Sgber compatible = "mrvl,nfc"; 87208561Sraj reg = <0x0 0x0 0x00100000>; 88208561Sraj bank-width = <2>; 89208561Sraj device-width = <1>; 90208561Sraj 91235778Sgber slice@0 { 92235778Sgber reg = <0x0 0x200000>; 93235778Sgber label = "u-boot"; 94235778Sgber read-only; 95235778Sgber }; 96208561Sraj 97235778Sgber slice@200000 { 98235778Sgber reg = <0x200000 0x1fe00000>; 99235778Sgber label = "root"; 100235778Sgber }; 101208561Sraj }; 102208561Sraj }; 103208561Sraj 104208561Sraj SOC: soc88f6281@f1000000 { 105208561Sraj #address-cells = <1>; 106208561Sraj #size-cells = <1>; 107208561Sraj compatible = "simple-bus"; 108208561Sraj ranges = <0x0 0xf1000000 0x00100000>; 109208561Sraj bus-frequency = <0>; 110208561Sraj 111208561Sraj PIC: pic@20200 { 112208561Sraj interrupt-controller; 113208561Sraj #address-cells = <0>; 114208561Sraj #interrupt-cells = <1>; 115208561Sraj reg = <0x20200 0x3c>; 116208561Sraj compatible = "mrvl,pic"; 117208561Sraj }; 118208561Sraj 119208561Sraj timer@20300 { 120208561Sraj compatible = "mrvl,timer"; 121208561Sraj reg = <0x20300 0x30>; 122208561Sraj interrupts = <1>; 123208561Sraj interrupt-parent = <&PIC>; 124208561Sraj mrvl,has-wdt; 125208561Sraj }; 126208561Sraj 127208561Sraj MPP: mpp@10000 { 128208561Sraj #pin-cells = <2>; 129208561Sraj compatible = "mrvl,mpp"; 130208561Sraj reg = <0x10000 0x34>; 131208561Sraj pin-count = <50>; 132208561Sraj pin-map = < 133208561Sraj 0 1 /* MPP[0]: NF_IO[2] */ 134208561Sraj 1 1 /* MPP[1]: NF_IO[3] */ 135208561Sraj 2 1 /* MPP[2]: NF_IO[4] */ 136208561Sraj 3 1 /* MPP[3]: NF_IO[5] */ 137208561Sraj 4 1 /* MPP[4]: NF_IO[6] */ 138208561Sraj 5 1 /* MPP[5]: NF_IO[7] */ 139208561Sraj 6 1 /* MPP[6]: SYSRST_OUTn */ 140208561Sraj 8 2 /* MPP[8]: UA0_RTS */ 141208561Sraj 9 2 /* MPP[9]: UA0_CTS */ 142208561Sraj 10 3 /* MPP[10]: UA0_TXD */ 143208561Sraj 11 3 /* MPP[11]: UA0_RXD */ 144208561Sraj 12 1 /* MPP[12]: SD_CLK */ 145208561Sraj 13 1 /* MPP[13]: SD_CMD */ 146208561Sraj 14 1 /* MPP[14]: SD_D[0] */ 147208561Sraj 15 1 /* MPP[15]: SD_D[1] */ 148208561Sraj 16 1 /* MPP[16]: SD_D[2] */ 149208561Sraj 17 1 /* MPP[17]: SD_D[3] */ 150208561Sraj 18 1 /* MPP[18]: NF_IO[0] */ 151208561Sraj 19 1 /* MPP[19]: NF_IO[1] */ 152208561Sraj 29 1 >; /* MPP[29]: TSMP[9] */ 153208561Sraj }; 154208561Sraj 155208561Sraj GPIO: gpio@10100 { 156208561Sraj #gpio-cells = <3>; 157208561Sraj compatible = "mrvl,gpio"; 158208561Sraj reg = <0x10100 0x20>; 159208561Sraj gpio-controller; 160208561Sraj interrupts = <35 36 37 38 39 40 41>; 161208561Sraj interrupt-parent = <&PIC>; 162208561Sraj }; 163208561Sraj 164208561Sraj rtc@10300 { 165208561Sraj compatible = "mrvl,rtc"; 166208561Sraj reg = <0x10300 0x08>; 167208561Sraj }; 168208561Sraj 169208561Sraj twsi@11000 { 170208561Sraj #address-cells = <1>; 171208561Sraj #size-cells = <0>; 172208561Sraj compatible = "mrvl,twsi"; 173208561Sraj reg = <0x11000 0x20>; 174208561Sraj interrupts = <43>; 175208561Sraj interrupt-parent = <&PIC>; 176208561Sraj }; 177208561Sraj 178208561Sraj enet0: ethernet@72000 { 179208561Sraj #address-cells = <1>; 180208561Sraj #size-cells = <1>; 181208561Sraj model = "V2"; 182208561Sraj compatible = "mrvl,ge"; 183208561Sraj reg = <0x72000 0x2000>; 184208561Sraj ranges = <0x0 0x72000 0x2000>; 185208561Sraj local-mac-address = [ 00 00 00 00 00 00 ]; 186208561Sraj interrupts = <12 13 14 11 46>; 187208561Sraj interrupt-parent = <&PIC>; 188208561Sraj phy-handle = <&phy0>; 189208561Sraj 190208561Sraj mdio@0 { 191208561Sraj #address-cells = <1>; 192208561Sraj #size-cells = <0>; 193208561Sraj compatible = "mrvl,mdio"; 194208561Sraj 195208561Sraj phy0: ethernet-phy@0 { 196208561Sraj reg = <0x0>; 197208561Sraj }; 198208561Sraj }; 199208561Sraj }; 200208561Sraj 201208561Sraj serial0: serial@12000 { 202208561Sraj compatible = "ns16550"; 203208561Sraj reg = <0x12000 0x20>; 204208561Sraj reg-shift = <2>; 205208561Sraj clock-frequency = <0>; 206208561Sraj interrupts = <33>; 207208561Sraj interrupt-parent = <&PIC>; 208208561Sraj }; 209208561Sraj 210208561Sraj serial1: serial@12100 { 211208561Sraj compatible = "ns16550"; 212208561Sraj reg = <0x12100 0x20>; 213208561Sraj reg-shift = <2>; 214208561Sraj clock-frequency = <0>; 215208561Sraj interrupts = <34>; 216208561Sraj interrupt-parent = <&PIC>; 217208561Sraj }; 218208561Sraj 219208561Sraj crypto@30000 { 220208561Sraj compatible = "mrvl,cesa"; 221208561Sraj reg = <0x30000 0x10000>; 222208561Sraj interrupts = <22>; 223208561Sraj interrupt-parent = <&PIC>; 224227730Sraj 225227730Sraj sram-handle = <&SRAM>; 226208561Sraj }; 227208561Sraj 228208561Sraj usb@50000 { 229208561Sraj compatible = "mrvl,usb-ehci", "usb-ehci"; 230208561Sraj reg = <0x50000 0x1000>; 231208561Sraj interrupts = <48 19>; 232208561Sraj interrupt-parent = <&PIC>; 233208561Sraj }; 234208561Sraj 235208561Sraj xor@60000 { 236208561Sraj compatible = "mrvl,xor"; 237208561Sraj reg = <0x60000 0x1000>; 238208561Sraj interrupts = <5 6 7 8>; 239208561Sraj interrupt-parent = <&PIC>; 240208561Sraj }; 241208561Sraj }; 242208561Sraj 243208561Sraj SRAM: sram@fd000000 { 244208561Sraj compatible = "mrvl,cesa-sram"; 245208561Sraj reg = <0xfd000000 0x00100000>; 246208561Sraj }; 247208561Sraj 248208561Sraj chosen { 249208561Sraj stdin = "serial0"; 250208561Sraj stdout = "serial0"; 251208561Sraj }; 252208561Sraj}; 253