1/*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/** 29 * Driver for the MMC/SD/SDIO module on the TI OMAP series of SoCs. 30 * 31 * This driver is heavily based on the SD/MMC driver for the AT91 (at91_mci.c). 32 * 33 * It's important to realise that the MMC state machine is already in the kernel 34 * and this driver only exposes the specific interfaces of the controller. 35 * 36 * This driver is still very much a work in progress, I've verified that basic 37 * sector reading can be performed. But I've yet to test it with a file system 38 * or even writing. In addition I've only tested the driver with an SD card, 39 * I've no idea if MMC cards work. 40 * 41 */ 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: releng/10.3/sys/arm/ti/ti_mmchs.c 266159 2014-05-15 16:59:47Z ian $"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bio.h> 48#include <sys/bus.h> 49#include <sys/conf.h> 50#include <sys/endian.h> 51#include <sys/kernel.h> 52#include <sys/kthread.h> 53#include <sys/lock.h> 54#include <sys/malloc.h> 55#include <sys/module.h> 56#include <sys/mutex.h> 57#include <sys/queue.h> 58#include <sys/resource.h> 59#include <sys/rman.h> 60#include <sys/time.h> 61#include <sys/timetc.h> 62#include <sys/gpio.h> 63 64#include <machine/bus.h> 65#include <machine/cpu.h> 66#include <machine/cpufunc.h> 67#include <machine/resource.h> 68#include <machine/intr.h> 69 70#include <dev/mmc/bridge.h> 71#include <dev/mmc/mmcreg.h> 72#include <dev/mmc/mmcbrvar.h> 73 74#include <dev/fdt/fdt_common.h> 75#include <dev/ofw/openfirm.h> 76#include <dev/ofw/ofw_bus.h> 77#include <dev/ofw/ofw_bus_subr.h> 78 79#include "gpio_if.h" 80 81#include "mmcbr_if.h" 82#include "mmcbus_if.h" 83 84#include <arm/ti/ti_sdma.h> 85#include <arm/ti/ti_edma3.h> 86#include <arm/ti/ti_mmchs.h> 87#include <arm/ti/ti_cpuid.h> 88#include <arm/ti/ti_prcm.h> 89 90#include <arm/ti/twl/twl.h> 91#include <arm/ti/twl/twl_vreg.h> 92 93#ifdef DEBUG 94#define ti_mmchs_dbg(sc, fmt, args...) \ 95 device_printf((sc)->sc_dev, fmt, ## args); 96#else 97#define ti_mmchs_dbg(sc, fmt, args...) 98#endif 99 100/** 101 * Structure that stores the driver context 102 */ 103struct ti_mmchs_softc { 104 device_t sc_dev; 105 uint32_t device_id; 106 struct resource* sc_irq_res; 107 struct resource* sc_mem_res; 108 109 void* sc_irq_h; 110 111 bus_dma_tag_t sc_dmatag; 112 bus_dmamap_t sc_dmamap; 113 int sc_dmamapped; 114 115 unsigned int sc_dmach_rd; 116 unsigned int sc_dmach_wr; 117 int dma_rx_trig; 118 int dma_tx_trig; 119 120 device_t sc_gpio_dev; 121 int sc_wp_gpio_pin; /* GPIO pin for MMC write protect */ 122 123 device_t sc_vreg_dev; 124 const char* sc_vreg_name; 125 126 struct mtx sc_mtx; 127 128 struct mmc_host host; 129 struct mmc_request* req; 130 struct mmc_command* curcmd; 131 132 int flags; 133#define CMD_STARTED 1 134#define STOP_STARTED 2 135 136 int bus_busy; /* TODO: Needed ? */ 137 138 void* sc_cmd_data_vaddr; 139 int sc_cmd_data_len; 140 141 /* The offset applied to each of the register base addresses, OMAP4 142 * register sets are offset 0x100 from the OMAP3 series. 143 */ 144 unsigned long sc_reg_off; 145 146 /* The physical address of the MMCHS_DATA register, used for the DMA xfers */ 147 unsigned long sc_data_reg_paddr; 148 149 /* The reference clock frequency */ 150 unsigned int sc_ref_freq; 151 152 enum mmc_power_mode sc_cur_power_mode; 153}; 154 155/** 156 * Macros for driver mutex locking 157 */ 158#define TI_MMCHS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 159#define TI_MMCHS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 160#define TI_MMCHS_LOCK_INIT(_sc) \ 161 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 162 "ti_mmchs", MTX_DEF) 163#define TI_MMCHS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 164#define TI_MMCHS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 165#define TI_MMCHS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 166 167static void ti_mmchs_start(struct ti_mmchs_softc *sc); 168 169/** 170 * ti_mmchs_read_4 - reads a 32-bit value from a register 171 * ti_mmchs_write_4 - writes a 32-bit value to a register 172 * @sc: pointer to the driver context 173 * @off: register offset to read from 174 * @val: the value to write into the register 175 * 176 * LOCKING: 177 * None 178 * 179 * RETURNS: 180 * The 32-bit value read from the register 181 */ 182static inline uint32_t 183ti_mmchs_read_4(struct ti_mmchs_softc *sc, bus_size_t off) 184{ 185 return bus_read_4(sc->sc_mem_res, (sc->sc_reg_off + off)); 186} 187 188static inline void 189ti_mmchs_write_4(struct ti_mmchs_softc *sc, bus_size_t off, uint32_t val) 190{ 191 bus_write_4(sc->sc_mem_res, (sc->sc_reg_off + off), val); 192} 193 194/** 195 * ti_mmchs_reset_controller - 196 * @arg: caller supplied arg 197 * @segs: array of segments (although in our case should only be one) 198 * @nsegs: number of segments (in our case should be 1) 199 * @error: 200 * 201 * 202 * 203 */ 204static void 205ti_mmchs_reset_controller(struct ti_mmchs_softc *sc, uint32_t bit) 206{ 207 unsigned long attempts; 208 uint32_t sysctl; 209 210 ti_mmchs_dbg(sc, "reseting controller - bit 0x%08x\n", bit); 211 212 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 213 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | bit); 214 /* 215 * AM335x and OMAP4 >= ES2 have an updated reset logic. 216 * Monitor a 0->1 transition first. 217 */ 218 if ((ti_chip() == CHIP_AM335X) || 219 ((ti_chip() == CHIP_OMAP_4) && (ti_revision() > OMAP4430_REV_ES1_0))) { 220 attempts = 10000; 221 while (!(ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0)) 222 continue; 223 } 224 225 attempts = 10000; 226 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0)) 227 continue; 228 229 if (ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) 230 device_printf(sc->sc_dev, "Error - Timeout waiting on controller reset\n"); 231} 232 233/** 234 * ti_mmchs_getaddr - called by the DMA function to simply return the phys addr 235 * @arg: caller supplied arg 236 * @segs: array of segments (although in our case should only be one) 237 * @nsegs: number of segments (in our case should be 1) 238 * @error: 239 * 240 * This function is called by bus_dmamap_load() after it has compiled an array 241 * of segments, each segment is a phsyical chunk of memory. However in our case 242 * we should only have one segment, because we don't (yet?) support DMA scatter 243 * gather. To ensure we only have one segment, the DMA tag was created by 244 * bus_dma_tag_create() (called from ti_mmchs_attach) with nsegments set to 1. 245 * 246 */ 247static void 248ti_mmchs_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 249{ 250 if (error != 0) 251 return; 252 253 *(bus_addr_t *)arg = segs[0].ds_addr; 254} 255 256#ifndef SOC_TI_AM335X 257/** 258 * ti_mmchs_dma_intr - interrupt handler for DMA events triggered by the controller 259 * @ch: the dma channel number 260 * @status: bit field of the status bytes 261 * @data: callback data, in this case a pointer to the controller struct 262 * 263 * 264 * LOCKING: 265 * Called from interrupt context 266 * 267 */ 268static void 269ti_mmchs_dma_intr(unsigned int ch, uint32_t status, void *data) 270{ 271 /* Ignore for now ... we don't need this interrupt as we already have the 272 * interrupt from the MMC controller. 273 */ 274} 275#endif 276 277/** 278 * ti_mmchs_intr_xfer_compl - called if a 'transfer complete' IRQ was received 279 * @sc: pointer to the driver context 280 * @cmd: the command that was sent previously 281 * 282 * This function is simply responsible for syncing up the DMA buffer. 283 * 284 * LOCKING: 285 * Called from interrupt context 286 * 287 * RETURNS: 288 * Return value indicates if the transaction is complete, not done = 0, done != 0 289 */ 290static int 291ti_mmchs_intr_xfer_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 292{ 293 uint32_t cmd_reg; 294 295 /* Read command register to test whether this command was a read or write. */ 296 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD); 297 298 /* Sync-up the DMA buffer so the caller can access the new memory */ 299 if (cmd_reg & MMCHS_CMD_DDIR) { 300 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTREAD); 301 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 302 } 303 else { 304 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTWRITE); 305 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 306 } 307 sc->sc_dmamapped--; 308 309 /* Debugging dump of the data received */ 310#if 0 311 { 312 int i; 313 uint8_t *p = (uint8_t*) sc->sc_cmd_data_vaddr; 314 for (i=0; i<sc->sc_cmd_data_len; i++) { 315 if ((i % 16) == 0) 316 printf("\n0x%04x : ", i); 317 printf("%02X ", *p++); 318 } 319 printf("\n"); 320 } 321#endif 322 323 /* We are done, transfer complete */ 324 return 1; 325} 326 327/** 328 * ti_mmchs_intr_cmd_compl - called if a 'command complete' IRQ was received 329 * @sc: pointer to the driver context 330 * @cmd: the command that was sent previously 331 * 332 * 333 * LOCKING: 334 * Called from interrupt context 335 * 336 * RETURNS: 337 * Return value indicates if the transaction is complete, not done = 0, done != 0 338 */ 339static int 340ti_mmchs_intr_cmd_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 341{ 342 uint32_t cmd_reg; 343 344 /* Copy the response into the request struct ... if a response was 345 * expected */ 346 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) { 347 if (cmd->flags & MMC_RSP_136) { 348 cmd->resp[3] = ti_mmchs_read_4(sc, MMCHS_RSP10); 349 cmd->resp[2] = ti_mmchs_read_4(sc, MMCHS_RSP32); 350 cmd->resp[1] = ti_mmchs_read_4(sc, MMCHS_RSP54); 351 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP76); 352 } else { 353 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP10); 354 } 355 } 356 357 /* Check if the command was expecting some data transfer, if not 358 * we are done. */ 359 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD); 360 return ((cmd_reg & MMCHS_CMD_DP) == 0); 361} 362 363/** 364 * ti_mmchs_intr_error - handles error interrupts 365 * @sc: pointer to the driver context 366 * @cmd: the command that was sent previously 367 * @stat_reg: the value that was in the status register 368 * 369 * 370 * LOCKING: 371 * Called from interrupt context 372 * 373 * RETURNS: 374 * Return value indicates if the transaction is complete, not done = 0, done != 0 375 */ 376static int 377ti_mmchs_intr_error(struct ti_mmchs_softc *sc, struct mmc_command *cmd, 378 uint32_t stat_reg) 379{ 380 ti_mmchs_dbg(sc, "error in xfer - stat 0x%08x\n", stat_reg); 381 382 /* Ignore CRC errors on CMD2 and ACMD47, per relevant standards */ 383 if ((stat_reg & MMCHS_STAT_CCRC) && (cmd->opcode == MMC_SEND_OP_COND || 384 cmd->opcode == ACMD_SD_SEND_OP_COND)) 385 cmd->error = MMC_ERR_NONE; 386 else if (stat_reg & (MMCHS_STAT_CTO | MMCHS_STAT_DTO)) 387 cmd->error = MMC_ERR_TIMEOUT; 388 else if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_DCRC)) 389 cmd->error = MMC_ERR_BADCRC; 390 else 391 cmd->error = MMC_ERR_FAILED; 392 393 /* If a dma transaction we should also stop the dma transfer */ 394 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DE) { 395 396 /* Abort the DMA transfer (DDIR bit tells direction) */ 397 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DDIR) 398#ifdef SOC_TI_AM335X 399 printf("%s: DMA unimplemented\n", __func__); 400#else 401 ti_sdma_stop_xfer(sc->sc_dmach_rd); 402#endif 403 else 404#ifdef SOC_TI_AM335X 405 printf("%s: DMA unimplemented\n", __func__); 406#else 407 ti_sdma_stop_xfer(sc->sc_dmach_wr); 408#endif 409 410 /* If an error occure abort the DMA operation and free the dma map */ 411 if ((sc->sc_dmamapped > 0) && (cmd->error != MMC_ERR_NONE)) { 412 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 413 sc->sc_dmamapped--; 414 } 415 } 416 417 /* Command error occured? ... if so issue a soft reset for the cmd fsm */ 418 if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_CTO)) { 419 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRC); 420 } 421 422 /* Data error occured? ... if so issue a soft reset for the data line */ 423 if (stat_reg & (MMCHS_STAT_DEB | MMCHS_STAT_DCRC | MMCHS_STAT_DTO)) { 424 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRD); 425 } 426 427 /* On any error the command is cancelled ... so we are done */ 428 return 1; 429} 430 431/** 432 * ti_mmchs_intr - interrupt handler for MMC/SD/SDIO controller 433 * @arg: pointer to the driver context 434 * 435 * Interrupt handler for the MMC/SD/SDIO controller, responsible for handling 436 * the IRQ and clearing the status flags. 437 * 438 * LOCKING: 439 * Called from interrupt context 440 * 441 * RETURNS: 442 * nothing 443 */ 444static void 445ti_mmchs_intr(void *arg) 446{ 447 struct ti_mmchs_softc *sc = (struct ti_mmchs_softc *) arg; 448 uint32_t stat_reg; 449 int done = 0; 450 451 TI_MMCHS_LOCK(sc); 452 453 stat_reg = ti_mmchs_read_4(sc, MMCHS_STAT) & (ti_mmchs_read_4(sc, 454 MMCHS_IE) | MMCHS_STAT_ERRI); 455 456 if (sc->curcmd == NULL) { 457 device_printf(sc->sc_dev, "Error: current cmd NULL, already done?\n"); 458 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg); 459 TI_MMCHS_UNLOCK(sc); 460 return; 461 } 462 463 if (stat_reg & MMCHS_STAT_ERRI) { 464 /* An error has been tripped in the status register */ 465 done = ti_mmchs_intr_error(sc, sc->curcmd, stat_reg); 466 467 } else { 468 469 /* NOTE: This implementation could be a bit inefficent, I don't think 470 * it is necessary to handle both the 'command complete' and 'transfer 471 * complete' for data transfers ... presumably just transfer complete 472 * is enough. 473 */ 474 475 /* No error */ 476 sc->curcmd->error = MMC_ERR_NONE; 477 478 /* Check if the command completed */ 479 if (stat_reg & MMCHS_STAT_CC) { 480 done = ti_mmchs_intr_cmd_compl(sc, sc->curcmd); 481 } 482 483 /* Check if the transfer has completed */ 484 if (stat_reg & MMCHS_STAT_TC) { 485 done = ti_mmchs_intr_xfer_compl(sc, sc->curcmd); 486 } 487 488 } 489 490 /* Clear all the interrupt status bits by writing the value back */ 491 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg); 492 493 /* This may mark the command as done if there is no stop request */ 494 /* TODO: This is a bit ugly, needs fix-up */ 495 if (done) { 496 ti_mmchs_start(sc); 497 } 498 499 TI_MMCHS_UNLOCK(sc); 500} 501 502#ifdef SOC_TI_AM335X 503static void 504ti_mmchs_edma3_rx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr, 505 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks) 506{ 507 struct ti_edma3cc_param_set ps; 508 509 bzero(&ps, sizeof(struct ti_edma3cc_param_set)); 510 ps.src = src_paddr; 511 ps.dst = dst_paddr; 512 ps.dstbidx = 4; 513 ps.dstcidx = blk_size; 514 ps.acnt = 4; 515 ps.bcnt = blk_size/4; 516 ps.ccnt = num_blks; 517 ps.link = 0xffff; 518 ps.opt.tcc = sc->dma_rx_trig; 519 ps.opt.tcinten = 1; 520 ps.opt.fwid = 2; /* fifo width is 32 */ 521 ps.opt.sam = 1; 522 ps.opt.syncdim = 1; 523 524 ti_edma3_param_write(sc->dma_rx_trig, &ps); 525 ti_edma3_enable_transfer_event(sc->dma_rx_trig); 526} 527 528static void 529ti_mmchs_edma3_tx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr, 530 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks) 531{ 532 struct ti_edma3cc_param_set ps; 533 534 bzero(&ps, sizeof(struct ti_edma3cc_param_set)); 535 ps.src = src_paddr; 536 ps.dst = dst_paddr; 537 ps.srccidx = blk_size; 538 ps.bcnt = blk_size/4; 539 ps.ccnt = num_blks; 540 ps.srcbidx = 4; 541 ps.acnt = 0x4; 542 ps.link = 0xffff; 543 ps.opt.tcc = sc->dma_tx_trig; 544 ps.opt.tcinten = 1; 545 ps.opt.fwid = 2; /* fifo width is 32 */ 546 ps.opt.dam = 1; 547 ps.opt.syncdim = 1; 548 549 ti_edma3_param_write(sc->dma_tx_trig, &ps); 550 ti_edma3_enable_transfer_event(sc->dma_tx_trig); 551} 552#endif 553 554/** 555 * ti_mmchs_start_cmd - starts the given command 556 * @sc: pointer to the driver context 557 * @cmd: the command to start 558 * 559 * The call tree for this function is 560 * - ti_mmchs_start_cmd 561 * - ti_mmchs_start 562 * - ti_mmchs_request 563 * 564 * LOCKING: 565 * Caller should be holding the OMAP_MMC lock. 566 * 567 * RETURNS: 568 * nothing 569 */ 570static void 571ti_mmchs_start_cmd(struct ti_mmchs_softc *sc, struct mmc_command *cmd) 572{ 573 uint32_t cmd_reg, con_reg, ise_reg; 574 struct mmc_data *data; 575 struct mmc_request *req; 576 void *vaddr; 577 bus_addr_t paddr; 578#ifndef SOC_TI_AM335X 579 uint32_t pktsize; 580#endif 581 sc->curcmd = cmd; 582 data = cmd->data; 583 req = cmd->mrq; 584 585 /* Ensure the STR and MIT bits are cleared, these are only used for special 586 * command types. 587 */ 588 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 589 con_reg &= ~(MMCHS_CON_STR | MMCHS_CON_MIT); 590 591 /* Load the command into bits 29:24 of the CMD register */ 592 cmd_reg = (uint32_t)(cmd->opcode & 0x3F) << 24; 593 594 /* Set the default set of interrupts */ 595 ise_reg = (MMCHS_STAT_CERR | MMCHS_STAT_CTO | MMCHS_STAT_CC | MMCHS_STAT_CEB); 596 597 /* Enable CRC checking if requested */ 598 if (cmd->flags & MMC_RSP_CRC) 599 ise_reg |= MMCHS_STAT_CCRC; 600 601 /* Enable reply index checking if the response supports it */ 602 if (cmd->flags & MMC_RSP_OPCODE) 603 ise_reg |= MMCHS_STAT_CIE; 604 605 /* Set the expected response length */ 606 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) { 607 cmd_reg |= MMCHS_CMD_RSP_TYPE_NO; 608 } else { 609 if (cmd->flags & MMC_RSP_136) 610 cmd_reg |= MMCHS_CMD_RSP_TYPE_136; 611 else if (cmd->flags & MMC_RSP_BUSY) 612 cmd_reg |= MMCHS_CMD_RSP_TYPE_48_BSY; 613 else 614 cmd_reg |= MMCHS_CMD_RSP_TYPE_48; 615 616 /* Enable command index/crc checks if necessary expected */ 617 if (cmd->flags & MMC_RSP_CRC) 618 cmd_reg |= MMCHS_CMD_CCCE; 619 if (cmd->flags & MMC_RSP_OPCODE) 620 cmd_reg |= MMCHS_CMD_CICE; 621 } 622 623 /* Set the bits for the special commands CMD12 (MMC_STOP_TRANSMISSION) and 624 * CMD52 (SD_IO_RW_DIRECT) */ 625 if (cmd->opcode == MMC_STOP_TRANSMISSION) 626 cmd_reg |= MMCHS_CMD_CMD_TYPE_IO_ABORT; 627 628 /* Check if there is any data to write */ 629 if (data == NULL) { 630 /* Clear the block count */ 631 ti_mmchs_write_4(sc, MMCHS_BLK, 0); 632 633 /* The no data case is fairly simple */ 634 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 635 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg); 636 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg); 637 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg); 638 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg); 639 return; 640 } 641 642 /* Indicate that data is present */ 643 cmd_reg |= MMCHS_CMD_DP | MMCHS_CMD_MSBS | MMCHS_CMD_BCE; 644 645 /* Indicate a read operation */ 646 if (data->flags & MMC_DATA_READ) 647 cmd_reg |= MMCHS_CMD_DDIR; 648 649 /* Streaming mode */ 650 if (data->flags & MMC_DATA_STREAM) { 651 con_reg |= MMCHS_CON_STR; 652 } 653 654 /* Multi-block mode */ 655 if (data->flags & MMC_DATA_MULTI) { 656 cmd_reg |= MMCHS_CMD_MSBS; 657 } 658 659 /* Enable extra interrupt sources for the transfer */ 660 ise_reg |= (MMCHS_STAT_TC | MMCHS_STAT_DTO | MMCHS_STAT_DEB | MMCHS_STAT_CEB); 661 if (cmd->flags & MMC_RSP_CRC) 662 ise_reg |= MMCHS_STAT_DCRC; 663 664 /* Enable the DMA transfer bit */ 665 cmd_reg |= MMCHS_CMD_DE; 666 667 /* Set the block size and block count */ 668 ti_mmchs_write_4(sc, MMCHS_BLK, (1 << 16) | data->len); 669 670 /* Setup the DMA stuff */ 671 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) { 672 673 vaddr = data->data; 674 data->xfer_len = 0; 675 676 /* Map the buffer buf into bus space using the dmamap map. */ 677 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, vaddr, data->len, 678 ti_mmchs_getaddr, &paddr, 0) != 0) { 679 680 if (req->cmd->flags & STOP_STARTED) 681 req->stop->error = MMC_ERR_NO_MEMORY; 682 else 683 req->cmd->error = MMC_ERR_NO_MEMORY; 684 sc->req = NULL; 685 sc->curcmd = NULL; 686 req->done(req); 687 return; 688 } 689 690#ifndef SOC_TI_AM335X 691 /* Calculate the packet size, the max packet size is 512 bytes 692 * (or 128 32-bit elements). 693 */ 694 pktsize = min((data->len / 4), (512 / 4)); 695#endif 696 /* Sync the DMA buffer and setup the DMA controller */ 697 if (data->flags & MMC_DATA_READ) { 698 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREREAD); 699#ifdef SOC_TI_AM335X 700 ti_mmchs_edma3_rx_xfer_setup(sc, sc->sc_data_reg_paddr, 701 paddr, data->len, 1); 702#else 703 ti_sdma_start_xfer_packet(sc->sc_dmach_rd, sc->sc_data_reg_paddr, 704 paddr, 1, (data->len / 4), pktsize); 705#endif 706 } else { 707 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREWRITE); 708#ifdef SOC_TI_AM335X 709 ti_mmchs_edma3_tx_xfer_setup(sc, paddr, 710 sc->sc_data_reg_paddr, data->len, 1); 711#else 712 ti_sdma_start_xfer_packet(sc->sc_dmach_wr, paddr, 713 sc->sc_data_reg_paddr, 1, (data->len / 4), pktsize); 714#endif 715 } 716 717 /* Increase the mapped count */ 718 sc->sc_dmamapped++; 719 720 sc->sc_cmd_data_vaddr = vaddr; 721 sc->sc_cmd_data_len = data->len; 722 } 723 724 /* Finally kick off the command */ 725 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 726 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg); 727 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg); 728 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg); 729 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg); 730 731 /* and we're done */ 732} 733 734/** 735 * ti_mmchs_start - starts a request stored in the driver context 736 * @sc: pointer to the driver context 737 * 738 * This function is called by ti_mmchs_request() in response to a read/write 739 * request from the MMC core module. 740 * 741 * LOCKING: 742 * Caller should be holding the OMAP_MMC lock. 743 * 744 * RETURNS: 745 * nothing 746 */ 747static void 748ti_mmchs_start(struct ti_mmchs_softc *sc) 749{ 750 struct mmc_request *req; 751 752 /* Sanity check we have a request */ 753 req = sc->req; 754 if (req == NULL) 755 return; 756 757 /* assert locked */ 758 if (!(sc->flags & CMD_STARTED)) { 759 sc->flags |= CMD_STARTED; 760 ti_mmchs_start_cmd(sc, req->cmd); 761 return; 762 } 763 764 if (!(sc->flags & STOP_STARTED) && req->stop) { 765 sc->flags |= STOP_STARTED; 766 ti_mmchs_start_cmd(sc, req->stop); 767 return; 768 } 769 770 /* We must be done -- bad idea to do this while locked? */ 771 sc->req = NULL; 772 sc->curcmd = NULL; 773 req->done(req); 774} 775 776/** 777 * ti_mmchs_request - entry point for all read/write/cmd requests 778 * @brdev: mmc bridge device handle 779 * @reqdev: the device doing the requesting ? 780 * @req: the action requested 781 * 782 * LOCKING: 783 * None, internally takes the OMAP_MMC lock. 784 * 785 * RETURNS: 786 * 0 on success 787 * EBUSY if the driver is already performing a request 788 */ 789static int 790ti_mmchs_request(device_t brdev, device_t reqdev, struct mmc_request *req) 791{ 792 struct ti_mmchs_softc *sc = device_get_softc(brdev); 793 794 TI_MMCHS_LOCK(sc); 795 796 /* 797 * XXX do we want to be able to queue up multiple commands? 798 * XXX sounds like a good idea, but all protocols are sync, so 799 * XXX maybe the idea is naive... 800 */ 801 if (sc->req != NULL) { 802 TI_MMCHS_UNLOCK(sc); 803 return (EBUSY); 804 } 805 806 /* Store the request and start the command */ 807 sc->req = req; 808 sc->flags = 0; 809 ti_mmchs_start(sc); 810 811 TI_MMCHS_UNLOCK(sc); 812 813 return (0); 814} 815 816/** 817 * ti_mmchs_get_ro - returns the status of the read-only setting 818 * @brdev: mmc bridge device handle 819 * @reqdev: device doing the request 820 * 821 * This function is relies on hint'ed values to determine which GPIO is used 822 * to determine if the write protect is enabled. On the BeagleBoard the pin 823 * is GPIO_23. 824 * 825 * LOCKING: 826 * - 827 * 828 * RETURNS: 829 * 0 if not read-only 830 * 1 if read only 831 */ 832static int 833ti_mmchs_get_ro(device_t brdev, device_t reqdev) 834{ 835 struct ti_mmchs_softc *sc = device_get_softc(brdev); 836 unsigned int readonly = 0; 837 838 TI_MMCHS_LOCK(sc); 839 840 if ((sc->sc_wp_gpio_pin != -1) && (sc->sc_gpio_dev != NULL)) { 841 if (GPIO_PIN_GET(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, &readonly) != 0) 842 readonly = 0; 843 else 844 readonly = (readonly == 0) ? 0 : 1; 845 } 846 847 TI_MMCHS_UNLOCK(sc); 848 849 return (readonly); 850} 851 852/** 853 * ti_mmchs_send_init_stream - sets bus/controller settings 854 * @brdev: mmc bridge device handle 855 * @reqdev: device doing the request 856 * 857 * Send init stream sequence to card before sending IDLE command 858 * 859 * LOCKING: 860 * 861 * 862 * RETURNS: 863 * 0 if function succeeded 864 */ 865static void 866ti_mmchs_send_init_stream(struct ti_mmchs_softc *sc) 867{ 868 unsigned long timeout; 869 uint32_t ie, ise, con; 870 871 ti_mmchs_dbg(sc, "Performing init sequence\n"); 872 873 /* Prior to issuing any command, the MMCHS controller has to execute a 874 * special INIT procedure. The MMCHS controller has to generate a clock 875 * during 1ms. During the INIT procedure, the MMCHS controller generates 80 876 * clock periods. In order to keep the 1ms gap, the MMCHS controller should 877 * be configured to generate a clock whose frequency is smaller or equal to 878 * 80 KHz. If the MMCHS controller divider bitfield width doesn't allow to 879 * choose big values, the MMCHS controller driver should perform the INIT 880 * procedure twice or three times. Twice is generally enough. 881 * 882 * The INIt procedure is executed by setting MMCHS1.MMCHS_CON[1] INIT 883 * bitfield to 1 and by sending a dummy command, writing 0x00000000 in 884 * MMCHS1.MMCHS_CMD register. 885 */ 886 887 /* Disable interrupt status events but enable interrupt generation. 888 * This doesn't seem right to me, but if the interrupt generation is not 889 * enabled the CC bit doesn't seem to be set in the STAT register. 890 */ 891 892 /* Enable interrupt generation */ 893 ie = ti_mmchs_read_4(sc, MMCHS_IE); 894 ti_mmchs_write_4(sc, MMCHS_IE, 0x307F0033); 895 896 /* Disable generation of status events (stops interrupt triggering) */ 897 ise = ti_mmchs_read_4(sc, MMCHS_ISE); 898 ti_mmchs_write_4(sc, MMCHS_ISE, 0); 899 900 /* Set the initialise stream bit */ 901 con = ti_mmchs_read_4(sc, MMCHS_CON); 902 con |= MMCHS_CON_INIT; 903 ti_mmchs_write_4(sc, MMCHS_CON, con); 904 905 /* Write a dummy command 0x00 */ 906 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000); 907 908 /* Loop waiting for the command to finish */ 909 timeout = hz; 910 do { 911 pause("MMCINIT", 1); 912 if (timeout-- == 0) { 913 device_printf(sc->sc_dev, "Error: first stream init timed out\n"); 914 break; 915 } 916 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC)); 917 918 /* Clear the command complete status bit */ 919 ti_mmchs_write_4(sc, MMCHS_STAT, MMCHS_STAT_CC); 920 921 /* Write another dummy command 0x00 */ 922 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000); 923 924 /* Loop waiting for the second command to finish */ 925 timeout = hz; 926 do { 927 pause("MMCINIT", 1); 928 if (timeout-- == 0) { 929 device_printf(sc->sc_dev, "Error: second stream init timed out\n"); 930 break; 931 } 932 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC)); 933 934 /* Clear the stream init bit */ 935 con &= ~MMCHS_CON_INIT; 936 ti_mmchs_write_4(sc, MMCHS_CON, con); 937 938 /* Clear the status register, then restore the IE and ISE registers */ 939 ti_mmchs_write_4(sc, MMCHS_STAT, 0xffffffff); 940 ti_mmchs_read_4(sc, MMCHS_STAT); 941 942 ti_mmchs_write_4(sc, MMCHS_ISE, ise); 943 ti_mmchs_write_4(sc, MMCHS_IE, ie); 944} 945 946/** 947 * ti_mmchs_update_ios - sets bus/controller settings 948 * @brdev: mmc bridge device handle 949 * @reqdev: device doing the request 950 * 951 * Called to set the bus and controller settings that need to be applied to 952 * the actual HW. Currently this function just sets the bus width and the 953 * clock speed. 954 * 955 * LOCKING: 956 * 957 * 958 * RETURNS: 959 * 0 if function succeeded 960 */ 961static int 962ti_mmchs_update_ios(device_t brdev, device_t reqdev) 963{ 964 struct ti_mmchs_softc *sc; 965 struct mmc_host *host; 966 struct mmc_ios *ios; 967 uint32_t clkdiv; 968 uint32_t hctl_reg; 969 uint32_t con_reg; 970 uint32_t sysctl_reg; 971#ifndef SOC_TI_AM335X 972 uint16_t mv; 973#endif 974 unsigned long timeout; 975 int do_card_init = 0; 976 977 sc = device_get_softc(brdev); 978 host = &sc->host; 979 ios = &host->ios; 980 981 /* Read the initial values of the registers */ 982 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 983 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 984 985 /* Set the bus width */ 986 switch (ios->bus_width) { 987 case bus_width_1: 988 hctl_reg &= ~MMCHS_HCTL_DTW; 989 con_reg &= ~MMCHS_CON_DW8; 990 break; 991 case bus_width_4: 992 hctl_reg |= MMCHS_HCTL_DTW; 993 con_reg &= ~MMCHS_CON_DW8; 994 break; 995 case bus_width_8: 996 con_reg |= MMCHS_CON_DW8; 997 break; 998 } 999 1000 /* Finally write all these settings back to the registers */ 1001 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg); 1002 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 1003 1004 /* Check if we need to change the external voltage regulator */ 1005 if (sc->sc_cur_power_mode != ios->power_mode) { 1006 1007 if (ios->power_mode == power_up) { 1008 1009 /* Set the power level */ 1010 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 1011 hctl_reg &= ~(MMCHS_HCTL_SDVS_MASK | MMCHS_HCTL_SDBP); 1012 1013 if ((ios->vdd == -1) || (ios->vdd >= vdd_240)) { 1014#ifndef SOC_TI_AM335X 1015 mv = 3000; 1016#endif 1017 hctl_reg |= MMCHS_HCTL_SDVS_V30; 1018 } else { 1019#ifndef SOC_TI_AM335X 1020 mv = 1800; 1021#endif 1022 hctl_reg |= MMCHS_HCTL_SDVS_V18; 1023 } 1024 1025 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg); 1026 1027#ifdef SOC_TI_AM335X 1028 printf("%s: TWL unimplemented\n", __func__); 1029#else 1030 /* Set the desired voltage on the regulator */ 1031 if (sc->sc_vreg_dev && sc->sc_vreg_name) 1032 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, mv); 1033#endif 1034 /* Enable the bus power */ 1035 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg | MMCHS_HCTL_SDBP)); 1036 timeout = hz; 1037 while (!(ti_mmchs_read_4(sc, MMCHS_HCTL) & MMCHS_HCTL_SDBP)) { 1038 if (timeout-- == 0) 1039 break; 1040 pause("MMC_PWRON", 1); 1041 } 1042 1043 } else if (ios->power_mode == power_off) { 1044 /* Disable the bus power */ 1045 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL); 1046 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg & ~MMCHS_HCTL_SDBP)); 1047 1048#ifdef SOC_TI_AM335X 1049 printf("%s: TWL unimplemented\n", __func__); 1050#else 1051 /* Turn the power off on the voltage regulator */ 1052 if (sc->sc_vreg_dev && sc->sc_vreg_name) 1053 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, 0); 1054#endif 1055 } else if (ios->power_mode == power_on) { 1056 /* Force a card re-initialisation sequence */ 1057 do_card_init = 1; 1058 } 1059 1060 /* Save the new power state */ 1061 sc->sc_cur_power_mode = ios->power_mode; 1062 } 1063 1064 /* need the MMCHS_SYSCTL register */ 1065 sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 1066 1067 /* Just in case this hasn't been setup before, set the timeout to the default */ 1068 sysctl_reg &= ~MMCHS_SYSCTL_DTO_MASK; 1069 sysctl_reg |= MMCHS_SYSCTL_DTO(0xe); 1070 1071 /* Disable the clock output while configuring the new clock */ 1072 sysctl_reg &= ~(MMCHS_SYSCTL_ICE | MMCHS_SYSCTL_CEN); 1073 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1074 1075 /* bus mode? */ 1076 if (ios->clock == 0) { 1077 clkdiv = 0; 1078 } else { 1079 clkdiv = sc->sc_ref_freq / ios->clock; 1080 if (clkdiv < 1) 1081 clkdiv = 1; 1082 if ((sc->sc_ref_freq / clkdiv) > ios->clock) 1083 clkdiv += 1; 1084 if (clkdiv > 250) 1085 clkdiv = 250; 1086 } 1087 1088 /* Set the new clock divider */ 1089 sysctl_reg &= ~MMCHS_SYSCTL_CLKD_MASK; 1090 sysctl_reg |= MMCHS_SYSCTL_CLKD(clkdiv); 1091 1092 /* Write the new settings ... */ 1093 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1094 /* ... write the internal clock enable bit ... */ 1095 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg | MMCHS_SYSCTL_ICE); 1096 /* ... wait for the clock to stablise ... */ 1097 while (((sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL)) & 1098 MMCHS_SYSCTL_ICS) == 0) { 1099 continue; 1100 } 1101 /* ... then enable */ 1102 sysctl_reg |= MMCHS_SYSCTL_CEN; 1103 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg); 1104 1105 /* If the power state has changed to 'power_on' then run the init sequence*/ 1106 if (do_card_init) { 1107 ti_mmchs_send_init_stream(sc); 1108 } 1109 1110 /* Set the bus mode (opendrain or normal) */ 1111 con_reg = ti_mmchs_read_4(sc, MMCHS_CON); 1112 if (ios->bus_mode == opendrain) 1113 con_reg |= MMCHS_CON_OD; 1114 else 1115 con_reg &= ~MMCHS_CON_OD; 1116 ti_mmchs_write_4(sc, MMCHS_CON, con_reg); 1117 1118 return (0); 1119} 1120 1121/** 1122 * ti_mmchs_acquire_host - 1123 * @brdev: mmc bridge device handle 1124 * @reqdev: device doing the request 1125 * 1126 * TODO: Is this function needed ? 1127 * 1128 * LOCKING: 1129 * none 1130 * 1131 * RETURNS: 1132 * 0 function succeeded 1133 * 1134 */ 1135static int 1136ti_mmchs_acquire_host(device_t brdev, device_t reqdev) 1137{ 1138 struct ti_mmchs_softc *sc = device_get_softc(brdev); 1139 int err = 0; 1140 1141 TI_MMCHS_LOCK(sc); 1142 1143 while (sc->bus_busy) { 1144 msleep(sc, &sc->sc_mtx, PZERO, "mmc", hz / 5); 1145 } 1146 1147 sc->bus_busy++; 1148 1149 TI_MMCHS_UNLOCK(sc); 1150 1151 return (err); 1152} 1153 1154/** 1155 * ti_mmchs_release_host - 1156 * @brdev: mmc bridge device handle 1157 * @reqdev: device doing the request 1158 * 1159 * TODO: Is this function needed ? 1160 * 1161 * LOCKING: 1162 * none 1163 * 1164 * RETURNS: 1165 * 0 function succeeded 1166 * 1167 */ 1168static int 1169ti_mmchs_release_host(device_t brdev, device_t reqdev) 1170{ 1171 struct ti_mmchs_softc *sc = device_get_softc(brdev); 1172 1173 TI_MMCHS_LOCK(sc); 1174 1175 sc->bus_busy--; 1176 wakeup(sc); 1177 1178 TI_MMCHS_UNLOCK(sc); 1179 1180 return (0); 1181} 1182 1183/** 1184 * ti_mmchs_read_ivar - returns driver conf variables 1185 * @bus: 1186 * @child: 1187 * @which: The variable to get the result for 1188 * @result: Upon return will store the variable value 1189 * 1190 * 1191 * 1192 * LOCKING: 1193 * None, caller must hold locks 1194 * 1195 * RETURNS: 1196 * 0 on success 1197 * EINVAL if the variable requested is invalid 1198 */ 1199static int 1200ti_mmchs_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1201{ 1202 struct ti_mmchs_softc *sc = device_get_softc(bus); 1203 1204 switch (which) { 1205 case MMCBR_IVAR_BUS_MODE: 1206 *(int *)result = sc->host.ios.bus_mode; 1207 break; 1208 case MMCBR_IVAR_BUS_WIDTH: 1209 *(int *)result = sc->host.ios.bus_width; 1210 break; 1211 case MMCBR_IVAR_CHIP_SELECT: 1212 *(int *)result = sc->host.ios.chip_select; 1213 break; 1214 case MMCBR_IVAR_CLOCK: 1215 *(int *)result = sc->host.ios.clock; 1216 break; 1217 case MMCBR_IVAR_F_MIN: 1218 *(int *)result = sc->host.f_min; 1219 break; 1220 case MMCBR_IVAR_F_MAX: 1221 *(int *)result = sc->host.f_max; 1222 break; 1223 case MMCBR_IVAR_HOST_OCR: 1224 *(int *)result = sc->host.host_ocr; 1225 break; 1226 case MMCBR_IVAR_MODE: 1227 *(int *)result = sc->host.mode; 1228 break; 1229 case MMCBR_IVAR_OCR: 1230 *(int *)result = sc->host.ocr; 1231 break; 1232 case MMCBR_IVAR_POWER_MODE: 1233 *(int *)result = sc->host.ios.power_mode; 1234 break; 1235 case MMCBR_IVAR_VDD: 1236 *(int *)result = sc->host.ios.vdd; 1237 break; 1238 case MMCBR_IVAR_CAPS: 1239 *(int *)result = sc->host.caps; 1240 break; 1241 case MMCBR_IVAR_MAX_DATA: 1242 *(int *)result = 1; 1243 break; 1244 default: 1245 return (EINVAL); 1246 } 1247 return (0); 1248} 1249 1250/** 1251 * ti_mmchs_write_ivar - writes a driver conf variables 1252 * @bus: 1253 * @child: 1254 * @which: The variable to set 1255 * @value: The value to write into the variable 1256 * 1257 * 1258 * 1259 * LOCKING: 1260 * None, caller must hold locks 1261 * 1262 * RETURNS: 1263 * 0 on success 1264 * EINVAL if the variable requested is invalid 1265 */ 1266static int 1267ti_mmchs_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1268{ 1269 struct ti_mmchs_softc *sc = device_get_softc(bus); 1270 1271 switch (which) { 1272 case MMCBR_IVAR_BUS_MODE: 1273 sc->host.ios.bus_mode = value; 1274 break; 1275 case MMCBR_IVAR_BUS_WIDTH: 1276 sc->host.ios.bus_width = value; 1277 break; 1278 case MMCBR_IVAR_CHIP_SELECT: 1279 sc->host.ios.chip_select = value; 1280 break; 1281 case MMCBR_IVAR_CLOCK: 1282 sc->host.ios.clock = value; 1283 break; 1284 case MMCBR_IVAR_MODE: 1285 sc->host.mode = value; 1286 break; 1287 case MMCBR_IVAR_OCR: 1288 sc->host.ocr = value; 1289 break; 1290 case MMCBR_IVAR_POWER_MODE: 1291 sc->host.ios.power_mode = value; 1292 break; 1293 case MMCBR_IVAR_VDD: 1294 sc->host.ios.vdd = value; 1295 break; 1296 /* These are read-only */ 1297 case MMCBR_IVAR_CAPS: 1298 case MMCBR_IVAR_HOST_OCR: 1299 case MMCBR_IVAR_F_MIN: 1300 case MMCBR_IVAR_F_MAX: 1301 case MMCBR_IVAR_MAX_DATA: 1302 return (EINVAL); 1303 default: 1304 return (EINVAL); 1305 } 1306 return (0); 1307} 1308 1309/** 1310 * ti_mmchs_hw_init - initialises the MMC/SD/SIO controller 1311 * @dev: mmc device handle 1312 * 1313 * Called by the driver attach function during driver initialisation. This 1314 * function is responsibly to setup the controller ready for transactions. 1315 * 1316 * LOCKING: 1317 * No locking, assumed to only be called during initialisation. 1318 * 1319 * RETURNS: 1320 * nothing 1321 */ 1322static void 1323ti_mmchs_hw_init(device_t dev) 1324{ 1325 struct ti_mmchs_softc *sc = device_get_softc(dev); 1326 clk_ident_t clk; 1327 unsigned long timeout; 1328 uint32_t sysctl; 1329 uint32_t capa; 1330 uint32_t con, sysconfig; 1331 1332 /* 1: Enable the controller and interface/functional clocks */ 1333 clk = MMC0_CLK + sc->device_id; 1334 1335 if (ti_prcm_clk_enable(clk) != 0) { 1336 device_printf(dev, "Error: failed to enable MMC clock\n"); 1337 return; 1338 } 1339 1340 /* 1a: Get the frequency of the source clock */ 1341 if (ti_prcm_clk_get_source_freq(clk, &sc->sc_ref_freq) != 0) { 1342 device_printf(dev, "Error: failed to get source clock freq\n"); 1343 return; 1344 } 1345 1346 /* 2: Issue a softreset to the controller */ 1347 sysconfig = ti_mmchs_read_4(sc, MMCHS_SYSCONFIG); 1348 sysconfig |= MMCHS_SYSCONFIG_SRST; 1349 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, sysconfig); 1350 timeout = 100; 1351 while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 0x01) == 0x0) { 1352 DELAY(1000); 1353 if (timeout-- == 0) { 1354 device_printf(dev, "Error: reset operation timed out\n"); 1355 return; 1356 } 1357 } 1358 1359 /* 3: Reset both the command and data state machines */ 1360 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL); 1361 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | MMCHS_SYSCTL_SRA); 1362 timeout = 100; 1363 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & MMCHS_SYSCTL_SRA) != 0x0) { 1364 DELAY(1000); 1365 if (timeout-- == 0) { 1366 device_printf(dev, "Error: reset operation timed out\n"); 1367 return; 1368 } 1369 } 1370 1371 /* 4: Set initial host configuration (1-bit mode, pwroff) and capabilities */ 1372 ti_mmchs_write_4(sc, MMCHS_HCTL, MMCHS_HCTL_SDVS_V30); 1373 1374 capa = ti_mmchs_read_4(sc, MMCHS_CAPA); 1375 ti_mmchs_write_4(sc, MMCHS_CAPA, capa | MMCHS_CAPA_VS30 | MMCHS_CAPA_VS18); 1376 1377 /* 5: Set the initial bus configuration 1378 * 0 CTPL_MMC_SD : Control Power for DAT1 line 1379 * 0 WPP_ACTIVE_HIGH : Write protect polarity 1380 * 0 CDP_ACTIVE_HIGH : Card detect polarity 1381 * 0 CTO_ENABLED : MMC interrupt command 1382 * 0 DW8_DISABLED : 8-bit mode MMC select 1383 * 0 MODE_FUNC : Mode select 1384 * 0 STREAM_DISABLED : Stream command 1385 * 0 HR_DISABLED : Broadcast host response 1386 * 0 INIT_DISABLED : Send initialization stream 1387 * 0 OD_DISABLED : No Open Drain 1388 */ 1389 con = ti_mmchs_read_4(sc, MMCHS_CON) & MMCHS_CON_DVAL_MASK; 1390 ti_mmchs_write_4(sc, MMCHS_CON, con); 1391 1392} 1393 1394/** 1395 * ti_mmchs_fini - shutdown the MMC/SD/SIO controller 1396 * @dev: mmc device handle 1397 * 1398 * Responsible for shutting done the MMC controller, this function may be 1399 * called as part of a reset sequence. 1400 * 1401 * LOCKING: 1402 * No locking, assumed to be called during tear-down/reset. 1403 * 1404 * RETURNS: 1405 * nothing 1406 */ 1407static void 1408ti_mmchs_hw_fini(device_t dev) 1409{ 1410 struct ti_mmchs_softc *sc = device_get_softc(dev); 1411 1412 /* Disable all interrupts */ 1413 ti_mmchs_write_4(sc, MMCHS_ISE, 0x00000000); 1414 ti_mmchs_write_4(sc, MMCHS_IE, 0x00000000); 1415 1416 /* Disable the functional and interface clocks */ 1417 ti_prcm_clk_disable(MMC0_CLK + sc->device_id); 1418} 1419 1420/** 1421 * ti_mmchs_init_dma_channels - initalise the DMA channels 1422 * @sc: driver soft context 1423 * 1424 * Attempts to activate an RX and TX DMA channel for the MMC device. 1425 * 1426 * LOCKING: 1427 * No locking, assumed to be called during tear-down/reset. 1428 * 1429 * RETURNS: 1430 * 0 on success, a negative error code on failure. 1431 */ 1432static int 1433ti_mmchs_init_dma_channels(struct ti_mmchs_softc *sc) 1434{ 1435#ifdef SOC_TI_AM335X 1436 switch (sc->device_id) { 1437 case 0: 1438 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT0; 1439 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT0; 1440 break; 1441 case 1: 1442 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT1; 1443 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT1; 1444 break; 1445 default: 1446 return(EINVAL); 1447 } 1448 1449#define EVTQNUM 0 1450 /* TODO EDMA3 have 3 queues, so we need some queue allocation call */ 1451 ti_edma3_init(EVTQNUM); 1452 ti_edma3_request_dma_ch(sc->dma_tx_trig, sc->dma_tx_trig, EVTQNUM); 1453 ti_edma3_request_dma_ch(sc->dma_rx_trig, sc->dma_rx_trig, EVTQNUM); 1454#else 1455 int err; 1456 uint32_t rev; 1457 1458 /* Get the current chip revision */ 1459 rev = ti_revision(); 1460 if ((OMAP_REV_DEVICE(rev) != OMAP4430_DEV) && (sc->device_id > 3)) 1461 return(EINVAL); 1462 1463 /* Get the DMA MMC triggers */ 1464 switch (sc->device_id) { 1465 case 1: 1466 sc->dma_tx_trig = 60; 1467 sc->dma_rx_trig = 61; 1468 break; 1469 case 2: 1470 sc->dma_tx_trig = 46; 1471 sc->dma_rx_trig = 47; 1472 break; 1473 case 3: 1474 sc->dma_tx_trig = 76; 1475 sc->dma_rx_trig = 77; 1476 break; 1477 /* The following are OMAP4 only */ 1478 case 4: 1479 sc->dma_tx_trig = 56; 1480 sc->dma_rx_trig = 57; 1481 break; 1482 case 5: 1483 sc->dma_tx_trig = 58; 1484 sc->dma_rx_trig = 59; 1485 break; 1486 default: 1487 return(EINVAL); 1488 } 1489 1490 /* Activate a RX channel from the OMAP DMA driver */ 1491 err = ti_sdma_activate_channel(&sc->sc_dmach_rd, ti_mmchs_dma_intr, sc); 1492 if (err != 0) 1493 return(err); 1494 1495 /* Setup the RX channel for MMC data transfers */ 1496 ti_sdma_set_xfer_burst(sc->sc_dmach_rd, TI_SDMA_BURST_NONE, 1497 TI_SDMA_BURST_64); 1498 ti_sdma_set_xfer_data_type(sc->sc_dmach_rd, TI_SDMA_DATA_32BITS_SCALAR); 1499 ti_sdma_sync_params(sc->sc_dmach_rd, sc->dma_rx_trig, 1500 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_SRC); 1501 ti_sdma_set_addr_mode(sc->sc_dmach_rd, TI_SDMA_ADDR_CONSTANT, 1502 TI_SDMA_ADDR_POST_INCREMENT); 1503 1504 /* Activate and configure the TX DMA channel */ 1505 err = ti_sdma_activate_channel(&sc->sc_dmach_wr, ti_mmchs_dma_intr, sc); 1506 if (err != 0) 1507 return(err); 1508 1509 /* Setup the TX channel for MMC data transfers */ 1510 ti_sdma_set_xfer_burst(sc->sc_dmach_wr, TI_SDMA_BURST_64, 1511 TI_SDMA_BURST_NONE); 1512 ti_sdma_set_xfer_data_type(sc->sc_dmach_wr, TI_SDMA_DATA_32BITS_SCALAR); 1513 ti_sdma_sync_params(sc->sc_dmach_wr, sc->dma_tx_trig, 1514 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_DST); 1515 ti_sdma_set_addr_mode(sc->sc_dmach_wr, TI_SDMA_ADDR_POST_INCREMENT, 1516 TI_SDMA_ADDR_CONSTANT); 1517#endif 1518 return(0); 1519} 1520 1521/** 1522 * ti_mmchs_deactivate - deactivates the driver 1523 * @dev: mmc device handle 1524 * 1525 * Unmaps the register set and releases the IRQ resource. 1526 * 1527 * LOCKING: 1528 * None required 1529 * 1530 * RETURNS: 1531 * nothing 1532 */ 1533static void 1534ti_mmchs_deactivate(device_t dev) 1535{ 1536 struct ti_mmchs_softc *sc= device_get_softc(dev); 1537 1538 /* Remove the IRQ handler */ 1539 if (sc->sc_irq_h != NULL) { 1540 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 1541 sc->sc_irq_h = NULL; 1542 } 1543 1544 /* Do the generic detach */ 1545 bus_generic_detach(sc->sc_dev); 1546 1547#ifdef SOC_TI_AM335X 1548 printf("%s: DMA unimplemented\n", __func__); 1549#else 1550 /* Deactivate the DMA channels */ 1551 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1552 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1553#endif 1554 1555 /* Unmap the MMC controller registers */ 1556 if (sc->sc_mem_res != 0) { 1557 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_irq_res), 1558 sc->sc_mem_res); 1559 sc->sc_mem_res = NULL; 1560 } 1561 1562 /* Release the IRQ resource */ 1563 if (sc->sc_irq_res != NULL) { 1564 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res), 1565 sc->sc_irq_res); 1566 sc->sc_irq_res = NULL; 1567 } 1568 1569 return; 1570} 1571 1572/** 1573 * ti_mmchs_activate - activates the driver 1574 * @dev: mmc device handle 1575 * 1576 * Maps in the register set and requests an IRQ handler for the MMC controller. 1577 * 1578 * LOCKING: 1579 * None required 1580 * 1581 * RETURNS: 1582 * 0 on sucess 1583 * ENOMEM if failed to map register set 1584 */ 1585static int 1586ti_mmchs_activate(device_t dev) 1587{ 1588 struct ti_mmchs_softc *sc = device_get_softc(dev); 1589 int rid; 1590 int err; 1591 1592 /* Get the memory resource for the register mapping */ 1593 rid = 0; 1594 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1595 RF_ACTIVE); 1596 if (sc->sc_mem_res == NULL) 1597 panic("%s: Cannot map registers", device_get_name(dev)); 1598 1599 /* Allocate an IRQ resource for the MMC controller */ 1600 rid = 0; 1601 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1602 RF_ACTIVE | RF_SHAREABLE); 1603 if (sc->sc_irq_res == NULL) 1604 goto errout; 1605 1606 /* Allocate DMA tags and maps */ 1607 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1608 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1609 NULL, MAXPHYS, 1, MAXPHYS, BUS_DMA_ALLOCNOW, NULL, 1610 NULL, &sc->sc_dmatag); 1611 if (err != 0) 1612 goto errout; 1613 1614 err = bus_dmamap_create(sc->sc_dmatag, 0, &sc->sc_dmamap); 1615 if (err != 0) 1616 goto errout; 1617 1618 /* Initialise the DMA channels to be used by the controller */ 1619 err = ti_mmchs_init_dma_channels(sc); 1620 if (err != 0) 1621 goto errout; 1622 1623 /* Set the register offset */ 1624 if (ti_chip() == CHIP_OMAP_3) 1625 sc->sc_reg_off = OMAP3_MMCHS_REG_OFFSET; 1626 else if (ti_chip() == CHIP_OMAP_4) 1627 sc->sc_reg_off = OMAP4_MMCHS_REG_OFFSET; 1628 else if (ti_chip() == CHIP_AM335X) 1629 sc->sc_reg_off = AM335X_MMCHS_REG_OFFSET; 1630 else 1631 panic("Unknown OMAP device\n"); 1632 1633 /* Get the physical address of the MMC data register, needed for DMA */ 1634 sc->sc_data_reg_paddr = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 1635 sc->sc_reg_off + MMCHS_DATA); 1636 1637 /* Set the initial power state to off */ 1638 sc->sc_cur_power_mode = power_off; 1639 1640 return (0); 1641 1642errout: 1643 ti_mmchs_deactivate(dev); 1644 return (ENOMEM); 1645} 1646 1647/** 1648 * ti_mmchs_probe - probe function for the driver 1649 * @dev: mmc device handle 1650 * 1651 * 1652 * 1653 * RETURNS: 1654 * always returns 0 1655 */ 1656static int 1657ti_mmchs_probe(device_t dev) 1658{ 1659 1660 if (!ofw_bus_status_okay(dev)) 1661 return (ENXIO); 1662 1663 if (!ofw_bus_is_compatible(dev, "ti,mmchs")) 1664 return (ENXIO); 1665 1666 device_set_desc(dev, "TI MMC/SD/SDIO High Speed Interface"); 1667 return (0); 1668} 1669 1670/** 1671 * ti_mmchs_attach - attach function for the driver 1672 * @dev: mmc device handle 1673 * 1674 * Driver initialisation, sets-up the bus mappings, DMA mapping/channels and 1675 * the actual controller by calling ti_mmchs_init(). 1676 * 1677 * RETURNS: 1678 * Returns 0 on success or a negative error code. 1679 */ 1680static int 1681ti_mmchs_attach(device_t dev) 1682{ 1683 struct ti_mmchs_softc *sc = device_get_softc(dev); 1684 int unit = device_get_unit(dev); 1685 phandle_t node; 1686 pcell_t did; 1687 int err; 1688 1689 /* Save the device and bus tag */ 1690 sc->sc_dev = dev; 1691 1692 /* Get the mmchs device id from FDT */ 1693 node = ofw_bus_get_node(dev); 1694 if ((OF_getprop(node, "mmchs-device-id", &did, sizeof(did))) <= 0) { 1695 device_printf(dev, "missing mmchs-device-id attribute in FDT\n"); 1696 return (ENXIO); 1697 } 1698 sc->device_id = fdt32_to_cpu(did); 1699 1700 /* Initiate the mtex lock */ 1701 TI_MMCHS_LOCK_INIT(sc); 1702 1703 /* Indicate the DMA channels haven't yet been allocated */ 1704 sc->sc_dmach_rd = (unsigned int)-1; 1705 sc->sc_dmach_wr = (unsigned int)-1; 1706 1707 /* Get the hint'ed write detect pin */ 1708 /* TODO: take this from FDT */ 1709 if (resource_int_value("ti_mmchs", unit, "wp_gpio", &sc->sc_wp_gpio_pin) != 0){ 1710 sc->sc_wp_gpio_pin = -1; 1711 } else { 1712 /* Get the GPIO device, we need this for the write protect pin */ 1713 sc->sc_gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 1714 if (sc->sc_gpio_dev == NULL) 1715 device_printf(dev, "Error: failed to get the GPIO device\n"); 1716 else 1717 GPIO_PIN_SETFLAGS(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, 1718 GPIO_PIN_INPUT); 1719 } 1720 1721 /* Get the TWL voltage regulator device, we need this to for setting the 1722 * voltage of the bus on certain OMAP platforms. 1723 */ 1724 sc->sc_vreg_name = NULL; 1725 1726 /* TODO: add voltage regulator knob to FDT */ 1727#ifdef notyet 1728 sc->sc_vreg_dev = devclass_get_device(devclass_find("twl_vreg"), 0); 1729 if (sc->sc_vreg_dev == NULL) { 1730 device_printf(dev, "Error: failed to get the votlage regulator" 1731 " device\n"); 1732 sc->sc_vreg_name = NULL; 1733 } 1734#endif 1735 1736 /* Activate the device */ 1737 err = ti_mmchs_activate(dev); 1738 if (err) 1739 goto out; 1740 1741 /* Initialise the controller */ 1742 ti_mmchs_hw_init(dev); 1743 1744 /* Activate the interrupt and attach a handler */ 1745 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 1746 NULL, ti_mmchs_intr, sc, &sc->sc_irq_h); 1747 if (err != 0) 1748 goto out; 1749 1750 /* Add host details */ 1751 sc->host.f_min = sc->sc_ref_freq / 1023; 1752 sc->host.f_max = sc->sc_ref_freq; 1753 sc->host.host_ocr = MMC_OCR_290_300 | MMC_OCR_300_310; 1754 sc->host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 1755 1756 device_add_child(dev, "mmc", 0); 1757 1758 err = bus_generic_attach(dev); 1759 1760out: 1761 if (err) { 1762 TI_MMCHS_LOCK_DESTROY(sc); 1763 ti_mmchs_deactivate(dev); 1764 1765#ifdef SOC_TI_AM335X 1766 printf("%s: DMA unimplemented\n", __func__); 1767#else 1768 if (sc->sc_dmach_rd != (unsigned int)-1) 1769 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1770 if (sc->sc_dmach_wr != (unsigned int)-1) 1771 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1772#endif 1773 } 1774 1775 return (err); 1776} 1777 1778/** 1779 * ti_mmchs_detach - dettach function for the driver 1780 * @dev: mmc device handle 1781 * 1782 * Shutdowns the controll and release resources allocated by the driver. 1783 * 1784 * RETURNS: 1785 * Always returns 0. 1786 */ 1787static int 1788ti_mmchs_detach(device_t dev) 1789{ 1790#ifndef SOC_TI_AM335X 1791 struct ti_mmchs_softc *sc = device_get_softc(dev); 1792#endif 1793 1794 ti_mmchs_hw_fini(dev); 1795 ti_mmchs_deactivate(dev); 1796 1797#ifdef SOC_TI_AM335X 1798 printf("%s: DMA unimplemented\n", __func__); 1799#else 1800 ti_sdma_deactivate_channel(sc->sc_dmach_wr); 1801 ti_sdma_deactivate_channel(sc->sc_dmach_rd); 1802#endif 1803 1804 return (0); 1805} 1806 1807static device_method_t ti_mmchs_methods[] = { 1808 /* device_if */ 1809 DEVMETHOD(device_probe, ti_mmchs_probe), 1810 DEVMETHOD(device_attach, ti_mmchs_attach), 1811 DEVMETHOD(device_detach, ti_mmchs_detach), 1812 1813 /* Bus interface */ 1814 DEVMETHOD(bus_read_ivar, ti_mmchs_read_ivar), 1815 DEVMETHOD(bus_write_ivar, ti_mmchs_write_ivar), 1816 1817 /* mmcbr_if - MMC state machine callbacks */ 1818 DEVMETHOD(mmcbr_update_ios, ti_mmchs_update_ios), 1819 DEVMETHOD(mmcbr_request, ti_mmchs_request), 1820 DEVMETHOD(mmcbr_get_ro, ti_mmchs_get_ro), 1821 DEVMETHOD(mmcbr_acquire_host, ti_mmchs_acquire_host), 1822 DEVMETHOD(mmcbr_release_host, ti_mmchs_release_host), 1823 1824 {0, 0}, 1825}; 1826 1827static driver_t ti_mmchs_driver = { 1828 "ti_mmchs", 1829 ti_mmchs_methods, 1830 sizeof(struct ti_mmchs_softc), 1831}; 1832static devclass_t ti_mmchs_devclass; 1833 1834DRIVER_MODULE(ti_mmchs, simplebus, ti_mmchs_driver, ti_mmchs_devclass, 0, 0); 1835MODULE_DEPEND(ti_mmchs, ti_prcm, 1, 1, 1); 1836#ifdef SOC_TI_AM335X 1837MODULE_DEPEND(ti_mmchs, ti_edma, 1, 1, 1); 1838#else 1839MODULE_DEPEND(ti_mmchs, ti_sdma, 1, 1, 1); 1840#endif 1841MODULE_DEPEND(ti_mmchs, ti_gpio, 1, 1, 1); 1842 1843/* FIXME: MODULE_DEPEND(ti_mmchs, twl_vreg, 1, 1, 1); */ 1844