1/*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/** 29 * Driver for the I2C module on the TI SoC. 30 * 31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 32 * 33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 34 * 32 bit data access is not allowed and can corrupt register content. 35 * 36 * This driver currently doesn't use DMA for the transfer, although I hope to 37 * incorporate that sometime in the future. The idea being that for transaction 38 * larger than a certain size the DMA engine is used, for anything less the 39 * normal interrupt/fifo driven option is used. 40 * 41 * 42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, 43 * which means you can't do a transaction during startup before the interrupts 44 * have been enabled. Hint - the freebsd function config_intrhook_establish(). 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: releng/10.3/sys/arm/ti/ti_i2c.c 276278 2014-12-27 02:37:52Z ian $"); 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/bus.h> 53#include <sys/conf.h> 54#include <sys/kernel.h> 55#include <sys/lock.h> 56#include <sys/mbuf.h> 57#include <sys/malloc.h> 58#include <sys/module.h> 59#include <sys/mutex.h> 60#include <sys/rman.h> 61#include <sys/sysctl.h> 62#include <machine/bus.h> 63 64#include <dev/ofw/openfirm.h> 65#include <dev/ofw/ofw_bus.h> 66#include <dev/ofw/ofw_bus_subr.h> 67 68#include <arm/ti/ti_cpuid.h> 69#include <arm/ti/ti_prcm.h> 70#include <arm/ti/ti_i2c.h> 71 72#include <dev/iicbus/iiconf.h> 73#include <dev/iicbus/iicbus.h> 74 75#include "iicbus_if.h" 76 77/** 78 * I2C device driver context, a pointer to this is stored in the device 79 * driver structure. 80 */ 81struct ti_i2c_softc 82{ 83 device_t sc_dev; 84 uint32_t device_id; 85 struct resource* sc_irq_res; 86 struct resource* sc_mem_res; 87 device_t sc_iicbus; 88 89 void* sc_irq_h; 90 91 struct mtx sc_mtx; 92 93 struct iic_msg* sc_buffer; 94 int sc_bus_inuse; 95 int sc_buffer_pos; 96 int sc_error; 97 int sc_fifo_trsh; 98 99 uint16_t sc_con_reg; 100 uint16_t sc_rev; 101}; 102 103struct ti_i2c_clock_config 104{ 105 u_int frequency; /* Bus frequency in Hz */ 106 uint8_t psc; /* Fast/Standard mode prescale divider */ 107 uint8_t scll; /* Fast/Standard mode SCL low time */ 108 uint8_t sclh; /* Fast/Standard mode SCL high time */ 109 uint8_t hsscll; /* High Speed mode SCL low time */ 110 uint8_t hssclh; /* High Speed mode SCL high time */ 111}; 112 113#if defined(SOC_OMAP3) 114#error "Unsupported SoC" 115#endif 116 117#if defined(SOC_OMAP4) 118/* 119 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). 120 * The prescaler values for 100KHz and 400KHz modes come from the table in the 121 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. 122 */ 123static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 124 { 100000, 23, 13, 15, 0, 0}, 125 { 400000, 9, 5, 7, 0, 0}, 126 { 1000000, 3, 5, 7, 0, 0}, 127/* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ 128 { 0 /* Table terminator */ } 129}; 130#endif 131 132#if defined(SOC_TI_AM335X) 133/* 134 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) 135 * In all cases we prescale the clock to 24MHz as recommended in the manual. 136 */ 137static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 138 { 100000, 1, 111, 117, 0, 0}, 139 { 400000, 1, 23, 25, 0, 0}, 140 { 1000000, 1, 5, 7, 0, 0}, 141 { 0 /* Table terminator */ } 142}; 143#endif 144 145/** 146 * Locking macros used throughout the driver 147 */ 148#define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 149#define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 150#define TI_I2C_LOCK_INIT(_sc) \ 151 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 152 "ti_i2c", MTX_DEF) 153#define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 154#define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 155#define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 156 157#ifdef DEBUG 158#define ti_i2c_dbg(_sc, fmt, args...) \ 159 device_printf((_sc)->sc_dev, fmt, ##args) 160#else 161#define ti_i2c_dbg(_sc, fmt, args...) 162#endif 163 164/** 165 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 166 * @sc: I2C device context 167 * @off: the byte offset within the register bank to read from. 168 * 169 * 170 * LOCKING: 171 * No locking required 172 * 173 * RETURNS: 174 * 16-bit value read from the register. 175 */ 176static inline uint16_t 177ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 178{ 179 180 return (bus_read_2(sc->sc_mem_res, off)); 181} 182 183/** 184 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 185 * @sc: I2C device context 186 * @off: the byte offset within the register bank to read from. 187 * @val: the value to write into the register 188 * 189 * LOCKING: 190 * No locking required 191 * 192 * RETURNS: 193 * 16-bit value read from the register. 194 */ 195static inline void 196ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 197{ 198 199 bus_write_2(sc->sc_mem_res, off, val); 200} 201 202static int 203ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 204{ 205 int amount, done, i; 206 207 done = 0; 208 amount = 0; 209 /* Check for the error conditions. */ 210 if (status & I2C_STAT_NACK) { 211 /* No ACK from slave. */ 212 ti_i2c_dbg(sc, "NACK\n"); 213 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 214 sc->sc_error = ENXIO; 215 } else if (status & I2C_STAT_AL) { 216 /* Arbitration lost. */ 217 ti_i2c_dbg(sc, "Arbitration lost\n"); 218 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 219 sc->sc_error = ENXIO; 220 } 221 222 /* Check if we have finished. */ 223 if (status & I2C_STAT_ARDY) { 224 /* Register access ready - transaction complete basically. */ 225 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 226 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 227 ti_i2c_write_2(sc, I2C_REG_CON, 228 sc->sc_con_reg | I2C_CON_STP); 229 } 230 ti_i2c_write_2(sc, I2C_REG_STATUS, 231 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 232 I2C_STAT_XDR | I2C_STAT_XRDY); 233 return (1); 234 } 235 236 if (sc->sc_buffer->flags & IIC_M_RD) { 237 /* Read some data. */ 238 if (status & I2C_STAT_RDR) { 239 /* 240 * Receive draining interrupt - last data received. 241 * The set FIFO threshold wont be reached to trigger 242 * RRDY. 243 */ 244 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 245 246 /* 247 * Drain the FIFO. Read the pending data in the FIFO. 248 */ 249 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 250 } else if (status & I2C_STAT_RRDY) { 251 /* 252 * Receive data ready interrupt - FIFO has reached the 253 * set threshold. 254 */ 255 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 256 257 amount = min(sc->sc_fifo_trsh, 258 sc->sc_buffer->len - sc->sc_buffer_pos); 259 } 260 261 /* Read the bytes from the fifo. */ 262 for (i = 0; i < amount; i++) 263 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 264 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 265 266 if (status & I2C_STAT_RDR) 267 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 268 if (status & I2C_STAT_RRDY) 269 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 270 271 } else { 272 /* Write some data. */ 273 if (status & I2C_STAT_XDR) { 274 /* 275 * Transmit draining interrupt - FIFO level is below 276 * the set threshold and the amount of data still to 277 * be transferred wont reach the set FIFO threshold. 278 */ 279 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 280 281 /* 282 * Drain the TX data. Write the pending data in the 283 * FIFO. 284 */ 285 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 286 } else if (status & I2C_STAT_XRDY) { 287 /* 288 * Transmit data ready interrupt - the FIFO level 289 * is below the set threshold. 290 */ 291 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 292 293 amount = min(sc->sc_fifo_trsh, 294 sc->sc_buffer->len - sc->sc_buffer_pos); 295 } 296 297 /* Write the bytes from the fifo. */ 298 for (i = 0; i < amount; i++) 299 ti_i2c_write_2(sc, I2C_REG_DATA, 300 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 301 302 if (status & I2C_STAT_XDR) 303 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 304 if (status & I2C_STAT_XRDY) 305 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 306 } 307 308 return (done); 309} 310 311/** 312 * ti_i2c_intr - interrupt handler for the I2C module 313 * @dev: i2c device handle 314 * 315 * 316 * 317 * LOCKING: 318 * Called from timer context 319 * 320 * RETURNS: 321 * EH_HANDLED or EH_NOT_HANDLED 322 */ 323static void 324ti_i2c_intr(void *arg) 325{ 326 int done; 327 struct ti_i2c_softc *sc; 328 uint16_t events, status; 329 330 sc = (struct ti_i2c_softc *)arg; 331 332 TI_I2C_LOCK(sc); 333 334 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 335 if (status == 0) { 336 TI_I2C_UNLOCK(sc); 337 return; 338 } 339 340 /* Save enabled interrupts. */ 341 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 342 343 /* We only care about enabled interrupts. */ 344 status &= events; 345 346 done = 0; 347 348 if (sc->sc_buffer != NULL) 349 done = ti_i2c_transfer_intr(sc, status); 350 else { 351 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 352 sc->sc_error = EINVAL; 353 done = 1; 354 } 355 356 if (done) 357 /* Wakeup the process that started the transaction. */ 358 wakeup(sc); 359 360 TI_I2C_UNLOCK(sc); 361} 362 363/** 364 * ti_i2c_transfer - called to perform the transfer 365 * @dev: i2c device handle 366 * @msgs: the messages to send/receive 367 * @nmsgs: the number of messages in the msgs array 368 * 369 * 370 * LOCKING: 371 * Internally locked 372 * 373 * RETURNS: 374 * 0 on function succeeded 375 * EINVAL if invalid message is passed as an arg 376 */ 377static int 378ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 379{ 380 int err, i, repstart, timeout; 381 struct ti_i2c_softc *sc; 382 uint16_t reg; 383 384 sc = device_get_softc(dev); 385 TI_I2C_LOCK(sc); 386 387 /* If the controller is busy wait until it is available. */ 388 while (sc->sc_bus_inuse == 1) 389 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 390 391 /* Now we have control over the I2C controller. */ 392 sc->sc_bus_inuse = 1; 393 394 err = 0; 395 repstart = 0; 396 for (i = 0; i < nmsgs; i++) { 397 398 sc->sc_buffer = &msgs[i]; 399 sc->sc_buffer_pos = 0; 400 sc->sc_error = 0; 401 402 /* Zero byte transfers aren't allowed. */ 403 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 404 sc->sc_buffer->len == 0) { 405 err = EINVAL; 406 break; 407 } 408 409 /* Check if the i2c bus is free. */ 410 if (repstart == 0) { 411 /* 412 * On repeated start we send the START condition while 413 * the bus _is_ busy. 414 */ 415 timeout = 0; 416 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 417 if (timeout++ > 100) { 418 err = EBUSY; 419 goto out; 420 } 421 DELAY(1000); 422 } 423 timeout = 0; 424 } else 425 repstart = 0; 426 427 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 428 repstart = 1; 429 430 /* Set the slave address. */ 431 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 432 433 /* Write the data length. */ 434 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 435 436 /* Clear the RX and the TX FIFO. */ 437 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 438 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 439 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 440 441 reg = sc->sc_con_reg | I2C_CON_STT; 442 if (repstart == 0) 443 reg |= I2C_CON_STP; 444 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 445 reg |= I2C_CON_TRX; 446 ti_i2c_write_2(sc, I2C_REG_CON, reg); 447 448 /* Wait for an event. */ 449 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz); 450 if (err == 0) 451 err = sc->sc_error; 452 453 if (err) 454 break; 455 } 456 457out: 458 if (timeout == 0) { 459 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 460 if (timeout++ > 100) 461 break; 462 DELAY(1000); 463 } 464 } 465 /* Put the controller in master mode again. */ 466 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 467 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 468 469 sc->sc_buffer = NULL; 470 sc->sc_bus_inuse = 0; 471 472 /* Wake up the processes that are waiting for the bus. */ 473 wakeup(sc); 474 475 TI_I2C_UNLOCK(sc); 476 477 return (err); 478} 479 480/** 481 * ti_i2c_callback - as we only provide iicbus_transfer() interface 482 * we don't need to implement the serialization here. 483 * @dev: i2c device handle 484 * 485 * 486 * 487 * LOCKING: 488 * Called from timer context 489 * 490 * RETURNS: 491 * EH_HANDLED or EH_NOT_HANDLED 492 */ 493static int 494ti_i2c_callback(device_t dev, int index, caddr_t data) 495{ 496 int error = 0; 497 498 switch (index) { 499 case IIC_REQUEST_BUS: 500 break; 501 502 case IIC_RELEASE_BUS: 503 break; 504 505 default: 506 error = EINVAL; 507 } 508 509 return (error); 510} 511 512static int 513ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 514{ 515 int timeout; 516 struct ti_i2c_clock_config *clkcfg; 517 u_int busfreq; 518 uint16_t fifo_trsh, reg, scll, sclh; 519 520 switch (ti_chip()) { 521#ifdef SOC_OMAP4 522 case CHIP_OMAP_4: 523 clkcfg = ti_omap4_i2c_clock_configs; 524 break; 525#endif 526#ifdef SOC_TI_AM335X 527 case CHIP_AM335X: 528 clkcfg = ti_am335x_i2c_clock_configs; 529 break; 530#endif 531 default: 532 panic("Unknown Ti SoC, unable to reset the i2c"); 533 } 534 535 /* 536 * If we haven't attached the bus yet, just init at the default slow 537 * speed. This lets us get the hardware initialized enough to attach 538 * the bus which is where the real speed configuration is handled. After 539 * the bus is attached, get the configured speed from it. Search the 540 * configuration table for the best speed we can do that doesn't exceed 541 * the requested speed. 542 */ 543 if (sc->sc_iicbus == NULL) 544 busfreq = 100000; 545 else 546 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 547 for (;;) { 548 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) 549 break; 550 clkcfg++; 551 } 552 553 /* 554 * 23.1.4.3 - HS I2C Software Reset 555 * From OMAP4 TRM at page 4068. 556 * 557 * 1. Ensure that the module is disabled. 558 */ 559 sc->sc_con_reg = 0; 560 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 561 562 /* 2. Issue a softreset to the controller. */ 563 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 564 565 /* 566 * 3. Enable the module. 567 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 568 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 569 */ 570 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 571 572 /* 4. Wait for the software reset to complete. */ 573 timeout = 0; 574 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 575 if (timeout++ > 100) 576 return (EBUSY); 577 DELAY(100); 578 } 579 580 /* 581 * Disable the I2C controller once again, now that the reset has 582 * finished. 583 */ 584 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 585 586 /* 587 * The following sequence is taken from the OMAP4 TRM at page 4077. 588 * 589 * 1. Enable the functional and interface clocks (see Section 590 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 591 * 592 * 2. Program the prescaler to obtain an approximately 12MHz internal 593 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 594 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 595 * This value depends on the frequency of the functional clock 596 * (I2Ci_FCLK). Because this frequency is 96MHz, the 597 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 598 */ 599 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 600 601 /* 602 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 603 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 604 * These values depend on the internal sampling clock frequency 605 * (see Table 23-8). 606 */ 607 scll = clkcfg->scll & I2C_SCLL_MASK; 608 sclh = clkcfg->sclh & I2C_SCLH_MASK; 609 610 /* 611 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 612 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 613 * 400K bps or 3.4M bps (for the second phase of HS mode). These 614 * values depend on the internal sampling clock frequency (see 615 * Table 23-8). 616 * 617 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 618 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 619 * Multiplexing and Configuration). 620 */ 621 switch (ti_chip()) { 622#ifdef SOC_OMAP4 623 case CHIP_OMAP_4: 624 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 625 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 626 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 627 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 628 } 629 break; 630#endif 631 } 632 633 /* Write the selected bit rate. */ 634 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 635 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 636 637 /* 638 * 6. Configure the Own Address of the I2C controller by storing it in 639 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 640 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 641 * for each I2C controller. 642 * 643 * Note: For a 10-bit address, set the corresponding expand Own Address 644 * bit in the I2Ci.I2C_CON register. 645 * 646 * Driver currently always in single master mode so ignore this step. 647 */ 648 649 /* 650 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 651 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 652 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 653 * threshold - 1), where the TX and RX thresholds are greater than 654 * or equal to 1. 655 * 656 * The threshold is set to 5 for now. 657 */ 658 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 659 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 660 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 661 662 /* 663 * 8. Take the I2C controller out of reset by setting the 664 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 665 * 666 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 667 * 668 * To initialize the I2C controller, perform the following steps: 669 * 670 * 1. Configure the I2Ci.I2C_CON register: 671 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 672 * (0: slave, 1: master). 673 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 674 * bit (0: receiver, 1: transmitter). 675 */ 676 677 /* Enable the I2C controller in master mode. */ 678 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 679 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 680 681 /* 682 * 2. If using an interrupt to transmit/receive data, set the 683 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 684 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 685 * bit for the receive interrupt). 686 */ 687 688 /* Set the interrupts we want to be notified. */ 689 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 690 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 691 I2C_IE_RDR | /* Receive draining interrupt. */ 692 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 693 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 694 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 695 I2C_IE_AL; /* Arbitration lost interrupt. */ 696 697 /* Enable the interrupts. */ 698 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 699 700 /* 701 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 702 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 703 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 704 * for the transmit DMA channel). 705 * 706 * Not using DMA for now, so ignore this. 707 */ 708 709 return (0); 710} 711 712static int 713ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 714{ 715 struct ti_i2c_softc *sc; 716 int err; 717 718 sc = device_get_softc(dev); 719 TI_I2C_LOCK(sc); 720 err = ti_i2c_reset(sc, speed); 721 TI_I2C_UNLOCK(sc); 722 if (err) 723 return (err); 724 725 return (IIC_ENOADDR); 726} 727 728static int 729ti_i2c_activate(device_t dev) 730{ 731 clk_ident_t clk; 732 int err; 733 struct ti_i2c_softc *sc; 734 735 sc = (struct ti_i2c_softc*)device_get_softc(dev); 736 737 /* 738 * 1. Enable the functional and interface clocks (see Section 739 * 23.1.5.1.1.1.1). 740 */ 741 clk = I2C0_CLK + sc->device_id; 742 err = ti_prcm_clk_enable(clk); 743 if (err) 744 return (err); 745 746 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 747} 748 749/** 750 * ti_i2c_deactivate - deactivates the controller and releases resources 751 * @dev: i2c device handle 752 * 753 * 754 * 755 * LOCKING: 756 * Assumed called in an atomic context. 757 * 758 * RETURNS: 759 * nothing 760 */ 761static void 762ti_i2c_deactivate(device_t dev) 763{ 764 struct ti_i2c_softc *sc = device_get_softc(dev); 765 clk_ident_t clk; 766 767 /* Disable the controller - cancel all transactions. */ 768 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 769 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 770 ti_i2c_write_2(sc, I2C_REG_CON, 0); 771 772 /* Release the interrupt handler. */ 773 if (sc->sc_irq_h != NULL) { 774 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 775 sc->sc_irq_h = NULL; 776 } 777 778 bus_generic_detach(sc->sc_dev); 779 780 /* Unmap the I2C controller registers. */ 781 if (sc->sc_mem_res != NULL) { 782 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 783 sc->sc_mem_res = NULL; 784 } 785 786 /* Release the IRQ resource. */ 787 if (sc->sc_irq_res != NULL) { 788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 789 sc->sc_irq_res = NULL; 790 } 791 792 /* Finally disable the functional and interface clocks. */ 793 clk = I2C0_CLK + sc->device_id; 794 ti_prcm_clk_disable(clk); 795} 796 797static int 798ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 799{ 800 device_t dev; 801 int clk, psc, sclh, scll; 802 struct ti_i2c_softc *sc; 803 804 dev = (device_t)arg1; 805 sc = device_get_softc(dev); 806 807 TI_I2C_LOCK(sc); 808 /* Get the system prescaler value. */ 809 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 810 811 /* Get the bitrate. */ 812 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 813 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 814 815 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 816 TI_I2C_UNLOCK(sc); 817 818 return (sysctl_handle_int(oidp, &clk, 0, req)); 819} 820 821static int 822ti_i2c_probe(device_t dev) 823{ 824 825 if (!ofw_bus_status_okay(dev)) 826 return (ENXIO); 827 if (!ofw_bus_is_compatible(dev, "ti,i2c")) 828 return (ENXIO); 829 device_set_desc(dev, "TI I2C Controller"); 830 831 return (0); 832} 833 834static int 835ti_i2c_attach(device_t dev) 836{ 837 int err, rid; 838 phandle_t node; 839 struct ti_i2c_softc *sc; 840 struct sysctl_ctx_list *ctx; 841 struct sysctl_oid_list *tree; 842 uint16_t fifosz; 843 844 sc = device_get_softc(dev); 845 sc->sc_dev = dev; 846 847 /* Get the i2c device id from FDT. */ 848 node = ofw_bus_get_node(dev); 849 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id, 850 sizeof(sc->device_id))) <= 0) { 851 device_printf(dev, "missing i2c-device-id attribute in FDT\n"); 852 return (ENXIO); 853 } 854 855 /* Get the memory resource for the register mapping. */ 856 rid = 0; 857 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 858 RF_ACTIVE); 859 if (sc->sc_mem_res == NULL) { 860 device_printf(dev, "Cannot map registers.\n"); 861 return (ENXIO); 862 } 863 864 /* Allocate our IRQ resource. */ 865 rid = 0; 866 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 867 RF_ACTIVE | RF_SHAREABLE); 868 if (sc->sc_irq_res == NULL) { 869 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 870 device_printf(dev, "Cannot allocate interrupt.\n"); 871 return (ENXIO); 872 } 873 874 TI_I2C_LOCK_INIT(sc); 875 876 /* First of all, we _must_ activate the H/W. */ 877 err = ti_i2c_activate(dev); 878 if (err) { 879 device_printf(dev, "ti_i2c_activate failed\n"); 880 goto out; 881 } 882 883 /* Read the version number of the I2C module */ 884 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 885 886 /* Get the fifo size. */ 887 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 888 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 889 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 890 891 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 892 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 893 894 /* Set the FIFO threshold to 5 for now. */ 895 sc->sc_fifo_trsh = 5; 896 897 ctx = device_get_sysctl_ctx(dev); 898 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 899 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 900 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0, 901 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 902 903 /* Activate the interrupt. */ 904 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 905 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 906 if (err) 907 goto out; 908 909 /* Attach the iicbus. */ 910 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 911 device_printf(dev, "could not allocate iicbus instance\n"); 912 err = ENXIO; 913 goto out; 914 } 915 916 /* Probe and attach the iicbus */ 917 bus_generic_attach(dev); 918 919out: 920 if (err) { 921 ti_i2c_deactivate(dev); 922 TI_I2C_LOCK_DESTROY(sc); 923 } 924 925 return (err); 926} 927 928static int 929ti_i2c_detach(device_t dev) 930{ 931 struct ti_i2c_softc *sc; 932 int rv; 933 934 sc = device_get_softc(dev); 935 ti_i2c_deactivate(dev); 936 TI_I2C_LOCK_DESTROY(sc); 937 if (sc->sc_iicbus && 938 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 939 return (rv); 940 941 return (0); 942} 943 944static phandle_t 945ti_i2c_get_node(device_t bus, device_t dev) 946{ 947 948 /* Share controller node with iibus device. */ 949 return (ofw_bus_get_node(bus)); 950} 951 952static device_method_t ti_i2c_methods[] = { 953 /* Device interface */ 954 DEVMETHOD(device_probe, ti_i2c_probe), 955 DEVMETHOD(device_attach, ti_i2c_attach), 956 DEVMETHOD(device_detach, ti_i2c_detach), 957 958 /* OFW methods */ 959 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 960 961 /* iicbus interface */ 962 DEVMETHOD(iicbus_callback, ti_i2c_callback), 963 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 964 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 965 966 DEVMETHOD_END 967}; 968 969static driver_t ti_i2c_driver = { 970 "iichb", 971 ti_i2c_methods, 972 sizeof(struct ti_i2c_softc), 973}; 974 975static devclass_t ti_i2c_devclass; 976 977DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 978DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 979 980MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); 981MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 982