1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Based on OMAP3 INTC code by Ben Gray
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: releng/10.3/sys/arm/ti/aintc.c 283329 2015-05-23 21:12:51Z ian $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/ktr.h>
38#include <sys/module.h>
39#include <sys/rman.h>
40#include <machine/bus.h>
41#include <machine/intr.h>
42
43#include <dev/fdt/fdt_common.h>
44#include <dev/ofw/openfirm.h>
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#define INTC_REVISION		0x00
49#define INTC_SYSCONFIG		0x10
50#define INTC_SYSSTATUS		0x14
51#define INTC_SIR_IRQ		0x40
52#define INTC_CONTROL		0x48
53#define INTC_THRESHOLD		0x68
54#define INTC_MIR_CLEAR(x)	(0x88 + ((x) * 0x20))
55#define INTC_MIR_SET(x)		(0x8C + ((x) * 0x20))
56#define INTC_ISR_SET(x)		(0x90 + ((x) * 0x20))
57#define INTC_ISR_CLEAR(x)	(0x94 + ((x) * 0x20))
58
59struct ti_aintc_softc {
60	device_t		sc_dev;
61	struct resource *	aintc_res[3];
62	bus_space_tag_t		aintc_bst;
63	bus_space_handle_t	aintc_bsh;
64	uint8_t			ver;
65};
66
67static struct resource_spec ti_aintc_spec[] = {
68	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
69	{ -1, 0 }
70};
71
72
73static struct ti_aintc_softc *ti_aintc_sc = NULL;
74
75#define	aintc_read_4(_sc, reg)		\
76    bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))
77#define	aintc_write_4(_sc, reg, val)		\
78    bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))
79
80
81static void
82aintc_post_filter(void *arg)
83{
84
85	arm_irq_memory_barrier(0);
86	aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */
87}
88
89static int
90ti_aintc_probe(device_t dev)
91{
92	if (!ofw_bus_status_okay(dev))
93		return (ENXIO);
94
95
96	if (!ofw_bus_is_compatible(dev, "ti,aintc"))
97		return (ENXIO);
98	device_set_desc(dev, "TI AINTC Interrupt Controller");
99	return (BUS_PROBE_DEFAULT);
100}
101
102static int
103ti_aintc_attach(device_t dev)
104{
105	struct		ti_aintc_softc *sc = device_get_softc(dev);
106	uint32_t x;
107
108	sc->sc_dev = dev;
109
110	if (ti_aintc_sc)
111		return (ENXIO);
112
113	if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
114		device_printf(dev, "could not allocate resources\n");
115		return (ENXIO);
116	}
117
118	sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
119	sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
120
121	ti_aintc_sc = sc;
122
123	x = aintc_read_4(sc, INTC_REVISION);
124	device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
125
126	/* SoftReset */
127	aintc_write_4(sc, INTC_SYSCONFIG, 2);
128
129	/* Wait for reset to complete */
130	while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));
131
132	/*Set Priority Threshold */
133	aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
134
135	arm_post_filter = aintc_post_filter;
136
137	return (0);
138}
139
140static device_method_t ti_aintc_methods[] = {
141	DEVMETHOD(device_probe,		ti_aintc_probe),
142	DEVMETHOD(device_attach,	ti_aintc_attach),
143	{ 0, 0 }
144};
145
146static driver_t ti_aintc_driver = {
147	"aintc",
148	ti_aintc_methods,
149	sizeof(struct ti_aintc_softc),
150};
151
152static devclass_t ti_aintc_devclass;
153
154DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 0, 0);
155
156int
157arm_get_next_irq(int last_irq)
158{
159	struct ti_aintc_softc *sc = ti_aintc_sc;
160	uint32_t active_irq;
161
162	/* Get the next active interrupt */
163	active_irq = aintc_read_4(sc, INTC_SIR_IRQ);
164
165	/* Check for spurious interrupt */
166	if ((active_irq & 0xffffff80)) {
167		device_printf(sc->sc_dev,
168		    "Spurious interrupt detected (0x%08x)\n", active_irq);
169		aintc_write_4(sc, INTC_SIR_IRQ, 0);
170		return -1;
171	}
172
173	if (active_irq != last_irq)
174		return active_irq;
175	else
176		return -1;
177}
178
179void
180arm_mask_irq(uintptr_t nb)
181{
182	struct ti_aintc_softc *sc = ti_aintc_sc;
183
184	aintc_write_4(sc, INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
185	aintc_write_4(sc, INTC_CONTROL, 1); /* EOI */
186}
187
188void
189arm_unmask_irq(uintptr_t nb)
190{
191	struct ti_aintc_softc *sc = ti_aintc_sc;
192
193	arm_irq_memory_barrier(nb);
194	aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));
195}
196