1/*- 2 * Copyright (C) 2009 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.3/sys/arm/samsung/s3c2xx0/s3c2440reg.h 272103 2014-09-25 11:38:26Z gavin $ 27 */ 28 29/* 30 * Samsung S3C2440X processor is ARM920T based integrated CPU 31 * 32 * Reference: 33 * S3C2440A/S3C2442B User's Manual 34 */ 35#ifndef _ARM_S3C2XX0_S3C2440REG_H_ 36#define _ARM_S3C2XX0_S3C2440REG_H_ 37 38/* common definitions for S3C2410 and S3C2440 */ 39#include <arm/samsung/s3c2xx0/s3c24x0reg.h> 40 41/* 42 * Memory Map 43 */ 44#define S3C2440_BANK_SIZE 0x08000000 45#define S3C2440_BANK_START(n) (S3C2410_BANK_SIZE*(n)) 46#define S3C2440_SDRAM_START S3C2410_BANK_START(6) 47 48 49/* interrupt control */ 50#define S3C2440_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10) 51 52/* Clock control */ 53/* CLKMAN_CLKCON */ 54#define S3C2440_CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ 55/* CLKMAN_CLKDIVN */ 56#define S3C2440_CLKDIVN_HDIVN (3<<1) /* hclk */ 57#define S3C2440_CLKMAN_CAMDIVN 0x18 58#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 59#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) 60 61/* NAND Flash controller */ 62#define S3C2440_NANDFC_SIZE 0x40 63 64#define S3C2440_NANDFC_NFCONT 0x04 65#define S3C2440_NFCONT_LOCK_TIGHT (1<<13) /* Lock part of the NAND */ 66#define S3C2440_NFCONT_SOFT_LOCK (1<<12) /* Soft lock part of the NAND */ 67#define S3C2440_NFCONT_ILLEGAL_ACC_INT (1<<10) /* Illegal access interrupt */ 68#define S3C2440_NFCONT_RNB_INT (1<<9) /* RnB transition interrupt */ 69#define S3C2440_NFCONT_RNB_TRANS_MODE (1<<8) /* RnB transition mode */ 70#define S3C2440_NFCONT_SPARE_ECC_LOCK (1<<6) /* Lock spare ECC generation */ 71#define S3C2440_NFCONT_MAIN_ECC_LOCK (1<<5) /* Lock main ECC generation */ 72#define S3C2440_NFCONT_INIT_ECC (1<<4) /* Init ECC encoder/decoder */ 73#define S3C2440_NFCONT_NCE (1<<1) /* NAND Chip select */ 74#define S3C2440_NFCONT_ENABLE (1<<0) /* Enable the controller */ 75#define S3C2440_NANDFC_NFCMMD 0x08 76#define S3C2440_NANDFC_NFADDR 0x0c 77#define S3C2440_NANDFC_NFDATA 0x10 78#define S3C2440_NANDFC_NFSTAT 0x20 79 80/* MMC/SD */ 81/* SDI_CON */ 82#define S3C2440_CON_RESET (1<<8) 83#define S3C2440_CON_CLOCK_TYPE (1<<5) 84/* SDI_FSTA */ 85#define S3c2440_FSTA_RESET (1<<16) 86#define S3C2440_FSTA_FAIL_ERROR_MSK (3<<14) 87#define S3C2440_FSTA_FAIL_NONE (0<<14) 88#define S3C2440_FSTA_FAIL_FIFO (1<<14) 89#define S3C2440_FSTA_FAIL_LAST_TRANS (2<<14) 90 91/* GPIO */ 92#define S3C2440_GPIO_SIZE 0xd0 93 94/* SD interface */ 95#define S3C2410_SDI_SIZE 0x44 96#define DCON_START (1<<14) /* Start the data transfer */ 97#define S3C2440_SDI_IMSK 0x3c /* Interrupt mask */ 98#define S3C2440_SDI_IMASK_ALL 0x3C7C0 99#define S3C2440_SDI_DAT 0x40 100 101/* ADC */ 102#define ADCTSC_UD_SEN (1<<8) 103#define S3C2440_ADC_SIZE 0x18 104 105/* UART */ 106#define S3C2440_UFSTAT_TXCOUNT (0x3f << 8) 107#define S3C2440_UFSTAT_RXCOUNT (0x3f << 0) 108 109#endif /* _ARM_S3C2XX0_S3C2440REG_H_ */ 110