1/*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: releng/10.3/sys/arm/mv/mpic.c 289184 2015-10-12 13:20:17Z andrew $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/cpuset.h> 41#include <sys/ktr.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44 45#include <machine/bus.h> 46#include <machine/intr.h> 47#include <machine/cpufunc.h> 48#include <machine/smp.h> 49 50#include <arm/mv/mvvar.h> 51 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54#include <dev/fdt/fdt_common.h> 55 56#ifdef DEBUG 57#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 58 printf(fmt,##args); } while (0) 59#else 60#define debugf(fmt, args...) 61#endif 62 63#define MPIC_INT_ERR 4 64#define MPIC_INT_MSI 96 65 66#define IRQ_MASK 0x3ff 67 68#define MPIC_CTRL 0x0 69#define MPIC_SOFT_INT 0x4 70#define MPIC_SOFT_INT_DRBL1 (1 << 5) 71#define MPIC_ERR_CAUSE 0x20 72#define MPIC_ISE 0x30 73#define MPIC_ICE 0x34 74 75 76#define MPIC_IN_DRBL 0x78 77#define MPIC_IN_DRBL_MASK 0x7c 78#define MPIC_CTP 0xb0 79#define MPIC_CTP 0xb0 80#define MPIC_IIACK 0xb4 81#define MPIC_ISM 0xb8 82#define MPIC_ICM 0xbc 83#define MPIC_ERR_MASK 0xec0 84 85struct mv_mpic_softc { 86 device_t sc_dev; 87 struct resource * mpic_res[3]; 88 bus_space_tag_t mpic_bst; 89 bus_space_handle_t mpic_bsh; 90 bus_space_tag_t cpu_bst; 91 bus_space_handle_t cpu_bsh; 92 bus_space_tag_t drbl_bst; 93 bus_space_handle_t drbl_bsh; 94}; 95 96static struct resource_spec mv_mpic_spec[] = { 97 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 98 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 99 { SYS_RES_MEMORY, 2, RF_ACTIVE }, 100 { -1, 0 } 101}; 102 103static struct mv_mpic_softc *mv_mpic_sc = NULL; 104 105void mpic_send_ipi(int cpus, u_int ipi); 106 107static int mv_mpic_probe(device_t); 108static int mv_mpic_attach(device_t); 109uint32_t mv_mpic_get_cause(void); 110uint32_t mv_mpic_get_cause_err(void); 111uint32_t mv_mpic_get_msi(void); 112static void arm_mask_irq_err(uintptr_t); 113static void arm_unmask_irq_err(uintptr_t); 114static void arm_unmask_msi(void); 115 116#define MPIC_CPU_WRITE(softc, reg, val) \ 117 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 118#define MPIC_CPU_READ(softc, reg) \ 119 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 120 121#define MPIC_DRBL_WRITE(softc, reg, val) \ 122 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 123#define MPIC_DRBL_READ(softc, reg) \ 124 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 125 126static int 127mv_mpic_probe(device_t dev) 128{ 129 130 if (!ofw_bus_status_okay(dev)) 131 return (ENXIO); 132 133 if (!ofw_bus_is_compatible(dev, "mrvl,mpic")) 134 return (ENXIO); 135 136 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 137 return (0); 138} 139 140static int 141mv_mpic_attach(device_t dev) 142{ 143 struct mv_mpic_softc *sc; 144 int error; 145 146 sc = (struct mv_mpic_softc *)device_get_softc(dev); 147 148 if (mv_mpic_sc != NULL) 149 return (ENXIO); 150 mv_mpic_sc = sc; 151 152 sc->sc_dev = dev; 153 154 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 155 if (error) { 156 device_printf(dev, "could not allocate resources\n"); 157 return (ENXIO); 158 } 159 160 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 161 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 162 163 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 164 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 165 166 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 167 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 168 169 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 170 MPIC_CTRL, 1); 171 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 172 173 arm_unmask_msi(); 174 175 return (0); 176} 177 178static device_method_t mv_mpic_methods[] = { 179 DEVMETHOD(device_probe, mv_mpic_probe), 180 DEVMETHOD(device_attach, mv_mpic_attach), 181 { 0, 0 } 182}; 183 184static driver_t mv_mpic_driver = { 185 "mpic", 186 mv_mpic_methods, 187 sizeof(struct mv_mpic_softc), 188}; 189 190static devclass_t mv_mpic_devclass; 191 192DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0); 193 194int 195arm_get_next_irq(int last) 196{ 197 u_int irq, next = -1; 198 199 irq = mv_mpic_get_cause() & IRQ_MASK; 200 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 201 202 if (irq != IRQ_MASK) { 203 if (irq == MPIC_INT_ERR) 204 irq = mv_mpic_get_cause_err(); 205 if (irq == MPIC_INT_MSI) 206 irq = mv_mpic_get_msi(); 207 next = irq; 208 } 209 210 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 211 return (next); 212} 213 214/* 215 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 216 * by ISM/ICM and remove access to ICE in masking operation 217 */ 218void 219arm_mask_irq(uintptr_t nb) 220{ 221 222 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1); 223 224 if (nb < ERR_IRQ) { 225 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 226 MPIC_ICE, nb); 227 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 228 } else if (nb < MSI_IRQ) 229 arm_mask_irq_err(nb); 230} 231 232 233static void 234arm_mask_irq_err(uintptr_t nb) 235{ 236 uint32_t mask; 237 uint8_t bit_off; 238 239 bit_off = nb - ERR_IRQ; 240 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 241 mask &= ~(1 << bit_off); 242 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 243} 244 245void 246arm_unmask_irq(uintptr_t nb) 247{ 248 249 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 250 251 if (nb < ERR_IRQ) { 252 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 253 MPIC_ISE, nb); 254 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 255 } else if (nb < MSI_IRQ) 256 arm_unmask_irq_err(nb); 257 258 if (nb == 0) 259 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 260} 261 262void 263arm_unmask_irq_err(uintptr_t nb) 264{ 265 uint32_t mask; 266 uint8_t bit_off; 267 268 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 269 MPIC_ISE, MPIC_INT_ERR); 270 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 271 272 bit_off = nb - ERR_IRQ; 273 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 274 mask |= (1 << bit_off); 275 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 276} 277 278static void 279arm_unmask_msi(void) 280{ 281 282 arm_unmask_irq(MPIC_INT_MSI); 283} 284 285uint32_t 286mv_mpic_get_cause(void) 287{ 288 289 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 290} 291 292uint32_t 293mv_mpic_get_cause_err(void) 294{ 295 uint32_t err_cause; 296 uint8_t bit_off; 297 298 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 299 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 300 301 if (err_cause) 302 bit_off = ffs(err_cause) - 1; 303 else 304 return (-1); 305 306 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 307 return (ERR_IRQ + bit_off); 308} 309 310uint32_t 311mv_mpic_get_msi(void) 312{ 313 uint32_t cause; 314 uint8_t bit_off; 315 316 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 317 318 if (cause) 319 bit_off = ffs(cause) - 1; 320 else 321 return (-1); 322 323 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 324 325 cause &= ~(1 << bit_off); 326 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 327 328 return (MSI_IRQ + bit_off); 329} 330 331int 332mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 333{ 334 u_long phys, base, size; 335 phandle_t node; 336 int error; 337 338 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 339 340 /* Get physical addres of register space */ 341 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 342 if (error) { 343 printf("%s: Cannot get register physical address, err:%d", 344 __func__, error); 345 return (error); 346 } 347 348 /* Get offset of MPIC register space */ 349 error = fdt_regsize(node, &base, &size); 350 if (error) { 351 printf("%s: Cannot get MPIC register offset, err:%d", 352 __func__, error); 353 return (error); 354 } 355 356 *addr = phys + base + MPIC_SOFT_INT; 357 *data = MPIC_SOFT_INT_DRBL1 | irq; 358 359 return (0); 360} 361 362#if defined(SMP) 363void 364pic_ipi_send(cpuset_t cpus, u_int ipi) 365{ 366 uint32_t val, i; 367 368 val = 0x00000000; 369 for (i = 0; i < MAXCPU; i++) 370 if (CPU_ISSET(i, &cpus)) 371 val |= (1 << (8 + i)); 372 val |= ipi; 373 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 374 MPIC_SOFT_INT, val); 375} 376 377int 378pic_ipi_get(int i __unused) 379{ 380 uint32_t val; 381 int ipi; 382 383 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 384 if (val) { 385 ipi = ffs(val) - 1; 386 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 387 return (ipi); 388 } 389 390 return (0x3ff); 391} 392 393void 394pic_ipi_clear(int ipi) 395{ 396} 397 398#endif 399