1/*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: releng/10.3/sys/arm/freescale/imx/imx6_anatop.c 294678 2016-01-24 19:34:05Z ian $");
30
31/*
32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs.
33 * Also, temperature montoring and cpu frequency control.  It was Freescale who
34 * kitchen-sinked this device, not us. :)
35 *
36 * We don't really do anything with analog PLLs, but the registers for
37 * controlling them belong to the same block as the power regulator registers.
38 * Since the newbus hierarchy makes it hard for anyone other than us to get at
39 * them, we just export a couple public functions to allow the imx6 CCM clock
40 * driver to read and write those registers.
41 *
42 * We also don't do anything about power regulation yet, but when the need
43 * arises, this would be the place for that code to live.
44 *
45 * I have no idea where the "anatop" name comes from.  It's in the standard DTS
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
47 * from Freescale, but it's not in the SoC manual.
48 *
49 * Note that temperature values throughout this code are handled in two types of
50 * units.  Items with '_cnt' in the name use the hardware temperature count
51 * units (higher counts are lower temperatures).  Items with '_val' in the name
52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl
53 * handlers (dK is the standard unit for temperature in sysctl).
54 */
55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/callout.h>
59#include <sys/kernel.h>
60#include <sys/limits.h>
61#include <sys/sysctl.h>
62#include <sys/module.h>
63#include <sys/bus.h>
64#include <sys/rman.h>
65
66#include <dev/ofw/ofw_bus.h>
67#include <dev/ofw/ofw_bus_subr.h>
68
69#include <machine/bus.h>
70#include <machine/fdt.h>
71
72#include <arm/arm/mpcore_timervar.h>
73#include <arm/freescale/fsl_ocotpreg.h>
74#include <arm/freescale/fsl_ocotpvar.h>
75#include <arm/freescale/imx/imx_ccmvar.h>
76#include <arm/freescale/imx/imx_machdep.h>
77#include <arm/freescale/imx/imx6_anatopreg.h>
78#include <arm/freescale/imx/imx6_anatopvar.h>
79
80static struct resource_spec imx6_anatop_spec[] = {
81	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
82	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
83	{ -1, 0 }
84};
85#define	MEMRES	0
86#define	IRQRES	1
87
88struct imx6_anatop_softc {
89	device_t	dev;
90	struct resource	*res[2];
91	struct intr_config_hook
92			intr_setup_hook;
93	uint32_t	cpu_curmhz;
94	uint32_t	cpu_curmv;
95	uint32_t	cpu_minmhz;
96	uint32_t	cpu_minmv;
97	uint32_t	cpu_maxmhz;
98	uint32_t	cpu_maxmv;
99	uint32_t	cpu_maxmhz_hw;
100	boolean_t	cpu_overclock_enable;
101	boolean_t	cpu_init_done;
102	uint32_t	refosc_mhz;
103	void		*temp_intrhand;
104	uint32_t	temp_high_val;
105	uint32_t	temp_high_cnt;
106	uint32_t	temp_last_cnt;
107	uint32_t	temp_room_cnt;
108	struct callout	temp_throttle_callout;
109	sbintime_t	temp_throttle_delay;
110	uint32_t	temp_throttle_reset_cnt;
111	uint32_t	temp_throttle_trigger_cnt;
112	uint32_t	temp_throttle_val;
113};
114
115static struct imx6_anatop_softc *imx6_anatop_sc;
116
117/*
118 * Table of "operating points".
119 * These are combinations of frequency and voltage blessed by Freescale.
120 * While the datasheet says the ARM voltage can be as low as 925mV at
121 * 396MHz, it also says that the ARM and SOC voltages can't differ by
122 * more than 200mV, and the minimum SOC voltage is 1150mV, so that
123 * dictates the 950mV entry in this table.
124 */
125static struct oppt {
126	uint32_t	mhz;
127	uint32_t	mv;
128} imx6_oppt_table[] = {
129	{ 396,	 950},
130	{ 792,	1150},
131	{ 852,	1225},
132	{ 996,	1225},
133	{1200,	1275},
134};
135
136/*
137 * Table of CPU max frequencies.  This is used to translate the max frequency
138 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
139 * up in the operating points table.
140 */
141static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200};
142
143#define	TZ_ZEROC	2732	/* deci-Kelvin <-> deci-Celcius offset. */
144
145uint32_t
146imx6_anatop_read_4(bus_size_t offset)
147{
148
149	KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL"));
150
151	return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
152}
153
154void
155imx6_anatop_write_4(bus_size_t offset, uint32_t value)
156{
157
158	KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));
159
160	bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
161}
162
163static void
164vdd_set(struct imx6_anatop_softc *sc, int mv)
165{
166	int newtarg, newtargSoc, oldtarg;
167	uint32_t delay, pmureg;
168	static boolean_t init_done = false;
169
170	/*
171	 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
172	 * can't be more than 50mV above or 200mV below them.  We keep them the
173	 * same except in the case of the lowest operating point, which is
174	 * handled as a special case below.
175	 */
176
177	pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
178	oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
179
180	/* Convert mV to target value.  Clamp target to valid range. */
181	if (mv < 725)
182		newtarg = 0x00;
183	else if (mv > 1450)
184		newtarg = 0x1F;
185	else
186		newtarg = (mv - 700) / 25;
187
188	/*
189	 * The SOC voltage can't go below 1150mV, and thus because of the 200mV
190	 * rule, the ARM voltage can't go below 950mV.  The 950 is encoded in
191	 * our oppt table, here we handle the SOC 1150 rule as a special case.
192	 * (1150-700/25=18).
193	 */
194	newtargSoc = (newtarg < 18) ? 18 : newtarg;
195
196	/*
197	 * The first time through the 3 voltages might not be equal so use a
198	 * long conservative delay.  After that we need to delay 3uS for every
199	 * 25mV step upward; we actually delay 6uS because empirically, it works
200	 * and the 3uS per step recommended by the docs doesn't (3uS fails when
201	 * going from 400->1200, but works for smaller changes).
202	 */
203	if (init_done) {
204		if (newtarg == oldtarg)
205			return;
206		else if (newtarg > oldtarg)
207			delay = (newtarg - oldtarg) * 6;
208		else
209			delay = 0;
210	} else {
211		delay = (700 / 25) * 6;
212		init_done = true;
213	}
214
215	/*
216	 * Make the change and wait for it to take effect.
217	 */
218	pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
219	    IMX6_ANALOG_PMU_REG1_TARG_MASK |
220	    IMX6_ANALOG_PMU_REG2_TARG_MASK);
221
222	pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
223	pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
224	pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
225
226	imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
227	DELAY(delay);
228	sc->cpu_curmv = newtarg * 25 + 700;
229}
230
231static inline uint32_t
232cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv,
233    uint32_t plldiv)
234{
235
236	return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1));
237}
238
239static inline void
240cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz,
241    uint32_t *corediv, uint32_t *plldiv)
242{
243
244	*corediv = (cpu_mhz < 650) ? 1 : 0;
245	*plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2);
246}
247
248static inline uint32_t
249cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
250{
251	uint32_t corediv, plldiv;
252
253	cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv);
254	return (cpufreq_mhz_from_div(sc, corediv, plldiv));
255}
256
257static struct oppt *
258cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz)
259{
260	int d, diff, i, nearest;
261
262	if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
263		cpu_newmhz = sc->cpu_maxmhz_hw;
264
265	diff = INT_MAX;
266	nearest = 0;
267	for (i = 0; i < nitems(imx6_oppt_table); ++i) {
268		d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
269		if (diff > d) {
270			diff = d;
271			nearest = i;
272		}
273	}
274	return (&imx6_oppt_table[nearest]);
275}
276
277static void
278cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
279{
280	uint32_t corediv, plldiv, timeout, wrk32;
281
282	/* If increasing the frequency, we must first increase the voltage. */
283	if (op->mhz > sc->cpu_curmhz) {
284		vdd_set(sc, op->mv);
285	}
286
287	/*
288	 * I can't find a documented procedure for changing the ARM PLL divisor,
289	 * but some trial and error came up with this:
290	 *  - Set the bypass clock source to REF_CLK_24M (source #0).
291	 *  - Set the PLL into bypass mode; cpu should now be running at 24mhz.
292	 *  - Change the divisor.
293	 *  - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
294	 *  - Turn off bypass mode; cpu should now be running at the new speed.
295	 */
296	cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
297	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
298	    IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
299	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
300	    IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
301
302	wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
303	wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
304	wrk32 |= plldiv;
305	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
306
307	timeout = 10000;
308	while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
309	    IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
310		if (--timeout == 0)
311			panic("imx6_set_cpu_clock(): PLL never locked");
312
313	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
314	    IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
315	imx_ccm_set_cacrr(corediv);
316
317	/* If lowering the frequency, it is now safe to lower the voltage. */
318	if (op->mhz < sc->cpu_curmhz)
319		vdd_set(sc, op->mv);
320	sc->cpu_curmhz = op->mhz;
321
322	/* Tell the mpcore timer that its frequency has changed. */
323	arm_tmr_change_frequency(
324	    cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
325}
326
327static int
328cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS)
329{
330	struct imx6_anatop_softc *sc;
331	struct oppt * op;
332	uint32_t temp;
333	int err;
334
335	sc = arg1;
336
337	temp = sc->cpu_minmhz;
338	err = sysctl_handle_int(oidp, &temp, 0, req);
339	if (err != 0 || req->newptr == NULL)
340		return (err);
341
342	op = cpufreq_nearest_oppt(sc, temp);
343	if (op->mhz > sc->cpu_maxmhz)
344		return (ERANGE);
345	else if (op->mhz == sc->cpu_minmhz)
346		return (0);
347
348	/*
349	 * Value changed, update softc.  If the new min is higher than the
350	 * current speed, raise the current speed to match.
351	 */
352	sc->cpu_minmhz = op->mhz;
353	if (sc->cpu_minmhz > sc->cpu_curmhz) {
354		cpufreq_set_clock(sc, op);
355	}
356	return (err);
357}
358
359static int
360cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS)
361{
362	struct imx6_anatop_softc *sc;
363	struct oppt * op;
364	uint32_t temp;
365	int err;
366
367	sc = arg1;
368
369	temp = sc->cpu_maxmhz;
370	err = sysctl_handle_int(oidp, &temp, 0, req);
371	if (err != 0 || req->newptr == NULL)
372		return (err);
373
374	op = cpufreq_nearest_oppt(sc, temp);
375	if (op->mhz < sc->cpu_minmhz)
376		return (ERANGE);
377	else if (op->mhz == sc->cpu_maxmhz)
378		return (0);
379
380	/*
381	 *  Value changed, update softc and hardware.  The hardware update is
382	 *  unconditional.  We always try to run at max speed, so any change of
383	 *  the max means we need to change the current speed too, regardless of
384	 *  whether it is higher or lower than the old max.
385	 */
386	sc->cpu_maxmhz = op->mhz;
387	cpufreq_set_clock(sc, op);
388
389	return (err);
390}
391
392static void
393cpufreq_initialize(struct imx6_anatop_softc *sc)
394{
395	uint32_t cfg3speed;
396	struct oppt * op;
397
398	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
399	    OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
400	    "CPU frequency");
401
402	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
403	    OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
404	    cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency");
405
406	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
407	    OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
408	    cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency");
409
410	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
411	    OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
412	    "Maximum CPU frequency allowed by hardware");
413
414	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
415	    OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN,
416	    &sc->cpu_overclock_enable, 0,
417	    "Allow setting CPU frequency higher than cpu_maxmhz_hw");
418
419	/*
420	 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
421	 * (even though in the real world it will always be 24mhz).  Oh wait a
422	 * sec, I never wrote imx6_ccm.
423	 */
424	sc->refosc_mhz = 24;
425
426	/*
427	 * Get the maximum speed this cpu can be set to.  The values in the
428	 * OCOTP CFG3 register are not documented in the reference manual.
429	 * The following info was in an archived email found via web search:
430	 *   - 2b'11: 1200000000Hz;
431	 *   - 2b'10: 996000000Hz;
432	 *   - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
433	 *   - 2b'00: 792000000Hz;
434	 * The default hardware max speed can be overridden by a tunable.
435	 */
436	cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) &
437	    FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT;
438	sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
439	sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
440
441	TUNABLE_INT_FETCH("hw.imx6.cpu_overclock_enable",
442	    &sc->cpu_overclock_enable);
443
444	TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
445	op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
446	sc->cpu_minmhz = op->mhz;
447	sc->cpu_minmv = op->mv;
448
449	TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
450	op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
451	sc->cpu_maxmhz = op->mhz;
452	sc->cpu_maxmv = op->mv;
453
454	/*
455	 * Set the CPU to maximum speed.
456	 *
457	 * We won't have thermal throttling until interrupts are enabled, but we
458	 * want to run at full speed through all the device init stuff.  This
459	 * basically assumes that a single core can't overheat before interrupts
460	 * are enabled; empirical testing shows that to be a safe assumption.
461	 */
462	cpufreq_set_clock(sc, op);
463}
464
465static inline uint32_t
466temp_from_count(struct imx6_anatop_softc *sc, uint32_t count)
467{
468
469	return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
470	    (sc->temp_high_val - 250) /
471	    (sc->temp_room_cnt - sc->temp_high_cnt))));
472}
473
474static inline uint32_t
475temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp)
476{
477
478	return ((sc->temp_room_cnt - sc->temp_high_cnt) *
479	    (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
480	    sc->temp_high_cnt);
481}
482
483static void
484temp_update_count(struct imx6_anatop_softc *sc)
485{
486	uint32_t val;
487
488	val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0);
489	if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID))
490		return;
491	sc->temp_last_cnt =
492	    (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >>
493	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
494}
495
496static int
497temp_sysctl_handler(SYSCTL_HANDLER_ARGS)
498{
499	struct imx6_anatop_softc *sc = arg1;
500	uint32_t t;
501
502	temp_update_count(sc);
503
504	t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
505
506	return (sysctl_handle_int(oidp, &t, 0, req));
507}
508
509static int
510temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
511{
512	struct imx6_anatop_softc *sc = arg1;
513	int err;
514	uint32_t temp;
515
516	temp = sc->temp_throttle_val + TZ_ZEROC;
517	err = sysctl_handle_int(oidp, &temp, 0, req);
518	if (temp < TZ_ZEROC)
519		return (ERANGE);
520	temp -= TZ_ZEROC;
521	if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
522		return (err);
523
524	/* Value changed, update counts in softc and hardware. */
525	sc->temp_throttle_val = temp;
526	sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
527	sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
528	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
529	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
530	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
531	    (sc->temp_throttle_trigger_cnt <<
532	     IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
533	return (err);
534}
535
536static void
537tempmon_gofast(struct imx6_anatop_softc *sc)
538{
539
540	if (sc->cpu_curmhz < sc->cpu_maxmhz) {
541		cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
542	}
543}
544
545static void
546tempmon_goslow(struct imx6_anatop_softc *sc)
547{
548
549	if (sc->cpu_curmhz > sc->cpu_minmhz) {
550		cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
551	}
552}
553
554static int
555tempmon_intr(void *arg)
556{
557	struct imx6_anatop_softc *sc = arg;
558
559	/*
560	 * XXX Note that this code doesn't currently run (for some mysterious
561	 * reason we just never get an interrupt), so the real monitoring is
562	 * done by tempmon_throttle_check().
563	 */
564	tempmon_goslow(sc);
565	/* XXX Schedule callout to speed back up eventually. */
566	return (FILTER_HANDLED);
567}
568
569static void
570tempmon_throttle_check(void *arg)
571{
572	struct imx6_anatop_softc *sc = arg;
573
574	/* Lower counts are higher temperatures. */
575	if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
576		tempmon_goslow(sc);
577	else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
578		tempmon_gofast(sc);
579
580	callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
581		0, tempmon_throttle_check, sc, 0);
582
583}
584
585static void
586initialize_tempmon(struct imx6_anatop_softc *sc)
587{
588	uint32_t cal;
589
590	/*
591	 * Fetch calibration data: a sensor count at room temperature (25C),
592	 * a sensor count at a high temperature, and that temperature
593	 */
594	cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
595	sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
596	sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
597	sc->temp_high_val = (cal & 0x000000FF) * 10;
598
599	/*
600	 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and
601	 * reset back to max cpu freq at 5C below the trigger.
602	 */
603	sc->temp_throttle_val = sc->temp_high_val - 100;
604	sc->temp_throttle_trigger_cnt =
605	    temp_to_count(sc, sc->temp_throttle_val);
606	sc->temp_throttle_reset_cnt =
607	    temp_to_count(sc, sc->temp_throttle_val - 50);
608
609	/*
610	 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
611	 * the throttle count, and begin making measurements.
612	 */
613	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
614	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
615	    (sc->temp_throttle_trigger_cnt <<
616	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
617	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
618
619	/*
620	 * XXX Note that the alarm-interrupt feature isn't working yet, so
621	 * we'll use a callout handler to check at 10Hz.  Make sure we have an
622	 * initial temperature reading before starting up the callouts so we
623	 * don't get a bogus reading of zero.
624	 */
625	while (sc->temp_last_cnt == 0)
626		temp_update_count(sc);
627	sc->temp_throttle_delay = 100 * SBT_1MS;
628	callout_init(&sc->temp_throttle_callout, 0);
629	callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
630	    0, tempmon_throttle_check, sc, 0);
631
632	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
633	    OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
634	    temp_sysctl_handler, "IK", "Current die temperature");
635	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
636	    OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc,
637	    0, temp_throttle_sysctl_handler, "IK",
638	    "Throttle CPU when exceeding this temperature");
639}
640
641static void
642intr_setup(void *arg)
643{
644	struct imx6_anatop_softc *sc;
645
646	sc = arg;
647	bus_setup_intr(sc->dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE,
648	    tempmon_intr, NULL, sc, &sc->temp_intrhand);
649	config_intrhook_disestablish(&sc->intr_setup_hook);
650}
651
652static void
653imx6_anatop_new_pass(device_t dev)
654{
655	struct imx6_anatop_softc *sc;
656	const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE;
657
658	/*
659	 * We attach during BUS_PASS_BUS (because some day we will be a
660	 * simplebus that has regulator devices as children), but some of our
661	 * init work cannot be done until BUS_PASS_CPU (we rely on other devices
662	 * that attach on the CPU pass).
663	 */
664	sc = device_get_softc(dev);
665	if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) {
666		sc->cpu_init_done = true;
667		cpufreq_initialize(sc);
668		initialize_tempmon(sc);
669		if (bootverbose) {
670			device_printf(sc->dev, "CPU %uMHz @ %umV\n",
671			    sc->cpu_curmhz, sc->cpu_curmv);
672		}
673	}
674	bus_generic_new_pass(dev);
675}
676
677static int
678imx6_anatop_detach(device_t dev)
679{
680
681	/* This device can never detach. */
682	return (EBUSY);
683}
684
685static int
686imx6_anatop_attach(device_t dev)
687{
688	struct imx6_anatop_softc *sc;
689	int err;
690
691	sc = device_get_softc(dev);
692	sc->dev = dev;
693
694	/* Allocate bus_space resources. */
695	if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
696		device_printf(dev, "Cannot allocate resources\n");
697		err = ENXIO;
698		goto out;
699	}
700
701	sc->intr_setup_hook.ich_func = intr_setup;
702	sc->intr_setup_hook.ich_arg = sc;
703	config_intrhook_establish(&sc->intr_setup_hook);
704
705	SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
706	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
707	    OID_AUTO, "cpu_voltage", CTLFLAG_RD,
708	    &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
709
710	imx6_anatop_sc = sc;
711
712	/*
713	 * Other code seen on the net sets this SELFBIASOFF flag around the same
714	 * time the temperature sensor is set up, although it's unclear how the
715	 * two are related (if at all).
716	 */
717	imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
718	    IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
719
720	/*
721	 * Some day, when we're ready to deal with the actual anatop regulators
722	 * that are described in fdt data as children of this "bus", this would
723	 * be the place to invoke a simplebus helper routine to instantiate the
724	 * children from the fdt data.
725	 */
726
727	err = 0;
728
729out:
730
731	if (err != 0) {
732		bus_release_resources(dev, imx6_anatop_spec, sc->res);
733	}
734
735	return (err);
736}
737
738uint32_t
739pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
740{
741	int reg;
742
743	/*
744	 * Audio PLL (PLL4).
745	 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
746	 */
747
748	reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
749	reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
750		IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
751	reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
752	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
753	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
754	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
755
756	return (0);
757}
758
759static int
760imx6_anatop_probe(device_t dev)
761{
762
763	if (!ofw_bus_status_okay(dev))
764		return (ENXIO);
765
766	if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)
767		return (ENXIO);
768
769	device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power");
770
771	return (BUS_PROBE_DEFAULT);
772}
773
774uint32_t
775imx6_get_cpu_clock()
776{
777	uint32_t corediv, plldiv;
778
779	corediv = imx_ccm_get_cacrr();
780	plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
781	    IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
782	return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv));
783}
784
785static device_method_t imx6_anatop_methods[] = {
786	/* Device interface */
787	DEVMETHOD(device_probe,  imx6_anatop_probe),
788	DEVMETHOD(device_attach, imx6_anatop_attach),
789	DEVMETHOD(device_detach, imx6_anatop_detach),
790
791	/* Bus interface */
792	DEVMETHOD(bus_new_pass,  imx6_anatop_new_pass),
793
794	DEVMETHOD_END
795};
796
797static driver_t imx6_anatop_driver = {
798	"imx6_anatop",
799	imx6_anatop_methods,
800	sizeof(struct imx6_anatop_softc)
801};
802
803static devclass_t imx6_anatop_devclass;
804
805EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver,
806    imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
807EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver,
808    imx6_anatop_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
809
810