bcm2835_sdhci.c revision 252449
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 252449 2013-07-01 06:32:56Z rpaulo $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/taskqueue.h> 46#include <sys/time.h> 47#include <sys/timetc.h> 48#include <sys/watchdog.h> 49 50#include <sys/kdb.h> 51 52#include <machine/bus.h> 53#include <machine/cpu.h> 54#include <machine/cpufunc.h> 55#include <machine/resource.h> 56#include <machine/frame.h> 57#include <machine/intr.h> 58 59#include <dev/fdt/fdt_common.h> 60#include <dev/ofw/ofw_bus.h> 61#include <dev/ofw/ofw_bus_subr.h> 62 63#include <dev/mmc/bridge.h> 64#include <dev/mmc/mmcreg.h> 65#include <dev/mmc/mmcbrvar.h> 66 67#include <dev/sdhci/sdhci.h> 68#include "sdhci_if.h" 69 70#include "bcm2835_dma.h" 71#include "bcm2835_vcbus.h" 72 73#define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75#define BCM_SDHCI_BUFFER_SIZE 512 76 77#ifdef DEBUG 78#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 79 printf(fmt,##args); } while (0) 80#else 81#define dprintf(fmt, args...) 82#endif 83 84/* 85 * Arasan HC seems to have problem with Data CRC on lower frequencies. 86 * Use this tunable to cap initialization sequence frequency at higher 87 * value. Default is standard 400kHz 88 */ 89static int bcm2835_sdhci_min_freq = 400000; 90static int bcm2835_sdhci_hs = 1; 91static int bcm2835_sdhci_pio_mode = 0; 92 93TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 94TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 95TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 96 97struct bcm_sdhci_dmamap_arg { 98 bus_addr_t sc_dma_busaddr; 99}; 100 101struct bcm_sdhci_softc { 102 device_t sc_dev; 103 struct mtx sc_mtx; 104 struct resource * sc_mem_res; 105 struct resource * sc_irq_res; 106 bus_space_tag_t sc_bst; 107 bus_space_handle_t sc_bsh; 108 void * sc_intrhand; 109 struct mmc_request * sc_req; 110 struct mmc_data * sc_data; 111 uint32_t sc_flags; 112#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 113 int sc_xfer_direction; 114#define DIRECTION_READ 0 115#define DIRECTION_WRITE 1 116 int sc_xfer_done; 117 int sc_bus_busy; 118 struct sdhci_slot sc_slot; 119 int sc_dma_inuse; 120 int sc_dma_ch; 121 bus_dma_tag_t sc_dma_tag; 122 bus_dmamap_t sc_dma_map; 123 vm_paddr_t sc_sdhci_buffer_phys; 124}; 125 126static int bcm_sdhci_probe(device_t); 127static int bcm_sdhci_attach(device_t); 128static int bcm_sdhci_detach(device_t); 129static void bcm_sdhci_intr(void *); 130 131static int bcm_sdhci_get_ro(device_t, device_t); 132static void bcm_sdhci_dma_intr(int ch, void *arg); 133 134#define bcm_sdhci_lock(_sc) \ 135 mtx_lock(&_sc->sc_mtx); 136#define bcm_sdhci_unlock(_sc) \ 137 mtx_unlock(&_sc->sc_mtx); 138 139static void 140bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 141 int nseg, int err) 142{ 143 bus_addr_t *addr; 144 145 if (err) 146 return; 147 148 addr = (bus_addr_t*)arg; 149 *addr = segs[0].ds_addr; 150} 151 152static int 153bcm_sdhci_probe(device_t dev) 154{ 155 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 156 return (ENXIO); 157 158 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 159 return (BUS_PROBE_DEFAULT); 160} 161 162static int 163bcm_sdhci_attach(device_t dev) 164{ 165 struct bcm_sdhci_softc *sc = device_get_softc(dev); 166 int rid, err; 167 phandle_t node; 168 pcell_t cell; 169 int default_freq; 170 171 sc->sc_dev = dev; 172 sc->sc_req = NULL; 173 err = 0; 174 175 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 176 node = ofw_bus_get_node(sc->sc_dev); 177 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 178 default_freq = (int)fdt32_to_cpu(cell)/1000000; 179 180 dprintf("SDHCI frequency: %dMHz\n", default_freq); 181 182 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 183 184 rid = 0; 185 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 186 RF_ACTIVE); 187 if (!sc->sc_mem_res) { 188 device_printf(dev, "cannot allocate memory window\n"); 189 err = ENXIO; 190 goto fail; 191 } 192 193 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 194 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 195 196 rid = 0; 197 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 198 RF_ACTIVE); 199 if (!sc->sc_irq_res) { 200 device_printf(dev, "cannot allocate interrupt\n"); 201 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 202 err = ENXIO; 203 goto fail; 204 } 205 206 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 207 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 208 { 209 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 210 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 211 device_printf(dev, "cannot setup interrupt handler\n"); 212 err = ENXIO; 213 goto fail; 214 } 215 216 if (!bcm2835_sdhci_pio_mode) 217 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 218 219 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 220 if (bcm2835_sdhci_hs) 221 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 222 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 223 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 224 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 225 | SDHCI_QUIRK_MISSING_CAPS; 226 227 sdhci_init_slot(dev, &sc->sc_slot, 0); 228 229 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 230 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 231 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 232 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 233 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 234 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 235 goto fail; 236 237 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 238 239 /* Allocate bus_dma resources. */ 240 err = bus_dma_tag_create(bus_get_dma_tag(dev), 241 1, 0, BUS_SPACE_MAXADDR_32BIT, 242 BUS_SPACE_MAXADDR, NULL, NULL, 243 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE, 244 BUS_DMA_ALLOCNOW, NULL, NULL, 245 &sc->sc_dma_tag); 246 247 if (err) { 248 device_printf(dev, "failed allocate DMA tag"); 249 goto fail; 250 } 251 252 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 253 if (err) { 254 device_printf(dev, "bus_dmamap_create failed\n"); 255 goto fail; 256 } 257 258 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 259 SDHCI_BUFFER); 260 261 bus_generic_probe(dev); 262 bus_generic_attach(dev); 263 264 sdhci_start_slot(&sc->sc_slot); 265 266 return (0); 267 268fail: 269 if (sc->sc_intrhand) 270 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 271 if (sc->sc_irq_res) 272 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 273 if (sc->sc_mem_res) 274 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 275 276 return (err); 277} 278 279static int 280bcm_sdhci_detach(device_t dev) 281{ 282 283 return (EBUSY); 284} 285 286static void 287bcm_sdhci_intr(void *arg) 288{ 289 struct bcm_sdhci_softc *sc = arg; 290 291 sdhci_generic_intr(&sc->sc_slot); 292} 293 294static int 295bcm_sdhci_get_ro(device_t bus, device_t child) 296{ 297 298 return (0); 299} 300 301static inline uint32_t 302RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 303{ 304 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 305 return val; 306} 307 308static inline void 309WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 310{ 311 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 312 313 if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) 314 { 315 int timeout = 100000; 316 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) 317 && --timeout > 0) 318 continue; 319 320 if (timeout <= 0) 321 printf("sdhci_brcm: writing 0x%X to reg 0x%X " 322 "always gives 0x%X\n", 323 val, (uint32_t)off, 324 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); 325 } 326} 327 328static uint8_t 329bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 330{ 331 struct bcm_sdhci_softc *sc = device_get_softc(dev); 332 uint32_t val = RD4(sc, off & ~3); 333 334 return ((val >> (off & 3)*8) & 0xff); 335} 336 337static uint16_t 338bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 339{ 340 struct bcm_sdhci_softc *sc = device_get_softc(dev); 341 uint32_t val = RD4(sc, off & ~3); 342 343 return ((val >> (off & 3)*8) & 0xffff); 344} 345 346static uint32_t 347bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 348{ 349 struct bcm_sdhci_softc *sc = device_get_softc(dev); 350 351 return RD4(sc, off); 352} 353 354static void 355bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 356 uint32_t *data, bus_size_t count) 357{ 358 struct bcm_sdhci_softc *sc = device_get_softc(dev); 359 360 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 361} 362 363static void 364bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 365{ 366 struct bcm_sdhci_softc *sc = device_get_softc(dev); 367 uint32_t val32 = RD4(sc, off & ~3); 368 val32 &= ~(0xff << (off & 3)*8); 369 val32 |= (val << (off & 3)*8); 370 WR4(sc, off & ~3, val32); 371} 372 373static void 374bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 375{ 376 struct bcm_sdhci_softc *sc = device_get_softc(dev); 377 static uint32_t cmd_and_trandfer_mode; 378 uint32_t val32; 379 if (off == SDHCI_COMMAND_FLAGS) 380 val32 = cmd_and_trandfer_mode; 381 else 382 val32 = RD4(sc, off & ~3); 383 val32 &= ~(0xffff << (off & 3)*8); 384 val32 |= (val << (off & 3)*8); 385 if (off == SDHCI_TRANSFER_MODE) 386 cmd_and_trandfer_mode = val32; 387 else 388 WR4(sc, off & ~3, val32); 389} 390 391static void 392bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 393{ 394 struct bcm_sdhci_softc *sc = device_get_softc(dev); 395 WR4(sc, off, val); 396} 397 398static void 399bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 400 uint32_t *data, bus_size_t count) 401{ 402 struct bcm_sdhci_softc *sc = device_get_softc(dev); 403 404 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 405} 406 407static uint32_t 408bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 409{ 410 411 return bcm2835_sdhci_min_freq; 412} 413 414static void 415bcm_sdhci_dma_intr(int ch, void *arg) 416{ 417 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 418 struct sdhci_slot *slot = &sc->sc_slot; 419 uint32_t reg, mask; 420 bus_addr_t pmem; 421 vm_paddr_t pdst, psrc; 422 size_t len; 423 int left, sync_op; 424 425 mtx_lock(&slot->mtx); 426 427 len = bcm_dma_length(sc->sc_dma_ch); 428 if (slot->curcmd->data->flags & MMC_DATA_READ) { 429 sync_op = BUS_DMASYNC_POSTREAD; 430 mask = SDHCI_INT_DATA_AVAIL; 431 } else { 432 sync_op = BUS_DMASYNC_POSTWRITE; 433 mask = SDHCI_INT_SPACE_AVAIL; 434 } 435 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 436 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 437 438 slot->offset += len; 439 sc->sc_dma_inuse = 0; 440 441 left = min(BCM_SDHCI_BUFFER_SIZE, 442 slot->curcmd->data->len - slot->offset); 443 444 /* DATA END? */ 445 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 446 447 if (reg & SDHCI_INT_DATA_END) { 448 /* ACK for all outstanding interrupts */ 449 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 450 451 /* enable INT */ 452 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 453 | SDHCI_INT_DATA_END; 454 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 455 slot->intmask); 456 457 /* finish this data */ 458 sdhci_finish_data(slot); 459 } 460 else { 461 /* already available? */ 462 if (reg & mask) { 463 sc->sc_dma_inuse = 1; 464 465 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 466 bcm_sdhci_write_4(slot->bus, slot, 467 SDHCI_INT_STATUS, mask); 468 469 /* continue next DMA transfer */ 470 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 471 (uint8_t *)slot->curcmd->data->data + 472 slot->offset, left, bcm_dmamap_cb, &pmem, 0); 473 if (slot->curcmd->data->flags & MMC_DATA_READ) { 474 psrc = sc->sc_sdhci_buffer_phys; 475 pdst = pmem; 476 sync_op = BUS_DMASYNC_PREREAD; 477 } else { 478 psrc = pmem; 479 pdst = sc->sc_sdhci_buffer_phys; 480 sync_op = BUS_DMASYNC_PREWRITE; 481 } 482 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 483 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) { 484 /* XXX stop xfer, other error recovery? */ 485 device_printf(sc->sc_dev, "failed DMA start\n"); 486 } 487 } else { 488 /* wait for next data by INT */ 489 490 /* enable INT */ 491 slot->intmask |= SDHCI_INT_DATA_AVAIL | 492 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 493 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 494 slot->intmask); 495 } 496 } 497 498 mtx_unlock(&slot->mtx); 499} 500 501static void 502bcm_sdhci_read_dma(struct sdhci_slot *slot) 503{ 504 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 505 size_t left; 506 bus_addr_t paddr; 507 508 if (sc->sc_dma_inuse) { 509 device_printf(sc->sc_dev, "DMA in use\n"); 510 return; 511 } 512 513 sc->sc_dma_inuse = 1; 514 515 left = min(BCM_SDHCI_BUFFER_SIZE, 516 slot->curcmd->data->len - slot->offset); 517 518 KASSERT((left & 3) == 0, 519 ("%s: len = %d, not word-aligned", __func__, left)); 520 521 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 522 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 523 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 524 BCM_DMA_INC_ADDR, 525 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 526 527 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 528 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 529 bcm_dmamap_cb, &paddr, 0); 530 531 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 532 BUS_DMASYNC_PREREAD); 533 534 /* DMA start */ 535 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys, 536 paddr, left) != 0) 537 device_printf(sc->sc_dev, "failed DMA start\n"); 538} 539 540static void 541bcm_sdhci_write_dma(struct sdhci_slot *slot) 542{ 543 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 544 size_t left; 545 bus_addr_t paddr; 546 547 if (sc->sc_dma_inuse) { 548 device_printf(sc->sc_dev, "DMA in use\n"); 549 return; 550 } 551 552 sc->sc_dma_inuse = 1; 553 554 left = min(BCM_SDHCI_BUFFER_SIZE, 555 slot->curcmd->data->len - slot->offset); 556 557 KASSERT((left & 3) == 0, 558 ("%s: len = %d, not word-aligned", __func__, left)); 559 560 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 561 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 562 bcm_dmamap_cb, &paddr, 0); 563 564 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 565 BCM_DMA_INC_ADDR, 566 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 567 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 568 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 569 570 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 571 BUS_DMASYNC_PREWRITE); 572 573 /* DMA start */ 574 if (bcm_dma_start(sc->sc_dma_ch, paddr, 575 sc->sc_sdhci_buffer_phys, left) != 0) 576 device_printf(sc->sc_dev, "failed DMA start\n"); 577} 578 579static int 580bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 581{ 582 size_t left; 583 584 /* 585 * Do not use DMA for transfers less than block size or with a length 586 * that is not a multiple of four. 587 */ 588 left = min(BCM_DMA_BLOCK_SIZE, 589 slot->curcmd->data->len - slot->offset); 590 if (left < BCM_DMA_BLOCK_SIZE) 591 return (0); 592 if (left & 0x03) 593 return (0); 594 595 return (1); 596} 597 598static void 599bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 600 uint32_t *intmask) 601{ 602 603 /* Disable INT */ 604 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 605 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 606 607 /* DMA transfer FIFO 1KB */ 608 if (slot->curcmd->data->flags & MMC_DATA_READ) 609 bcm_sdhci_read_dma(slot); 610 else 611 bcm_sdhci_write_dma(slot); 612} 613 614static void 615bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 616{ 617 618 sdhci_finish_data(slot); 619} 620 621static device_method_t bcm_sdhci_methods[] = { 622 /* Device interface */ 623 DEVMETHOD(device_probe, bcm_sdhci_probe), 624 DEVMETHOD(device_attach, bcm_sdhci_attach), 625 DEVMETHOD(device_detach, bcm_sdhci_detach), 626 627 /* Bus interface */ 628 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 629 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 630 DEVMETHOD(bus_print_child, bus_generic_print_child), 631 632 /* MMC bridge interface */ 633 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 634 DEVMETHOD(mmcbr_request, sdhci_generic_request), 635 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 636 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 637 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 638 639 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 640 /* Platform transfer methods */ 641 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 642 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 643 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 644 /* SDHCI registers accessors */ 645 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 646 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 647 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 648 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 649 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 650 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 651 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 652 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 653 654 { 0, 0 } 655}; 656 657static devclass_t bcm_sdhci_devclass; 658 659static driver_t bcm_sdhci_driver = { 660 "sdhci_bcm", 661 bcm_sdhci_methods, 662 sizeof(struct bcm_sdhci_softc), 663}; 664 665DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 666MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 667