bcm2835_sdhci.c revision 248430
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 248430 2013-03-17 16:31:09Z ian $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/taskqueue.h> 46#include <sys/time.h> 47#include <sys/timetc.h> 48#include <sys/watchdog.h> 49 50#include <sys/kdb.h> 51 52#include <machine/bus.h> 53#include <machine/cpu.h> 54#include <machine/cpufunc.h> 55#include <machine/resource.h> 56#include <machine/frame.h> 57#include <machine/intr.h> 58 59#include <dev/fdt/fdt_common.h> 60#include <dev/ofw/ofw_bus.h> 61#include <dev/ofw/ofw_bus_subr.h> 62 63#include <dev/mmc/bridge.h> 64#include <dev/mmc/mmcreg.h> 65#include <dev/mmc/mmcbrvar.h> 66 67#include <dev/sdhci/sdhci.h> 68#include "sdhci_if.h" 69 70#include "bcm2835_dma.h" 71#include "bcm2835_vcbus.h" 72 73#define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75#define BCM_SDHCI_BUFFER_SIZE 512 76 77#define DEBUG 78 79#ifdef DEBUG 80#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 81 printf(fmt,##args); } while (0) 82#else 83#define dprintf(fmt, args...) 84#endif 85 86/* 87 * Arasan HC seems to have problem with Data CRC on lower frequencies. 88 * Use this tunable to cap initialization sequence frequency at higher 89 * value. Default is standard 400kHz 90 */ 91static int bcm2835_sdhci_min_freq = 400000; 92static int bcm2835_sdhci_hs = 1; 93static int bcm2835_sdhci_pio_mode = 0; 94 95TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 96TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 97TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 98 99struct bcm_sdhci_dmamap_arg { 100 bus_addr_t sc_dma_busaddr; 101}; 102 103struct bcm_sdhci_softc { 104 device_t sc_dev; 105 struct mtx sc_mtx; 106 struct resource * sc_mem_res; 107 struct resource * sc_irq_res; 108 bus_space_tag_t sc_bst; 109 bus_space_handle_t sc_bsh; 110 void * sc_intrhand; 111 struct mmc_request * sc_req; 112 struct mmc_data * sc_data; 113 uint32_t sc_flags; 114#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 115 int sc_xfer_direction; 116#define DIRECTION_READ 0 117#define DIRECTION_WRITE 1 118 int sc_xfer_done; 119 int sc_bus_busy; 120 struct sdhci_slot sc_slot; 121 int sc_dma_inuse; 122 int sc_dma_ch; 123 bus_dma_tag_t sc_dma_tag; 124 bus_dmamap_t sc_dma_map; 125 vm_paddr_t sc_sdhci_buffer_phys; 126}; 127 128static int bcm_sdhci_probe(device_t); 129static int bcm_sdhci_attach(device_t); 130static int bcm_sdhci_detach(device_t); 131static void bcm_sdhci_intr(void *); 132 133static int bcm_sdhci_get_ro(device_t, device_t); 134static void bcm_sdhci_dma_intr(int ch, void *arg); 135 136#define bcm_sdhci_lock(_sc) \ 137 mtx_lock(&_sc->sc_mtx); 138#define bcm_sdhci_unlock(_sc) \ 139 mtx_unlock(&_sc->sc_mtx); 140 141static void 142bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 143 int nseg, int err) 144{ 145 bus_addr_t *addr; 146 147 if (err) 148 return; 149 150 addr = (bus_addr_t*)arg; 151 *addr = segs[0].ds_addr; 152} 153 154static int 155bcm_sdhci_probe(device_t dev) 156{ 157 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 158 return (ENXIO); 159 160 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 161 return (BUS_PROBE_DEFAULT); 162} 163 164static int 165bcm_sdhci_attach(device_t dev) 166{ 167 struct bcm_sdhci_softc *sc = device_get_softc(dev); 168 int rid, err; 169 phandle_t node; 170 pcell_t cell; 171 int default_freq; 172 173 sc->sc_dev = dev; 174 sc->sc_req = NULL; 175 err = 0; 176 177 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 178 node = ofw_bus_get_node(sc->sc_dev); 179 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 180 default_freq = (int)fdt32_to_cpu(cell)/1000000; 181 182 dprintf("SDHCI frequency: %dMHz\n", default_freq); 183 184 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 185 186 rid = 0; 187 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 188 RF_ACTIVE); 189 if (!sc->sc_mem_res) { 190 device_printf(dev, "cannot allocate memory window\n"); 191 err = ENXIO; 192 goto fail; 193 } 194 195 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 196 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 197 198 rid = 0; 199 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 200 RF_ACTIVE); 201 if (!sc->sc_irq_res) { 202 device_printf(dev, "cannot allocate interrupt\n"); 203 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 204 err = ENXIO; 205 goto fail; 206 } 207 208 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 209 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 210 { 211 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 213 device_printf(dev, "cannot setup interrupt handler\n"); 214 err = ENXIO; 215 goto fail; 216 } 217 218 if (!bcm2835_sdhci_pio_mode) 219 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 220 221 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 222 if (bcm2835_sdhci_hs) 223 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 224 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 225 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 226 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 227 | SDHCI_QUIRK_MISSING_CAPS; 228 229 sdhci_init_slot(dev, &sc->sc_slot, 0); 230 231 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 232 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 233 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 234 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 235 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 236 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 237 goto fail; 238 239 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 240 241 /* Allocate bus_dma resources. */ 242 err = bus_dma_tag_create(bus_get_dma_tag(dev), 243 1, 0, BUS_SPACE_MAXADDR_32BIT, 244 BUS_SPACE_MAXADDR, NULL, NULL, 245 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE, 246 BUS_DMA_ALLOCNOW, NULL, NULL, 247 &sc->sc_dma_tag); 248 249 if (err) { 250 device_printf(dev, "failed allocate DMA tag"); 251 goto fail; 252 } 253 254 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 255 if (err) { 256 device_printf(dev, "bus_dmamap_create failed\n"); 257 goto fail; 258 } 259 260 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 261 SDHCI_BUFFER); 262 263 bus_generic_probe(dev); 264 bus_generic_attach(dev); 265 266 sdhci_start_slot(&sc->sc_slot); 267 268 return (0); 269 270fail: 271 if (sc->sc_intrhand) 272 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 273 if (sc->sc_irq_res) 274 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 275 if (sc->sc_mem_res) 276 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 277 278 return (err); 279} 280 281static int 282bcm_sdhci_detach(device_t dev) 283{ 284 285 return (EBUSY); 286} 287 288static void 289bcm_sdhci_intr(void *arg) 290{ 291 struct bcm_sdhci_softc *sc = arg; 292 293 sdhci_generic_intr(&sc->sc_slot); 294} 295 296static int 297bcm_sdhci_get_ro(device_t bus, device_t child) 298{ 299 300 return (0); 301} 302 303static inline uint32_t 304RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 305{ 306 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 307 return val; 308} 309 310static inline void 311WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 312{ 313 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 314 315 if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) 316 { 317 int timeout = 100000; 318 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) 319 && --timeout > 0) 320 continue; 321 322 if (timeout <= 0) 323 printf("sdhci_brcm: writing 0x%X to reg 0x%X " 324 "always gives 0x%X\n", 325 val, (uint32_t)off, 326 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); 327 } 328} 329 330static uint8_t 331bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 332{ 333 struct bcm_sdhci_softc *sc = device_get_softc(dev); 334 uint32_t val = RD4(sc, off & ~3); 335 336 return ((val >> (off & 3)*8) & 0xff); 337} 338 339static uint16_t 340bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 341{ 342 struct bcm_sdhci_softc *sc = device_get_softc(dev); 343 uint32_t val = RD4(sc, off & ~3); 344 345 return ((val >> (off & 3)*8) & 0xffff); 346} 347 348static uint32_t 349bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 350{ 351 struct bcm_sdhci_softc *sc = device_get_softc(dev); 352 353 return RD4(sc, off); 354} 355 356static void 357bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 358 uint32_t *data, bus_size_t count) 359{ 360 struct bcm_sdhci_softc *sc = device_get_softc(dev); 361 362 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 363} 364 365static void 366bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 367{ 368 struct bcm_sdhci_softc *sc = device_get_softc(dev); 369 uint32_t val32 = RD4(sc, off & ~3); 370 val32 &= ~(0xff << (off & 3)*8); 371 val32 |= (val << (off & 3)*8); 372 WR4(sc, off & ~3, val32); 373} 374 375static void 376bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 377{ 378 struct bcm_sdhci_softc *sc = device_get_softc(dev); 379 static uint32_t cmd_and_trandfer_mode; 380 uint32_t val32; 381 if (off == SDHCI_COMMAND_FLAGS) 382 val32 = cmd_and_trandfer_mode; 383 else 384 val32 = RD4(sc, off & ~3); 385 val32 &= ~(0xffff << (off & 3)*8); 386 val32 |= (val << (off & 3)*8); 387 if (off == SDHCI_TRANSFER_MODE) 388 cmd_and_trandfer_mode = val32; 389 else 390 WR4(sc, off & ~3, val32); 391} 392 393static void 394bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 395{ 396 struct bcm_sdhci_softc *sc = device_get_softc(dev); 397 WR4(sc, off, val); 398} 399 400static void 401bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 402 uint32_t *data, bus_size_t count) 403{ 404 struct bcm_sdhci_softc *sc = device_get_softc(dev); 405 406 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 407} 408 409static uint32_t 410bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 411{ 412 413 return bcm2835_sdhci_min_freq; 414} 415 416static void 417bcm_sdhci_dma_intr(int ch, void *arg) 418{ 419 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 420 struct sdhci_slot *slot = &sc->sc_slot; 421 uint32_t reg, mask; 422 bus_addr_t pmem; 423 vm_paddr_t pdst, psrc; 424 size_t len; 425 int left, sync_op; 426 427 mtx_lock(&slot->mtx); 428 429 len = bcm_dma_length(sc->sc_dma_ch); 430 if (slot->curcmd->data->flags & MMC_DATA_READ) { 431 sync_op = BUS_DMASYNC_POSTREAD; 432 mask = SDHCI_INT_DATA_AVAIL; 433 } else { 434 sync_op = BUS_DMASYNC_POSTWRITE; 435 mask = SDHCI_INT_SPACE_AVAIL; 436 } 437 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 438 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 439 440 slot->offset += len; 441 sc->sc_dma_inuse = 0; 442 443 left = min(BCM_SDHCI_BUFFER_SIZE, 444 slot->curcmd->data->len - slot->offset); 445 446 /* DATA END? */ 447 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 448 449 if (reg & SDHCI_INT_DATA_END) { 450 /* ACK for all outstanding interrupts */ 451 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 452 453 /* enable INT */ 454 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 455 | SDHCI_INT_DATA_END; 456 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 457 slot->intmask); 458 459 /* finish this data */ 460 sdhci_finish_data(slot); 461 } 462 else { 463 /* already available? */ 464 if (reg & mask) { 465 sc->sc_dma_inuse = 1; 466 467 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 468 bcm_sdhci_write_4(slot->bus, slot, 469 SDHCI_INT_STATUS, mask); 470 471 /* continue next DMA transfer */ 472 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 473 (uint8_t *)slot->curcmd->data->data + 474 slot->offset, left, bcm_dmamap_cb, &pmem, 0); 475 if (slot->curcmd->data->flags & MMC_DATA_READ) { 476 psrc = sc->sc_sdhci_buffer_phys; 477 pdst = pmem; 478 sync_op = BUS_DMASYNC_PREREAD; 479 } else { 480 psrc = pmem; 481 pdst = sc->sc_sdhci_buffer_phys; 482 sync_op = BUS_DMASYNC_PREWRITE; 483 } 484 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 485 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) { 486 /* XXX stop xfer, other error recovery? */ 487 device_printf(sc->sc_dev, "failed DMA start\n"); 488 } 489 } else { 490 /* wait for next data by INT */ 491 492 /* enable INT */ 493 slot->intmask |= SDHCI_INT_DATA_AVAIL | 494 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 495 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 496 slot->intmask); 497 } 498 } 499 500 mtx_unlock(&slot->mtx); 501} 502 503static void 504bcm_sdhci_read_dma(struct sdhci_slot *slot) 505{ 506 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 507 size_t left; 508 bus_addr_t paddr; 509 510 if (sc->sc_dma_inuse) { 511 device_printf(sc->sc_dev, "DMA in use\n"); 512 return; 513 } 514 515 sc->sc_dma_inuse = 1; 516 517 left = min(BCM_SDHCI_BUFFER_SIZE, 518 slot->curcmd->data->len - slot->offset); 519 520 KASSERT((left & 3) == 0, 521 ("%s: len = %d, not word-aligned", __func__, left)); 522 523 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 524 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 525 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 526 BCM_DMA_INC_ADDR, 527 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 528 529 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 530 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 531 bcm_dmamap_cb, &paddr, 0); 532 533 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 534 BUS_DMASYNC_PREREAD); 535 536 /* DMA start */ 537 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys, 538 paddr, left) != 0) 539 device_printf(sc->sc_dev, "failed DMA start\n"); 540} 541 542static void 543bcm_sdhci_write_dma(struct sdhci_slot *slot) 544{ 545 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 546 size_t left; 547 bus_addr_t paddr; 548 549 if (sc->sc_dma_inuse) { 550 device_printf(sc->sc_dev, "DMA in use\n"); 551 return; 552 } 553 554 sc->sc_dma_inuse = 1; 555 556 left = min(BCM_SDHCI_BUFFER_SIZE, 557 slot->curcmd->data->len - slot->offset); 558 559 KASSERT((left & 3) == 0, 560 ("%s: len = %d, not word-aligned", __func__, left)); 561 562 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 563 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 564 bcm_dmamap_cb, &paddr, 0); 565 566 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 567 BCM_DMA_INC_ADDR, 568 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 569 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 570 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 571 572 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 573 BUS_DMASYNC_PREWRITE); 574 575 /* DMA start */ 576 if (bcm_dma_start(sc->sc_dma_ch, paddr, 577 sc->sc_sdhci_buffer_phys, left) != 0) 578 device_printf(sc->sc_dev, "failed DMA start\n"); 579} 580 581static int 582bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 583{ 584 size_t left; 585 586 /* 587 * Do not use DMA for transfers less than block size or with a length 588 * that is not a multiple of four. 589 */ 590 left = min(BCM_DMA_BLOCK_SIZE, 591 slot->curcmd->data->len - slot->offset); 592 if (left < BCM_DMA_BLOCK_SIZE) 593 return (0); 594 if (left & 0x03) 595 return (0); 596 597 return (1); 598} 599 600static void 601bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 602 uint32_t *intmask) 603{ 604 605 /* Disable INT */ 606 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 607 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 608 609 /* DMA transfer FIFO 1KB */ 610 if (slot->curcmd->data->flags & MMC_DATA_READ) 611 bcm_sdhci_read_dma(slot); 612 else 613 bcm_sdhci_write_dma(slot); 614} 615 616static void 617bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 618{ 619 620 sdhci_finish_data(slot); 621} 622 623static device_method_t bcm_sdhci_methods[] = { 624 /* Device interface */ 625 DEVMETHOD(device_probe, bcm_sdhci_probe), 626 DEVMETHOD(device_attach, bcm_sdhci_attach), 627 DEVMETHOD(device_detach, bcm_sdhci_detach), 628 629 /* Bus interface */ 630 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 631 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 632 DEVMETHOD(bus_print_child, bus_generic_print_child), 633 634 /* MMC bridge interface */ 635 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 636 DEVMETHOD(mmcbr_request, sdhci_generic_request), 637 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 638 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 639 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 640 641 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 642 /* Platform transfer methods */ 643 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 644 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 645 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 646 /* SDHCI registers accessors */ 647 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 648 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 649 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 650 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 651 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 652 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 653 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 654 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 655 656 { 0, 0 } 657}; 658 659static devclass_t bcm_sdhci_devclass; 660 661static driver_t bcm_sdhci_driver = { 662 "sdhci_bcm", 663 bcm_sdhci_methods, 664 sizeof(struct bcm_sdhci_softc), 665}; 666 667DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 668MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 669