bcm2835_sdhci.c revision 247010 
1/*-
2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 247010 2013-02-19 21:24:52Z gonzo $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bio.h>
33#include <sys/bus.h>
34#include <sys/conf.h>
35#include <sys/endian.h>
36#include <sys/kernel.h>
37#include <sys/kthread.h>
38#include <sys/lock.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/mutex.h>
42#include <sys/queue.h>
43#include <sys/resource.h>
44#include <sys/rman.h>
45#include <sys/taskqueue.h>
46#include <sys/time.h>
47#include <sys/timetc.h>
48#include <sys/watchdog.h>
49
50#include <sys/kdb.h>
51
52#include <machine/bus.h>
53#include <machine/cpu.h>
54#include <machine/cpufunc.h>
55#include <machine/resource.h>
56#include <machine/frame.h>
57#include <machine/intr.h>
58
59#include <dev/fdt/fdt_common.h>
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62
63#include <dev/mmc/bridge.h>
64#include <dev/mmc/mmcreg.h>
65#include <dev/mmc/mmcbrvar.h>
66
67#include <dev/sdhci/sdhci.h>
68#include "sdhci_if.h"
69
70#define	BCM2835_DEFAULT_SDHCI_FREQ	50
71
72#define	DEBUG
73
74#ifdef DEBUG
75#define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
76    printf(fmt,##args); } while (0)
77#else
78#define dprintf(fmt, args...)
79#endif
80
81/*
82 * Arasan HC seems to have problem with Data CRC on lower frequencies.
83 * Use this tunable to cap initialization sequence frequency at higher
84 * value. Default is standard 400kHz
85 */
86static int bcm2835_sdhci_min_freq = 400000;
87static int bcm2835_sdhci_hs = 1;
88
89TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
90TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
91
92struct bcm_sdhci_dmamap_arg {
93	bus_addr_t		sc_dma_busaddr;
94};
95
96struct bcm_sdhci_softc {
97	device_t		sc_dev;
98	struct mtx		sc_mtx;
99	struct resource *	sc_mem_res;
100	struct resource *	sc_irq_res;
101	bus_space_tag_t		sc_bst;
102	bus_space_handle_t	sc_bsh;
103	void *			sc_intrhand;
104	struct mmc_request *	sc_req;
105	struct mmc_data *	sc_data;
106	uint32_t		sc_flags;
107#define	LPC_SD_FLAGS_IGNORECRC		(1 << 0)
108	int			sc_xfer_direction;
109#define	DIRECTION_READ		0
110#define	DIRECTION_WRITE		1
111	int			sc_xfer_done;
112	int			sc_bus_busy;
113	struct sdhci_slot	sc_slot;
114};
115
116#define	SD_MAX_BLOCKSIZE	1024
117/* XXX */
118
119static int bcm_sdhci_probe(device_t);
120static int bcm_sdhci_attach(device_t);
121static int bcm_sdhci_detach(device_t);
122static void bcm_sdhci_intr(void *);
123
124static int bcm_sdhci_get_ro(device_t, device_t);
125
126#define	bcm_sdhci_lock(_sc)						\
127    mtx_lock(&_sc->sc_mtx);
128#define	bcm_sdhci_unlock(_sc)						\
129    mtx_unlock(&_sc->sc_mtx);
130
131static int
132bcm_sdhci_probe(device_t dev)
133{
134	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
135		return (ENXIO);
136
137	device_set_desc(dev, "Broadcom 2708 SDHCI controller");
138	return (BUS_PROBE_DEFAULT);
139}
140
141static int
142bcm_sdhci_attach(device_t dev)
143{
144	struct bcm_sdhci_softc *sc = device_get_softc(dev);
145	int rid, err;
146	phandle_t node;
147	pcell_t cell;
148	int default_freq;
149
150	sc->sc_dev = dev;
151	sc->sc_req = NULL;
152
153	default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
154	node = ofw_bus_get_node(sc->sc_dev);
155	if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
156		default_freq = (int)fdt32_to_cpu(cell)/1000000;
157
158	dprintf("SDHCI frequency: %dMHz\n", default_freq);
159
160	mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
161
162	rid = 0;
163	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
164	    RF_ACTIVE);
165	if (!sc->sc_mem_res) {
166		device_printf(dev, "cannot allocate memory window\n");
167		err = ENXIO;
168		goto fail;
169	}
170
171	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
172	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
173
174	rid = 0;
175	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
176	    RF_ACTIVE);
177	if (!sc->sc_irq_res) {
178		device_printf(dev, "cannot allocate interrupt\n");
179		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
180		err = ENXIO;
181		goto fail;
182	}
183
184	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
185	    NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand))
186	{
187		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
188		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
189		device_printf(dev, "cannot setup interrupt handler\n");
190		err = ENXIO;
191		goto fail;
192	}
193
194	sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
195	if (bcm2835_sdhci_hs)
196		sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
197	sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
198	sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
199		| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
200		| SDHCI_QUIRK_MISSING_CAPS;
201
202	sdhci_init_slot(dev, &sc->sc_slot, 0);
203
204	bus_generic_probe(dev);
205	bus_generic_attach(dev);
206
207	sdhci_start_slot(&sc->sc_slot);
208
209	return (0);
210
211fail:
212	if (sc->sc_intrhand)
213		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
214	if (sc->sc_irq_res)
215		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
216	if (sc->sc_mem_res)
217		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
218
219	return (err);
220}
221
222static int
223bcm_sdhci_detach(device_t dev)
224{
225
226	return (EBUSY);
227}
228
229static void
230bcm_sdhci_intr(void *arg)
231{
232	struct bcm_sdhci_softc *sc = arg;
233
234	sdhci_generic_intr(&sc->sc_slot);
235}
236
237static int
238bcm_sdhci_get_ro(device_t bus, device_t child)
239{
240
241	return (0);
242}
243
244static inline uint32_t
245RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
246{
247	uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
248	return val;
249}
250
251static inline void
252WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
253{
254	bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
255
256	if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL))
257	{
258		int timeout = 100000;
259		while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)
260		    && --timeout > 0)
261			continue;
262
263		if (timeout <= 0)
264			printf("sdhci_brcm: writing 0x%X to reg 0x%X "
265				"always gives 0x%X\n",
266				val, (uint32_t)off,
267				bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
268	}
269}
270
271static uint8_t
272bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
273{
274	struct bcm_sdhci_softc *sc = device_get_softc(dev);
275	uint32_t val = RD4(sc, off & ~3);
276
277	return ((val >> (off & 3)*8) & 0xff);
278}
279
280static uint16_t
281bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
282{
283	struct bcm_sdhci_softc *sc = device_get_softc(dev);
284	uint32_t val = RD4(sc, off & ~3);
285
286	return ((val >> (off & 3)*8) & 0xffff);
287}
288
289static uint32_t
290bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
291{
292	struct bcm_sdhci_softc *sc = device_get_softc(dev);
293
294	return RD4(sc, off);
295}
296
297static void
298bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
299    uint32_t *data, bus_size_t count)
300{
301	struct bcm_sdhci_softc *sc = device_get_softc(dev);
302
303	bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
304}
305
306static void
307bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
308{
309	struct bcm_sdhci_softc *sc = device_get_softc(dev);
310	uint32_t val32 = RD4(sc, off & ~3);
311	val32 &= ~(0xff << (off & 3)*8);
312	val32 |= (val << (off & 3)*8);
313	WR4(sc, off & ~3, val32);
314}
315
316static void
317bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
318{
319	struct bcm_sdhci_softc *sc = device_get_softc(dev);
320	static uint32_t cmd_and_trandfer_mode;
321	uint32_t val32;
322	if (off == SDHCI_COMMAND_FLAGS)
323		val32 = cmd_and_trandfer_mode;
324	else
325		val32 = RD4(sc, off & ~3);
326	val32 &= ~(0xffff << (off & 3)*8);
327	val32 |= (val << (off & 3)*8);
328	if (off == SDHCI_TRANSFER_MODE)
329		cmd_and_trandfer_mode = val32;
330	else
331		WR4(sc, off & ~3, val32);
332}
333
334static void
335bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
336{
337	struct bcm_sdhci_softc *sc = device_get_softc(dev);
338	WR4(sc, off, val);
339}
340
341static void
342bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
343    uint32_t *data, bus_size_t count)
344{
345	struct bcm_sdhci_softc *sc = device_get_softc(dev);
346
347	bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
348}
349
350static uint32_t
351bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
352{
353
354	return bcm2835_sdhci_min_freq;
355}
356
357static device_method_t bcm_sdhci_methods[] = {
358	/* Device interface */
359	DEVMETHOD(device_probe,		bcm_sdhci_probe),
360	DEVMETHOD(device_attach,	bcm_sdhci_attach),
361	DEVMETHOD(device_detach,	bcm_sdhci_detach),
362
363	/* Bus interface */
364	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
365	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
366	DEVMETHOD(bus_print_child,	bus_generic_print_child),
367
368	/* MMC bridge interface */
369	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
370	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
371	DEVMETHOD(mmcbr_get_ro,		bcm_sdhci_get_ro),
372	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
373	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
374
375	/* SDHCI registers accessors */
376	DEVMETHOD(sdhci_min_freq,	bcm_sdhci_min_freq),
377	DEVMETHOD(sdhci_read_1,		bcm_sdhci_read_1),
378	DEVMETHOD(sdhci_read_2,		bcm_sdhci_read_2),
379	DEVMETHOD(sdhci_read_4,		bcm_sdhci_read_4),
380	DEVMETHOD(sdhci_read_multi_4,	bcm_sdhci_read_multi_4),
381	DEVMETHOD(sdhci_write_1,	bcm_sdhci_write_1),
382	DEVMETHOD(sdhci_write_2,	bcm_sdhci_write_2),
383	DEVMETHOD(sdhci_write_4,	bcm_sdhci_write_4),
384	DEVMETHOD(sdhci_write_multi_4,	bcm_sdhci_write_multi_4),
385
386	{ 0, 0 }
387};
388
389static devclass_t bcm_sdhci_devclass;
390
391static driver_t bcm_sdhci_driver = {
392	"sdhci_bcm",
393	bcm_sdhci_methods,
394	sizeof(struct bcm_sdhci_softc),
395};
396
397DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
398MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
399