bcm2835_sdhci.c revision 246888
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 246888 2013-02-17 00:23:42Z gonzo $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/taskqueue.h> 46#include <sys/time.h> 47#include <sys/timetc.h> 48#include <sys/watchdog.h> 49 50#include <sys/kdb.h> 51 52#include <machine/bus.h> 53#include <machine/cpu.h> 54#include <machine/cpufunc.h> 55#include <machine/resource.h> 56#include <machine/frame.h> 57#include <machine/intr.h> 58 59#include <dev/fdt/fdt_common.h> 60#include <dev/ofw/ofw_bus.h> 61#include <dev/ofw/ofw_bus_subr.h> 62 63#include <dev/mmc/bridge.h> 64#include <dev/mmc/mmcreg.h> 65#include <dev/mmc/mmcbrvar.h> 66 67#include <dev/sdhci/sdhci.h> 68#include "sdhci_if.h" 69 70#define BCM2835_DEFAULT_SDHCI_FREQ 50 71 72#define DEBUG 73 74#ifdef DEBUG 75#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 76 printf(fmt,##args); } while (0) 77#else 78#define dprintf(fmt, args...) 79#endif 80 81static int bcm2835_sdhci_min_freq = 8000000; 82static int bcm2835_sdhci_hs = 1; 83 84TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 85TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 86 87struct bcm_sdhci_dmamap_arg { 88 bus_addr_t sc_dma_busaddr; 89}; 90 91struct bcm_sdhci_softc { 92 device_t sc_dev; 93 struct mtx sc_mtx; 94 struct resource * sc_mem_res; 95 struct resource * sc_irq_res; 96 bus_space_tag_t sc_bst; 97 bus_space_handle_t sc_bsh; 98 void * sc_intrhand; 99 struct mmc_request * sc_req; 100 struct mmc_data * sc_data; 101 uint32_t sc_flags; 102#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 103 int sc_xfer_direction; 104#define DIRECTION_READ 0 105#define DIRECTION_WRITE 1 106 int sc_xfer_done; 107 int sc_bus_busy; 108 struct sdhci_slot sc_slot; 109}; 110 111#define SD_MAX_BLOCKSIZE 1024 112/* XXX */ 113 114static int bcm_sdhci_probe(device_t); 115static int bcm_sdhci_attach(device_t); 116static int bcm_sdhci_detach(device_t); 117static void bcm_sdhci_intr(void *); 118 119static int bcm_sdhci_get_ro(device_t, device_t); 120 121#define bcm_sdhci_lock(_sc) \ 122 mtx_lock(&_sc->sc_mtx); 123#define bcm_sdhci_unlock(_sc) \ 124 mtx_unlock(&_sc->sc_mtx); 125 126static int 127bcm_sdhci_probe(device_t dev) 128{ 129 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 130 return (ENXIO); 131 132 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 133 return (BUS_PROBE_DEFAULT); 134} 135 136static int 137bcm_sdhci_attach(device_t dev) 138{ 139 struct bcm_sdhci_softc *sc = device_get_softc(dev); 140 int rid, err; 141 phandle_t node; 142 pcell_t cell; 143 int default_freq; 144 145 sc->sc_dev = dev; 146 sc->sc_req = NULL; 147 148 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 149 node = ofw_bus_get_node(sc->sc_dev); 150 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 151 default_freq = (int)fdt32_to_cpu(cell)/1000000; 152 153 dprintf("SDHCI frequency: %dMHz\n", default_freq); 154 155 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 156 157 rid = 0; 158 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 159 RF_ACTIVE); 160 if (!sc->sc_mem_res) { 161 device_printf(dev, "cannot allocate memory window\n"); 162 err = ENXIO; 163 goto fail; 164 } 165 166 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 167 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 168 169 rid = 0; 170 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 171 RF_ACTIVE); 172 if (!sc->sc_irq_res) { 173 device_printf(dev, "cannot allocate interrupt\n"); 174 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 175 err = ENXIO; 176 goto fail; 177 } 178 179 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 180 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 181 { 182 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 183 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 184 device_printf(dev, "cannot setup interrupt handler\n"); 185 err = ENXIO; 186 goto fail; 187 } 188 189 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 190 if (bcm2835_sdhci_hs) 191 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 192 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 193 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 194 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 195 | SDHCI_QUIRK_MISSING_CAPS; 196 197 sdhci_init_slot(dev, &sc->sc_slot, 0); 198 199 bus_generic_probe(dev); 200 bus_generic_attach(dev); 201 202 sdhci_start_slot(&sc->sc_slot); 203 204 return (0); 205 206fail: 207 if (sc->sc_intrhand) 208 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 209 if (sc->sc_irq_res) 210 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 211 if (sc->sc_mem_res) 212 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 213 214 return (err); 215} 216 217static int 218bcm_sdhci_detach(device_t dev) 219{ 220 221 return (EBUSY); 222} 223 224static void 225bcm_sdhci_intr(void *arg) 226{ 227 struct bcm_sdhci_softc *sc = arg; 228 229 sdhci_generic_intr(&sc->sc_slot); 230} 231 232static int 233bcm_sdhci_get_ro(device_t bus, device_t child) 234{ 235 236 return (0); 237} 238 239static inline uint32_t 240RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 241{ 242 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 243 return val; 244} 245 246static inline void 247WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 248{ 249 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 250 251 if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) 252 { 253 int timeout = 100000; 254 while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) 255 && --timeout > 0) 256 continue; 257 258 if (timeout <= 0) 259 printf("sdhci_brcm: writing 0x%X to reg 0x%X " 260 "always gives 0x%X\n", 261 val, (uint32_t)off, 262 bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); 263 } 264} 265 266static uint8_t 267bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 268{ 269 struct bcm_sdhci_softc *sc = device_get_softc(dev); 270 uint32_t val = RD4(sc, off & ~3); 271 272 return ((val >> (off & 3)*8) & 0xff); 273} 274 275static uint16_t 276bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 277{ 278 struct bcm_sdhci_softc *sc = device_get_softc(dev); 279 uint32_t val = RD4(sc, off & ~3); 280 281 return ((val >> (off & 3)*8) & 0xffff); 282} 283 284static uint32_t 285bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 286{ 287 struct bcm_sdhci_softc *sc = device_get_softc(dev); 288 289 return RD4(sc, off); 290} 291 292static void 293bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 294 uint32_t *data, bus_size_t count) 295{ 296 struct bcm_sdhci_softc *sc = device_get_softc(dev); 297 298 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 299} 300 301static void 302bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 303{ 304 struct bcm_sdhci_softc *sc = device_get_softc(dev); 305 uint32_t val32 = RD4(sc, off & ~3); 306 val32 &= ~(0xff << (off & 3)*8); 307 val32 |= (val << (off & 3)*8); 308 WR4(sc, off & ~3, val32); 309} 310 311static void 312bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 313{ 314 struct bcm_sdhci_softc *sc = device_get_softc(dev); 315 static uint32_t cmd_and_trandfer_mode; 316 uint32_t val32; 317 if (off == SDHCI_COMMAND_FLAGS) 318 val32 = cmd_and_trandfer_mode; 319 else 320 val32 = RD4(sc, off & ~3); 321 val32 &= ~(0xffff << (off & 3)*8); 322 val32 |= (val << (off & 3)*8); 323 if (off == SDHCI_TRANSFER_MODE) 324 cmd_and_trandfer_mode = val32; 325 else 326 WR4(sc, off & ~3, val32); 327} 328 329static void 330bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 331{ 332 struct bcm_sdhci_softc *sc = device_get_softc(dev); 333 WR4(sc, off, val); 334} 335 336static void 337bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 338 uint32_t *data, bus_size_t count) 339{ 340 struct bcm_sdhci_softc *sc = device_get_softc(dev); 341 342 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 343} 344 345static uint32_t 346bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 347{ 348 349 /* 350 * Arasan HC seems to have problem with 351 * Data CRC on lower frequencies. Cap minimum 352 * frequncy at 8MHz (or whatever set via tunable) 353 * to work around this issue 354 */ 355 return bcm2835_sdhci_min_freq; 356} 357 358static device_method_t bcm_sdhci_methods[] = { 359 /* Device interface */ 360 DEVMETHOD(device_probe, bcm_sdhci_probe), 361 DEVMETHOD(device_attach, bcm_sdhci_attach), 362 DEVMETHOD(device_detach, bcm_sdhci_detach), 363 364 /* Bus interface */ 365 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 366 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 367 DEVMETHOD(bus_print_child, bus_generic_print_child), 368 369 /* MMC bridge interface */ 370 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 371 DEVMETHOD(mmcbr_request, sdhci_generic_request), 372 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 373 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 374 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 375 376 /* SDHCI registers accessors */ 377 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 378 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 379 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 380 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 381 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 382 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 383 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 384 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 385 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 386 387 { 0, 0 } 388}; 389 390static devclass_t bcm_sdhci_devclass; 391 392static driver_t bcm_sdhci_driver = { 393 "sdhci_bcm", 394 bcm_sdhci_methods, 395 sizeof(struct bcm_sdhci_softc), 396}; 397 398DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 399MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 400