1239268Sgonzo/*- 2276274Sian * Copyright (c) 2012-2014 Ian Lepore 3239268Sgonzo * Copyright (c) 2010 Mark Tinguely 4239268Sgonzo * Copyright (c) 2004 Olivier Houchard 5239268Sgonzo * Copyright (c) 2002 Peter Grehan 6239268Sgonzo * Copyright (c) 1997, 1998 Justin T. Gibbs. 7239268Sgonzo * All rights reserved. 8239268Sgonzo * 9239268Sgonzo * Redistribution and use in source and binary forms, with or without 10239268Sgonzo * modification, are permitted provided that the following conditions 11239268Sgonzo * are met: 12239268Sgonzo * 1. Redistributions of source code must retain the above copyright 13239268Sgonzo * notice, this list of conditions, and the following disclaimer, 14239268Sgonzo * without modification, immediately at the beginning of the file. 15239268Sgonzo * 2. The name of the author may not be used to endorse or promote products 16239268Sgonzo * derived from this software without specific prior written permission. 17239268Sgonzo * 18239268Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19239268Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20239268Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21239268Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22239268Sgonzo * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23239268Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24239268Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25239268Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26239268Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27239268Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28239268Sgonzo * SUCH DAMAGE. 29239268Sgonzo * 30239268Sgonzo * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31239268Sgonzo */ 32239268Sgonzo 33239268Sgonzo#include <sys/cdefs.h> 34239268Sgonzo__FBSDID("$FreeBSD: releng/10.3/sys/arm/arm/busdma_machdep-v6.c 282506 2015-05-05 19:47:17Z hselasky $"); 35239268Sgonzo 36239268Sgonzo#define _ARM32_BUS_DMA_PRIVATE 37239268Sgonzo#include <sys/param.h> 38239268Sgonzo#include <sys/kdb.h> 39239268Sgonzo#include <ddb/ddb.h> 40239268Sgonzo#include <ddb/db_output.h> 41239268Sgonzo#include <sys/systm.h> 42239268Sgonzo#include <sys/malloc.h> 43239268Sgonzo#include <sys/bus.h> 44244469Scognet#include <sys/busdma_bufalloc.h> 45239268Sgonzo#include <sys/interrupt.h> 46239268Sgonzo#include <sys/kernel.h> 47239268Sgonzo#include <sys/ktr.h> 48239268Sgonzo#include <sys/lock.h> 49246713Skib#include <sys/memdesc.h> 50239268Sgonzo#include <sys/proc.h> 51239268Sgonzo#include <sys/mutex.h> 52246713Skib#include <sys/sysctl.h> 53239268Sgonzo#include <sys/uio.h> 54239268Sgonzo 55239268Sgonzo#include <vm/vm.h> 56239268Sgonzo#include <vm/vm_page.h> 57239268Sgonzo#include <vm/vm_map.h> 58244469Scognet#include <vm/vm_extern.h> 59244469Scognet#include <vm/vm_kern.h> 60239268Sgonzo 61239268Sgonzo#include <machine/atomic.h> 62239268Sgonzo#include <machine/bus.h> 63239268Sgonzo#include <machine/cpufunc.h> 64239268Sgonzo#include <machine/md_var.h> 65239268Sgonzo 66239268Sgonzo#define MAX_BPAGES 64 67269794Sian#define MAX_DMA_SEGMENTS 4096 68269794Sian#define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2 69269794Sian#define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3 70269794Sian#define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE) 71239268Sgonzo#define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 72239268Sgonzo 73239268Sgonzostruct bounce_zone; 74239268Sgonzo 75239268Sgonzostruct bus_dma_tag { 76239268Sgonzo bus_dma_tag_t parent; 77239268Sgonzo bus_size_t alignment; 78239268Sgonzo bus_size_t boundary; 79239268Sgonzo bus_addr_t lowaddr; 80239268Sgonzo bus_addr_t highaddr; 81239268Sgonzo bus_dma_filter_t *filter; 82239268Sgonzo void *filterarg; 83239268Sgonzo bus_size_t maxsize; 84239268Sgonzo u_int nsegments; 85239268Sgonzo bus_size_t maxsegsz; 86239268Sgonzo int flags; 87239268Sgonzo int ref_count; 88239268Sgonzo int map_count; 89239268Sgonzo bus_dma_lock_t *lockfunc; 90239268Sgonzo void *lockfuncarg; 91239268Sgonzo struct bounce_zone *bounce_zone; 92239268Sgonzo /* 93239268Sgonzo * DMA range for this tag. If the page doesn't fall within 94239268Sgonzo * one of these ranges, an error is returned. The caller 95239268Sgonzo * may then decide what to do with the transfer. If the 96239268Sgonzo * range pointer is NULL, it is ignored. 97239268Sgonzo */ 98239268Sgonzo struct arm32_dma_range *ranges; 99239268Sgonzo int _nranges; 100239268Sgonzo}; 101239268Sgonzo 102239268Sgonzostruct bounce_page { 103239268Sgonzo vm_offset_t vaddr; /* kva of bounce buffer */ 104239268Sgonzo bus_addr_t busaddr; /* Physical address */ 105239268Sgonzo vm_offset_t datavaddr; /* kva of client data */ 106246713Skib bus_addr_t dataaddr; /* client physical address */ 107239268Sgonzo bus_size_t datacount; /* client data count */ 108239268Sgonzo STAILQ_ENTRY(bounce_page) links; 109239268Sgonzo}; 110239268Sgonzo 111239268Sgonzostruct sync_list { 112239268Sgonzo vm_offset_t vaddr; /* kva of bounce buffer */ 113239268Sgonzo bus_addr_t busaddr; /* Physical address */ 114239268Sgonzo bus_size_t datacount; /* client data count */ 115239268Sgonzo}; 116239268Sgonzo 117239268Sgonzoint busdma_swi_pending; 118239268Sgonzo 119239268Sgonzostruct bounce_zone { 120239268Sgonzo STAILQ_ENTRY(bounce_zone) links; 121239268Sgonzo STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 122239268Sgonzo int total_bpages; 123239268Sgonzo int free_bpages; 124239268Sgonzo int reserved_bpages; 125239268Sgonzo int active_bpages; 126239268Sgonzo int total_bounced; 127239268Sgonzo int total_deferred; 128239268Sgonzo int map_count; 129239268Sgonzo bus_size_t alignment; 130239268Sgonzo bus_addr_t lowaddr; 131239268Sgonzo char zoneid[8]; 132239268Sgonzo char lowaddrid[20]; 133239268Sgonzo struct sysctl_ctx_list sysctl_tree; 134239268Sgonzo struct sysctl_oid *sysctl_tree_top; 135239268Sgonzo}; 136239268Sgonzo 137239268Sgonzostatic struct mtx bounce_lock; 138239268Sgonzostatic int total_bpages; 139239268Sgonzostatic int busdma_zonecount; 140269794Sianstatic uint32_t tags_total; 141269794Sianstatic uint32_t maps_total; 142269794Sianstatic uint32_t maps_dmamem; 143269794Sianstatic uint32_t maps_coherent; 144269794Sianstatic uint64_t maploads_total; 145269794Sianstatic uint64_t maploads_bounced; 146269794Sianstatic uint64_t maploads_coherent; 147269794Sianstatic uint64_t maploads_dmamem; 148269794Sianstatic uint64_t maploads_mbuf; 149269794Sianstatic uint64_t maploads_physmem; 150269794Sian 151239268Sgonzostatic STAILQ_HEAD(, bounce_zone) bounce_zone_list; 152239268Sgonzo 153239268SgonzoSYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 154269794SianSYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0, 155269794Sian "Number of active tags"); 156269794SianSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0, 157269794Sian "Number of active maps"); 158269794SianSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0, 159269794Sian "Number of active maps for bus_dmamem_alloc buffers"); 160269794SianSYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0, 161269794Sian "Number of active maps with BUS_DMA_COHERENT flag set"); 162269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, &maploads_total, 0, 163269794Sian "Number of load operations performed"); 164269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, &maploads_bounced, 0, 165269794Sian "Number of load operations that used bounce buffers"); 166269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, &maploads_dmamem, 0, 167269794Sian "Number of load operations on BUS_DMA_COHERENT memory"); 168269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, &maploads_dmamem, 0, 169269794Sian "Number of load operations on bus_dmamem_alloc buffers"); 170269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, &maploads_mbuf, 0, 171269794Sian "Number of load operations for mbufs"); 172269794SianSYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, &maploads_physmem, 0, 173269794Sian "Number of load operations on physical buffers"); 174239268SgonzoSYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 175239268Sgonzo "Total bounce pages"); 176239268Sgonzo 177239268Sgonzostruct bus_dmamap { 178239268Sgonzo struct bp_list bpages; 179239268Sgonzo int pagesneeded; 180239268Sgonzo int pagesreserved; 181239268Sgonzo bus_dma_tag_t dmat; 182246713Skib struct memdesc mem; 183239268Sgonzo pmap_t pmap; 184239268Sgonzo bus_dmamap_callback_t *callback; 185239268Sgonzo void *callback_arg; 186244469Scognet int flags; 187244469Scognet#define DMAMAP_COHERENT (1 << 0) 188269794Sian#define DMAMAP_DMAMEM_ALLOC (1 << 1) 189269794Sian#define DMAMAP_MBUF (1 << 2) 190239268Sgonzo STAILQ_ENTRY(bus_dmamap) links; 191269794Sian bus_dma_segment_t *segments; 192246713Skib int sync_count; 193246713Skib struct sync_list slist[]; 194239268Sgonzo}; 195239268Sgonzo 196239268Sgonzostatic STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 197239268Sgonzostatic STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 198239268Sgonzo 199239268Sgonzostatic void init_bounce_pages(void *dummy); 200239268Sgonzostatic int alloc_bounce_zone(bus_dma_tag_t dmat); 201239268Sgonzostatic int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 202239268Sgonzostatic int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 203239268Sgonzo int commit); 204239268Sgonzostatic bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 205246713Skib vm_offset_t vaddr, bus_addr_t addr, 206246713Skib bus_size_t size); 207239268Sgonzostatic void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 208246713Skibstatic void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 209239268Sgonzo void *buf, bus_size_t buflen, int flags); 210246713Skibstatic void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, 211246713Skib vm_paddr_t buf, bus_size_t buflen, int flags); 212246713Skibstatic int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 213246713Skib int flags); 214239268Sgonzo 215244469Scognetstatic busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */ 216244469Scognetstatic busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */ 217244469Scognetstatic void 218244469Scognetbusdma_init(void *dummy) 219244469Scognet{ 220252652Sgonzo int uma_flags; 221244469Scognet 222252652Sgonzo uma_flags = 0; 223252652Sgonzo 224244469Scognet /* Create a cache of buffers in standard (cacheable) memory. */ 225244469Scognet standard_allocator = busdma_bufalloc_create("buffer", 226244469Scognet arm_dcache_align, /* minimum_alignment */ 227244469Scognet NULL, /* uma_alloc func */ 228244469Scognet NULL, /* uma_free func */ 229252652Sgonzo uma_flags); /* uma_zcreate_flags */ 230244469Scognet 231252652Sgonzo#ifdef INVARIANTS 232252652Sgonzo /* 233252652Sgonzo * Force UMA zone to allocate service structures like 234252652Sgonzo * slabs using own allocator. uma_debug code performs 235252652Sgonzo * atomic ops on uma_slab_t fields and safety of this 236252652Sgonzo * operation is not guaranteed for write-back caches 237252652Sgonzo */ 238252652Sgonzo uma_flags = UMA_ZONE_OFFPAGE; 239252652Sgonzo#endif 240244469Scognet /* 241244469Scognet * Create a cache of buffers in uncacheable memory, to implement the 242244469Scognet * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. 243244469Scognet */ 244244469Scognet coherent_allocator = busdma_bufalloc_create("coherent", 245244469Scognet arm_dcache_align, /* minimum_alignment */ 246244469Scognet busdma_bufalloc_alloc_uncacheable, 247244469Scognet busdma_bufalloc_free_uncacheable, 248252652Sgonzo uma_flags); /* uma_zcreate_flags */ 249244469Scognet} 250244469Scognet 251244469Scognet/* 252244469Scognet * This init historically used SI_SUB_VM, but now the init code requires 253244469Scognet * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by 254244469Scognet * SI_SUB_KMEM and SI_ORDER_SECOND, so we'll go right after that by using 255244469Scognet * SI_SUB_KMEM and SI_ORDER_THIRD. 256244469Scognet */ 257244469ScognetSYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_THIRD, busdma_init, NULL); 258244469Scognet 259269794Sianstatic int 260269794Sianexclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr) 261239268Sgonzo{ 262239268Sgonzo int i; 263239268Sgonzo for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 264269794Sian if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) || 265269794Sian (lowaddr < phys_avail[i] && highaddr >= phys_avail[i])) 266239268Sgonzo return (1); 267239268Sgonzo } 268239268Sgonzo return (0); 269239268Sgonzo} 270239268Sgonzo 271269794Sian/* 272269794Sian * Return true if the tag has an exclusion zone that could lead to bouncing. 273269794Sian */ 274269794Sianstatic __inline int 275269794Sianexclusion_bounce(bus_dma_tag_t dmat) 276269794Sian{ 277269794Sian 278269794Sian return (dmat->flags & BUS_DMA_EXCL_BOUNCE); 279269794Sian} 280269794Sian 281269794Sian/* 282269794Sian * Return true if the given address does not fall on the alignment boundary. 283269794Sian */ 284269794Sianstatic __inline int 285269794Sianalignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr) 286269794Sian{ 287269794Sian 288269794Sian return (addr & (dmat->alignment - 1)); 289269794Sian} 290269794Sian 291269794Sian/* 292269794Sian * Return true if the DMA should bounce because the start or end does not fall 293269794Sian * on a cacheline boundary (which would require a partial cacheline flush). 294269794Sian * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by 295269794Sian * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a 296269794Sian * strict rule that such memory cannot be accessed by the CPU while DMA is in 297269794Sian * progress (or by multiple DMA engines at once), so that it's always safe to do 298269794Sian * full cacheline flushes even if that affects memory outside the range of a 299269794Sian * given DMA operation that doesn't involve the full allocated buffer. If we're 300269794Sian * mapping an mbuf, that follows the same rules as a buffer we allocated. 301269794Sian */ 302269794Sianstatic __inline int 303269794Siancacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size) 304269794Sian{ 305269794Sian 306269794Sian if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF)) 307269794Sian return (0); 308269794Sian return ((addr | size) & arm_dcache_align_mask); 309269794Sian} 310269794Sian 311269794Sian/* 312269794Sian * Return true if we might need to bounce the DMA described by addr and size. 313269794Sian * 314269794Sian * This is used to quick-check whether we need to do the more expensive work of 315269794Sian * checking the DMA page-by-page looking for alignment and exclusion bounces. 316269794Sian * 317269794Sian * Note that the addr argument might be either virtual or physical. It doesn't 318269794Sian * matter because we only look at the low-order bits, which are the same in both 319269794Sian * address spaces. 320269794Sian */ 321269794Sianstatic __inline int 322269794Sianmight_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 323269794Sian bus_size_t size) 324269794Sian{ 325276274Sian 326269794Sian return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) || 327269794Sian alignment_bounce(dmat, addr) || 328269794Sian cacheline_bounce(map, addr, size)); 329269794Sian} 330269794Sian 331269794Sian/* 332269794Sian * Return true if we must bounce the DMA described by paddr and size. 333269794Sian * 334269794Sian * Bouncing can be triggered by DMA that doesn't begin and end on cacheline 335269794Sian * boundaries, or doesn't begin on an alignment boundary, or falls within the 336269794Sian * exclusion zone of any tag in the ancestry chain. 337269794Sian * 338269794Sian * For exclusions, walk the chain of tags comparing paddr to the exclusion zone 339269794Sian * within each tag. If the tag has a filter function, use it to decide whether 340269794Sian * the DMA needs to bounce, otherwise any DMA within the zone bounces. 341269794Sian */ 342269794Sianstatic int 343269794Sianmust_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 344269794Sian bus_size_t size) 345269794Sian{ 346269794Sian 347269794Sian if (cacheline_bounce(map, paddr, size)) 348269794Sian return (1); 349269794Sian 350269794Sian /* 351269794Sian * The tag already contains ancestors' alignment restrictions so this 352269794Sian * check doesn't need to be inside the loop. 353269794Sian */ 354269794Sian if (alignment_bounce(dmat, paddr)) 355269794Sian return (1); 356269794Sian 357269794Sian /* 358269794Sian * Even though each tag has an exclusion zone that is a superset of its 359269794Sian * own and all its ancestors' exclusions, the exclusion zone of each tag 360269794Sian * up the chain must be checked within the loop, because the busdma 361269794Sian * rules say the filter function is called only when the address lies 362269794Sian * within the low-highaddr range of the tag that filterfunc belongs to. 363269794Sian */ 364269794Sian while (dmat != NULL && exclusion_bounce(dmat)) { 365269794Sian if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) && 366269794Sian (dmat->filter == NULL || 367269794Sian dmat->filter(dmat->filterarg, paddr) != 0)) 368269794Sian return (1); 369269794Sian dmat = dmat->parent; 370269794Sian } 371269794Sian 372269794Sian return (0); 373269794Sian} 374269794Sian 375239268Sgonzostatic __inline struct arm32_dma_range * 376239268Sgonzo_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 377239268Sgonzo bus_addr_t curaddr) 378239268Sgonzo{ 379239268Sgonzo struct arm32_dma_range *dr; 380239268Sgonzo int i; 381239268Sgonzo 382239268Sgonzo for (i = 0, dr = ranges; i < nranges; i++, dr++) { 383239268Sgonzo if (curaddr >= dr->dr_sysbase && 384239268Sgonzo round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 385239268Sgonzo return (dr); 386239268Sgonzo } 387239268Sgonzo 388239268Sgonzo return (NULL); 389239268Sgonzo} 390239268Sgonzo 391239268Sgonzo/* 392239268Sgonzo * Convenience function for manipulating driver locks from busdma (during 393239268Sgonzo * busdma_swi, for example). Drivers that don't provide their own locks 394239268Sgonzo * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 395239268Sgonzo * non-mutex locking scheme don't have to use this at all. 396239268Sgonzo */ 397239268Sgonzovoid 398239268Sgonzobusdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 399239268Sgonzo{ 400239268Sgonzo struct mtx *dmtx; 401239268Sgonzo 402239268Sgonzo dmtx = (struct mtx *)arg; 403239268Sgonzo switch (op) { 404239268Sgonzo case BUS_DMA_LOCK: 405239268Sgonzo mtx_lock(dmtx); 406239268Sgonzo break; 407239268Sgonzo case BUS_DMA_UNLOCK: 408239268Sgonzo mtx_unlock(dmtx); 409239268Sgonzo break; 410239268Sgonzo default: 411239268Sgonzo panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 412239268Sgonzo } 413239268Sgonzo} 414239268Sgonzo 415239268Sgonzo/* 416239268Sgonzo * dflt_lock should never get called. It gets put into the dma tag when 417239268Sgonzo * lockfunc == NULL, which is only valid if the maps that are associated 418239268Sgonzo * with the tag are meant to never be defered. 419239268Sgonzo * XXX Should have a way to identify which driver is responsible here. 420239268Sgonzo */ 421239268Sgonzostatic void 422239268Sgonzodflt_lock(void *arg, bus_dma_lock_op_t op) 423239268Sgonzo{ 424276274Sian 425239268Sgonzo panic("driver error: busdma dflt_lock called"); 426239268Sgonzo} 427239268Sgonzo 428239268Sgonzo/* 429239268Sgonzo * Allocate a device specific dma_tag. 430239268Sgonzo */ 431239268Sgonzoint 432239268Sgonzobus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 433239268Sgonzo bus_size_t boundary, bus_addr_t lowaddr, 434239268Sgonzo bus_addr_t highaddr, bus_dma_filter_t *filter, 435239268Sgonzo void *filterarg, bus_size_t maxsize, int nsegments, 436239268Sgonzo bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 437239268Sgonzo void *lockfuncarg, bus_dma_tag_t *dmat) 438239268Sgonzo{ 439239268Sgonzo bus_dma_tag_t newtag; 440239268Sgonzo int error = 0; 441239268Sgonzo 442239268Sgonzo#if 0 443239268Sgonzo if (!parent) 444239268Sgonzo parent = arm_root_dma_tag; 445239268Sgonzo#endif 446239268Sgonzo 447239268Sgonzo /* Basic sanity checking */ 448239268Sgonzo if (boundary != 0 && boundary < maxsegsz) 449239268Sgonzo maxsegsz = boundary; 450239268Sgonzo 451239268Sgonzo /* Return a NULL tag on failure */ 452239268Sgonzo *dmat = NULL; 453239268Sgonzo 454239268Sgonzo if (maxsegsz == 0) { 455239268Sgonzo return (EINVAL); 456239268Sgonzo } 457239268Sgonzo 458239268Sgonzo newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, 459239268Sgonzo M_ZERO | M_NOWAIT); 460239268Sgonzo if (newtag == NULL) { 461239268Sgonzo CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 462239268Sgonzo __func__, newtag, 0, error); 463239268Sgonzo return (ENOMEM); 464239268Sgonzo } 465239268Sgonzo 466239268Sgonzo newtag->parent = parent; 467239268Sgonzo newtag->alignment = alignment; 468239268Sgonzo newtag->boundary = boundary; 469239268Sgonzo newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1); 470239268Sgonzo newtag->highaddr = trunc_page((vm_paddr_t)highaddr) + 471239268Sgonzo (PAGE_SIZE - 1); 472239268Sgonzo newtag->filter = filter; 473239268Sgonzo newtag->filterarg = filterarg; 474239268Sgonzo newtag->maxsize = maxsize; 475239268Sgonzo newtag->nsegments = nsegments; 476239268Sgonzo newtag->maxsegsz = maxsegsz; 477239268Sgonzo newtag->flags = flags; 478239268Sgonzo newtag->ref_count = 1; /* Count ourself */ 479239268Sgonzo newtag->map_count = 0; 480239268Sgonzo newtag->ranges = bus_dma_get_range(); 481239268Sgonzo newtag->_nranges = bus_dma_get_range_nb(); 482239268Sgonzo if (lockfunc != NULL) { 483239268Sgonzo newtag->lockfunc = lockfunc; 484239268Sgonzo newtag->lockfuncarg = lockfuncarg; 485239268Sgonzo } else { 486239268Sgonzo newtag->lockfunc = dflt_lock; 487239268Sgonzo newtag->lockfuncarg = NULL; 488239268Sgonzo } 489239268Sgonzo 490239268Sgonzo /* Take into account any restrictions imposed by our parent tag */ 491239268Sgonzo if (parent != NULL) { 492239268Sgonzo newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr); 493239268Sgonzo newtag->highaddr = MAX(parent->highaddr, newtag->highaddr); 494269794Sian newtag->alignment = MAX(parent->alignment, newtag->alignment); 495269794Sian newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE; 496239268Sgonzo if (newtag->boundary == 0) 497239268Sgonzo newtag->boundary = parent->boundary; 498239268Sgonzo else if (parent->boundary != 0) 499239268Sgonzo newtag->boundary = MIN(parent->boundary, 500239268Sgonzo newtag->boundary); 501239268Sgonzo if (newtag->filter == NULL) { 502239268Sgonzo /* 503269794Sian * Short circuit to looking at our parent directly 504239268Sgonzo * since we have encapsulated all of its information 505239268Sgonzo */ 506239268Sgonzo newtag->filter = parent->filter; 507239268Sgonzo newtag->filterarg = parent->filterarg; 508239268Sgonzo newtag->parent = parent->parent; 509239268Sgonzo } 510239268Sgonzo if (newtag->parent != NULL) 511239268Sgonzo atomic_add_int(&parent->ref_count, 1); 512239268Sgonzo } 513239268Sgonzo 514269794Sian if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr)) 515269794Sian newtag->flags |= BUS_DMA_EXCL_BOUNCE; 516269794Sian if (alignment_bounce(newtag, 1)) 517269794Sian newtag->flags |= BUS_DMA_ALIGN_BOUNCE; 518239268Sgonzo 519259309Sian /* 520259309Sian * Any request can auto-bounce due to cacheline alignment, in addition 521259309Sian * to any alignment or boundary specifications in the tag, so if the 522259309Sian * ALLOCNOW flag is set, there's always work to do. 523259309Sian */ 524254061Scognet if ((flags & BUS_DMA_ALLOCNOW) != 0) { 525239268Sgonzo struct bounce_zone *bz; 526259309Sian /* 527259309Sian * Round size up to a full page, and add one more page because 528259309Sian * there can always be one more boundary crossing than the 529259309Sian * number of pages in a transfer. 530259309Sian */ 531259309Sian maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE; 532259309Sian 533239268Sgonzo if ((error = alloc_bounce_zone(newtag)) != 0) { 534239268Sgonzo free(newtag, M_DEVBUF); 535239268Sgonzo return (error); 536239268Sgonzo } 537239268Sgonzo bz = newtag->bounce_zone; 538239268Sgonzo 539239268Sgonzo if (ptoa(bz->total_bpages) < maxsize) { 540239268Sgonzo int pages; 541239268Sgonzo 542239268Sgonzo pages = atop(maxsize) - bz->total_bpages; 543239268Sgonzo 544239268Sgonzo /* Add pages to our bounce pool */ 545239268Sgonzo if (alloc_bounce_pages(newtag, pages) < pages) 546239268Sgonzo error = ENOMEM; 547239268Sgonzo } 548239268Sgonzo /* Performed initial allocation */ 549239268Sgonzo newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 550239268Sgonzo } else 551239268Sgonzo newtag->bounce_zone = NULL; 552239268Sgonzo 553239268Sgonzo if (error != 0) { 554239268Sgonzo free(newtag, M_DEVBUF); 555239268Sgonzo } else { 556269794Sian atomic_add_32(&tags_total, 1); 557239268Sgonzo *dmat = newtag; 558239268Sgonzo } 559239268Sgonzo CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 560239268Sgonzo __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 561239268Sgonzo return (error); 562239268Sgonzo} 563239268Sgonzo 564239268Sgonzoint 565239268Sgonzobus_dma_tag_destroy(bus_dma_tag_t dmat) 566239268Sgonzo{ 567239268Sgonzo bus_dma_tag_t dmat_copy; 568239268Sgonzo int error; 569239268Sgonzo 570239268Sgonzo error = 0; 571239268Sgonzo dmat_copy = dmat; 572239268Sgonzo 573239268Sgonzo if (dmat != NULL) { 574239268Sgonzo 575239268Sgonzo if (dmat->map_count != 0) { 576239268Sgonzo error = EBUSY; 577239268Sgonzo goto out; 578239268Sgonzo } 579239268Sgonzo 580239268Sgonzo while (dmat != NULL) { 581239268Sgonzo bus_dma_tag_t parent; 582239268Sgonzo 583239268Sgonzo parent = dmat->parent; 584239268Sgonzo atomic_subtract_int(&dmat->ref_count, 1); 585239268Sgonzo if (dmat->ref_count == 0) { 586269794Sian atomic_subtract_32(&tags_total, 1); 587239268Sgonzo free(dmat, M_DEVBUF); 588239268Sgonzo /* 589239268Sgonzo * Last reference count, so 590239268Sgonzo * release our reference 591239268Sgonzo * count on our parent. 592239268Sgonzo */ 593239268Sgonzo dmat = parent; 594239268Sgonzo } else 595239268Sgonzo dmat = NULL; 596239268Sgonzo } 597239268Sgonzo } 598239268Sgonzoout: 599239268Sgonzo CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 600239268Sgonzo return (error); 601239268Sgonzo} 602239268Sgonzo 603254061Scognetstatic int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp) 604254061Scognet{ 605276274Sian struct bounce_zone *bz; 606254061Scognet int maxpages; 607254061Scognet int error; 608254061Scognet 609254061Scognet if (dmat->bounce_zone == NULL) 610254061Scognet if ((error = alloc_bounce_zone(dmat)) != 0) 611254061Scognet return (error); 612254061Scognet bz = dmat->bounce_zone; 613254061Scognet /* Initialize the new map */ 614254061Scognet STAILQ_INIT(&(mapp->bpages)); 615254061Scognet 616254061Scognet /* 617259309Sian * Attempt to add pages to our pool on a per-instance basis up to a sane 618259309Sian * limit. Even if the tag isn't flagged as COULD_BOUNCE due to 619259309Sian * alignment and boundary constraints, it could still auto-bounce due to 620259309Sian * cacheline alignment, which requires at most two bounce pages. 621254061Scognet */ 622254229Scognet if (dmat->flags & BUS_DMA_COULD_BOUNCE) 623254229Scognet maxpages = MAX_BPAGES; 624254229Scognet else 625259309Sian maxpages = 2 * bz->map_count; 626269794Sian if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 || 627269794Sian (bz->map_count > 0 && bz->total_bpages < maxpages)) { 628254061Scognet int pages; 629254061Scognet 630259309Sian pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1; 631254061Scognet pages = MIN(maxpages - bz->total_bpages, pages); 632259309Sian pages = MAX(pages, 2); 633254061Scognet if (alloc_bounce_pages(dmat, pages) < pages) 634254061Scognet return (ENOMEM); 635254061Scognet 636254061Scognet if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) 637254061Scognet dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 638254061Scognet } 639254061Scognet bz->map_count++; 640254061Scognet return (0); 641254061Scognet} 642254061Scognet 643269794Sianstatic bus_dmamap_t 644269794Sianallocate_map(bus_dma_tag_t dmat, int mflags) 645269794Sian{ 646269794Sian int mapsize, segsize; 647269794Sian bus_dmamap_t map; 648269794Sian 649269794Sian /* 650269794Sian * Allocate the map. The map structure ends with an embedded 651269794Sian * variable-sized array of sync_list structures. Following that 652269794Sian * we allocate enough extra space to hold the array of bus_dma_segments. 653269794Sian */ 654269794Sian KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS, 655269794Sian ("cannot allocate %u dma segments (max is %u)", 656269794Sian dmat->nsegments, MAX_DMA_SEGMENTS)); 657269794Sian segsize = sizeof(struct bus_dma_segment) * dmat->nsegments; 658269794Sian mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments; 659269794Sian map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO); 660269794Sian if (map == NULL) { 661269794Sian CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 662269794Sian return (NULL); 663269794Sian } 664269794Sian map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize); 665269794Sian return (map); 666269794Sian} 667269794Sian 668239268Sgonzo/* 669239268Sgonzo * Allocate a handle for mapping from kva/uva/physical 670239268Sgonzo * address space into bus device space. 671239268Sgonzo */ 672239268Sgonzoint 673239268Sgonzobus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 674239268Sgonzo{ 675269794Sian bus_dmamap_t map; 676254061Scognet int error = 0; 677239268Sgonzo 678269794Sian *mapp = map = allocate_map(dmat, M_NOWAIT); 679269794Sian if (map == NULL) { 680239268Sgonzo CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 681239268Sgonzo return (ENOMEM); 682239268Sgonzo } 683239268Sgonzo 684239268Sgonzo /* 685269794Sian * Bouncing might be required if the driver asks for an exclusion 686269794Sian * region, a data alignment that is stricter than 1, or DMA that begins 687269794Sian * or ends with a partial cacheline. Whether bouncing will actually 688269794Sian * happen can't be known until mapping time, but we need to pre-allocate 689269794Sian * resources now because we might not be allowed to at mapping time. 690239268Sgonzo */ 691269794Sian error = allocate_bz_and_pages(dmat, map); 692254061Scognet if (error != 0) { 693269794Sian free(map, M_DEVBUF); 694254061Scognet *mapp = NULL; 695254061Scognet return (error); 696239268Sgonzo } 697269794Sian if (map->flags & DMAMAP_COHERENT) 698269794Sian atomic_add_32(&maps_coherent, 1); 699269794Sian atomic_add_32(&maps_total, 1); 700276874Sloos dmat->map_count++; 701276874Sloos 702269794Sian return (0); 703239268Sgonzo} 704239268Sgonzo 705239268Sgonzo/* 706239268Sgonzo * Destroy a handle for mapping from kva/uva/physical 707239268Sgonzo * address space into bus device space. 708239268Sgonzo */ 709239268Sgonzoint 710239268Sgonzobus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 711239268Sgonzo{ 712246713Skib if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) { 713239268Sgonzo CTR3(KTR_BUSDMA, "%s: tag %p error %d", 714239268Sgonzo __func__, dmat, EBUSY); 715239268Sgonzo return (EBUSY); 716239268Sgonzo } 717239268Sgonzo if (dmat->bounce_zone) 718239268Sgonzo dmat->bounce_zone->map_count--; 719269794Sian if (map->flags & DMAMAP_COHERENT) 720269794Sian atomic_subtract_32(&maps_coherent, 1); 721269794Sian atomic_subtract_32(&maps_total, 1); 722239268Sgonzo free(map, M_DEVBUF); 723239268Sgonzo dmat->map_count--; 724239268Sgonzo CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 725239268Sgonzo return (0); 726239268Sgonzo} 727239268Sgonzo 728239268Sgonzo 729239268Sgonzo/* 730239268Sgonzo * Allocate a piece of memory that can be efficiently mapped into 731239268Sgonzo * bus device space based on the constraints lited in the dma tag. 732239268Sgonzo * A dmamap to for use with dmamap_load is also allocated. 733239268Sgonzo */ 734239268Sgonzoint 735239268Sgonzobus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 736239268Sgonzo bus_dmamap_t *mapp) 737239268Sgonzo{ 738244469Scognet busdma_bufalloc_t ba; 739244469Scognet struct busdma_bufzone *bufzone; 740269794Sian bus_dmamap_t map; 741244469Scognet vm_memattr_t memattr; 742244469Scognet int mflags; 743239268Sgonzo 744239268Sgonzo if (flags & BUS_DMA_NOWAIT) 745239268Sgonzo mflags = M_NOWAIT; 746239268Sgonzo else 747239268Sgonzo mflags = M_WAITOK; 748269794Sian if (flags & BUS_DMA_ZERO) 749269794Sian mflags |= M_ZERO; 750239268Sgonzo 751269794Sian *mapp = map = allocate_map(dmat, mflags); 752269794Sian if (map == NULL) { 753239268Sgonzo CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 754239268Sgonzo __func__, dmat, dmat->flags, ENOMEM); 755239268Sgonzo return (ENOMEM); 756239268Sgonzo } 757269794Sian map->flags = DMAMAP_DMAMEM_ALLOC; 758239268Sgonzo 759269794Sian /* Choose a busdma buffer allocator based on memory type flags. */ 760244469Scognet if (flags & BUS_DMA_COHERENT) { 761244469Scognet memattr = VM_MEMATTR_UNCACHEABLE; 762244469Scognet ba = coherent_allocator; 763269794Sian map->flags |= DMAMAP_COHERENT; 764244469Scognet } else { 765244469Scognet memattr = VM_MEMATTR_DEFAULT; 766244469Scognet ba = standard_allocator; 767244469Scognet } 768239268Sgonzo 769244469Scognet /* 770244469Scognet * Try to find a bufzone in the allocator that holds a cache of buffers 771244469Scognet * of the right size for this request. If the buffer is too big to be 772244469Scognet * held in the allocator cache, this returns NULL. 773239268Sgonzo */ 774244469Scognet bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 775244469Scognet 776244469Scognet /* 777244469Scognet * Allocate the buffer from the uma(9) allocator if... 778244469Scognet * - It's small enough to be in the allocator (bufzone not NULL). 779244469Scognet * - The alignment constraint isn't larger than the allocation size 780244469Scognet * (the allocator aligns buffers to their size boundaries). 781244469Scognet * - There's no need to handle lowaddr/highaddr exclusion zones. 782244469Scognet * else allocate non-contiguous pages if... 783244469Scognet * - The page count that could get allocated doesn't exceed nsegments. 784244469Scognet * - The alignment constraint isn't larger than a page boundary. 785244469Scognet * - There are no boundary-crossing constraints. 786244469Scognet * else allocate a block of contiguous pages because one or more of the 787244469Scognet * constraints is something that only the contig allocator can fulfill. 788244469Scognet */ 789244469Scognet if (bufzone != NULL && dmat->alignment <= bufzone->size && 790269794Sian !exclusion_bounce(dmat)) { 791244469Scognet *vaddr = uma_zalloc(bufzone->umazone, mflags); 792244469Scognet } else if (dmat->nsegments >= btoc(dmat->maxsize) && 793244469Scognet dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) { 794254025Sjeff *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize, 795244469Scognet mflags, 0, dmat->lowaddr, memattr); 796239268Sgonzo } else { 797254025Sjeff *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize, 798244469Scognet mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary, 799244469Scognet memattr); 800239268Sgonzo } 801244469Scognet 802244469Scognet 803239268Sgonzo if (*vaddr == NULL) { 804239268Sgonzo CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 805239268Sgonzo __func__, dmat, dmat->flags, ENOMEM); 806269794Sian free(map, M_DEVBUF); 807239268Sgonzo *mapp = NULL; 808239268Sgonzo return (ENOMEM); 809239268Sgonzo } else if ((uintptr_t)*vaddr & (dmat->alignment - 1)) { 810239268Sgonzo printf("bus_dmamem_alloc failed to align memory properly.\n"); 811239268Sgonzo } 812269794Sian if (map->flags & DMAMAP_COHERENT) 813269794Sian atomic_add_32(&maps_coherent, 1); 814269794Sian atomic_add_32(&maps_dmamem, 1); 815269794Sian atomic_add_32(&maps_total, 1); 816239268Sgonzo dmat->map_count++; 817239268Sgonzo 818239268Sgonzo CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 819239268Sgonzo __func__, dmat, dmat->flags, 0); 820239268Sgonzo return (0); 821239268Sgonzo} 822239268Sgonzo 823239268Sgonzo/* 824239268Sgonzo * Free a piece of memory and it's allociated dmamap, that was allocated 825239268Sgonzo * via bus_dmamem_alloc. Make the same choice for free/contigfree. 826239268Sgonzo */ 827239268Sgonzovoid 828239268Sgonzobus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 829239268Sgonzo{ 830244469Scognet struct busdma_bufzone *bufzone; 831244469Scognet busdma_bufalloc_t ba; 832239268Sgonzo 833244469Scognet if (map->flags & DMAMAP_COHERENT) 834244469Scognet ba = coherent_allocator; 835244469Scognet else 836244469Scognet ba = standard_allocator; 837244469Scognet 838244469Scognet bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize); 839244469Scognet 840244469Scognet if (bufzone != NULL && dmat->alignment <= bufzone->size && 841269794Sian !exclusion_bounce(dmat)) 842244469Scognet uma_zfree(bufzone->umazone, vaddr); 843244469Scognet else 844254025Sjeff kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize); 845244469Scognet 846239268Sgonzo dmat->map_count--; 847269794Sian if (map->flags & DMAMAP_COHERENT) 848269794Sian atomic_subtract_32(&maps_coherent, 1); 849269794Sian atomic_subtract_32(&maps_total, 1); 850269794Sian atomic_subtract_32(&maps_dmamem, 1); 851239268Sgonzo free(map, M_DEVBUF); 852239268Sgonzo CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 853239268Sgonzo} 854239268Sgonzo 855246713Skibstatic void 856246713Skib_bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf, 857246713Skib bus_size_t buflen, int flags) 858246713Skib{ 859246713Skib bus_addr_t curaddr; 860246713Skib bus_size_t sgsize; 861246713Skib 862246713Skib if (map->pagesneeded == 0) { 863246713Skib CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 864246713Skib " map= %p, pagesneeded= %d", 865246713Skib dmat->lowaddr, dmat->boundary, dmat->alignment, 866246713Skib map, map->pagesneeded); 867246713Skib /* 868246713Skib * Count the number of bounce pages 869246713Skib * needed in order to complete this transfer 870246713Skib */ 871246713Skib curaddr = buf; 872246713Skib while (buflen != 0) { 873246713Skib sgsize = MIN(buflen, dmat->maxsegsz); 874269794Sian if (must_bounce(dmat, map, curaddr, sgsize) != 0) { 875246713Skib sgsize = MIN(sgsize, PAGE_SIZE); 876246713Skib map->pagesneeded++; 877246713Skib } 878246713Skib curaddr += sgsize; 879246713Skib buflen -= sgsize; 880246713Skib } 881246713Skib CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 882246713Skib } 883246713Skib} 884246713Skib 885246713Skibstatic void 886239268Sgonzo_bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 887239268Sgonzo void *buf, bus_size_t buflen, int flags) 888239268Sgonzo{ 889239268Sgonzo vm_offset_t vaddr; 890239268Sgonzo vm_offset_t vendaddr; 891239268Sgonzo bus_addr_t paddr; 892239268Sgonzo 893239268Sgonzo if (map->pagesneeded == 0) { 894239268Sgonzo CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d" 895239268Sgonzo " map= %p, pagesneeded= %d", 896239268Sgonzo dmat->lowaddr, dmat->boundary, dmat->alignment, 897239268Sgonzo map, map->pagesneeded); 898239268Sgonzo /* 899239268Sgonzo * Count the number of bounce pages 900239268Sgonzo * needed in order to complete this transfer 901239268Sgonzo */ 902239268Sgonzo vaddr = (vm_offset_t)buf; 903239268Sgonzo vendaddr = (vm_offset_t)buf + buflen; 904239268Sgonzo 905239268Sgonzo while (vaddr < vendaddr) { 906246713Skib if (__predict_true(map->pmap == kernel_pmap)) 907239268Sgonzo paddr = pmap_kextract(vaddr); 908239268Sgonzo else 909239268Sgonzo paddr = pmap_extract(map->pmap, vaddr); 910269794Sian if (must_bounce(dmat, map, paddr, 911269794Sian min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 912269794Sian PAGE_MASK)))) != 0) { 913239268Sgonzo map->pagesneeded++; 914239268Sgonzo } 915239268Sgonzo vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK)); 916239268Sgonzo 917239268Sgonzo } 918239268Sgonzo CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded); 919239268Sgonzo } 920246713Skib} 921239268Sgonzo 922246713Skibstatic int 923246713Skib_bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags) 924246713Skib{ 925246713Skib 926239268Sgonzo /* Reserve Necessary Bounce Pages */ 927246713Skib mtx_lock(&bounce_lock); 928246713Skib if (flags & BUS_DMA_NOWAIT) { 929246713Skib if (reserve_bounce_pages(dmat, map, 0) != 0) { 930246713Skib map->pagesneeded = 0; 931246713Skib mtx_unlock(&bounce_lock); 932246713Skib return (ENOMEM); 933239268Sgonzo } 934246713Skib } else { 935246713Skib if (reserve_bounce_pages(dmat, map, 1) != 0) { 936246713Skib /* Queue us for resources */ 937246713Skib STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links); 938246713Skib mtx_unlock(&bounce_lock); 939246713Skib return (EINPROGRESS); 940246713Skib } 941239268Sgonzo } 942246713Skib mtx_unlock(&bounce_lock); 943239268Sgonzo 944239268Sgonzo return (0); 945239268Sgonzo} 946239268Sgonzo 947239268Sgonzo/* 948246713Skib * Add a single contiguous physical range to the segment list. 949246713Skib */ 950246713Skibstatic int 951246713Skib_bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, 952246713Skib bus_size_t sgsize, bus_dma_segment_t *segs, int *segp) 953246713Skib{ 954246713Skib bus_addr_t baddr, bmask; 955246713Skib int seg; 956246713Skib 957246713Skib /* 958246713Skib * Make sure we don't cross any boundaries. 959246713Skib */ 960246713Skib bmask = ~(dmat->boundary - 1); 961246713Skib if (dmat->boundary > 0) { 962246713Skib baddr = (curaddr + dmat->boundary) & bmask; 963246713Skib if (sgsize > (baddr - curaddr)) 964246713Skib sgsize = (baddr - curaddr); 965246713Skib } 966246713Skib 967246713Skib if (dmat->ranges) { 968246713Skib struct arm32_dma_range *dr; 969246713Skib 970246713Skib dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 971246713Skib curaddr); 972246713Skib if (dr == NULL) { 973246713Skib _bus_dmamap_unload(dmat, map); 974246881Sian return (0); 975246713Skib } 976246713Skib /* 977246713Skib * In a valid DMA range. Translate the physical 978246713Skib * memory address to an address in the DMA window. 979246713Skib */ 980246713Skib curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 981246713Skib } 982246713Skib 983246713Skib /* 984246713Skib * Insert chunk into a segment, coalescing with 985246713Skib * previous segment if possible. 986246713Skib */ 987246713Skib seg = *segp; 988246713Skib if (seg == -1) { 989246713Skib seg = 0; 990246713Skib segs[seg].ds_addr = curaddr; 991246713Skib segs[seg].ds_len = sgsize; 992246713Skib } else { 993246713Skib if (curaddr == segs[seg].ds_addr + segs[seg].ds_len && 994246713Skib (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 995246713Skib (dmat->boundary == 0 || 996246713Skib (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 997246713Skib segs[seg].ds_len += sgsize; 998246713Skib else { 999246713Skib if (++seg >= dmat->nsegments) 1000246713Skib return (0); 1001246713Skib segs[seg].ds_addr = curaddr; 1002246713Skib segs[seg].ds_len = sgsize; 1003246713Skib } 1004246713Skib } 1005246713Skib *segp = seg; 1006246713Skib return (sgsize); 1007246713Skib} 1008246713Skib 1009246713Skib/* 1010246713Skib * Utility function to load a physical buffer. segp contains 1011239268Sgonzo * the starting segment on entrace, and the ending segment on exit. 1012239268Sgonzo */ 1013246713Skibint 1014246713Skib_bus_dmamap_load_phys(bus_dma_tag_t dmat, 1015246713Skib bus_dmamap_t map, 1016246713Skib vm_paddr_t buf, bus_size_t buflen, 1017246713Skib int flags, 1018246713Skib bus_dma_segment_t *segs, 1019246713Skib int *segp) 1020246713Skib{ 1021246713Skib bus_addr_t curaddr; 1022246713Skib bus_size_t sgsize; 1023246713Skib int error; 1024246713Skib 1025246713Skib if (segs == NULL) 1026269794Sian segs = map->segments; 1027246713Skib 1028269794Sian maploads_total++; 1029269794Sian maploads_physmem++; 1030269794Sian 1031269794Sian if (might_bounce(dmat, map, buflen, buflen)) { 1032246713Skib _bus_dmamap_count_phys(dmat, map, buf, buflen, flags); 1033246713Skib if (map->pagesneeded != 0) { 1034269794Sian maploads_bounced++; 1035246713Skib error = _bus_dmamap_reserve_pages(dmat, map, flags); 1036246713Skib if (error) 1037246713Skib return (error); 1038246713Skib } 1039246713Skib } 1040246713Skib 1041246713Skib while (buflen > 0) { 1042246713Skib curaddr = buf; 1043246713Skib sgsize = MIN(buflen, dmat->maxsegsz); 1044269794Sian if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1045269794Sian sgsize)) { 1046246713Skib sgsize = MIN(sgsize, PAGE_SIZE); 1047246713Skib curaddr = add_bounce_page(dmat, map, 0, curaddr, 1048246713Skib sgsize); 1049246713Skib } 1050246713Skib sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1051246713Skib segp); 1052246713Skib if (sgsize == 0) 1053246713Skib break; 1054246713Skib buf += sgsize; 1055246713Skib buflen -= sgsize; 1056246713Skib } 1057246713Skib 1058246713Skib /* 1059246713Skib * Did we fit? 1060246713Skib */ 1061246713Skib if (buflen != 0) { 1062246713Skib _bus_dmamap_unload(dmat, map); 1063246713Skib return (EFBIG); /* XXX better return value here? */ 1064246713Skib } 1065246713Skib return (0); 1066246713Skib} 1067246713Skib 1068259510Skibint 1069259510Skib_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, 1070259510Skib struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 1071259510Skib bus_dma_segment_t *segs, int *segp) 1072259510Skib{ 1073259510Skib 1074259510Skib return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags, 1075259510Skib segs, segp)); 1076259510Skib} 1077259510Skib 1078246713Skib/* 1079246713Skib * Utility function to load a linear buffer. segp contains 1080246713Skib * the starting segment on entrace, and the ending segment on exit. 1081246713Skib */ 1082246713Skibint 1083239268Sgonzo_bus_dmamap_load_buffer(bus_dma_tag_t dmat, 1084239268Sgonzo bus_dmamap_t map, 1085239268Sgonzo void *buf, bus_size_t buflen, 1086246713Skib pmap_t pmap, 1087239268Sgonzo int flags, 1088239268Sgonzo bus_dma_segment_t *segs, 1089246713Skib int *segp) 1090239268Sgonzo{ 1091239268Sgonzo bus_size_t sgsize; 1092246713Skib bus_addr_t curaddr; 1093239268Sgonzo vm_offset_t vaddr; 1094239268Sgonzo struct sync_list *sl; 1095246713Skib int error; 1096239268Sgonzo 1097269794Sian maploads_total++; 1098269794Sian if (map->flags & DMAMAP_COHERENT) 1099269794Sian maploads_coherent++; 1100269794Sian if (map->flags & DMAMAP_DMAMEM_ALLOC) 1101269794Sian maploads_dmamem++; 1102269794Sian 1103246713Skib if (segs == NULL) 1104269794Sian segs = map->segments; 1105246713Skib 1106269794Sian if (flags & BUS_DMA_LOAD_MBUF) { 1107269794Sian maploads_mbuf++; 1108269794Sian map->flags |= DMAMAP_MBUF; 1109269794Sian } 1110269794Sian 1111246859Sian map->pmap = pmap; 1112246859Sian 1113269794Sian if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) { 1114246713Skib _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); 1115246713Skib if (map->pagesneeded != 0) { 1116269794Sian maploads_bounced++; 1117246713Skib error = _bus_dmamap_reserve_pages(dmat, map, flags); 1118246713Skib if (error) 1119246713Skib return (error); 1120246713Skib } 1121239268Sgonzo } 1122239268Sgonzo 1123239268Sgonzo sl = NULL; 1124239268Sgonzo vaddr = (vm_offset_t)buf; 1125239268Sgonzo 1126246713Skib while (buflen > 0) { 1127239268Sgonzo /* 1128239268Sgonzo * Get the physical address for this segment. 1129239268Sgonzo */ 1130246713Skib if (__predict_true(map->pmap == kernel_pmap)) 1131239268Sgonzo curaddr = pmap_kextract(vaddr); 1132239268Sgonzo else 1133239268Sgonzo curaddr = pmap_extract(map->pmap, vaddr); 1134239268Sgonzo 1135239268Sgonzo /* 1136239268Sgonzo * Compute the segment size, and adjust counts. 1137239268Sgonzo */ 1138239268Sgonzo sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 1139239268Sgonzo if (sgsize > dmat->maxsegsz) 1140239268Sgonzo sgsize = dmat->maxsegsz; 1141239268Sgonzo if (buflen < sgsize) 1142239268Sgonzo sgsize = buflen; 1143239268Sgonzo 1144269794Sian if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr, 1145269794Sian sgsize)) { 1146246713Skib curaddr = add_bounce_page(dmat, map, vaddr, curaddr, 1147246713Skib sgsize); 1148239268Sgonzo } else { 1149246713Skib sl = &map->slist[map->sync_count - 1]; 1150246713Skib if (map->sync_count == 0 || 1151247776Scognet#ifdef ARM_L2_PIPT 1152247776Scognet curaddr != sl->busaddr + sl->datacount || 1153247776Scognet#endif 1154246713Skib vaddr != sl->vaddr + sl->datacount) { 1155246713Skib if (++map->sync_count > dmat->nsegments) 1156246713Skib goto cleanup; 1157246713Skib sl++; 1158246713Skib sl->vaddr = vaddr; 1159246713Skib sl->datacount = sgsize; 1160246713Skib sl->busaddr = curaddr; 1161246713Skib } else 1162246713Skib sl->datacount += sgsize; 1163239268Sgonzo } 1164246713Skib sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs, 1165246713Skib segp); 1166246713Skib if (sgsize == 0) 1167246713Skib break; 1168239268Sgonzo vaddr += sgsize; 1169239268Sgonzo buflen -= sgsize; 1170239268Sgonzo } 1171239268Sgonzo 1172239268Sgonzocleanup: 1173239268Sgonzo /* 1174239268Sgonzo * Did we fit? 1175239268Sgonzo */ 1176239268Sgonzo if (buflen != 0) { 1177239268Sgonzo _bus_dmamap_unload(dmat, map); 1178246713Skib return (EFBIG); /* XXX better return value here? */ 1179239268Sgonzo } 1180239268Sgonzo return (0); 1181239268Sgonzo} 1182239268Sgonzo 1183246713Skib 1184246713Skibvoid 1185246713Skib__bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map, 1186246713Skib struct memdesc *mem, bus_dmamap_callback_t *callback, 1187246713Skib void *callback_arg) 1188239268Sgonzo{ 1189239268Sgonzo 1190246713Skib map->mem = *mem; 1191246713Skib map->dmat = dmat; 1192239268Sgonzo map->callback = callback; 1193239268Sgonzo map->callback_arg = callback_arg; 1194239268Sgonzo} 1195239268Sgonzo 1196246713Skibbus_dma_segment_t * 1197246713Skib_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map, 1198246713Skib bus_dma_segment_t *segs, int nsegs, int error) 1199239268Sgonzo{ 1200239268Sgonzo 1201246713Skib if (segs == NULL) 1202269794Sian segs = map->segments; 1203246713Skib return (segs); 1204239268Sgonzo} 1205239268Sgonzo 1206239268Sgonzo/* 1207239268Sgonzo * Release the mapping held by map. 1208239268Sgonzo */ 1209239268Sgonzovoid 1210239268Sgonzo_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1211239268Sgonzo{ 1212239268Sgonzo struct bounce_page *bpage; 1213239268Sgonzo struct bounce_zone *bz; 1214239268Sgonzo 1215239268Sgonzo if ((bz = dmat->bounce_zone) != NULL) { 1216239268Sgonzo while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1217239268Sgonzo STAILQ_REMOVE_HEAD(&map->bpages, links); 1218239268Sgonzo free_bounce_page(dmat, bpage); 1219239268Sgonzo } 1220239268Sgonzo 1221239268Sgonzo bz = dmat->bounce_zone; 1222239268Sgonzo bz->free_bpages += map->pagesreserved; 1223239268Sgonzo bz->reserved_bpages -= map->pagesreserved; 1224239268Sgonzo map->pagesreserved = 0; 1225239268Sgonzo map->pagesneeded = 0; 1226239268Sgonzo } 1227246713Skib map->sync_count = 0; 1228269794Sian map->flags &= ~DMAMAP_MBUF; 1229239268Sgonzo} 1230239268Sgonzo 1231239268Sgonzo#ifdef notyetbounceuser 1232276274Sian/* If busdma uses user pages, then the interrupt handler could 1233276274Sian * be use the kernel vm mapping. Both bounce pages and sync list 1234276274Sian * do not cross page boundaries. 1235276274Sian * Below is a rough sequence that a person would do to fix the 1236276274Sian * user page reference in the kernel vmspace. This would be 1237276274Sian * done in the dma post routine. 1238276274Sian */ 1239239268Sgonzovoid 1240239268Sgonzo_bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len, 1241239268Sgonzo pmap_t pmap, int op) 1242239268Sgonzo{ 1243239268Sgonzo bus_size_t sgsize; 1244239268Sgonzo bus_addr_t curaddr; 1245239268Sgonzo vm_offset_t va; 1246239268Sgonzo 1247276274Sian /* 1248276274Sian * each synclist entry is contained within a single page. 1249276274Sian * this would be needed if BUS_DMASYNC_POSTxxxx was implemented 1250276274Sian */ 1251239268Sgonzo curaddr = pmap_extract(pmap, buf); 1252239268Sgonzo va = pmap_dma_map(curaddr); 1253239268Sgonzo switch (op) { 1254239268Sgonzo case SYNC_USER_INV: 1255239268Sgonzo cpu_dcache_wb_range(va, sgsize); 1256239268Sgonzo break; 1257239268Sgonzo 1258239268Sgonzo case SYNC_USER_COPYTO: 1259239268Sgonzo bcopy((void *)va, (void *)bounce, sgsize); 1260239268Sgonzo break; 1261239268Sgonzo 1262239268Sgonzo case SYNC_USER_COPYFROM: 1263239268Sgonzo bcopy((void *) bounce, (void *)va, sgsize); 1264239268Sgonzo break; 1265239268Sgonzo 1266239268Sgonzo default: 1267239268Sgonzo break; 1268239268Sgonzo } 1269239268Sgonzo 1270239268Sgonzo pmap_dma_unmap(va); 1271239268Sgonzo} 1272239268Sgonzo#endif 1273239268Sgonzo 1274239268Sgonzo#ifdef ARM_L2_PIPT 1275239268Sgonzo#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size) 1276239268Sgonzo#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size) 1277239268Sgonzo#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size) 1278239268Sgonzo#else 1279239268Sgonzo#define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size) 1280239268Sgonzo#define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size) 1281243909Scognet#define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size) 1282239268Sgonzo#endif 1283239268Sgonzo 1284239268Sgonzovoid 1285239268Sgonzo_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1286239268Sgonzo{ 1287239268Sgonzo struct bounce_page *bpage; 1288246713Skib struct sync_list *sl, *end; 1289248655Sian /* 1290248655Sian * If the buffer was from user space, it is possible that this is not 1291248655Sian * the same vm map, especially on a POST operation. It's not clear that 1292276274Sian * dma on userland buffers can work at all right now. To be safe, until 1293276274Sian * we're able to test direct userland dma, panic on a map mismatch. 1294248655Sian */ 1295239268Sgonzo if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1296248655Sian if (!pmap_dmap_iscurrent(map->pmap)) 1297248655Sian panic("_bus_dmamap_sync: wrong user map for bounce sync."); 1298276274Sian 1299239268Sgonzo CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1300239268Sgonzo "performing bounce", __func__, dmat, dmat->flags, op); 1301239268Sgonzo 1302276274Sian /* 1303276274Sian * For PREWRITE do a writeback. Clean the caches from the 1304276274Sian * innermost to the outermost levels. 1305276274Sian */ 1306239268Sgonzo if (op & BUS_DMASYNC_PREWRITE) { 1307239268Sgonzo while (bpage != NULL) { 1308246713Skib if (bpage->datavaddr != 0) 1309246713Skib bcopy((void *)bpage->datavaddr, 1310269794Sian (void *)bpage->vaddr, 1311269794Sian bpage->datacount); 1312246713Skib else 1313246713Skib physcopyout(bpage->dataaddr, 1314269794Sian (void *)bpage->vaddr, 1315269794Sian bpage->datacount); 1316239268Sgonzo cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, 1317276274Sian bpage->datacount); 1318239268Sgonzo l2cache_wb_range((vm_offset_t)bpage->vaddr, 1319239268Sgonzo (vm_offset_t)bpage->busaddr, 1320239268Sgonzo bpage->datacount); 1321239268Sgonzo bpage = STAILQ_NEXT(bpage, links); 1322239268Sgonzo } 1323239268Sgonzo dmat->bounce_zone->total_bounced++; 1324239268Sgonzo } 1325239268Sgonzo 1326276274Sian /* 1327276274Sian * Do an invalidate for PREREAD unless a writeback was already 1328276274Sian * done above due to PREWRITE also being set. The reason for a 1329276274Sian * PREREAD invalidate is to prevent dirty lines currently in the 1330276274Sian * cache from being evicted during the DMA. If a writeback was 1331276274Sian * done due to PREWRITE also being set there will be no dirty 1332276274Sian * lines and the POSTREAD invalidate handles the rest. The 1333276274Sian * invalidate is done from the innermost to outermost level. If 1334276274Sian * L2 were done first, a dirty cacheline could be automatically 1335276274Sian * evicted from L1 before we invalidated it, re-dirtying the L2. 1336276274Sian */ 1337276274Sian if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) { 1338266159Sian bpage = STAILQ_FIRST(&map->bpages); 1339266159Sian while (bpage != NULL) { 1340266159Sian cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1341266159Sian bpage->datacount); 1342266159Sian l2cache_inv_range((vm_offset_t)bpage->vaddr, 1343266159Sian (vm_offset_t)bpage->busaddr, 1344266159Sian bpage->datacount); 1345266159Sian bpage = STAILQ_NEXT(bpage, links); 1346266159Sian } 1347266159Sian } 1348276274Sian 1349276274Sian /* 1350276274Sian * Re-invalidate the caches on a POSTREAD, even though they were 1351276274Sian * already invalidated at PREREAD time. Aggressive prefetching 1352276274Sian * due to accesses to other data near the dma buffer could have 1353276274Sian * brought buffer data into the caches which is now stale. The 1354276274Sian * caches are invalidated from the outermost to innermost; the 1355276274Sian * prefetches could be happening right now, and if L1 were 1356276274Sian * invalidated first, stale L2 data could be prefetched into L1. 1357276274Sian */ 1358239268Sgonzo if (op & BUS_DMASYNC_POSTREAD) { 1359239268Sgonzo while (bpage != NULL) { 1360239268Sgonzo vm_offset_t startv; 1361239268Sgonzo vm_paddr_t startp; 1362239268Sgonzo int len; 1363239268Sgonzo 1364239268Sgonzo startv = bpage->vaddr &~ arm_dcache_align_mask; 1365239268Sgonzo startp = bpage->busaddr &~ arm_dcache_align_mask; 1366239268Sgonzo len = bpage->datacount; 1367239268Sgonzo 1368239268Sgonzo if (startv != bpage->vaddr) 1369239268Sgonzo len += bpage->vaddr & arm_dcache_align_mask; 1370239268Sgonzo if (len & arm_dcache_align_mask) 1371239268Sgonzo len = (len - 1372239268Sgonzo (len & arm_dcache_align_mask)) + 1373239268Sgonzo arm_dcache_align; 1374276274Sian l2cache_inv_range(startv, startp, len); 1375239268Sgonzo cpu_dcache_inv_range(startv, len); 1376246713Skib if (bpage->datavaddr != 0) 1377246713Skib bcopy((void *)bpage->vaddr, 1378269794Sian (void *)bpage->datavaddr, 1379269794Sian bpage->datacount); 1380246713Skib else 1381246713Skib physcopyin((void *)bpage->vaddr, 1382269794Sian bpage->dataaddr, 1383269794Sian bpage->datacount); 1384239268Sgonzo bpage = STAILQ_NEXT(bpage, links); 1385239268Sgonzo } 1386239268Sgonzo dmat->bounce_zone->total_bounced++; 1387239268Sgonzo } 1388239268Sgonzo } 1389276274Sian 1390276274Sian /* 1391276274Sian * For COHERENT memory no cache maintenance is necessary, but ensure all 1392276274Sian * writes have reached memory for the PREWRITE case. No action is 1393276274Sian * needed for a PREREAD without PREWRITE also set, because that would 1394276274Sian * imply that the cpu had written to the COHERENT buffer and expected 1395276274Sian * the dma device to see that change, and by definition a PREWRITE sync 1396276274Sian * is required to make that happen. 1397276274Sian */ 1398276274Sian if (map->flags & DMAMAP_COHERENT) { 1399276274Sian if (op & BUS_DMASYNC_PREWRITE) { 1400276274Sian dsb(); 1401276274Sian cpu_l2cache_drain_writebuf(); 1402276274Sian } 1403244469Scognet return; 1404276274Sian } 1405239268Sgonzo 1406276274Sian /* 1407276274Sian * Cache maintenance for normal (non-COHERENT non-bounce) buffers. All 1408276274Sian * the comments about the sequences for flushing cache levels in the 1409276274Sian * bounce buffer code above apply here as well. In particular, the fact 1410276274Sian * that the sequence is inner-to-outer for PREREAD invalidation and 1411276274Sian * outer-to-inner for POSTREAD invalidation is not a mistake. 1412276274Sian */ 1413246713Skib if (map->sync_count != 0) { 1414248655Sian if (!pmap_dmap_iscurrent(map->pmap)) 1415248655Sian panic("_bus_dmamap_sync: wrong user map for sync."); 1416239268Sgonzo 1417246713Skib sl = &map->slist[0]; 1418246713Skib end = &map->slist[map->sync_count]; 1419239268Sgonzo CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1420239268Sgonzo "performing sync", __func__, dmat, dmat->flags, op); 1421239268Sgonzo 1422239268Sgonzo switch (op) { 1423239268Sgonzo case BUS_DMASYNC_PREWRITE: 1424276274Sian case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: 1425246713Skib while (sl != end) { 1426276274Sian cpu_dcache_wb_range(sl->vaddr, sl->datacount); 1427276274Sian l2cache_wb_range(sl->vaddr, sl->busaddr, 1428276274Sian sl->datacount); 1429276274Sian sl++; 1430239268Sgonzo } 1431239268Sgonzo break; 1432239268Sgonzo 1433239268Sgonzo case BUS_DMASYNC_PREREAD: 1434276274Sian /* 1435276274Sian * An mbuf may start in the middle of a cacheline. There 1436276274Sian * will be no cpu writes to the beginning of that line 1437276274Sian * (which contains the mbuf header) while dma is in 1438276274Sian * progress. Handle that case by doing a writeback of 1439276274Sian * just the first cacheline before invalidating the 1440276274Sian * overall buffer. Any mbuf in a chain may have this 1441276274Sian * misalignment. Buffers which are not mbufs bounce if 1442276274Sian * they are not aligned to a cacheline. 1443276274Sian */ 1444246713Skib while (sl != end) { 1445276274Sian if (sl->vaddr & arm_dcache_align_mask) { 1446276274Sian KASSERT(map->flags & DMAMAP_MBUF, 1447276274Sian ("unaligned buffer is not an mbuf")); 1448276274Sian cpu_dcache_wb_range(sl->vaddr, 1); 1449276274Sian l2cache_wb_range(sl->vaddr, 1450276274Sian sl->busaddr, 1); 1451276274Sian } 1452254061Scognet cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1453254061Scognet l2cache_inv_range(sl->vaddr, sl->busaddr, 1454254061Scognet sl->datacount); 1455246713Skib sl++; 1456239268Sgonzo } 1457239268Sgonzo break; 1458239268Sgonzo 1459276274Sian case BUS_DMASYNC_POSTWRITE: 1460276274Sian break; 1461276274Sian 1462276274Sian case BUS_DMASYNC_POSTREAD: 1463276274Sian case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: 1464246713Skib while (sl != end) { 1465276274Sian l2cache_inv_range(sl->vaddr, sl->busaddr, 1466276274Sian sl->datacount); 1467276274Sian cpu_dcache_inv_range(sl->vaddr, sl->datacount); 1468246713Skib sl++; 1469239268Sgonzo } 1470239268Sgonzo break; 1471239268Sgonzo 1472239268Sgonzo default: 1473259310Sian panic("unsupported combination of sync operations: 0x%08x\n", op); 1474239268Sgonzo break; 1475239268Sgonzo } 1476239268Sgonzo } 1477239268Sgonzo} 1478239268Sgonzo 1479239268Sgonzostatic void 1480239268Sgonzoinit_bounce_pages(void *dummy __unused) 1481239268Sgonzo{ 1482239268Sgonzo 1483239268Sgonzo total_bpages = 0; 1484239268Sgonzo STAILQ_INIT(&bounce_zone_list); 1485239268Sgonzo STAILQ_INIT(&bounce_map_waitinglist); 1486239268Sgonzo STAILQ_INIT(&bounce_map_callbacklist); 1487239268Sgonzo mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1488239268Sgonzo} 1489239268SgonzoSYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1490239268Sgonzo 1491239268Sgonzostatic struct sysctl_ctx_list * 1492239268Sgonzobusdma_sysctl_tree(struct bounce_zone *bz) 1493239268Sgonzo{ 1494276274Sian 1495239268Sgonzo return (&bz->sysctl_tree); 1496239268Sgonzo} 1497239268Sgonzo 1498239268Sgonzostatic struct sysctl_oid * 1499239268Sgonzobusdma_sysctl_tree_top(struct bounce_zone *bz) 1500239268Sgonzo{ 1501276274Sian 1502239268Sgonzo return (bz->sysctl_tree_top); 1503239268Sgonzo} 1504239268Sgonzo 1505239268Sgonzostatic int 1506239268Sgonzoalloc_bounce_zone(bus_dma_tag_t dmat) 1507239268Sgonzo{ 1508239268Sgonzo struct bounce_zone *bz; 1509239268Sgonzo 1510239268Sgonzo /* Check to see if we already have a suitable zone */ 1511239268Sgonzo STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1512269794Sian if ((dmat->alignment <= bz->alignment) && 1513269794Sian (dmat->lowaddr >= bz->lowaddr)) { 1514239268Sgonzo dmat->bounce_zone = bz; 1515239268Sgonzo return (0); 1516239268Sgonzo } 1517239268Sgonzo } 1518239268Sgonzo 1519239268Sgonzo if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1520239268Sgonzo M_NOWAIT | M_ZERO)) == NULL) 1521239268Sgonzo return (ENOMEM); 1522239268Sgonzo 1523239268Sgonzo STAILQ_INIT(&bz->bounce_page_list); 1524239268Sgonzo bz->free_bpages = 0; 1525239268Sgonzo bz->reserved_bpages = 0; 1526239268Sgonzo bz->active_bpages = 0; 1527239268Sgonzo bz->lowaddr = dmat->lowaddr; 1528239268Sgonzo bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1529239268Sgonzo bz->map_count = 0; 1530239268Sgonzo snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1531239268Sgonzo busdma_zonecount++; 1532239268Sgonzo snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1533239268Sgonzo STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1534239268Sgonzo dmat->bounce_zone = bz; 1535239268Sgonzo 1536239268Sgonzo sysctl_ctx_init(&bz->sysctl_tree); 1537239268Sgonzo bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1538239268Sgonzo SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1539239268Sgonzo CTLFLAG_RD, 0, ""); 1540239268Sgonzo if (bz->sysctl_tree_top == NULL) { 1541239268Sgonzo sysctl_ctx_free(&bz->sysctl_tree); 1542239268Sgonzo return (0); /* XXX error code? */ 1543239268Sgonzo } 1544239268Sgonzo 1545239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1546239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1547239268Sgonzo "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1548239268Sgonzo "Total bounce pages"); 1549239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1550239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1551239268Sgonzo "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1552239268Sgonzo "Free bounce pages"); 1553239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1554239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1555239268Sgonzo "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1556239268Sgonzo "Reserved bounce pages"); 1557239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1558239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1559239268Sgonzo "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1560239268Sgonzo "Active bounce pages"); 1561239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1562239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1563239268Sgonzo "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1564269794Sian "Total bounce requests (pages bounced)"); 1565239268Sgonzo SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1566239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1567239268Sgonzo "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1568239268Sgonzo "Total bounce requests that were deferred"); 1569239268Sgonzo SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1570239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1571239268Sgonzo "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1572273736Shselasky SYSCTL_ADD_ULONG(busdma_sysctl_tree(bz), 1573239268Sgonzo SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1574273736Shselasky "alignment", CTLFLAG_RD, &bz->alignment, ""); 1575239268Sgonzo 1576239268Sgonzo return (0); 1577239268Sgonzo} 1578239268Sgonzo 1579239268Sgonzostatic int 1580239268Sgonzoalloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1581239268Sgonzo{ 1582239268Sgonzo struct bounce_zone *bz; 1583239268Sgonzo int count; 1584239268Sgonzo 1585239268Sgonzo bz = dmat->bounce_zone; 1586239268Sgonzo count = 0; 1587239268Sgonzo while (numpages > 0) { 1588239268Sgonzo struct bounce_page *bpage; 1589239268Sgonzo 1590239268Sgonzo bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1591269794Sian M_NOWAIT | M_ZERO); 1592239268Sgonzo 1593239268Sgonzo if (bpage == NULL) 1594239268Sgonzo break; 1595239268Sgonzo bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1596269794Sian M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); 1597239268Sgonzo if (bpage->vaddr == 0) { 1598239268Sgonzo free(bpage, M_DEVBUF); 1599239268Sgonzo break; 1600239268Sgonzo } 1601239268Sgonzo bpage->busaddr = pmap_kextract(bpage->vaddr); 1602239268Sgonzo mtx_lock(&bounce_lock); 1603239268Sgonzo STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1604239268Sgonzo total_bpages++; 1605239268Sgonzo bz->total_bpages++; 1606239268Sgonzo bz->free_bpages++; 1607239268Sgonzo mtx_unlock(&bounce_lock); 1608239268Sgonzo count++; 1609239268Sgonzo numpages--; 1610239268Sgonzo } 1611239268Sgonzo return (count); 1612239268Sgonzo} 1613239268Sgonzo 1614239268Sgonzostatic int 1615239268Sgonzoreserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1616239268Sgonzo{ 1617239268Sgonzo struct bounce_zone *bz; 1618239268Sgonzo int pages; 1619239268Sgonzo 1620239268Sgonzo mtx_assert(&bounce_lock, MA_OWNED); 1621239268Sgonzo bz = dmat->bounce_zone; 1622239268Sgonzo pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1623239268Sgonzo if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1624239268Sgonzo return (map->pagesneeded - (map->pagesreserved + pages)); 1625239268Sgonzo bz->free_bpages -= pages; 1626239268Sgonzo bz->reserved_bpages += pages; 1627239268Sgonzo map->pagesreserved += pages; 1628239268Sgonzo pages = map->pagesneeded - map->pagesreserved; 1629239268Sgonzo 1630239268Sgonzo return (pages); 1631239268Sgonzo} 1632239268Sgonzo 1633239268Sgonzostatic bus_addr_t 1634239268Sgonzoadd_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1635246713Skib bus_addr_t addr, bus_size_t size) 1636239268Sgonzo{ 1637239268Sgonzo struct bounce_zone *bz; 1638239268Sgonzo struct bounce_page *bpage; 1639239268Sgonzo 1640239268Sgonzo KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1641239268Sgonzo KASSERT(map != NULL, 1642239268Sgonzo ("add_bounce_page: bad map %p", map)); 1643239268Sgonzo 1644239268Sgonzo bz = dmat->bounce_zone; 1645239268Sgonzo if (map->pagesneeded == 0) 1646239268Sgonzo panic("add_bounce_page: map doesn't need any pages"); 1647239268Sgonzo map->pagesneeded--; 1648239268Sgonzo 1649239268Sgonzo if (map->pagesreserved == 0) 1650239268Sgonzo panic("add_bounce_page: map doesn't need any pages"); 1651239268Sgonzo map->pagesreserved--; 1652239268Sgonzo 1653239268Sgonzo mtx_lock(&bounce_lock); 1654239268Sgonzo bpage = STAILQ_FIRST(&bz->bounce_page_list); 1655239268Sgonzo if (bpage == NULL) 1656239268Sgonzo panic("add_bounce_page: free page list is empty"); 1657239268Sgonzo 1658239268Sgonzo STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1659239268Sgonzo bz->reserved_bpages--; 1660239268Sgonzo bz->active_bpages++; 1661239268Sgonzo mtx_unlock(&bounce_lock); 1662239268Sgonzo 1663239268Sgonzo if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1664239268Sgonzo /* Page offset needs to be preserved. */ 1665282506Shselasky bpage->vaddr |= addr & PAGE_MASK; 1666282506Shselasky bpage->busaddr |= addr & PAGE_MASK; 1667239268Sgonzo } 1668239268Sgonzo bpage->datavaddr = vaddr; 1669246713Skib bpage->dataaddr = addr; 1670239268Sgonzo bpage->datacount = size; 1671239268Sgonzo STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1672239268Sgonzo return (bpage->busaddr); 1673239268Sgonzo} 1674239268Sgonzo 1675239268Sgonzostatic void 1676239268Sgonzofree_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1677239268Sgonzo{ 1678239268Sgonzo struct bus_dmamap *map; 1679239268Sgonzo struct bounce_zone *bz; 1680239268Sgonzo 1681239268Sgonzo bz = dmat->bounce_zone; 1682239268Sgonzo bpage->datavaddr = 0; 1683239268Sgonzo bpage->datacount = 0; 1684239268Sgonzo if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) { 1685239268Sgonzo /* 1686239268Sgonzo * Reset the bounce page to start at offset 0. Other uses 1687239268Sgonzo * of this bounce page may need to store a full page of 1688239268Sgonzo * data and/or assume it starts on a page boundary. 1689239268Sgonzo */ 1690239268Sgonzo bpage->vaddr &= ~PAGE_MASK; 1691239268Sgonzo bpage->busaddr &= ~PAGE_MASK; 1692239268Sgonzo } 1693239268Sgonzo 1694239268Sgonzo mtx_lock(&bounce_lock); 1695239268Sgonzo STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1696239268Sgonzo bz->free_bpages++; 1697239268Sgonzo bz->active_bpages--; 1698239268Sgonzo if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1699239268Sgonzo if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1700239268Sgonzo STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1701239268Sgonzo STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1702269794Sian map, links); 1703239268Sgonzo busdma_swi_pending = 1; 1704239268Sgonzo bz->total_deferred++; 1705239268Sgonzo swi_sched(vm_ih, 0); 1706239268Sgonzo } 1707239268Sgonzo } 1708239268Sgonzo mtx_unlock(&bounce_lock); 1709239268Sgonzo} 1710239268Sgonzo 1711239268Sgonzovoid 1712239268Sgonzobusdma_swi(void) 1713239268Sgonzo{ 1714239268Sgonzo bus_dma_tag_t dmat; 1715239268Sgonzo struct bus_dmamap *map; 1716239268Sgonzo 1717239268Sgonzo mtx_lock(&bounce_lock); 1718239268Sgonzo while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1719239268Sgonzo STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1720239268Sgonzo mtx_unlock(&bounce_lock); 1721239268Sgonzo dmat = map->dmat; 1722269794Sian dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK); 1723246713Skib bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback, 1724269794Sian map->callback_arg, BUS_DMA_WAITOK); 1725269794Sian dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1726239268Sgonzo mtx_lock(&bounce_lock); 1727239268Sgonzo } 1728239268Sgonzo mtx_unlock(&bounce_lock); 1729239268Sgonzo} 1730