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296373 |
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04-Mar-2016 |
marius |
- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.3. - Update default pkg(8) configuration to use the quarterly branch.
Approved by: re (implicit) |
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282506 |
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05-May-2015 |
hselasky |
MFC r282120: The add_bounce_page() function can be called when loading physical pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET flag is set, use the physical address to compute the page offset instead. The physical address should always be valid when adding bounce pages and should contain the same page offset like the virtual address.
Submitted by: Svatopluk Kraus <onwahe@gmail.com> Reviewed by: jhb@
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278735 |
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13-Feb-2015 |
ian |
MFC r278031: Remove a stale comment.
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276874 |
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09-Jan-2015 |
loos |
MFC r273599:
Fix a bug where DMA maps created with bus_dmamap_create() won't increment the map count and without being able to keep track of the current map allocation, bus_dma_tag_destroy() will fail to proceed and will return EBUSY even after all the maps have been correctly destroyed with bus_dmamap_destroy().
Found while testing the detach method of a NIC.
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276274 |
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27-Dec-2014 |
ian |
MFC r274538, r274545, r274596, r274602, r274603, r274604, r274605, r274839:
When doing busdma sync ops for BUSDMA_COHERENT memory, there is no need for cache maintenance operations, but ensure that all prior writes have reached memory when doing a PREWRITE sync.
Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.
Do the cache invalidate sequence from the outermost to innermost, required for correct operation.
Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs.
When doing a PREREAD sync of an mbuf-type dma buffer, do a writeback of the first cacheline if the buffer start address is not on a cacheline boundary.
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273736 |
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27-Oct-2014 |
hselasky |
MFC r263710, r273377, r273378, r273423 and r273455:
- De-vnet hash sizes and hash masks. - Fix multiple issues related to arguments passed to SYSCTL macros.
Sponsored by: Mellanox Technologies
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269794 |
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11-Aug-2014 |
ian |
MFC r269206, r269207, r269208, r269209, r269210, r269211, r269212, r269213, r269214, r269215, r269216, r269217, r269221:
busdma-v6 improvements, primarily: - Allocate the temporary segments array per-map rather than per-tag. - Avoid needlessly bouncing IO for mbufs and buffers allocated by bus_dmamem_alloc() (in both situations we known they're allocated on cacheline boundaries and don't need bouncing). - Various minor reformatting and cleanups.
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266159 |
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15-May-2014 |
ian |
MFC r261414, r261415, r261417, r261418, r261419
Don't call device_set_ivars() for the mmchs
Change the way pcpu and curthread are stored per-core
Invalidate cachelines for bounce pages on PREREAD too, there may still be stale entries from a previous transfer.
Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu, such as the one found in the RPi, don't have it, and just hang when we try to access it.
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259510 |
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17-Dec-2013 |
kib |
MFC r257228: Add bus_dmamap_load_ma() function to load map with the array of vm_pages.
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259310 |
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13-Dec-2013 |
ian |
MFC r256638:
Add cases for the combinations of busdma sync op flags that we handle correctly by doing nothing, then add a panic for the default case, because that implies that some driver asked for a sync (probably incorrectly) and nothing was done.
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259309 |
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13-Dec-2013 |
ian |
MFC r256637:
When calculating the number of bounce pages needed, round the maxsize up to a multiple of PAGE_SIZE, and add one page because there can always be one more boundary crossing than the number of pages in the transfer.
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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254229 |
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11-Aug-2013 |
cognet |
Only allocate 2 bounce pages for maps that can only use them for buffers that are unaligned on cache lines boundary, as we will never need more.
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254061 |
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07-Aug-2013 |
cognet |
Don't bother trying to work around buffers which are not aligned on a cache line boundary. It has never been 100% correct, and it can't work on SMP, because nothing prevents another core from accessing data from an unrelated buffer in the same cache line while we invalidated it. Just use bounce pages instead.
Reviewed by: ian Approved by: mux (mentor) (implicit)
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254025 |
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07-Aug-2013 |
jeff |
Replace kernel virtual address space allocation with vmem. This provides transparent layering and better fragmentation.
- Normalize functions that allocate memory to use kmem_* - Those that allocate address space are named kva_* - Those that operate on maps are named kmap_* - Implement recursive allocation handling for kmem_arena in vmem.
Reviewed by: alc Tested by: pho Sponsored by: EMC / Isilon Storage Division
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253787 |
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29-Jul-2013 |
cognet |
Remove useless cache operations.
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252652 |
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03-Jul-2013 |
gonzo |
Fix one of INVARIANTS-related UMA panics on ARM
Force UMA zone to allocate service structures like slabs using own allocator. uma_debug code performs atomic ops on uma_slab_t fields and safety of this operation is not guaranteed for write-back caches
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248655 |
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23-Mar-2013 |
ian |
Don't check and warn about pmap mismatch on every call to busdma sync. With some recent busdma refactoring, sometimes it happens that a sync op gets called when bus_dmamap_load() never got called, which results in a spurious warning about a map mismatch when no sync operations will actually happen anyway. Now the check is done only if a sync operation is actually performed, and the result of the check is a panic, not just a printf.
Reviewed by: cognet (who prevented me from donning a point hat)
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247776 |
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04-Mar-2013 |
cognet |
If we're using a PIPT L2 cache, only merge 2 segments if both the virtual and the physical addreses are contiguous.
Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net>
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246881 |
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16-Feb-2013 |
ian |
In _bus_dmamap_addseg(), the return value must be zero for error, or the size actually added to the segment (possibly smaller than the requested size if boundary crossings had to be avoided).
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246859 |
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15-Feb-2013 |
ian |
Set map->pmap before _bus_dmamap_count_pages() tries to use it.
Obtained from: Thomas Skibo <ThomasSkibo@sbcglobal.net>
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246713 |
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12-Feb-2013 |
kib |
Reform the busdma API so that new types may be added without modifying every architecture's busdma_machdep.c. It is done by unifying the bus_dmamap_load_buffer() routines so that they may be called from MI code. The MD busdma is then given a chance to do any final processing in the complete() callback.
The cam changes unify the bus_dmamap_load* handling in cam drivers.
The arm and mips implementations are updated to track virtual addresses for sync(). Previously this was done in a type specific way. Now it is done in a generic way by recording the list of virtuals in the map.
Submitted by: jeff (sponsored by EMC/Isilon) Reviewed by: kan (previous version), scottl, mjacob (isp(4), no objections for target mode changes) Discussed with: ian (arm changes) Tested by: marius (sparc64), mips (jmallet), isci(4) on x86 (jharris), amd64 (Fabian Keil <freebsd-listen@fabiankeil.de>)
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244912 |
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31-Dec-2012 |
gonzo |
Merge r234561 from busdma_machdep.c to ARMv6 version of busdma:
Interrupts must be disabled while handling a partial cache line flush, as otherwise the interrupt handling code may modify data in the non-DMA part of the cache line while we have it stashed away in the temporary stack buffer, then we end up restoring a stale value.
PR: 160431 Submitted by: Ian Lepore
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244469 |
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20-Dec-2012 |
cognet |
Use the new allocator in bus_dmamem_alloc().
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243909 |
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05-Dec-2012 |
cognet |
Don't write-back the cachelines if we really just want to invalidate them.
Spotted out by: Ian Lepore <freebsd at damnhippie DOT dyndns dot org>
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243108 |
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15-Nov-2012 |
cognet |
Remove a useless printf
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239597 |
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22-Aug-2012 |
gonzo |
Do not change "cachable" attribute for DMA memory allocated with BUS_DMA_COHERENT attribute
The minimum unit for changing "cachable" attribute is page, so call to pmap_change_attr effectively disable cache for all pages that newly allocated DMA memory region spans on. The problem is that general-purpose memory could reside on these pages too and disabling cache might affect performance. Moreover ldrex/strex operators raise Data Abort exception when accessing memory on page with "cachable" attribute off.
BUS_DMA_COHERENT does nto require memory to be coherent. It just suggests to do best effort for reducing synchronization overhead.
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239268 |
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15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
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