1//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the PowerPC specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef PPC_TARGETMACHINE_H
15#define PPC_TARGETMACHINE_H
16
17#include "PPCFrameLowering.h"
18#include "PPCISelLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCJITInfo.h"
21#include "PPCSelectionDAGInfo.h"
22#include "PPCSubtarget.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/Target/TargetMachine.h"
25
26namespace llvm {
27
28/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
29///
30class PPCTargetMachine : public LLVMTargetMachine {
31  PPCSubtarget        Subtarget;
32  const DataLayout    DL;       // Calculates type size & alignment
33  PPCInstrInfo        InstrInfo;
34  PPCFrameLowering    FrameLowering;
35  PPCJITInfo          JITInfo;
36  PPCTargetLowering   TLInfo;
37  PPCSelectionDAGInfo TSInfo;
38  InstrItineraryData  InstrItins;
39
40public:
41  PPCTargetMachine(const Target &T, StringRef TT,
42                   StringRef CPU, StringRef FS, const TargetOptions &Options,
43                   Reloc::Model RM, CodeModel::Model CM,
44                   CodeGenOpt::Level OL, bool is64Bit);
45
46  virtual const PPCInstrInfo      *getInstrInfo() const { return &InstrInfo; }
47  virtual const PPCFrameLowering  *getFrameLowering() const {
48    return &FrameLowering;
49  }
50  virtual       PPCJITInfo        *getJITInfo()         { return &JITInfo; }
51  virtual const PPCTargetLowering *getTargetLowering() const {
52   return &TLInfo;
53  }
54  virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const {
55    return &TSInfo;
56  }
57  virtual const PPCRegisterInfo   *getRegisterInfo() const {
58    return &InstrInfo.getRegisterInfo();
59  }
60
61  virtual const DataLayout    *getDataLayout() const    { return &DL; }
62  virtual const PPCSubtarget  *getSubtargetImpl() const { return &Subtarget; }
63  virtual const InstrItineraryData *getInstrItineraryData() const {
64    return &InstrItins;
65  }
66
67  // Pass Pipeline Configuration
68  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
69  virtual bool addCodeEmitter(PassManagerBase &PM,
70                              JITCodeEmitter &JCE);
71
72  /// \brief Register PPC analysis passes with a pass manager.
73  virtual void addAnalysisPasses(PassManagerBase &PM);
74};
75
76/// PPC32TargetMachine - PowerPC 32-bit target machine.
77///
78class PPC32TargetMachine : public PPCTargetMachine {
79  virtual void anchor();
80public:
81  PPC32TargetMachine(const Target &T, StringRef TT,
82                     StringRef CPU, StringRef FS, const TargetOptions &Options,
83                     Reloc::Model RM, CodeModel::Model CM,
84                     CodeGenOpt::Level OL);
85};
86
87/// PPC64TargetMachine - PowerPC 64-bit target machine.
88///
89class PPC64TargetMachine : public PPCTargetMachine {
90  virtual void anchor();
91public:
92  PPC64TargetMachine(const Target &T, StringRef TT,
93                     StringRef CPU, StringRef FS, const TargetOptions &Options,
94                     Reloc::Model RM, CodeModel::Model CM,
95                     CodeGenOpt::Level OL);
96};
97
98} // end namespace llvm
99
100#endif
101