1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implements the info about Hexagon target spec. 11// 12//===----------------------------------------------------------------------===// 13 14#include "HexagonTargetMachine.h" 15#include "Hexagon.h" 16#include "HexagonISelLowering.h" 17#include "HexagonMachineScheduler.h" 18#include "HexagonTargetObjectFile.h" 19#include "llvm/CodeGen/Passes.h" 20#include "llvm/IR/Module.h" 21#include "llvm/PassManager.h" 22#include "llvm/Support/CommandLine.h" 23#include "llvm/Support/TargetRegistry.h" 24#include "llvm/Transforms/IPO/PassManagerBuilder.h" 25#include "llvm/Transforms/Scalar.h" 26 27using namespace llvm; 28 29static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops", 30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); 31 32static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched", 33 cl::Hidden, cl::ZeroOrMore, cl::init(false), 34 cl::desc("Disable Hexagon MI Scheduling")); 35 36static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt", 37 cl::Hidden, cl::ZeroOrMore, cl::init(false), 38 cl::desc("Disable Hexagon CFG Optimization")); 39 40 41/// HexagonTargetMachineModule - Note that this is used on hosts that 42/// cannot link in a library unless there are references into the 43/// library. In particular, it seems that it is not possible to get 44/// things to work on Win32 without this. Though it is unused, do not 45/// remove it. 46extern "C" int HexagonTargetMachineModule; 47int HexagonTargetMachineModule = 0; 48 49extern "C" void LLVMInitializeHexagonTarget() { 50 // Register the target. 51 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget); 52} 53 54static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { 55 return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler()); 56} 57 58static MachineSchedRegistry 59SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", 60 createVLIWMachineSched); 61 62/// HexagonTargetMachine ctor - Create an ILP32 architecture model. 63/// 64 65/// Hexagon_TODO: Do I need an aggregate alignment? 66/// 67HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, 68 StringRef CPU, StringRef FS, 69 const TargetOptions &Options, 70 Reloc::Model RM, 71 CodeModel::Model CM, 72 CodeGenOpt::Level OL) 73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 74 DL("e-p:32:32:32-" 75 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 76 "f64:64:64-f32:32:32-a0:0-n32") , 77 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), 78 TSInfo(*this), 79 FrameLowering(Subtarget), 80 InstrItins(&Subtarget.getInstrItineraryData()) { 81 setMCUseCFI(false); 82 initAsmInfo(); 83} 84 85// addPassesForOptimizations - Allow the backend (target) to add Target 86// Independent Optimization passes to the Pass Manager. 87bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { 88 if (getOptLevel() != CodeGenOpt::None) { 89 PM.add(createConstantPropagationPass()); 90 PM.add(createLoopSimplifyPass()); 91 PM.add(createDeadCodeEliminationPass()); 92 PM.add(createConstantPropagationPass()); 93 PM.add(createLoopUnrollPass()); 94 PM.add(createLoopStrengthReducePass()); 95 } 96 return true; 97} 98 99namespace { 100/// Hexagon Code Generator Pass Configuration Options. 101class HexagonPassConfig : public TargetPassConfig { 102public: 103 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) 104 : TargetPassConfig(TM, PM) { 105 // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define 106 // HexagonSubtarget::enableMachineScheduler() { return true; }. 107 // That will bypass the SelectionDAG VLIW scheduler, which is probably just 108 // hurting compile time and will be removed eventually anyway. 109 if (DisableHexagonMISched) 110 disablePass(&MachineSchedulerID); 111 else 112 enablePass(&MachineSchedulerID); 113 } 114 115 HexagonTargetMachine &getHexagonTargetMachine() const { 116 return getTM<HexagonTargetMachine>(); 117 } 118 119 virtual ScheduleDAGInstrs * 120 createMachineScheduler(MachineSchedContext *C) const { 121 return createVLIWMachineSched(C); 122 } 123 124 virtual bool addInstSelector(); 125 virtual bool addPreRegAlloc(); 126 virtual bool addPostRegAlloc(); 127 virtual bool addPreSched2(); 128 virtual bool addPreEmitPass(); 129}; 130} // namespace 131 132TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 133 return new HexagonPassConfig(this, PM); 134} 135 136bool HexagonPassConfig::addInstSelector() { 137 HexagonTargetMachine &TM = getHexagonTargetMachine(); 138 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 139 140 if (!NoOpt) 141 addPass(createHexagonRemoveExtendArgs(TM)); 142 143 addPass(createHexagonISelDag(TM, getOptLevel())); 144 145 if (!NoOpt) { 146 addPass(createHexagonPeephole()); 147 printAndVerify("After hexagon peephole pass"); 148 } 149 150 return false; 151} 152 153bool HexagonPassConfig::addPreRegAlloc() { 154 if (getOptLevel() != CodeGenOpt::None) 155 if (!DisableHardwareLoops) 156 addPass(createHexagonHardwareLoops()); 157 return false; 158} 159 160bool HexagonPassConfig::addPostRegAlloc() { 161 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 162 if (getOptLevel() != CodeGenOpt::None) 163 if (!DisableHexagonCFGOpt) 164 addPass(createHexagonCFGOptimizer(TM)); 165 return false; 166} 167 168bool HexagonPassConfig::addPreSched2() { 169 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 170 const HexagonTargetObjectFile &TLOF = 171 (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering(); 172 173 addPass(createHexagonCopyToCombine()); 174 if (getOptLevel() != CodeGenOpt::None) 175 addPass(&IfConverterID); 176 if (!TLOF.IsSmallDataEnabled()) { 177 addPass(createHexagonSplitConst32AndConst64(TM)); 178 printAndVerify("After hexagon split const32/64 pass"); 179 } 180 return true; 181} 182 183bool HexagonPassConfig::addPreEmitPass() { 184 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 185 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 186 187 if (!NoOpt) 188 addPass(createHexagonNewValueJump()); 189 190 // Expand Spill code for predicate registers. 191 addPass(createHexagonExpandPredSpillCode(TM)); 192 193 // Split up TFRcondsets into conditional transfers. 194 addPass(createHexagonSplitTFRCondSets(TM)); 195 196 // Create Packets. 197 if (!NoOpt) { 198 if (!DisableHardwareLoops) 199 addPass(createHexagonFixupHwLoops()); 200 addPass(createHexagonPacketizer()); 201 } 202 203 return false; 204} 205