1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/ADT/ArrayRef.h" 20#include "llvm/ADT/DenseMapInfo.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/ADT/StringRef.h" 23#include "llvm/ADT/ilist.h" 24#include "llvm/ADT/ilist_node.h" 25#include "llvm/CodeGen/MachineOperand.h" 26#include "llvm/IR/InlineAsm.h" 27#include "llvm/MC/MCInstrDesc.h" 28#include "llvm/Support/ArrayRecycler.h" 29#include "llvm/Support/DebugLoc.h" 30#include "llvm/Target/TargetOpcodes.h" 31#include <vector> 32 33namespace llvm { 34 35template <typename T> class SmallVectorImpl; 36class AliasAnalysis; 37class TargetInstrInfo; 38class TargetRegisterClass; 39class TargetRegisterInfo; 40class MachineFunction; 41class MachineMemOperand; 42 43//===----------------------------------------------------------------------===// 44/// MachineInstr - Representation of each machine instruction. 45/// 46/// This class isn't a POD type, but it must have a trivial destructor. When a 47/// MachineFunction is deleted, all the contained MachineInstrs are deallocated 48/// without having their destructor called. 49/// 50class MachineInstr : public ilist_node<MachineInstr> { 51public: 52 typedef MachineMemOperand **mmo_iterator; 53 54 /// Flags to specify different kinds of comments to output in 55 /// assembly code. These flags carry semantic information not 56 /// otherwise easily derivable from the IR text. 57 /// 58 enum CommentFlag { 59 ReloadReuse = 0x1 60 }; 61 62 enum MIFlag { 63 NoFlags = 0, 64 FrameSetup = 1 << 0, // Instruction is used as a part of 65 // function frame setup code. 66 BundledPred = 1 << 1, // Instruction has bundled predecessors. 67 BundledSucc = 1 << 2 // Instruction has bundled successors. 68 }; 69private: 70 const MCInstrDesc *MCID; // Instruction descriptor. 71 MachineBasicBlock *Parent; // Pointer to the owning basic block. 72 73 // Operands are allocated by an ArrayRecycler. 74 MachineOperand *Operands; // Pointer to the first operand. 75 unsigned NumOperands; // Number of operands on instruction. 76 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity; 77 OperandCapacity CapOperands; // Capacity of the Operands array. 78 79 uint8_t Flags; // Various bits of additional 80 // information about machine 81 // instruction. 82 83 uint8_t AsmPrinterFlags; // Various bits of information used by 84 // the AsmPrinter to emit helpful 85 // comments. This is *not* semantic 86 // information. Do not use this for 87 // anything other than to convey comment 88 // information to AsmPrinter. 89 90 uint8_t NumMemRefs; // Information on memory references. 91 mmo_iterator MemRefs; 92 93 DebugLoc debugLoc; // Source line information. 94 95 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION; 96 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION; 97 // Use MachineFunction::DeleteMachineInstr() instead. 98 ~MachineInstr() LLVM_DELETED_FUNCTION; 99 100 // Intrusive list support 101 friend struct ilist_traits<MachineInstr>; 102 friend struct ilist_traits<MachineBasicBlock>; 103 void setParent(MachineBasicBlock *P) { Parent = P; } 104 105 /// MachineInstr ctor - This constructor creates a copy of the given 106 /// MachineInstr in the given MachineFunction. 107 MachineInstr(MachineFunction &, const MachineInstr &); 108 109 /// MachineInstr ctor - This constructor create a MachineInstr and add the 110 /// implicit operands. It reserves space for number of operands specified by 111 /// MCInstrDesc. An explicit DebugLoc is supplied. 112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID, 113 const DebugLoc dl, bool NoImp = false); 114 115 // MachineInstrs are pool-allocated and owned by MachineFunction. 116 friend class MachineFunction; 117 118public: 119 const MachineBasicBlock* getParent() const { return Parent; } 120 MachineBasicBlock* getParent() { return Parent; } 121 122 /// getAsmPrinterFlags - Return the asm printer flags bitvector. 123 /// 124 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } 125 126 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector 127 /// 128 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } 129 130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. 131 /// 132 bool getAsmPrinterFlag(CommentFlag Flag) const { 133 return AsmPrinterFlags & Flag; 134 } 135 136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter. 137 /// 138 void setAsmPrinterFlag(CommentFlag Flag) { 139 AsmPrinterFlags |= (uint8_t)Flag; 140 } 141 142 /// clearAsmPrinterFlag - clear specific AsmPrinter flags 143 /// 144 void clearAsmPrinterFlag(CommentFlag Flag) { 145 AsmPrinterFlags &= ~Flag; 146 } 147 148 /// getFlags - Return the MI flags bitvector. 149 uint8_t getFlags() const { 150 return Flags; 151 } 152 153 /// getFlag - Return whether an MI flag is set. 154 bool getFlag(MIFlag Flag) const { 155 return Flags & Flag; 156 } 157 158 /// setFlag - Set a MI flag. 159 void setFlag(MIFlag Flag) { 160 Flags |= (uint8_t)Flag; 161 } 162 163 void setFlags(unsigned flags) { 164 // Filter out the automatically maintained flags. 165 unsigned Mask = BundledPred | BundledSucc; 166 Flags = (Flags & Mask) | (flags & ~Mask); 167 } 168 169 /// clearFlag - Clear a MI flag. 170 void clearFlag(MIFlag Flag) { 171 Flags &= ~((uint8_t)Flag); 172 } 173 174 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI 175 /// in a bundle). 176 /// 177 /// A bundle looks like this before it's finalized: 178 /// ---------------- 179 /// | MI | 180 /// ---------------- 181 /// | 182 /// ---------------- 183 /// | MI * | 184 /// ---------------- 185 /// | 186 /// ---------------- 187 /// | MI * | 188 /// ---------------- 189 /// In this case, the first MI starts a bundle but is not inside a bundle, the 190 /// next 2 MIs are considered "inside" the bundle. 191 /// 192 /// After a bundle is finalized, it looks like this: 193 /// ---------------- 194 /// | Bundle | 195 /// ---------------- 196 /// | 197 /// ---------------- 198 /// | MI * | 199 /// ---------------- 200 /// | 201 /// ---------------- 202 /// | MI * | 203 /// ---------------- 204 /// | 205 /// ---------------- 206 /// | MI * | 207 /// ---------------- 208 /// The first instruction has the special opcode "BUNDLE". It's not "inside" 209 /// a bundle, but the next three MIs are. 210 bool isInsideBundle() const { 211 return getFlag(BundledPred); 212 } 213 214 /// isBundled - Return true if this instruction part of a bundle. This is true 215 /// if either itself or its following instruction is marked "InsideBundle". 216 bool isBundled() const { 217 return isBundledWithPred() || isBundledWithSucc(); 218 } 219 220 /// Return true if this instruction is part of a bundle, and it is not the 221 /// first instruction in the bundle. 222 bool isBundledWithPred() const { return getFlag(BundledPred); } 223 224 /// Return true if this instruction is part of a bundle, and it is not the 225 /// last instruction in the bundle. 226 bool isBundledWithSucc() const { return getFlag(BundledSucc); } 227 228 /// Bundle this instruction with its predecessor. This can be an unbundled 229 /// instruction, or it can be the first instruction in a bundle. 230 void bundleWithPred(); 231 232 /// Bundle this instruction with its successor. This can be an unbundled 233 /// instruction, or it can be the last instruction in a bundle. 234 void bundleWithSucc(); 235 236 /// Break bundle above this instruction. 237 void unbundleFromPred(); 238 239 /// Break bundle below this instruction. 240 void unbundleFromSucc(); 241 242 /// getDebugLoc - Returns the debug location id of this MachineInstr. 243 /// 244 DebugLoc getDebugLoc() const { return debugLoc; } 245 246 /// emitError - Emit an error referring to the source location of this 247 /// instruction. This should only be used for inline assembly that is somehow 248 /// impossible to compile. Other errors should have been handled much 249 /// earlier. 250 /// 251 /// If this method returns, the caller should try to recover from the error. 252 /// 253 void emitError(StringRef Msg) const; 254 255 /// getDesc - Returns the target instruction descriptor of this 256 /// MachineInstr. 257 const MCInstrDesc &getDesc() const { return *MCID; } 258 259 /// getOpcode - Returns the opcode of this MachineInstr. 260 /// 261 int getOpcode() const { return MCID->Opcode; } 262 263 /// Access to explicit operands of the instruction. 264 /// 265 unsigned getNumOperands() const { return NumOperands; } 266 267 const MachineOperand& getOperand(unsigned i) const { 268 assert(i < getNumOperands() && "getOperand() out of range!"); 269 return Operands[i]; 270 } 271 MachineOperand& getOperand(unsigned i) { 272 assert(i < getNumOperands() && "getOperand() out of range!"); 273 return Operands[i]; 274 } 275 276 /// getNumExplicitOperands - Returns the number of non-implicit operands. 277 /// 278 unsigned getNumExplicitOperands() const; 279 280 /// iterator/begin/end - Iterate over all operands of a machine instruction. 281 typedef MachineOperand *mop_iterator; 282 typedef const MachineOperand *const_mop_iterator; 283 284 mop_iterator operands_begin() { return Operands; } 285 mop_iterator operands_end() { return Operands + NumOperands; } 286 287 const_mop_iterator operands_begin() const { return Operands; } 288 const_mop_iterator operands_end() const { return Operands + NumOperands; } 289 290 /// Access to memory operands of the instruction 291 mmo_iterator memoperands_begin() const { return MemRefs; } 292 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; } 293 bool memoperands_empty() const { return NumMemRefs == 0; } 294 295 /// hasOneMemOperand - Return true if this instruction has exactly one 296 /// MachineMemOperand. 297 bool hasOneMemOperand() const { 298 return NumMemRefs == 1; 299 } 300 301 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 302 /// queries but they are bundle aware. 303 304 enum QueryType { 305 IgnoreBundle, // Ignore bundles 306 AnyInBundle, // Return true if any instruction in bundle has property 307 AllInBundle // Return true if all instructions in bundle have property 308 }; 309 310 /// hasProperty - Return true if the instruction (or in the case of a bundle, 311 /// the instructions inside the bundle) has the specified property. 312 /// The first argument is the property being queried. 313 /// The second argument indicates whether the query should look inside 314 /// instruction bundles. 315 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { 316 // Inline the fast path for unbundled or bundle-internal instructions. 317 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) 318 return getDesc().getFlags() & (1 << MCFlag); 319 320 // If this is the first instruction in a bundle, take the slow path. 321 return hasPropertyInBundle(1 << MCFlag, Type); 322 } 323 324 /// isVariadic - Return true if this instruction can have a variable number of 325 /// operands. In this case, the variable operands will be after the normal 326 /// operands but before the implicit definitions and uses (if any are 327 /// present). 328 bool isVariadic(QueryType Type = IgnoreBundle) const { 329 return hasProperty(MCID::Variadic, Type); 330 } 331 332 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 333 /// ARM instructions which can set condition code if 's' bit is set. 334 bool hasOptionalDef(QueryType Type = IgnoreBundle) const { 335 return hasProperty(MCID::HasOptionalDef, Type); 336 } 337 338 /// isPseudo - Return true if this is a pseudo instruction that doesn't 339 /// correspond to a real machine instruction. 340 /// 341 bool isPseudo(QueryType Type = IgnoreBundle) const { 342 return hasProperty(MCID::Pseudo, Type); 343 } 344 345 bool isReturn(QueryType Type = AnyInBundle) const { 346 return hasProperty(MCID::Return, Type); 347 } 348 349 bool isCall(QueryType Type = AnyInBundle) const { 350 return hasProperty(MCID::Call, Type); 351 } 352 353 /// isBarrier - Returns true if the specified instruction stops control flow 354 /// from executing the instruction immediately following it. Examples include 355 /// unconditional branches and return instructions. 356 bool isBarrier(QueryType Type = AnyInBundle) const { 357 return hasProperty(MCID::Barrier, Type); 358 } 359 360 /// isTerminator - Returns true if this instruction part of the terminator for 361 /// a basic block. Typically this is things like return and branch 362 /// instructions. 363 /// 364 /// Various passes use this to insert code into the bottom of a basic block, 365 /// but before control flow occurs. 366 bool isTerminator(QueryType Type = AnyInBundle) const { 367 return hasProperty(MCID::Terminator, Type); 368 } 369 370 /// isBranch - Returns true if this is a conditional, unconditional, or 371 /// indirect branch. Predicates below can be used to discriminate between 372 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 373 /// get more information. 374 bool isBranch(QueryType Type = AnyInBundle) const { 375 return hasProperty(MCID::Branch, Type); 376 } 377 378 /// isIndirectBranch - Return true if this is an indirect branch, such as a 379 /// branch through a register. 380 bool isIndirectBranch(QueryType Type = AnyInBundle) const { 381 return hasProperty(MCID::IndirectBranch, Type); 382 } 383 384 /// isConditionalBranch - Return true if this is a branch which may fall 385 /// through to the next instruction or may transfer control flow to some other 386 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 387 /// information about this branch. 388 bool isConditionalBranch(QueryType Type = AnyInBundle) const { 389 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); 390 } 391 392 /// isUnconditionalBranch - Return true if this is a branch which always 393 /// transfers control flow to some other block. The 394 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 395 /// about this branch. 396 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { 397 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type); 398 } 399 400 /// Return true if this instruction has a predicate operand that 401 /// controls execution. It may be set to 'always', or may be set to other 402 /// values. There are various methods in TargetInstrInfo that can be used to 403 /// control and modify the predicate in this instruction. 404 bool isPredicable(QueryType Type = AllInBundle) const { 405 // If it's a bundle than all bundled instructions must be predicable for this 406 // to return true. 407 return hasProperty(MCID::Predicable, Type); 408 } 409 410 /// isCompare - Return true if this instruction is a comparison. 411 bool isCompare(QueryType Type = IgnoreBundle) const { 412 return hasProperty(MCID::Compare, Type); 413 } 414 415 /// isMoveImmediate - Return true if this instruction is a move immediate 416 /// (including conditional moves) instruction. 417 bool isMoveImmediate(QueryType Type = IgnoreBundle) const { 418 return hasProperty(MCID::MoveImm, Type); 419 } 420 421 /// isBitcast - Return true if this instruction is a bitcast instruction. 422 /// 423 bool isBitcast(QueryType Type = IgnoreBundle) const { 424 return hasProperty(MCID::Bitcast, Type); 425 } 426 427 /// isSelect - Return true if this instruction is a select instruction. 428 /// 429 bool isSelect(QueryType Type = IgnoreBundle) const { 430 return hasProperty(MCID::Select, Type); 431 } 432 433 /// isNotDuplicable - Return true if this instruction cannot be safely 434 /// duplicated. For example, if the instruction has a unique labels attached 435 /// to it, duplicating it would cause multiple definition errors. 436 bool isNotDuplicable(QueryType Type = AnyInBundle) const { 437 return hasProperty(MCID::NotDuplicable, Type); 438 } 439 440 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 441 /// which must be filled by the code generator. 442 bool hasDelaySlot(QueryType Type = AnyInBundle) const { 443 return hasProperty(MCID::DelaySlot, Type); 444 } 445 446 /// canFoldAsLoad - Return true for instructions that can be folded as 447 /// memory operands in other instructions. The most common use for this 448 /// is instructions that are simple loads from memory that don't modify 449 /// the loaded value in any way, but it can also be used for instructions 450 /// that can be expressed as constant-pool loads, such as V_SETALLONES 451 /// on x86, to allow them to be folded when it is beneficial. 452 /// This should only be set on instructions that return a value in their 453 /// only virtual register definition. 454 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { 455 return hasProperty(MCID::FoldableAsLoad, Type); 456 } 457 458 //===--------------------------------------------------------------------===// 459 // Side Effect Analysis 460 //===--------------------------------------------------------------------===// 461 462 /// mayLoad - Return true if this instruction could possibly read memory. 463 /// Instructions with this flag set are not necessarily simple load 464 /// instructions, they may load a value and modify it, for example. 465 bool mayLoad(QueryType Type = AnyInBundle) const { 466 if (isInlineAsm()) { 467 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 468 if (ExtraInfo & InlineAsm::Extra_MayLoad) 469 return true; 470 } 471 return hasProperty(MCID::MayLoad, Type); 472 } 473 474 475 /// mayStore - Return true if this instruction could possibly modify memory. 476 /// Instructions with this flag set are not necessarily simple store 477 /// instructions, they may store a modified value based on their operands, or 478 /// may not actually modify anything, for example. 479 bool mayStore(QueryType Type = AnyInBundle) const { 480 if (isInlineAsm()) { 481 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 482 if (ExtraInfo & InlineAsm::Extra_MayStore) 483 return true; 484 } 485 return hasProperty(MCID::MayStore, Type); 486 } 487 488 //===--------------------------------------------------------------------===// 489 // Flags that indicate whether an instruction can be modified by a method. 490 //===--------------------------------------------------------------------===// 491 492 /// isCommutable - Return true if this may be a 2- or 3-address 493 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 494 /// result if Y and Z are exchanged. If this flag is set, then the 495 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 496 /// instruction. 497 /// 498 /// Note that this flag may be set on instructions that are only commutable 499 /// sometimes. In these cases, the call to commuteInstruction will fail. 500 /// Also note that some instructions require non-trivial modification to 501 /// commute them. 502 bool isCommutable(QueryType Type = IgnoreBundle) const { 503 return hasProperty(MCID::Commutable, Type); 504 } 505 506 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 507 /// which can be changed into a 3-address instruction if needed. Doing this 508 /// transformation can be profitable in the register allocator, because it 509 /// means that the instruction can use a 2-address form if possible, but 510 /// degrade into a less efficient form if the source and dest register cannot 511 /// be assigned to the same register. For example, this allows the x86 512 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 513 /// is the same speed as the shift but has bigger code size. 514 /// 515 /// If this returns true, then the target must implement the 516 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 517 /// is allowed to fail if the transformation isn't valid for this specific 518 /// instruction (e.g. shl reg, 4 on x86). 519 /// 520 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { 521 return hasProperty(MCID::ConvertibleTo3Addr, Type); 522 } 523 524 /// usesCustomInsertionHook - Return true if this instruction requires 525 /// custom insertion support when the DAG scheduler is inserting it into a 526 /// machine basic block. If this is true for the instruction, it basically 527 /// means that it is a pseudo instruction used at SelectionDAG time that is 528 /// expanded out into magic code by the target when MachineInstrs are formed. 529 /// 530 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 531 /// is used to insert this into the MachineBasicBlock. 532 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { 533 return hasProperty(MCID::UsesCustomInserter, Type); 534 } 535 536 /// hasPostISelHook - Return true if this instruction requires *adjustment* 537 /// after instruction selection by calling a target hook. For example, this 538 /// can be used to fill in ARM 's' optional operand depending on whether 539 /// the conditional flag register is used. 540 bool hasPostISelHook(QueryType Type = IgnoreBundle) const { 541 return hasProperty(MCID::HasPostISelHook, Type); 542 } 543 544 /// isRematerializable - Returns true if this instruction is a candidate for 545 /// remat. This flag is deprecated, please don't use it anymore. If this 546 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 547 /// verify the instruction is really rematable. 548 bool isRematerializable(QueryType Type = AllInBundle) const { 549 // It's only possible to re-mat a bundle if all bundled instructions are 550 // re-materializable. 551 return hasProperty(MCID::Rematerializable, Type); 552 } 553 554 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 555 /// less) than a move instruction. This is useful during certain types of 556 /// optimizations (e.g., remat during two-address conversion or machine licm) 557 /// where we would like to remat or hoist the instruction, but not if it costs 558 /// more than moving the instruction into the appropriate register. Note, we 559 /// are not marking copies from and to the same register class with this flag. 560 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { 561 // Only returns true for a bundle if all bundled instructions are cheap. 562 // FIXME: This probably requires a target hook. 563 return hasProperty(MCID::CheapAsAMove, Type); 564 } 565 566 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 567 /// have special register allocation requirements that are not captured by the 568 /// operand register classes. e.g. ARM::STRD's two source registers must be an 569 /// even / odd pair, ARM::STM registers have to be in ascending order. 570 /// Post-register allocation passes should not attempt to change allocations 571 /// for sources of instructions with this flag. 572 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { 573 return hasProperty(MCID::ExtraSrcRegAllocReq, Type); 574 } 575 576 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 577 /// have special register allocation requirements that are not captured by the 578 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 579 /// even / odd pair, ARM::LDM registers have to be in ascending order. 580 /// Post-register allocation passes should not attempt to change allocations 581 /// for definitions of instructions with this flag. 582 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { 583 return hasProperty(MCID::ExtraDefRegAllocReq, Type); 584 } 585 586 587 enum MICheckType { 588 CheckDefs, // Check all operands for equality 589 CheckKillDead, // Check all operands including kill / dead markers 590 IgnoreDefs, // Ignore all definitions 591 IgnoreVRegDefs // Ignore virtual register definitions 592 }; 593 594 /// isIdenticalTo - Return true if this instruction is identical to (same 595 /// opcode and same operands as) the specified instruction. 596 bool isIdenticalTo(const MachineInstr *Other, 597 MICheckType Check = CheckDefs) const; 598 599 /// Unlink 'this' from the containing basic block, and return it without 600 /// deleting it. 601 /// 602 /// This function can not be used on bundled instructions, use 603 /// removeFromBundle() to remove individual instructions from a bundle. 604 MachineInstr *removeFromParent(); 605 606 /// Unlink this instruction from its basic block and return it without 607 /// deleting it. 608 /// 609 /// If the instruction is part of a bundle, the other instructions in the 610 /// bundle remain bundled. 611 MachineInstr *removeFromBundle(); 612 613 /// Unlink 'this' from the containing basic block and delete it. 614 /// 615 /// If this instruction is the header of a bundle, the whole bundle is erased. 616 /// This function can not be used for instructions inside a bundle, use 617 /// eraseFromBundle() to erase individual bundled instructions. 618 void eraseFromParent(); 619 620 /// Unlink 'this' form its basic block and delete it. 621 /// 622 /// If the instruction is part of a bundle, the other instructions in the 623 /// bundle remain bundled. 624 void eraseFromBundle(); 625 626 /// isLabel - Returns true if the MachineInstr represents a label. 627 /// 628 bool isLabel() const { 629 return getOpcode() == TargetOpcode::PROLOG_LABEL || 630 getOpcode() == TargetOpcode::EH_LABEL || 631 getOpcode() == TargetOpcode::GC_LABEL; 632 } 633 634 bool isPrologLabel() const { 635 return getOpcode() == TargetOpcode::PROLOG_LABEL; 636 } 637 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 638 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 639 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 640 /// A DBG_VALUE is indirect iff the first operand is a register and 641 /// the second operand is an immediate. 642 bool isIndirectDebugValue() const { 643 return isDebugValue() 644 && getOperand(0).isReg() 645 && getOperand(1).isImm(); 646 } 647 648 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } 649 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 650 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 651 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 652 bool isMSInlineAsm() const { 653 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect(); 654 } 655 bool isStackAligningInlineAsm() const; 656 InlineAsm::AsmDialect getInlineAsmDialect() const; 657 bool isInsertSubreg() const { 658 return getOpcode() == TargetOpcode::INSERT_SUBREG; 659 } 660 bool isSubregToReg() const { 661 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 662 } 663 bool isRegSequence() const { 664 return getOpcode() == TargetOpcode::REG_SEQUENCE; 665 } 666 bool isBundle() const { 667 return getOpcode() == TargetOpcode::BUNDLE; 668 } 669 bool isCopy() const { 670 return getOpcode() == TargetOpcode::COPY; 671 } 672 bool isFullCopy() const { 673 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 674 } 675 676 /// isCopyLike - Return true if the instruction behaves like a copy. 677 /// This does not include native copy instructions. 678 bool isCopyLike() const { 679 return isCopy() || isSubregToReg(); 680 } 681 682 /// isIdentityCopy - Return true is the instruction is an identity copy. 683 bool isIdentityCopy() const { 684 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && 685 getOperand(0).getSubReg() == getOperand(1).getSubReg(); 686 } 687 688 /// isTransient - Return true if this is a transient instruction that is 689 /// either very likely to be eliminated during register allocation (such as 690 /// copy-like instructions), or if this instruction doesn't have an 691 /// execution-time cost. 692 bool isTransient() const { 693 switch(getOpcode()) { 694 default: return false; 695 // Copy-like instructions are usually eliminated during register allocation. 696 case TargetOpcode::PHI: 697 case TargetOpcode::COPY: 698 case TargetOpcode::INSERT_SUBREG: 699 case TargetOpcode::SUBREG_TO_REG: 700 case TargetOpcode::REG_SEQUENCE: 701 // Pseudo-instructions that don't produce any real output. 702 case TargetOpcode::IMPLICIT_DEF: 703 case TargetOpcode::KILL: 704 case TargetOpcode::PROLOG_LABEL: 705 case TargetOpcode::EH_LABEL: 706 case TargetOpcode::GC_LABEL: 707 case TargetOpcode::DBG_VALUE: 708 return true; 709 } 710 } 711 712 /// Return the number of instructions inside the MI bundle, excluding the 713 /// bundle header. 714 /// 715 /// This is the number of instructions that MachineBasicBlock::iterator 716 /// skips, 0 for unbundled instructions. 717 unsigned getBundleSize() const; 718 719 /// readsRegister - Return true if the MachineInstr reads the specified 720 /// register. If TargetRegisterInfo is passed, then it also checks if there 721 /// is a read of a super-register. 722 /// This does not count partial redefines of virtual registers as reads: 723 /// %reg1024:6 = OP. 724 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 725 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 726 } 727 728 /// readsVirtualRegister - Return true if the MachineInstr reads the specified 729 /// virtual register. Take into account that a partial define is a 730 /// read-modify-write operation. 731 bool readsVirtualRegister(unsigned Reg) const { 732 return readsWritesVirtualRegister(Reg).first; 733 } 734 735 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 736 /// indicating if this instruction reads or writes Reg. This also considers 737 /// partial defines. 738 /// If Ops is not null, all operand indices for Reg are added. 739 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg, 740 SmallVectorImpl<unsigned> *Ops = 0) const; 741 742 /// killsRegister - Return true if the MachineInstr kills the specified 743 /// register. If TargetRegisterInfo is passed, then it also checks if there is 744 /// a kill of a super-register. 745 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 746 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 747 } 748 749 /// definesRegister - Return true if the MachineInstr fully defines the 750 /// specified register. If TargetRegisterInfo is passed, then it also checks 751 /// if there is a def of a super-register. 752 /// NOTE: It's ignoring subreg indices on virtual registers. 753 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const { 754 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 755 } 756 757 /// modifiesRegister - Return true if the MachineInstr modifies (fully define 758 /// or partially define) the specified register. 759 /// NOTE: It's ignoring subreg indices on virtual registers. 760 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { 761 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 762 } 763 764 /// registerDefIsDead - Returns true if the register is dead in this machine 765 /// instruction. If TargetRegisterInfo is passed, then it also checks 766 /// if there is a dead def of a super-register. 767 bool registerDefIsDead(unsigned Reg, 768 const TargetRegisterInfo *TRI = NULL) const { 769 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 770 } 771 772 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 773 /// the specific register or -1 if it is not found. It further tightens 774 /// the search criteria to a use that kills the register if isKill is true. 775 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 776 const TargetRegisterInfo *TRI = NULL) const; 777 778 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 779 /// a pointer to the MachineOperand rather than an index. 780 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 781 const TargetRegisterInfo *TRI = NULL) { 782 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 783 return (Idx == -1) ? NULL : &getOperand(Idx); 784 } 785 786 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 787 /// the specified register or -1 if it is not found. If isDead is true, defs 788 /// that are not dead are skipped. If Overlap is true, then it also looks for 789 /// defs that merely overlap the specified register. If TargetRegisterInfo is 790 /// non-null, then it also checks if there is a def of a super-register. 791 /// This may also return a register mask operand when Overlap is true. 792 int findRegisterDefOperandIdx(unsigned Reg, 793 bool isDead = false, bool Overlap = false, 794 const TargetRegisterInfo *TRI = NULL) const; 795 796 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 797 /// a pointer to the MachineOperand rather than an index. 798 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 799 const TargetRegisterInfo *TRI = NULL) { 800 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI); 801 return (Idx == -1) ? NULL : &getOperand(Idx); 802 } 803 804 /// findFirstPredOperandIdx() - Find the index of the first operand in the 805 /// operand list that is used to represent the predicate. It returns -1 if 806 /// none is found. 807 int findFirstPredOperandIdx() const; 808 809 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that 810 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 811 /// getOperand(OpIdx) does not belong to an inline asm operand group. 812 /// 813 /// If GroupNo is not NULL, it will receive the number of the operand group 814 /// containing OpIdx. 815 /// 816 /// The flag operand is an immediate that can be decoded with methods like 817 /// InlineAsm::hasRegClassConstraint(). 818 /// 819 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const; 820 821 /// getRegClassConstraint - Compute the static register class constraint for 822 /// operand OpIdx. For normal instructions, this is derived from the 823 /// MCInstrDesc. For inline assembly it is derived from the flag words. 824 /// 825 /// Returns NULL if the static register classs constraint cannot be 826 /// determined. 827 /// 828 const TargetRegisterClass* 829 getRegClassConstraint(unsigned OpIdx, 830 const TargetInstrInfo *TII, 831 const TargetRegisterInfo *TRI) const; 832 833 /// tieOperands - Add a tie between the register operands at DefIdx and 834 /// UseIdx. The tie will cause the register allocator to ensure that the two 835 /// operands are assigned the same physical register. 836 /// 837 /// Tied operands are managed automatically for explicit operands in the 838 /// MCInstrDesc. This method is for exceptional cases like inline asm. 839 void tieOperands(unsigned DefIdx, unsigned UseIdx); 840 841 /// findTiedOperandIdx - Given the index of a tied register operand, find the 842 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the 843 /// index of the tied operand which must exist. 844 unsigned findTiedOperandIdx(unsigned OpIdx) const; 845 846 /// isRegTiedToUseOperand - Given the index of a register def operand, 847 /// check if the register def is tied to a source operand, due to either 848 /// two-address elimination or inline assembly constraints. Returns the 849 /// first tied use operand index by reference if UseOpIdx is not null. 850 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const { 851 const MachineOperand &MO = getOperand(DefOpIdx); 852 if (!MO.isReg() || !MO.isDef() || !MO.isTied()) 853 return false; 854 if (UseOpIdx) 855 *UseOpIdx = findTiedOperandIdx(DefOpIdx); 856 return true; 857 } 858 859 /// isRegTiedToDefOperand - Return true if the use operand of the specified 860 /// index is tied to an def operand. It also returns the def operand index by 861 /// reference if DefOpIdx is not null. 862 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const { 863 const MachineOperand &MO = getOperand(UseOpIdx); 864 if (!MO.isReg() || !MO.isUse() || !MO.isTied()) 865 return false; 866 if (DefOpIdx) 867 *DefOpIdx = findTiedOperandIdx(UseOpIdx); 868 return true; 869 } 870 871 /// clearKillInfo - Clears kill flags on all operands. 872 /// 873 void clearKillInfo(); 874 875 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx, 876 /// properly composing subreg indices where necessary. 877 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, 878 const TargetRegisterInfo &RegInfo); 879 880 /// addRegisterKilled - We have determined MI kills a register. Look for the 881 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 882 /// add a implicit operand if it's not found. Returns true if the operand 883 /// exists / is added. 884 bool addRegisterKilled(unsigned IncomingReg, 885 const TargetRegisterInfo *RegInfo, 886 bool AddIfNotFound = false); 887 888 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is 889 /// provided, this includes super-register kills. 890 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo); 891 892 /// addRegisterDead - We have determined MI defined a register without a use. 893 /// Look for the operand that defines it and mark it as IsDead. If 894 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 895 /// true if the operand exists / is added. 896 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, 897 bool AddIfNotFound = false); 898 899 /// addRegisterDefined - We have determined MI defines a register. Make sure 900 /// there is an operand defining Reg. 901 void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo = 0); 902 903 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as 904 /// dead except those in the UsedRegs list. 905 /// 906 /// On instructions with register mask operands, also add implicit-def 907 /// operands for all registers in UsedRegs. 908 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 909 const TargetRegisterInfo &TRI); 910 911 /// isSafeToMove - Return true if it is safe to move this instruction. If 912 /// SawStore is set to true, it means that there is a store (or call) between 913 /// the instruction's location and its intended destination. 914 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, 915 bool &SawStore) const; 916 917 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered 918 /// or volatile memory reference, or if the information describing the memory 919 /// reference is not available. Return false if it is known to have no 920 /// ordered or volatile memory references. 921 bool hasOrderedMemoryRef() const; 922 923 /// isInvariantLoad - Return true if this instruction is loading from a 924 /// location whose value is invariant across the function. For example, 925 /// loading a value from the constant pool or from the argument area of 926 /// a function if it does not change. This should only return true of *all* 927 /// loads the instruction does are invariant (if it does multiple loads). 928 bool isInvariantLoad(AliasAnalysis *AA) const; 929 930 /// isConstantValuePHI - If the specified instruction is a PHI that always 931 /// merges together the same virtual register, return the register, otherwise 932 /// return 0. 933 unsigned isConstantValuePHI() const; 934 935 /// hasUnmodeledSideEffects - Return true if this instruction has side 936 /// effects that are not modeled by mayLoad / mayStore, etc. 937 /// For all instructions, the property is encoded in MCInstrDesc::Flags 938 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is 939 /// INLINEASM instruction, in which case the side effect property is encoded 940 /// in one of its operands (see InlineAsm::Extra_HasSideEffect). 941 /// 942 bool hasUnmodeledSideEffects() const; 943 944 /// allDefsAreDead - Return true if all the defs of this instruction are dead. 945 /// 946 bool allDefsAreDead() const; 947 948 /// copyImplicitOps - Copy implicit register operands from specified 949 /// instruction to this instruction. 950 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI); 951 952 // 953 // Debugging support 954 // 955 void print(raw_ostream &OS, const TargetMachine *TM = 0, 956 bool SkipOpers = false) const; 957 void dump() const; 958 959 //===--------------------------------------------------------------------===// 960 // Accessors used to build up machine instructions. 961 962 /// Add the specified operand to the instruction. If it is an implicit 963 /// operand, it is added to the end of the operand list. If it is an 964 /// explicit operand it is added at the end of the explicit operand list 965 /// (before the first implicit operand). 966 /// 967 /// MF must be the machine function that was used to allocate this 968 /// instruction. 969 /// 970 /// MachineInstrBuilder provides a more convenient interface for creating 971 /// instructions and adding operands. 972 void addOperand(MachineFunction &MF, const MachineOperand &Op); 973 974 /// Add an operand without providing an MF reference. This only works for 975 /// instructions that are inserted in a basic block. 976 /// 977 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be 978 /// preferred. 979 void addOperand(const MachineOperand &Op); 980 981 /// setDesc - Replace the instruction descriptor (thus opcode) of 982 /// the current instruction with a new one. 983 /// 984 void setDesc(const MCInstrDesc &tid) { MCID = &tid; } 985 986 /// setDebugLoc - Replace current source information with new such. 987 /// Avoid using this, the constructor argument is preferable. 988 /// 989 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } 990 991 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 992 /// fewer operand than it started with. 993 /// 994 void RemoveOperand(unsigned i); 995 996 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 997 /// This function should be used only occasionally. The setMemRefs function 998 /// is the primary method for setting up a MachineInstr's MemRefs list. 999 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 1000 1001 /// setMemRefs - Assign this MachineInstr's memory reference descriptor 1002 /// list. This does not transfer ownership. 1003 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { 1004 MemRefs = NewMemRefs; 1005 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs); 1006 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs"); 1007 } 1008 1009private: 1010 /// getRegInfo - If this instruction is embedded into a MachineFunction, 1011 /// return the MachineRegisterInfo object for the current function, otherwise 1012 /// return null. 1013 MachineRegisterInfo *getRegInfo(); 1014 1015 /// untieRegOperand - Break any tie involving OpIdx. 1016 void untieRegOperand(unsigned OpIdx) { 1017 MachineOperand &MO = getOperand(OpIdx); 1018 if (MO.isReg() && MO.isTied()) { 1019 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; 1020 MO.TiedTo = 0; 1021 } 1022 } 1023 1024 /// addImplicitDefUseOperands - Add all implicit def and use operands to 1025 /// this instruction. 1026 void addImplicitDefUseOperands(MachineFunction &MF); 1027 1028 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 1029 /// this instruction from their respective use lists. This requires that the 1030 /// operands already be on their use lists. 1031 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); 1032 1033 /// AddRegOperandsToUseLists - Add all of the register operands in 1034 /// this instruction from their respective use lists. This requires that the 1035 /// operands not be on their use lists yet. 1036 void AddRegOperandsToUseLists(MachineRegisterInfo&); 1037 1038 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a 1039 /// bundle. 1040 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const; 1041}; 1042 1043/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare 1044/// MachineInstr* by *value* of the instruction rather than by pointer value. 1045/// The hashing and equality testing functions ignore definitions so this is 1046/// useful for CSE, etc. 1047struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 1048 static inline MachineInstr *getEmptyKey() { 1049 return 0; 1050 } 1051 1052 static inline MachineInstr *getTombstoneKey() { 1053 return reinterpret_cast<MachineInstr*>(-1); 1054 } 1055 1056 static unsigned getHashValue(const MachineInstr* const &MI); 1057 1058 static bool isEqual(const MachineInstr* const &LHS, 1059 const MachineInstr* const &RHS) { 1060 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 1061 LHS == getEmptyKey() || LHS == getTombstoneKey()) 1062 return LHS == RHS; 1063 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs); 1064 } 1065}; 1066 1067//===----------------------------------------------------------------------===// 1068// Debugging Support 1069 1070inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 1071 MI.print(OS); 1072 return OS; 1073} 1074 1075} // End llvm namespace 1076 1077#endif 1078