rs6000.h revision 161651
1/* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 2, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to the 20 Free Software Foundation, 59 Temple Place - Suite 330, Boston, 21 MA 02111-1307, USA. */ 22 23/* Note that some other tm.h files include this one and then override 24 many of the definitions. */ 25 26/* Definitions for the object file format. These are set at 27 compile-time. */ 28 29#define OBJECT_XCOFF 1 30#define OBJECT_ELF 2 31#define OBJECT_PEF 3 32#define OBJECT_MACHO 4 33 34#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 35#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 36#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 37#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 38 39#ifndef TARGET_AIX 40#define TARGET_AIX 0 41#endif 42 43/* Default string to use for cpu if not specified. */ 44#ifndef TARGET_CPU_DEFAULT 45#define TARGET_CPU_DEFAULT ((char *)0) 46#endif 47 48/* Common ASM definitions used by ASM_SPEC among the various targets 49 for handling -mcpu=xxx switches. */ 50#define ASM_CPU_SPEC \ 51"%{!mcpu*: \ 52 %{mpower: %{!mpower2: -mpwr}} \ 53 %{mpower2: -mpwrx} \ 54 %{mpowerpc64*: -mppc64} \ 55 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ 56 %{mno-power: %{!mpowerpc*: -mcom}} \ 57 %{!mno-power: %{!mpower*: %(asm_default)}}} \ 58%{mcpu=common: -mcom} \ 59%{mcpu=power: -mpwr} \ 60%{mcpu=power2: -mpwrx} \ 61%{mcpu=power3: -mppc64} \ 62%{mcpu=power4: -mpower4} \ 63%{mcpu=power5: -mpower4} \ 64%{mcpu=powerpc: -mppc} \ 65%{mcpu=rios: -mpwr} \ 66%{mcpu=rios1: -mpwr} \ 67%{mcpu=rios2: -mpwrx} \ 68%{mcpu=rsc: -mpwr} \ 69%{mcpu=rsc1: -mpwr} \ 70%{mcpu=rs64a: -mppc64} \ 71%{mcpu=401: -mppc} \ 72%{mcpu=403: -m403} \ 73%{mcpu=405: -m405} \ 74%{mcpu=405fp: -m405} \ 75%{mcpu=440: -m440} \ 76%{mcpu=440fp: -m440} \ 77%{mcpu=505: -mppc} \ 78%{mcpu=601: -m601} \ 79%{mcpu=602: -mppc} \ 80%{mcpu=603: -mppc} \ 81%{mcpu=603e: -mppc} \ 82%{mcpu=ec603e: -mppc} \ 83%{mcpu=604: -mppc} \ 84%{mcpu=604e: -mppc} \ 85%{mcpu=620: -mppc64} \ 86%{mcpu=630: -mppc64} \ 87%{mcpu=740: -mppc} \ 88%{mcpu=750: -mppc} \ 89%{mcpu=G3: -mppc} \ 90%{mcpu=7400: -mppc -maltivec} \ 91%{mcpu=7450: -mppc -maltivec} \ 92%{mcpu=G4: -mppc -maltivec} \ 93%{mcpu=801: -mppc} \ 94%{mcpu=821: -mppc} \ 95%{mcpu=823: -mppc} \ 96%{mcpu=860: -mppc} \ 97%{mcpu=970: -mpower4 -maltivec} \ 98%{mcpu=G5: -mpower4 -maltivec} \ 99%{mcpu=8540: -me500} \ 100%{maltivec: -maltivec} \ 101-many" 102 103#define CPP_DEFAULT_SPEC "" 104 105#define ASM_DEFAULT_SPEC "" 106 107/* This macro defines names of additional specifications to put in the specs 108 that can be used in various specifications like CC1_SPEC. Its definition 109 is an initializer with a subgrouping for each command option. 110 111 Each subgrouping contains a string constant, that defines the 112 specification name, and a string constant that used by the GCC driver 113 program. 114 115 Do not define this macro if it does not need to do anything. */ 116 117#define SUBTARGET_EXTRA_SPECS 118 119#define EXTRA_SPECS \ 120 { "cpp_default", CPP_DEFAULT_SPEC }, \ 121 { "asm_cpu", ASM_CPU_SPEC }, \ 122 { "asm_default", ASM_DEFAULT_SPEC }, \ 123 SUBTARGET_EXTRA_SPECS 124 125/* Architecture type. */ 126 127extern int target_flags; 128 129/* Use POWER architecture instructions and MQ register. */ 130#define MASK_POWER 0x00000001 131 132/* Use POWER2 extensions to POWER architecture. */ 133#define MASK_POWER2 0x00000002 134 135/* Use PowerPC architecture instructions. */ 136#define MASK_POWERPC 0x00000004 137 138/* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */ 139#define MASK_PPC_GPOPT 0x00000008 140 141/* Use PowerPC Graphics group optional instructions, e.g. fsel. */ 142#define MASK_PPC_GFXOPT 0x00000010 143 144/* Use PowerPC-64 architecture instructions. */ 145#define MASK_POWERPC64 0x00000020 146 147/* Use revised mnemonic names defined for PowerPC architecture. */ 148#define MASK_NEW_MNEMONICS 0x00000040 149 150/* Disable placing fp constants in the TOC; can be turned on when the 151 TOC overflows. */ 152#define MASK_NO_FP_IN_TOC 0x00000080 153 154/* Disable placing symbol+offset constants in the TOC; can be turned on when 155 the TOC overflows. */ 156#define MASK_NO_SUM_IN_TOC 0x00000100 157 158/* Output only one TOC entry per module. Normally linking fails if 159 there are more than 16K unique variables/constants in an executable. With 160 this option, linking fails only if there are more than 16K modules, or 161 if there are more than 16K unique variables/constant in a single module. 162 163 This is at the cost of having 2 extra loads and one extra store per 164 function, and one less allocable register. */ 165#define MASK_MINIMAL_TOC 0x00000200 166 167/* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The 168 chip is running in "64-bit mode", in which CR0 is set in dot 169 operations based on all 64 bits of the register, bdnz works on 64-bit 170 ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */ 171#define MASK_64BIT 0x00000400 172 173/* Disable use of FPRs. */ 174#define MASK_SOFT_FLOAT 0x00000800 175 176/* Enable load/store multiple, even on PowerPC */ 177#define MASK_MULTIPLE 0x00001000 178 179/* Use string instructions for block moves */ 180#define MASK_STRING 0x00002000 181 182/* Disable update form of load/store */ 183#define MASK_NO_UPDATE 0x00004000 184 185/* Disable fused multiply/add operations */ 186#define MASK_NO_FUSED_MADD 0x00008000 187 188/* Nonzero if we need to schedule the prolog and epilog. */ 189#define MASK_SCHED_PROLOG 0x00010000 190 191/* Use AltiVec instructions. */ 192#define MASK_ALTIVEC 0x00020000 193 194/* Return small structures in memory (as the AIX ABI requires). */ 195#define MASK_AIX_STRUCT_RET 0x00040000 196 197/* Use single field mfcr instruction. */ 198#define MASK_MFCRF 0x00080000 199 200/* The only remaining free bits are 0x00600000. linux64.h uses 201 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000. 202 0x80000000 is not available because target_flags is signed. */ 203 204#define TARGET_POWER (target_flags & MASK_POWER) 205#define TARGET_POWER2 (target_flags & MASK_POWER2) 206#define TARGET_POWERPC (target_flags & MASK_POWERPC) 207#define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT) 208#define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT) 209#define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS) 210#define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC) 211#define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC) 212#define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC) 213#define TARGET_64BIT (target_flags & MASK_64BIT) 214#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) 215#define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE) 216#define TARGET_STRING (target_flags & MASK_STRING) 217#define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE) 218#define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) 219#define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG) 220#define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC) 221#define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET) 222 223/* Define TARGET_MFCRF if the target assembler supports the optional 224 field operand for mfcr and the target processor supports the 225 instruction. */ 226 227#ifdef HAVE_AS_MFCRF 228#define TARGET_MFCRF (target_flags & MASK_MFCRF) 229#else 230#define TARGET_MFCRF 0 231#endif 232 233 234#define TARGET_32BIT (! TARGET_64BIT) 235#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 236#define TARGET_UPDATE (! TARGET_NO_UPDATE) 237#define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) 238 239/* Emit a dtp-relative reference to a TLS variable. */ 240 241#ifdef HAVE_AS_TLS 242#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 243 rs6000_output_dwarf_dtprel (FILE, SIZE, X) 244#endif 245 246#ifndef HAVE_AS_TLS 247#define HAVE_AS_TLS 0 248#endif 249 250#ifdef IN_LIBGCC2 251/* For libgcc2 we make sure this is a compile time constant */ 252#if defined (__64BIT__) || defined (__powerpc64__) 253#define TARGET_POWERPC64 1 254#else 255#define TARGET_POWERPC64 0 256#endif 257#else 258#define TARGET_POWERPC64 (target_flags & MASK_POWERPC64) 259#endif 260 261#define TARGET_XL_COMPAT 0 262 263/* Run-time compilation parameters selecting different hardware subsets. 264 265 Macro to define tables used to set the flags. 266 This is a list in braces of pairs in braces, 267 each pair being { "NAME", VALUE } 268 where VALUE is the bits to set or minus the bits to clear. 269 An empty string NAME is used to identify the default VALUE. */ 270 271#define TARGET_SWITCHES \ 272 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \ 273 N_("Use POWER instruction set")}, \ 274 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \ 275 | MASK_POWER2), \ 276 N_("Use POWER2 instruction set")}, \ 277 {"no-power2", - MASK_POWER2, \ 278 N_("Do not use POWER2 instruction set")}, \ 279 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \ 280 | MASK_STRING), \ 281 N_("Do not use POWER instruction set")}, \ 282 {"powerpc", MASK_POWERPC, \ 283 N_("Use PowerPC instruction set")}, \ 284 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \ 285 | MASK_PPC_GFXOPT | MASK_POWERPC64), \ 286 N_("Do not use PowerPC instruction set")}, \ 287 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ 288 N_("Use PowerPC General Purpose group optional instructions")},\ 289 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ 290 N_("Do not use PowerPC General Purpose group optional instructions")},\ 291 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ 292 N_("Use PowerPC Graphics group optional instructions")},\ 293 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ 294 N_("Do not use PowerPC Graphics group optional instructions")},\ 295 {"powerpc64", MASK_POWERPC64, \ 296 N_("Use PowerPC-64 instruction set")}, \ 297 {"no-powerpc64", - MASK_POWERPC64, \ 298 N_("Do not use PowerPC-64 instruction set")}, \ 299 {"altivec", MASK_ALTIVEC , \ 300 N_("Use AltiVec instructions")}, \ 301 {"no-altivec", - MASK_ALTIVEC , \ 302 N_("Do not use AltiVec instructions")}, \ 303 {"new-mnemonics", MASK_NEW_MNEMONICS, \ 304 N_("Use new mnemonics for PowerPC architecture")},\ 305 {"old-mnemonics", -MASK_NEW_MNEMONICS, \ 306 N_("Use old mnemonics for PowerPC architecture")},\ 307 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \ 308 | MASK_MINIMAL_TOC), \ 309 N_("Put everything in the regular TOC")}, \ 310 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \ 311 N_("Place floating point constants in TOC")}, \ 312 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ 313 N_("Do not place floating point constants in TOC")},\ 314 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ 315 N_("Place symbol+offset constants in TOC")}, \ 316 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ 317 N_("Do not place symbol+offset constants in TOC")},\ 318 {"minimal-toc", MASK_MINIMAL_TOC, \ 319 "Use only one TOC entry per procedure"}, \ 320 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ 321 ""}, \ 322 {"no-minimal-toc", - MASK_MINIMAL_TOC, \ 323 N_("Place variable addresses in the regular TOC")},\ 324 {"hard-float", - MASK_SOFT_FLOAT, \ 325 N_("Use hardware floating point")}, \ 326 {"soft-float", MASK_SOFT_FLOAT, \ 327 N_("Do not use hardware floating point")}, \ 328 {"multiple", MASK_MULTIPLE, \ 329 N_("Generate load/store multiple instructions")}, \ 330 {"no-multiple", - MASK_MULTIPLE, \ 331 N_("Do not generate load/store multiple instructions")},\ 332 {"string", MASK_STRING, \ 333 N_("Generate string instructions for block moves")},\ 334 {"no-string", - MASK_STRING, \ 335 N_("Do not generate string instructions for block moves")},\ 336 {"update", - MASK_NO_UPDATE, \ 337 N_("Generate load/store with update instructions")},\ 338 {"no-update", MASK_NO_UPDATE, \ 339 N_("Do not generate load/store with update instructions")},\ 340 {"fused-madd", - MASK_NO_FUSED_MADD, \ 341 N_("Generate fused multiply/add instructions")},\ 342 {"no-fused-madd", MASK_NO_FUSED_MADD, \ 343 N_("Do not generate fused multiply/add instructions")},\ 344 {"sched-prolog", MASK_SCHED_PROLOG, \ 345 ""}, \ 346 {"no-sched-prolog", -MASK_SCHED_PROLOG, \ 347 N_("Do not schedule the start and end of the procedure")},\ 348 {"sched-epilog", MASK_SCHED_PROLOG, \ 349 ""}, \ 350 {"no-sched-epilog", -MASK_SCHED_PROLOG, \ 351 ""}, \ 352 {"aix-struct-return", MASK_AIX_STRUCT_RET, \ 353 N_("Return all structures in memory (AIX default)")},\ 354 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \ 355 N_("Return small structures in registers (SVR4 default)")},\ 356 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \ 357 ""}, \ 358 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \ 359 ""}, \ 360 {"mfcrf", MASK_MFCRF, \ 361 N_("Generate single field mfcr instruction")}, \ 362 {"no-mfcrf", - MASK_MFCRF, \ 363 N_("Do not generate single field mfcr instruction")},\ 364 SUBTARGET_SWITCHES \ 365 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ 366 ""}} 367 368#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) 369 370/* This is meant to be redefined in the host dependent files */ 371#define SUBTARGET_SWITCHES 372 373/* Processor type. Order must match cpu attribute in MD file. */ 374enum processor_type 375 { 376 PROCESSOR_RIOS1, 377 PROCESSOR_RIOS2, 378 PROCESSOR_RS64A, 379 PROCESSOR_MPCCORE, 380 PROCESSOR_PPC403, 381 PROCESSOR_PPC405, 382 PROCESSOR_PPC440, 383 PROCESSOR_PPC601, 384 PROCESSOR_PPC603, 385 PROCESSOR_PPC604, 386 PROCESSOR_PPC604e, 387 PROCESSOR_PPC620, 388 PROCESSOR_PPC630, 389 PROCESSOR_PPC750, 390 PROCESSOR_PPC7400, 391 PROCESSOR_PPC7450, 392 PROCESSOR_PPC8540, 393 PROCESSOR_POWER4, 394 PROCESSOR_POWER5 395}; 396 397extern enum processor_type rs6000_cpu; 398 399/* Recast the processor type to the cpu attribute. */ 400#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 401 402/* Define generic processor types based upon current deployment. */ 403#define PROCESSOR_COMMON PROCESSOR_PPC601 404#define PROCESSOR_POWER PROCESSOR_RIOS1 405#define PROCESSOR_POWERPC PROCESSOR_PPC604 406#define PROCESSOR_POWERPC64 PROCESSOR_RS64A 407 408/* Define the default processor. This is overridden by other tm.h files. */ 409#define PROCESSOR_DEFAULT PROCESSOR_RIOS1 410#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 411 412/* Specify the dialect of assembler to use. New mnemonics is dialect one 413 and the old mnemonics are dialect zero. */ 414#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) 415 416/* Types of costly dependences. */ 417enum rs6000_dependence_cost 418 { 419 max_dep_latency = 1000, 420 no_dep_costly, 421 all_deps_costly, 422 true_store_to_load_dep_costly, 423 store_to_load_dep_costly 424 }; 425 426/* Types of nop insertion schemes in sched target hook sched_finish. */ 427enum rs6000_nop_insertion 428 { 429 sched_finish_regroup_exact = 1000, 430 sched_finish_pad_groups, 431 sched_finish_none 432 }; 433 434/* Dispatch group termination caused by an insn. */ 435enum group_termination 436 { 437 current_group, 438 previous_group 439 }; 440 441/* This is meant to be overridden in target specific files. */ 442#define SUBTARGET_OPTIONS 443 444#define TARGET_OPTIONS \ 445{ \ 446 {"cpu=", &rs6000_select[1].string, \ 447 N_("Use features of and schedule code for given CPU"), 0}, \ 448 {"tune=", &rs6000_select[2].string, \ 449 N_("Schedule code for given CPU"), 0}, \ 450 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \ 451 {"traceback=", &rs6000_traceback_name, \ 452 N_("Select full, part, or no traceback table"), 0}, \ 453 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \ 454 {"long-double-", &rs6000_long_double_size_string, \ 455 N_("Specify size of long double (64 or 128 bits)"), 0}, \ 456 {"isel=", &rs6000_isel_string, \ 457 N_("Specify yes/no if isel instructions should be generated"), 0}, \ 458 {"spe=", &rs6000_spe_string, \ 459 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\ 460 {"float-gprs=", &rs6000_float_gprs_string, \ 461 N_("Specify yes/no if using floating point in the GPRs"), 0}, \ 462 {"vrsave=", &rs6000_altivec_vrsave_string, \ 463 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \ 464 {"longcall", &rs6000_longcall_switch, \ 465 N_("Avoid all range limits on call instructions"), 0}, \ 466 {"no-longcall", &rs6000_longcall_switch, "", 0}, \ 467 {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \ 468 N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \ 469 {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \ 470 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \ 471 N_("Determine which dependences between insns are considered costly"), 0}, \ 472 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \ 473 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \ 474 {"align-", &rs6000_alignment_string, \ 475 N_("Specify alignment of structure fields default/natural"), 0}, \ 476 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \ 477 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \ 478 SUBTARGET_OPTIONS \ 479} 480 481/* Support for a compile-time default CPU, et cetera. The rules are: 482 --with-cpu is ignored if -mcpu is specified. 483 --with-tune is ignored if -mtune is specified. 484 --with-float is ignored if -mhard-float or -msoft-float are 485 specified. */ 486#define OPTION_DEFAULT_SPECS \ 487 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 488 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 489 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } 490 491/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ 492struct rs6000_cpu_select 493{ 494 const char *string; 495 const char *name; 496 int set_tune_p; 497 int set_arch_p; 498}; 499 500extern struct rs6000_cpu_select rs6000_select[]; 501 502/* Debug support */ 503extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ 504extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */ 505extern int rs6000_debug_stack; /* debug stack applications */ 506extern int rs6000_debug_arg; /* debug argument handling */ 507 508#define TARGET_DEBUG_STACK rs6000_debug_stack 509#define TARGET_DEBUG_ARG rs6000_debug_arg 510 511extern const char *rs6000_traceback_name; /* Type of traceback table. */ 512 513/* These are separate from target_flags because we've run out of bits 514 there. */ 515extern const char *rs6000_long_double_size_string; 516extern int rs6000_long_double_type_size; 517extern int rs6000_altivec_abi; 518extern int rs6000_spe_abi; 519extern int rs6000_isel; 520extern int rs6000_spe; 521extern int rs6000_float_gprs; 522extern const char *rs6000_float_gprs_string; 523extern const char *rs6000_isel_string; 524extern const char *rs6000_spe_string; 525extern const char *rs6000_altivec_vrsave_string; 526extern int rs6000_altivec_vrsave; 527extern const char *rs6000_longcall_switch; 528extern int rs6000_default_long_calls; 529extern const char* rs6000_alignment_string; 530extern int rs6000_alignment_flags; 531extern const char *rs6000_sched_restricted_insns_priority_str; 532extern int rs6000_sched_restricted_insns_priority; 533extern const char *rs6000_sched_costly_dep_str; 534extern enum rs6000_dependence_cost rs6000_sched_costly_dep; 535extern const char *rs6000_sched_insert_nops_str; 536extern enum rs6000_nop_insertion rs6000_sched_insert_nops; 537 538extern int rs6000_warn_altivec_long; 539extern const char *rs6000_warn_altivec_long_switch; 540 541/* Alignment options for fields in structures for sub-targets following 542 AIX-like ABI. 543 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 544 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 545 546 Override the macro definitions when compiling libobjc to avoid undefined 547 reference to rs6000_alignment_flags due to library's use of GCC alignment 548 macros which use the macros below. */ 549 550#ifndef IN_TARGET_LIBS 551#define MASK_ALIGN_POWER 0x00000000 552#define MASK_ALIGN_NATURAL 0x00000001 553#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 554#else 555#define TARGET_ALIGN_NATURAL 0 556#endif 557 558#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 559#define TARGET_ALTIVEC_ABI rs6000_altivec_abi 560#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave 561 562#define TARGET_SPE_ABI 0 563#define TARGET_SPE 0 564#define TARGET_E500 0 565#define TARGET_ISEL 0 566#define TARGET_FPRS 1 567 568/* Sometimes certain combinations of command options do not make sense 569 on a particular target machine. You can define a macro 570 `OVERRIDE_OPTIONS' to take account of this. This macro, if 571 defined, is executed once just after all the command options have 572 been parsed. 573 574 Do not use this macro to turn on various extra optimizations for 575 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. 576 577 On the RS/6000 this is used to define the target cpu type. */ 578 579#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) 580 581/* Define this to change the optimizations performed by default. */ 582#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) 583 584/* Show we can debug even without a frame pointer. */ 585#define CAN_DEBUG_WITHOUT_FP 586 587/* Target pragma. */ 588#define REGISTER_TARGET_PRAGMAS() do { \ 589 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 590} while (0) 591 592/* Target #defines. */ 593#define TARGET_CPU_CPP_BUILTINS() \ 594 rs6000_cpu_cpp_builtins (pfile) 595 596/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 597 we're compiling for. Some configurations may need to override it. */ 598#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 599 do \ 600 { \ 601 if (BYTES_BIG_ENDIAN) \ 602 { \ 603 builtin_define ("__BIG_ENDIAN__"); \ 604 builtin_define ("_BIG_ENDIAN"); \ 605 builtin_assert ("machine=bigendian"); \ 606 } \ 607 else \ 608 { \ 609 builtin_define ("__LITTLE_ENDIAN__"); \ 610 builtin_define ("_LITTLE_ENDIAN"); \ 611 builtin_assert ("machine=littleendian"); \ 612 } \ 613 } \ 614 while (0) 615 616/* Target machine storage layout. */ 617 618/* Define this macro if it is advisable to hold scalars in registers 619 in a wider mode than that declared by the program. In such cases, 620 the value is constrained to be within the bounds of the declared 621 type, but kept valid in the wider mode. The signedness of the 622 extension may differ from that of the type. */ 623 624#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 625 if (GET_MODE_CLASS (MODE) == MODE_INT \ 626 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 627 (MODE) = TARGET_32BIT ? SImode : DImode; 628 629/* Define this if most significant bit is lowest numbered 630 in instructions that operate on numbered bit-fields. */ 631/* That is true on RS/6000. */ 632#define BITS_BIG_ENDIAN 1 633 634/* Define this if most significant byte of a word is the lowest numbered. */ 635/* That is true on RS/6000. */ 636#define BYTES_BIG_ENDIAN 1 637 638/* Define this if most significant word of a multiword number is lowest 639 numbered. 640 641 For RS/6000 we can decide arbitrarily since there are no machine 642 instructions for them. Might as well be consistent with bits and bytes. */ 643#define WORDS_BIG_ENDIAN 1 644 645#define MAX_BITS_PER_WORD 64 646 647/* Width of a word, in units (bytes). */ 648#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 649#ifdef IN_LIBGCC2 650#define MIN_UNITS_PER_WORD UNITS_PER_WORD 651#else 652#define MIN_UNITS_PER_WORD 4 653#endif 654#define UNITS_PER_FP_WORD 8 655#define UNITS_PER_ALTIVEC_WORD 16 656#define UNITS_PER_SPE_WORD 8 657 658/* Type used for ptrdiff_t, as a string used in a declaration. */ 659#define PTRDIFF_TYPE "int" 660 661/* Type used for size_t, as a string used in a declaration. */ 662#define SIZE_TYPE "long unsigned int" 663 664/* Type used for wchar_t, as a string used in a declaration. */ 665#define WCHAR_TYPE "short unsigned int" 666 667/* Width of wchar_t in bits. */ 668#define WCHAR_TYPE_SIZE 16 669 670/* A C expression for the size in bits of the type `short' on the 671 target machine. If you don't define this, the default is half a 672 word. (If this would be less than one storage unit, it is 673 rounded up to one unit.) */ 674#define SHORT_TYPE_SIZE 16 675 676/* A C expression for the size in bits of the type `int' on the 677 target machine. If you don't define this, the default is one 678 word. */ 679#define INT_TYPE_SIZE 32 680 681/* A C expression for the size in bits of the type `long' on the 682 target machine. If you don't define this, the default is one 683 word. */ 684#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 685#define MAX_LONG_TYPE_SIZE 64 686 687/* A C expression for the size in bits of the type `long long' on the 688 target machine. If you don't define this, the default is two 689 words. */ 690#define LONG_LONG_TYPE_SIZE 64 691 692/* A C expression for the size in bits of the type `float' on the 693 target machine. If you don't define this, the default is one 694 word. */ 695#define FLOAT_TYPE_SIZE 32 696 697/* A C expression for the size in bits of the type `double' on the 698 target machine. If you don't define this, the default is two 699 words. */ 700#define DOUBLE_TYPE_SIZE 64 701 702/* A C expression for the size in bits of the type `long double' on 703 the target machine. If you don't define this, the default is two 704 words. */ 705#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 706 707/* Constant which presents upper bound of the above value. */ 708#define MAX_LONG_DOUBLE_TYPE_SIZE 128 709 710/* Define this to set long double type size to use in libgcc2.c, which can 711 not depend on target_flags. */ 712#ifdef __LONG_DOUBLE_128__ 713#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 714#else 715#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 716#endif 717 718/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 719#define WIDEST_HARDWARE_FP_SIZE 64 720 721/* Width in bits of a pointer. 722 See also the macro `Pmode' defined below. */ 723#define POINTER_SIZE (TARGET_32BIT ? 32 : 64) 724 725/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 726#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 727 728/* Boundary (in *bits*) on which stack pointer should be aligned. */ 729#define STACK_BOUNDARY \ 730 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128) 731 732/* Allocation boundary (in *bits*) for the code of a function. */ 733#define FUNCTION_BOUNDARY 32 734 735/* No data type wants to be aligned rounder than this. */ 736#define BIGGEST_ALIGNMENT 128 737 738/* A C expression to compute the alignment for a variables in the 739 local store. TYPE is the data type, and ALIGN is the alignment 740 that the object would ordinarily have. */ 741#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 742 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ 743 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) 744 745/* Alignment of field after `int : 0' in a structure. */ 746#define EMPTY_FIELD_BOUNDARY 32 747 748/* Every structure's size must be a multiple of this. */ 749#define STRUCTURE_SIZE_BOUNDARY 8 750 751/* Return 1 if a structure or array containing FIELD should be 752 accessed using `BLKMODE'. 753 754 For the SPE, simd types are V2SI, and gcc can be tempted to put the 755 entire thing in a DI and use subregs to access the internals. 756 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the 757 back-end. Because a single GPR can hold a V2SI, but not a DI, the 758 best thing to do is set structs to BLKmode and avoid Severe Tire 759 Damage. */ 760#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 761 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) 762 763/* A bit-field declared as `int' forces `int' alignment for the struct. */ 764#define PCC_BITFIELD_TYPE_MATTERS 1 765 766/* Make strings word-aligned so strcpy from constants will be faster. 767 Make vector constants quadword aligned. */ 768#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 769 (TREE_CODE (EXP) == STRING_CST \ 770 && (ALIGN) < BITS_PER_WORD \ 771 ? BITS_PER_WORD \ 772 : (ALIGN)) 773 774/* Make arrays of chars word-aligned for the same reasons. 775 Align vectors to 128 bits. */ 776#define DATA_ALIGNMENT(TYPE, ALIGN) \ 777 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ 778 : TREE_CODE (TYPE) == ARRAY_TYPE \ 779 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 780 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 781 782/* Nonzero if move instructions will actually fail to work 783 when given unaligned data. */ 784#define STRICT_ALIGNMENT 0 785 786/* Define this macro to be the value 1 if unaligned accesses have a cost 787 many times greater than aligned accesses, for example if they are 788 emulated in a trap handler. */ 789#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 790 (STRICT_ALIGNMENT \ 791 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 792 || (MODE) == DImode) \ 793 && (ALIGN) < 32)) 794 795/* Standard register usage. */ 796 797/* Number of actual hardware registers. 798 The hardware registers are assigned numbers for the compiler 799 from 0 to just below FIRST_PSEUDO_REGISTER. 800 All registers that the compiler knows about must be given numbers, 801 even those that are not normally considered general registers. 802 803 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 804 an MQ register, a count register, a link register, and 8 condition 805 register fields, which we view here as separate registers. AltiVec 806 adds 32 vector registers and a VRsave register. 807 808 In addition, the difference between the frame and argument pointers is 809 a function of the number of registers saved, so we need to have a 810 register for AP that will later be eliminated in favor of SP or FP. 811 This is a normal register, but it is fixed. 812 813 We also create a pseudo register for float/int conversions, that will 814 really represent the memory location used. It is represented here as 815 a register, in order to work around problems in allocating stack storage 816 in inline functions. */ 817 818#define FIRST_PSEUDO_REGISTER 113 819 820/* This must be included for pre gcc 3.0 glibc compatibility. */ 821#define PRE_GCC3_DWARF_FRAME_REGISTERS 77 822 823/* Add 32 dwarf columns for synthetic SPE registers. */ 824#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32) 825 826/* The SPE has an additional 32 synthetic registers, with DWARF debug 827 info numbering for these registers starting at 1200. While eh_frame 828 register numbering need not be the same as the debug info numbering, 829 we choose to number these regs for eh_frame at 1200 too. This allows 830 future versions of the rs6000 backend to add hard registers and 831 continue to use the gcc hard register numbering for eh_frame. If the 832 extra SPE registers in eh_frame were numbered starting from the 833 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER 834 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to 835 avoid invalidating older SPE eh_frame info. 836 837 We must map them here to avoid huge unwinder tables mostly consisting 838 of unused space. */ 839#define DWARF_REG_TO_UNWIND_COLUMN(r) \ 840 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r)) 841 842/* Use gcc hard register numbering for eh_frame. */ 843#define DWARF_FRAME_REGNUM(REGNO) (REGNO) 844 845/* 1 for registers that have pervasive standard uses 846 and are not available for the register allocator. 847 848 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 849 as a local register; for all other OS's r2 is the TOC pointer. 850 851 cr5 is not supposed to be used. 852 853 On System V implementations, r13 is fixed and not available for use. */ 854 855#define FIXED_REGISTERS \ 856 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 857 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 860 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 861 /* AltiVec registers. */ \ 862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 864 1, 1 \ 865 , 1, 1 \ 866} 867 868/* 1 for registers not available across function calls. 869 These must include the FIXED_REGISTERS and also any 870 registers that can be used without being saved. 871 The latter must include the registers where values are returned 872 and the register where structure-value addresses are passed. 873 Aside from that, you can include as many other registers as you like. */ 874 875#define CALL_USED_REGISTERS \ 876 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 877 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 878 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 880 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 881 /* AltiVec registers. */ \ 882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 884 1, 1 \ 885 , 1, 1 \ 886} 887 888/* Like `CALL_USED_REGISTERS' except this macro doesn't require that 889 the entire set of `FIXED_REGISTERS' be included. 890 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 891 This macro is optional. If not specified, it defaults to the value 892 of `CALL_USED_REGISTERS'. */ 893 894#define CALL_REALLY_USED_REGISTERS \ 895 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 897 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 899 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 900 /* AltiVec registers. */ \ 901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 903 0, 0 \ 904 , 0, 0 \ 905} 906 907#define MQ_REGNO 64 908#define CR0_REGNO 68 909#define CR1_REGNO 69 910#define CR2_REGNO 70 911#define CR3_REGNO 71 912#define CR4_REGNO 72 913#define MAX_CR_REGNO 75 914#define XER_REGNO 76 915#define FIRST_ALTIVEC_REGNO 77 916#define LAST_ALTIVEC_REGNO 108 917#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 918#define VRSAVE_REGNO 109 919#define VSCR_REGNO 110 920#define SPE_ACC_REGNO 111 921#define SPEFSCR_REGNO 112 922 923/* List the order in which to allocate registers. Each register must be 924 listed once, even those in FIXED_REGISTERS. 925 926 We allocate in the following order: 927 fp0 (not saved or used for anything) 928 fp13 - fp2 (not saved; incoming fp arg registers) 929 fp1 (not saved; return value) 930 fp31 - fp14 (saved; order given to save least number) 931 cr7, cr6 (not saved or special) 932 cr1 (not saved, but used for FP operations) 933 cr0 (not saved, but used for arithmetic operations) 934 cr4, cr3, cr2 (saved) 935 r0 (not saved; cannot be base reg) 936 r9 (not saved; best for TImode) 937 r11, r10, r8-r4 (not saved; highest used first to make less conflict) 938 r3 (not saved; return value register) 939 r31 - r13 (saved; order given to save least number) 940 r12 (not saved; if used for DImode or DFmode would use r13) 941 mq (not saved; best to use it if we can) 942 ctr (not saved; when we have the choice ctr is better) 943 lr (saved) 944 cr5, r1, r2, ap, xer, vrsave, vscr (fixed) 945 spe_acc, spefscr (fixed) 946 947 AltiVec registers: 948 v0 - v1 (not saved or used for anything) 949 v13 - v3 (not saved; incoming vector arg registers) 950 v2 (not saved; incoming vector arg reg; return value) 951 v19 - v14 (not saved or used for anything) 952 v31 - v20 (saved; order given to save least number) 953*/ 954 955#if FIXED_R2 == 1 956#define MAYBE_R2_AVAILABLE 957#define MAYBE_R2_FIXED 2, 958#else 959#define MAYBE_R2_AVAILABLE 2, 960#define MAYBE_R2_FIXED 961#endif 962 963#define REG_ALLOC_ORDER \ 964 {32, \ 965 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 966 33, \ 967 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 968 50, 49, 48, 47, 46, \ 969 75, 74, 69, 68, 72, 71, 70, \ 970 0, MAYBE_R2_AVAILABLE \ 971 9, 11, 10, 8, 7, 6, 5, 4, \ 972 3, \ 973 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 974 18, 17, 16, 15, 14, 13, 12, \ 975 64, 66, 65, \ 976 73, 1, MAYBE_R2_FIXED 67, 76, \ 977 /* AltiVec registers. */ \ 978 77, 78, \ 979 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 980 79, \ 981 96, 95, 94, 93, 92, 91, \ 982 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \ 983 97, 109, 110 \ 984 , 111, 112 \ 985} 986 987/* True if register is floating-point. */ 988#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 989 990/* True if register is a condition register. */ 991#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) 992 993/* True if register is a condition register, but not cr0. */ 994#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) 995 996/* True if register is an integer register. */ 997#define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) 998 999/* SPE SIMD registers are just the GPRs. */ 1000#define SPE_SIMD_REGNO_P(N) ((N) <= 31) 1001 1002/* True if register is the XER register. */ 1003#define XER_REGNO_P(N) ((N) == XER_REGNO) 1004 1005/* True if register is an AltiVec register. */ 1006#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1007 1008/* Return number of consecutive hard regs needed starting at reg REGNO 1009 to hold something of mode MODE. 1010 This is ordinarily the length in words of a value of mode MODE 1011 but can be less for certain modes in special long registers. 1012 1013 For the SPE, GPRs are 64 bits but only 32 bits are visible in 1014 scalar instructions. The upper 32 bits are only available to the 1015 SIMD instructions. 1016 1017 POWER and PowerPC GPRs hold 32 bits worth; 1018 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ 1019 1020#define HARD_REGNO_NREGS(REGNO, MODE) \ 1021 (FP_REGNO_P (REGNO) \ 1022 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 1023 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ 1024 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \ 1025 : ALTIVEC_REGNO_P (REGNO) \ 1026 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \ 1027 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1028 1029#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1030 ((TARGET_32BIT && TARGET_POWERPC64 \ 1031 && (MODE == DImode || MODE == DFmode) \ 1032 && INT_REGNO_P (REGNO)) ? 1 : 0) 1033 1034#define ALTIVEC_VECTOR_MODE(MODE) \ 1035 ((MODE) == V16QImode \ 1036 || (MODE) == V8HImode \ 1037 || (MODE) == V4SFmode \ 1038 || (MODE) == V4SImode) 1039 1040#define SPE_VECTOR_MODE(MODE) \ 1041 ((MODE) == V4HImode \ 1042 || (MODE) == V2SFmode \ 1043 || (MODE) == V1DImode \ 1044 || (MODE) == V2SImode) 1045 1046/* Define this macro to be nonzero if the port is prepared to handle 1047 insns involving vector mode MODE. At the very least, it must have 1048 move patterns for this mode. */ 1049 1050#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1051 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ 1052 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) 1053 1054/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1055 For POWER and PowerPC, the GPRs can hold any mode, but values bigger 1056 than one register cannot go past R31. The float 1057 registers only can hold floating modes and DImode, and CR register only 1058 can hold CC modes. We cannot put TImode anywhere except general 1059 register and it must be able to fit within the register set. */ 1060 1061#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1062 (INT_REGNO_P (REGNO) ? \ 1063 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \ 1064 : FP_REGNO_P (REGNO) ? \ 1065 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1066 && FP_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1)) \ 1067 || (GET_MODE_CLASS (MODE) == MODE_INT \ 1068 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ 1069 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \ 1070 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \ 1071 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ 1072 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \ 1073 : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) 1074 1075/* Value is 1 if it is a good idea to tie two pseudo registers 1076 when one has mode MODE1 and one has mode MODE2. 1077 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1078 for any hard reg, then this must be 0 for correct output. */ 1079#define MODES_TIEABLE_P(MODE1, MODE2) \ 1080 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 1081 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 1082 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 1083 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 1084 : GET_MODE_CLASS (MODE1) == MODE_CC \ 1085 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 1086 : GET_MODE_CLASS (MODE2) == MODE_CC \ 1087 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 1088 : SPE_VECTOR_MODE (MODE1) \ 1089 ? SPE_VECTOR_MODE (MODE2) \ 1090 : SPE_VECTOR_MODE (MODE2) \ 1091 ? SPE_VECTOR_MODE (MODE1) \ 1092 : ALTIVEC_VECTOR_MODE (MODE1) \ 1093 ? ALTIVEC_VECTOR_MODE (MODE2) \ 1094 : ALTIVEC_VECTOR_MODE (MODE2) \ 1095 ? ALTIVEC_VECTOR_MODE (MODE1) \ 1096 : 1) 1097 1098/* Post-reload, we can't use any new AltiVec registers, as we already 1099 emitted the vrsave mask. */ 1100 1101#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1102 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST]) 1103 1104/* A C expression returning the cost of moving data from a register of class 1105 CLASS1 to one of CLASS2. */ 1106 1107#define REGISTER_MOVE_COST rs6000_register_move_cost 1108 1109/* A C expressions returning the cost of moving data of MODE from a register to 1110 or from memory. */ 1111 1112#define MEMORY_MOVE_COST rs6000_memory_move_cost 1113 1114/* Specify the cost of a branch insn; roughly the number of extra insns that 1115 should be added to avoid a branch. 1116 1117 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1118 unscheduled conditional branch. */ 1119 1120#define BRANCH_COST 3 1121 1122/* Override BRANCH_COST heuristic which empirically produces worse 1123 performance for fold_range_test(). */ 1124 1125#define RANGE_TEST_NON_SHORT_CIRCUIT 0 1126 1127/* A fixed register used at prologue and epilogue generation to fix 1128 addressing modes. The SPE needs heavy addressing fixes at the last 1129 minute, and it's best to save a register for it. 1130 1131 AltiVec also needs fixes, but we've gotten around using r11, which 1132 is actually wrong because when use_backchain_to_restore_sp is true, 1133 we end up clobbering r11. 1134 1135 The AltiVec case needs to be fixed. Dunno if we should break ABI 1136 compatibility and reserve a register for it as well.. */ 1137 1138#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) 1139 1140/* Define this macro to change register usage conditional on target flags. 1141 Set MQ register fixed (already call_used) if not POWER architecture 1142 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. 1143 64-bit AIX reserves GPR13 for thread-private data. 1144 Conditionally disable FPRs. */ 1145 1146#define CONDITIONAL_REGISTER_USAGE \ 1147{ \ 1148 int i; \ 1149 if (! TARGET_POWER) \ 1150 fixed_regs[64] = 1; \ 1151 if (TARGET_64BIT) \ 1152 fixed_regs[13] = call_used_regs[13] \ 1153 = call_really_used_regs[13] = 1; \ 1154 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \ 1155 for (i = 32; i < 64; i++) \ 1156 fixed_regs[i] = call_used_regs[i] \ 1157 = call_really_used_regs[i] = 1; \ 1158 if (DEFAULT_ABI == ABI_V4 \ 1159 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ 1160 && flag_pic == 2) \ 1161 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1162 if (DEFAULT_ABI == ABI_V4 \ 1163 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ 1164 && flag_pic == 1) \ 1165 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1166 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1167 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1168 if (DEFAULT_ABI == ABI_DARWIN \ 1169 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 1170 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1171 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1172 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1173 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1174 if (TARGET_TOC && TARGET_MINIMAL_TOC) \ 1175 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1176 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1177 if (TARGET_ALTIVEC) \ 1178 global_regs[VSCR_REGNO] = 1; \ 1179 if (TARGET_SPE) \ 1180 { \ 1181 global_regs[SPEFSCR_REGNO] = 1; \ 1182 fixed_regs[FIXED_SCRATCH] \ 1183 = call_used_regs[FIXED_SCRATCH] \ 1184 = call_really_used_regs[FIXED_SCRATCH] = 1; \ 1185 } \ 1186 if (! TARGET_ALTIVEC) \ 1187 { \ 1188 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ 1189 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ 1190 call_really_used_regs[VRSAVE_REGNO] = 1; \ 1191 } \ 1192 if (TARGET_ALTIVEC_ABI) \ 1193 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \ 1194 call_used_regs[i] = call_really_used_regs[i] = 1; \ 1195} 1196 1197/* Specify the registers used for certain standard purposes. 1198 The values of these macros are register numbers. */ 1199 1200/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1201/* #define PC_REGNUM */ 1202 1203/* Register to use for pushing function arguments. */ 1204#define STACK_POINTER_REGNUM 1 1205 1206/* Base register for access to local variables of the function. */ 1207#define FRAME_POINTER_REGNUM 31 1208 1209/* Value should be nonzero if functions must have frame pointers. 1210 Zero means the frame pointer need not be set up (and parms 1211 may be accessed via the stack pointer) in functions that seem suitable. 1212 This is computed in `reload', in reload1.c. */ 1213#define FRAME_POINTER_REQUIRED 0 1214 1215/* Base register for access to arguments of the function. */ 1216#define ARG_POINTER_REGNUM 67 1217 1218/* Place to put static chain when calling a function that requires it. */ 1219#define STATIC_CHAIN_REGNUM 11 1220 1221/* Link register number. */ 1222#define LINK_REGISTER_REGNUM 65 1223 1224/* Count register number. */ 1225#define COUNT_REGISTER_REGNUM 66 1226 1227/* Define the classes of registers for register constraints in the 1228 machine description. Also define ranges of constants. 1229 1230 One of the classes must always be named ALL_REGS and include all hard regs. 1231 If there is more than one class, another class must be named NO_REGS 1232 and contain no registers. 1233 1234 The name GENERAL_REGS must be the name of a class (or an alias for 1235 another name such as ALL_REGS). This is the class of registers 1236 that is allowed by "g" or "r" in a register constraint. 1237 Also, registers outside this class are allocated only when 1238 instructions express preferences for them. 1239 1240 The classes must be numbered in nondecreasing order; that is, 1241 a larger-numbered class must never be contained completely 1242 in a smaller-numbered class. 1243 1244 For any two classes, it is very desirable that there be another 1245 class that represents their union. */ 1246 1247/* The RS/6000 has three types of registers, fixed-point, floating-point, 1248 and condition registers, plus three special registers, MQ, CTR, and the 1249 link register. AltiVec adds a vector register class. 1250 1251 However, r0 is special in that it cannot be used as a base register. 1252 So make a class for registers valid as base registers. 1253 1254 Also, cr0 is the only condition code register that can be used in 1255 arithmetic insns, so make a separate class for it. */ 1256 1257enum reg_class 1258{ 1259 NO_REGS, 1260 BASE_REGS, 1261 GENERAL_REGS, 1262 FLOAT_REGS, 1263 ALTIVEC_REGS, 1264 VRSAVE_REGS, 1265 VSCR_REGS, 1266 SPE_ACC_REGS, 1267 SPEFSCR_REGS, 1268 NON_SPECIAL_REGS, 1269 MQ_REGS, 1270 LINK_REGS, 1271 CTR_REGS, 1272 LINK_OR_CTR_REGS, 1273 SPECIAL_REGS, 1274 SPEC_OR_GEN_REGS, 1275 CR0_REGS, 1276 CR_REGS, 1277 NON_FLOAT_REGS, 1278 XER_REGS, 1279 ALL_REGS, 1280 LIM_REG_CLASSES 1281}; 1282 1283#define N_REG_CLASSES (int) LIM_REG_CLASSES 1284 1285/* Give names of register classes as strings for dump file. */ 1286 1287#define REG_CLASS_NAMES \ 1288{ \ 1289 "NO_REGS", \ 1290 "BASE_REGS", \ 1291 "GENERAL_REGS", \ 1292 "FLOAT_REGS", \ 1293 "ALTIVEC_REGS", \ 1294 "VRSAVE_REGS", \ 1295 "VSCR_REGS", \ 1296 "SPE_ACC_REGS", \ 1297 "SPEFSCR_REGS", \ 1298 "NON_SPECIAL_REGS", \ 1299 "MQ_REGS", \ 1300 "LINK_REGS", \ 1301 "CTR_REGS", \ 1302 "LINK_OR_CTR_REGS", \ 1303 "SPECIAL_REGS", \ 1304 "SPEC_OR_GEN_REGS", \ 1305 "CR0_REGS", \ 1306 "CR_REGS", \ 1307 "NON_FLOAT_REGS", \ 1308 "XER_REGS", \ 1309 "ALL_REGS" \ 1310} 1311 1312/* Define which registers fit in which classes. 1313 This is an initializer for a vector of HARD_REG_SET 1314 of length N_REG_CLASSES. */ 1315 1316#define REG_CLASS_CONTENTS \ 1317{ \ 1318 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1319 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \ 1320 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \ 1321 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1322 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1323 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1324 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1325 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1326 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1327 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ 1328 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ 1329 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1330 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1331 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1332 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ 1333 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ 1334 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1335 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1336 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ 1337 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ 1338 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \ 1339} 1340 1341/* The same information, inverted: 1342 Return the class number of the smallest class containing 1343 reg number REGNO. This could be a conditional expression 1344 or could index an array. */ 1345 1346#define REGNO_REG_CLASS(REGNO) \ 1347 ((REGNO) == 0 ? GENERAL_REGS \ 1348 : (REGNO) < 32 ? BASE_REGS \ 1349 : FP_REGNO_P (REGNO) ? FLOAT_REGS \ 1350 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ 1351 : (REGNO) == CR0_REGNO ? CR0_REGS \ 1352 : CR_REGNO_P (REGNO) ? CR_REGS \ 1353 : (REGNO) == MQ_REGNO ? MQ_REGS \ 1354 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ 1355 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ 1356 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ 1357 : (REGNO) == XER_REGNO ? XER_REGS \ 1358 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ 1359 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ 1360 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ 1361 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ 1362 : NO_REGS) 1363 1364/* The class value for index registers, and the one for base regs. */ 1365#define INDEX_REG_CLASS GENERAL_REGS 1366#define BASE_REG_CLASS BASE_REGS 1367 1368/* Get reg_class from a letter such as appears in the machine description. */ 1369 1370#define REG_CLASS_FROM_LETTER(C) \ 1371 ((C) == 'f' ? FLOAT_REGS \ 1372 : (C) == 'b' ? BASE_REGS \ 1373 : (C) == 'h' ? SPECIAL_REGS \ 1374 : (C) == 'q' ? MQ_REGS \ 1375 : (C) == 'c' ? CTR_REGS \ 1376 : (C) == 'l' ? LINK_REGS \ 1377 : (C) == 'v' ? ALTIVEC_REGS \ 1378 : (C) == 'x' ? CR0_REGS \ 1379 : (C) == 'y' ? CR_REGS \ 1380 : (C) == 'z' ? XER_REGS \ 1381 : NO_REGS) 1382 1383/* The letters I, J, K, L, M, N, and P in a register constraint string 1384 can be used to stand for particular ranges of immediate operands. 1385 This macro defines what the ranges are. 1386 C is the letter, and VALUE is a constant value. 1387 Return 1 if VALUE is in the range specified by C. 1388 1389 `I' is a signed 16-bit constant 1390 `J' is a constant with only the high-order 16 bits nonzero 1391 `K' is a constant with only the low-order 16 bits nonzero 1392 `L' is a signed 16-bit constant shifted left 16 bits 1393 `M' is a constant that is greater than 31 1394 `N' is a positive constant that is an exact power of two 1395 `O' is the constant zero 1396 `P' is a constant whose negation is a signed 16-bit constant */ 1397 1398#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1399 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ 1400 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ 1401 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ 1402 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ 1403 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ 1404 : (C) == 'M' ? (VALUE) > 31 \ 1405 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ 1406 : (C) == 'O' ? (VALUE) == 0 \ 1407 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ 1408 : 0) 1409 1410/* Similar, but for floating constants, and defining letters G and H. 1411 Here VALUE is the CONST_DOUBLE rtx itself. 1412 1413 We flag for special constants when we can copy the constant into 1414 a general register in two insns for DF/DI and one insn for SF. 1415 1416 'H' is used for DI/DF constants that take 3 insns. */ 1417 1418#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1419 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ 1420 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ 1421 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ 1422 : 0) 1423 1424/* Optional extra constraints for this machine. 1425 1426 'Q' means that is a memory operand that is just an offset from a reg. 1427 'R' is for AIX TOC entries. 1428 'S' is a constant that can be placed into a 64-bit mask operand 1429 'T' is a constant that can be placed into a 32-bit mask operand 1430 'U' is for V.4 small data references. 1431 'W' is a vector constant that can be easily generated (no mem refs). 1432 'Y' is a indexed or word-aligned displacement memory operand. 1433 't' is for AND masks that can be performed by two rldic{l,r} insns. */ 1434 1435#define EXTRA_CONSTRAINT(OP, C) \ 1436 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 1437 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \ 1438 : (C) == 'S' ? mask64_operand (OP, DImode) \ 1439 : (C) == 'T' ? mask_operand (OP, SImode) \ 1440 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ 1441 && small_data_operand (OP, GET_MODE (OP))) \ 1442 : (C) == 't' ? (mask64_2_operand (OP, DImode) \ 1443 && (fixed_regs[CR0_REGNO] \ 1444 || !logical_operand (OP, DImode)) \ 1445 && !mask64_operand (OP, DImode)) \ 1446 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \ 1447 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \ 1448 : 0) 1449 1450/* Defining, which contraints are memory contraints. Tells reload, 1451 that any memory address can be reloaded by copying the 1452 memory address into a base register if required. */ 1453 1454#define EXTRA_MEMORY_CONSTRAINT(C, STR) \ 1455 ((C) == 'Q' || (C) == 'Y') 1456 1457/* Given an rtx X being reloaded into a reg required to be 1458 in class CLASS, return the class of reg to actually use. 1459 In general this is just CLASS; but on some machines 1460 in some cases it is preferable to use a more restrictive class. 1461 1462 On the RS/6000, we have to return NO_REGS when we want to reload a 1463 floating-point CONST_DOUBLE to force it to be copied to memory. 1464 1465 We also don't want to reload integer values into floating-point 1466 registers if we can at all help it. In fact, this can 1467 cause reload to abort, if it tries to generate a reload of CTR 1468 into a FP register and discovers it doesn't have the memory location 1469 required. 1470 1471 ??? Would it be a good idea to have reload do the converse, that is 1472 try to reload floating modes into FP registers if possible? 1473 */ 1474 1475#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1476 (((GET_CODE (X) == CONST_DOUBLE \ 1477 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 1478 ? NO_REGS \ 1479 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 1480 && (CLASS) == NON_SPECIAL_REGS) \ 1481 ? GENERAL_REGS \ 1482 : (CLASS))) 1483 1484#define DISPARAGE_RELOAD_CLASS(X, CLASS) \ 1485 (GET_CODE (X) == REG \ 1486 && REGNO (X) < FIRST_PSEUDO_REGISTER \ 1487 && SECONDARY_MEMORY_NEEDED (GET_MODE_CLASS (GET_MODE (X)), \ 1488 CLASS, GET_MODE (X)) \ 1489 ? 6 : 0) 1490 1491/* Return the register class of a scratch register needed to copy IN into 1492 or out of a register in CLASS in MODE. If it can be done directly, 1493 NO_REGS is returned. */ 1494 1495#define SECONDARY_RELOAD_CLASS(CLASS, MODE, IN) \ 1496 secondary_reload_class (CLASS, MODE, IN) 1497 1498/* If we are copying between FP or AltiVec registers and anything 1499 else, we need a memory location. */ 1500 1501#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1502 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ 1503 || (CLASS2) == FLOAT_REGS \ 1504 || (CLASS1) == ALTIVEC_REGS \ 1505 || (CLASS2) == ALTIVEC_REGS)) 1506 1507/* Return the maximum number of consecutive registers 1508 needed to represent mode MODE in a register of class CLASS. 1509 1510 On RS/6000, this is the size of MODE in words, 1511 except in the FP regs, where a single reg is enough for two words. */ 1512#define CLASS_MAX_NREGS(CLASS, MODE) \ 1513 (((CLASS) == FLOAT_REGS) \ 1514 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 1515 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1516 1517 1518/* Return a class of registers that cannot change FROM mode to TO mode. */ 1519 1520#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1521 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \ 1522 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \ 1523 ? 0 \ 1524 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1525 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \ 1526 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \ 1527 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ 1528 : 0) 1529 1530/* Stack layout; function entry, exit and calling. */ 1531 1532/* Enumeration to give which calling sequence to use. */ 1533enum rs6000_abi { 1534 ABI_NONE, 1535 ABI_AIX, /* IBM's AIX */ 1536 ABI_V4, /* System V.4/eabi */ 1537 ABI_DARWIN /* Apple's Darwin (OS X kernel) */ 1538}; 1539 1540extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ 1541 1542/* Define this if pushing a word on the stack 1543 makes the stack pointer a smaller address. */ 1544#define STACK_GROWS_DOWNWARD 1545 1546/* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1547#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1548 1549/* Define this if the nominal address of the stack frame 1550 is at the high-address end of the local variables; 1551 that is, each additional local variable allocated 1552 goes at a more negative offset in the frame. 1553 1554 On the RS/6000, we grow upwards, from the area after the outgoing 1555 arguments. */ 1556/* #define FRAME_GROWS_DOWNWARD */ 1557 1558/* Size of the outgoing register save area */ 1559#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1560 || DEFAULT_ABI == ABI_DARWIN) \ 1561 ? (TARGET_64BIT ? 64 : 32) \ 1562 : 0) 1563 1564/* Size of the fixed area on the stack */ 1565#define RS6000_SAVE_AREA \ 1566 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1567 << (TARGET_64BIT ? 1 : 0)) 1568 1569/* MEM representing address to save the TOC register */ 1570#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1571 plus_constant (stack_pointer_rtx, \ 1572 (TARGET_32BIT ? 20 : 40))) 1573 1574/* Size of the V.4 varargs area if needed */ 1575#define RS6000_VARARGS_AREA 0 1576 1577/* Align an address */ 1578#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1579 1580/* Size of V.4 varargs area in bytes */ 1581#define RS6000_VARARGS_SIZE \ 1582 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8) 1583 1584/* Offset within stack frame to start allocating local variables at. 1585 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1586 first local allocated. Otherwise, it is the offset to the BEGINNING 1587 of the first local allocated. 1588 1589 On the RS/6000, the frame pointer is the same as the stack pointer, 1590 except for dynamic allocations. So we start after the fixed area and 1591 outgoing parameter area. */ 1592 1593#define STARTING_FRAME_OFFSET \ 1594 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1595 TARGET_ALTIVEC ? 16 : 8) \ 1596 + RS6000_VARARGS_AREA \ 1597 + RS6000_SAVE_AREA) 1598 1599/* Offset from the stack pointer register to an item dynamically 1600 allocated on the stack, e.g., by `alloca'. 1601 1602 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1603 length of the outgoing arguments. The default is correct for most 1604 machines. See `function.c' for details. */ 1605#define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1606 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1607 TARGET_ALTIVEC ? 16 : 8) \ 1608 + (STACK_POINTER_OFFSET)) 1609 1610/* If we generate an insn to push BYTES bytes, 1611 this says how many the stack pointer really advances by. 1612 On RS/6000, don't define this because there are no push insns. */ 1613/* #define PUSH_ROUNDING(BYTES) */ 1614 1615/* Offset of first parameter from the argument pointer register value. 1616 On the RS/6000, we define the argument pointer to the start of the fixed 1617 area. */ 1618#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1619 1620/* Offset from the argument pointer register value to the top of 1621 stack. This is different from FIRST_PARM_OFFSET because of the 1622 register save area. */ 1623#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1624 1625/* Define this if stack space is still allocated for a parameter passed 1626 in a register. The value is the number of bytes allocated to this 1627 area. */ 1628#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1629 1630/* Define this if the above stack space is to be considered part of the 1631 space allocated by the caller. */ 1632#define OUTGOING_REG_PARM_STACK_SPACE 1633 1634/* This is the difference between the logical top of stack and the actual sp. 1635 1636 For the RS/6000, sp points past the fixed area. */ 1637#define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1638 1639/* Define this if the maximum size of all the outgoing args is to be 1640 accumulated and pushed during the prologue. The amount can be 1641 found in the variable current_function_outgoing_args_size. */ 1642#define ACCUMULATE_OUTGOING_ARGS 1 1643 1644/* Value is the number of bytes of arguments automatically 1645 popped when returning from a subroutine call. 1646 FUNDECL is the declaration node of the function (as a tree), 1647 FUNTYPE is the data type of the function (as a tree), 1648 or for a library call it is an identifier node for the subroutine name. 1649 SIZE is the number of bytes of arguments passed on the stack. */ 1650 1651#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1652 1653/* Define how to find the value returned by a function. 1654 VALTYPE is the data type of the value (as a tree). 1655 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1656 otherwise, FUNC is 0. */ 1657 1658#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC)) 1659 1660/* Define how to find the value returned by a library function 1661 assuming the value has mode MODE. */ 1662 1663#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1664 1665/* DRAFT_V4_STRUCT_RET defaults off. */ 1666#define DRAFT_V4_STRUCT_RET 0 1667 1668/* Let RETURN_IN_MEMORY control what happens. */ 1669#define DEFAULT_PCC_STRUCT_RETURN 0 1670 1671/* Mode of stack savearea. 1672 FUNCTION is VOIDmode because calling convention maintains SP. 1673 BLOCK needs Pmode for SP. 1674 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1675#define STACK_SAVEAREA_MODE(LEVEL) \ 1676 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1677 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1678 1679/* Minimum and maximum general purpose registers used to hold arguments. */ 1680#define GP_ARG_MIN_REG 3 1681#define GP_ARG_MAX_REG 10 1682#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1683 1684/* Minimum and maximum floating point registers used to hold arguments. */ 1685#define FP_ARG_MIN_REG 33 1686#define FP_ARG_AIX_MAX_REG 45 1687#define FP_ARG_V4_MAX_REG 40 1688#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1689 || DEFAULT_ABI == ABI_DARWIN) \ 1690 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1691#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1692 1693/* Minimum and maximum AltiVec registers used to hold arguments. */ 1694#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1695#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1696#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1697 1698/* Return registers */ 1699#define GP_ARG_RETURN GP_ARG_MIN_REG 1700#define FP_ARG_RETURN FP_ARG_MIN_REG 1701#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1702 1703/* Flags for the call/call_value rtl operations set up by function_arg */ 1704#define CALL_NORMAL 0x00000000 /* no special processing */ 1705/* Bits in 0x00000001 are unused. */ 1706#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1707#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1708#define CALL_LONG 0x00000008 /* always call indirect */ 1709#define CALL_LIBCALL 0x00000010 /* libcall */ 1710 1711/* 1 if N is a possible register number for a function value 1712 as seen by the caller. 1713 1714 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1715#define FUNCTION_VALUE_REGNO_P(N) \ 1716 ((N) == GP_ARG_RETURN \ 1717 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \ 1718 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1719 1720/* 1 if N is a possible register number for function argument passing. 1721 On RS/6000, these are r3-r10 and fp1-fp13. 1722 On AltiVec, v2 - v13 are used for passing vectors. */ 1723#define FUNCTION_ARG_REGNO_P(N) \ 1724 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1725 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1726 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1727 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1728 && TARGET_HARD_FLOAT)) 1729 1730/* A C structure for machine-specific, per-function data. 1731 This is added to the cfun structure. */ 1732typedef struct machine_function GTY(()) 1733{ 1734 /* Whether a System V.4 varargs area was created. */ 1735 int sysv_varargs_p; 1736 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 1737 int ra_needs_full_frame; 1738 /* Some local-dynamic symbol. */ 1739 const char *some_ld_name; 1740 /* Whether the instruction chain has been scanned already. */ 1741 int insn_chain_scanned_p; 1742 /* Flags if __builtin_return_address (0) was used. */ 1743 int ra_need_lr; 1744} machine_function; 1745 1746/* Define a data type for recording info about an argument list 1747 during the scan of that argument list. This data type should 1748 hold all necessary information about the function itself 1749 and about the args processed so far, enough to enable macros 1750 such as FUNCTION_ARG to determine where the next arg should go. 1751 1752 On the RS/6000, this is a structure. The first element is the number of 1753 total argument words, the second is used to store the next 1754 floating-point register number, and the third says how many more args we 1755 have prototype types for. 1756 1757 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1758 the next available GP register, `fregno' is the next available FP 1759 register, and `words' is the number of words used on the stack. 1760 1761 The varargs/stdarg support requires that this structure's size 1762 be a multiple of sizeof(int). */ 1763 1764typedef struct rs6000_args 1765{ 1766 int words; /* # words used for passing GP registers */ 1767 int fregno; /* next available FP register */ 1768 int vregno; /* next available AltiVec register */ 1769 int nargs_prototype; /* # args left in the current prototype */ 1770 int prototype; /* Whether a prototype was defined */ 1771 int stdarg; /* Whether function is a stdarg function. */ 1772 int call_cookie; /* Do special things for this call */ 1773 int sysv_gregno; /* next available GP register */ 1774} CUMULATIVE_ARGS; 1775 1776/* Initialize a variable CUM of type CUMULATIVE_ARGS 1777 for a call to a function whose data type is FNTYPE. 1778 For a library call, FNTYPE is 0. */ 1779 1780#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1781 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS) 1782 1783/* Similar, but when scanning the definition of a procedure. We always 1784 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1785 1786#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1787 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000) 1788 1789/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1790 1791#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1792 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0) 1793 1794/* Update the data in CUM to advance over an argument 1795 of mode MODE and data type TYPE. 1796 (TYPE is null for libcalls where that information may not be available.) */ 1797 1798#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1799 function_arg_advance (&CUM, MODE, TYPE, NAMED) 1800 1801/* Determine where to put an argument to a function. 1802 Value is zero to push the argument on the stack, 1803 or a hard register in which to store the argument. 1804 1805 MODE is the argument's machine mode. 1806 TYPE is the data type of the argument (as a tree). 1807 This is null for libcalls where that information may 1808 not be available. 1809 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1810 the preceding args and about the function being called. 1811 NAMED is nonzero if this argument is a named parameter 1812 (otherwise it is an extra parameter matching an ellipsis). 1813 1814 On RS/6000 the first eight words of non-FP are normally in registers 1815 and the rest are pushed. The first 13 FP args are in registers. 1816 1817 If this is floating-point and no prototype is specified, we use 1818 both an FP and integer register (or possibly FP reg and stack). Library 1819 functions (when TYPE is zero) always have the proper types for args, 1820 so we can pass the FP value just in one register. emit_library_function 1821 doesn't support EXPR_LIST anyway. */ 1822 1823#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1824 function_arg (&CUM, MODE, TYPE, NAMED) 1825 1826/* For an arg passed partly in registers and partly in memory, 1827 this is the number of registers used. 1828 For args passed entirely in registers or entirely in memory, zero. */ 1829 1830#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1831 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) 1832 1833/* A C expression that indicates when an argument must be passed by 1834 reference. If nonzero for an argument, a copy of that argument is 1835 made in memory and a pointer to the argument is passed instead of 1836 the argument itself. The pointer is passed in whatever way is 1837 appropriate for passing a pointer to that type. */ 1838 1839#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1840 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1841 1842/* If defined, a C expression which determines whether, and in which 1843 direction, to pad out an argument with extra space. The value 1844 should be of type `enum direction': either `upward' to pad above 1845 the argument, `downward' to pad below, or `none' to inhibit 1846 padding. */ 1847 1848#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1849 1850/* If defined, a C expression that gives the alignment boundary, in bits, 1851 of an argument with the specified mode and type. If it is not defined, 1852 PARM_BOUNDARY is used for all arguments. */ 1853 1854#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1855 function_arg_boundary (MODE, TYPE) 1856 1857/* Implement `va_start' for varargs and stdarg. */ 1858#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1859 rs6000_va_start (valist, nextarg) 1860 1861/* Implement `va_arg'. */ 1862#define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1863 rs6000_va_arg (valist, type) 1864 1865#define PAD_VARARGS_DOWN \ 1866 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1867 1868/* Define this macro to be a nonzero value if the location where a function 1869 argument is passed depends on whether or not it is a named argument. */ 1870#define STRICT_ARGUMENT_NAMING 1 1871 1872/* Output assembler code to FILE to increment profiler label # LABELNO 1873 for profiling a function entry. */ 1874 1875#define FUNCTION_PROFILER(FILE, LABELNO) \ 1876 output_function_profiler ((FILE), (LABELNO)); 1877 1878/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1879 the stack pointer does not matter. No definition is equivalent to 1880 always zero. 1881 1882 On the RS/6000, this is nonzero because we can restore the stack from 1883 its backpointer, which we maintain. */ 1884#define EXIT_IGNORE_STACK 1 1885 1886/* Define this macro as a C expression that is nonzero for registers 1887 that are used by the epilogue or the return' pattern. The stack 1888 and frame pointer registers are already be assumed to be used as 1889 needed. */ 1890 1891#define EPILOGUE_USES(REGNO) \ 1892 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ 1893 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1894 || (current_function_calls_eh_return \ 1895 && TARGET_AIX \ 1896 && (REGNO) == 2)) 1897 1898 1899/* TRAMPOLINE_TEMPLATE deleted */ 1900 1901/* Length in units of the trampoline for entering a nested function. */ 1902 1903#define TRAMPOLINE_SIZE rs6000_trampoline_size () 1904 1905/* Emit RTL insns to initialize the variable parts of a trampoline. 1906 FNADDR is an RTX for the address of the function's pure code. 1907 CXT is an RTX for the static chain value for the function. */ 1908 1909#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ 1910 rs6000_initialize_trampoline (ADDR, FNADDR, CXT) 1911 1912/* Definitions for __builtin_return_address and __builtin_frame_address. 1913 __builtin_return_address (0) should give link register (65), enable 1914 this. */ 1915/* This should be uncommented, so that the link register is used, but 1916 currently this would result in unmatched insns and spilling fixed 1917 registers so we'll leave it for another day. When these problems are 1918 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1919 (mrs) */ 1920/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1921 1922/* Number of bytes into the frame return addresses can be found. See 1923 rs6000_stack_info in rs6000.c for more information on how the different 1924 abi's store the return address. */ 1925#define RETURN_ADDRESS_OFFSET \ 1926 ((DEFAULT_ABI == ABI_AIX \ 1927 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ 1928 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1929 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1930 1931/* The current return address is in link register (65). The return address 1932 of anything farther back is accessed normally at an offset of 8 from the 1933 frame pointer. */ 1934#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1935 (rs6000_return_addr (COUNT, FRAME)) 1936 1937 1938/* Definitions for register eliminations. 1939 1940 We have two registers that can be eliminated on the RS/6000. First, the 1941 frame pointer register can often be eliminated in favor of the stack 1942 pointer register. Secondly, the argument pointer register can always be 1943 eliminated; it is replaced with either the stack or frame pointer. 1944 1945 In addition, we use the elimination mechanism to see if r30 is needed 1946 Initially we assume that it isn't. If it is, we spill it. This is done 1947 by making it an eliminable register. We replace it with itself so that 1948 if it isn't needed, then existing uses won't be modified. */ 1949 1950/* This is an array of structures. Each structure initializes one pair 1951 of eliminable registers. The "from" register number is given first, 1952 followed by "to". Eliminations of the same "from" register are listed 1953 in order of preference. */ 1954#define ELIMINABLE_REGS \ 1955{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1956 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1957 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 1958 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1959 1960/* Given FROM and TO register numbers, say whether this elimination is allowed. 1961 Frame pointer elimination is automatically handled. 1962 1963 For the RS/6000, if frame pointer elimination is being done, we would like 1964 to convert ap into fp, not sp. 1965 1966 We need r30 if -mminimal-toc was specified, and there are constant pool 1967 references. */ 1968 1969#define CAN_ELIMINATE(FROM, TO) \ 1970 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 1971 ? ! frame_pointer_needed \ 1972 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ 1973 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ 1974 : 1) 1975 1976/* Define the offset between two registers, one to be eliminated, and the other 1977 its replacement, at the start of a routine. */ 1978#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1979 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1980 1981/* Addressing modes, and classification of registers for them. */ 1982 1983#define HAVE_PRE_DECREMENT 1 1984#define HAVE_PRE_INCREMENT 1 1985 1986/* Macros to check register numbers against specific register classes. */ 1987 1988/* These assume that REGNO is a hard or pseudo reg number. 1989 They give nonzero only if REGNO is a hard reg of the suitable class 1990 or a pseudo reg currently allocated to a suitable hard reg. 1991 Since they use reg_renumber, they are safe only once reg_renumber 1992 has been allocated, which happens in local-alloc.c. */ 1993 1994#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1995((REGNO) < FIRST_PSEUDO_REGISTER \ 1996 ? (REGNO) <= 31 || (REGNO) == 67 \ 1997 : (reg_renumber[REGNO] >= 0 \ 1998 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) 1999 2000#define REGNO_OK_FOR_BASE_P(REGNO) \ 2001((REGNO) < FIRST_PSEUDO_REGISTER \ 2002 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 2003 : (reg_renumber[REGNO] > 0 \ 2004 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) 2005 2006/* Maximum number of registers that can appear in a valid memory address. */ 2007 2008#define MAX_REGS_PER_ADDRESS 2 2009 2010/* Recognize any constant value that is a valid address. */ 2011 2012#define CONSTANT_ADDRESS_P(X) \ 2013 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 2014 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 2015 || GET_CODE (X) == HIGH) 2016 2017/* Nonzero if the constant value X is a legitimate general operand. 2018 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 2019 2020 On the RS/6000, all integer constants are acceptable, most won't be valid 2021 for particular insns, though. Only easy FP constants are 2022 acceptable. */ 2023 2024#define LEGITIMATE_CONSTANT_P(X) \ 2025 (((GET_CODE (X) != CONST_DOUBLE \ 2026 && GET_CODE (X) != CONST_VECTOR) \ 2027 || GET_MODE (X) == VOIDmode \ 2028 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ 2029 || easy_fp_constant (X, GET_MODE (X)) \ 2030 || easy_vector_constant (X, GET_MODE (X))) \ 2031 && !rs6000_tls_referenced_p (X)) 2032 2033/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2034 and check its validity for a certain class. 2035 We have two alternate definitions for each of them. 2036 The usual definition accepts all pseudo regs; the other rejects 2037 them unless they have been allocated suitable hard regs. 2038 The symbol REG_OK_STRICT causes the latter definition to be used. 2039 2040 Most source files want to accept pseudo regs in the hope that 2041 they will get allocated to the class that the insn wants them to be in. 2042 Source files for reload pass need to be strict. 2043 After reload, it makes no difference, since pseudo regs have 2044 been eliminated by then. */ 2045 2046#ifdef REG_OK_STRICT 2047# define REG_OK_STRICT_FLAG 1 2048#else 2049# define REG_OK_STRICT_FLAG 0 2050#endif 2051 2052/* Nonzero if X is a hard reg that can be used as an index 2053 or if it is a pseudo reg in the non-strict case. */ 2054#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 2055 ((! (STRICT) \ 2056 && (REGNO (X) <= 31 \ 2057 || REGNO (X) == ARG_POINTER_REGNUM \ 2058 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \ 2059 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X)))) 2060 2061/* Nonzero if X is a hard reg that can be used as a base reg 2062 or if it is a pseudo reg in the non-strict case. */ 2063#define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 2064 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT))) 2065 2066#define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) 2067#define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) 2068 2069/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2070 that is a valid memory address for an instruction. 2071 The MODE argument is the machine mode for the MEM expression 2072 that wants to use this address. 2073 2074 On the RS/6000, there are four valid address: a SYMBOL_REF that 2075 refers to a constant pool entry of an address (or the sum of it 2076 plus a constant), a short (16-bit signed) constant plus a register, 2077 the sum of two registers, or a register indirect, possibly with an 2078 auto-increment. For DFmode and DImode with a constant plus register, 2079 we must ensure that both words are addressable or PowerPC64 with offset 2080 word aligned. 2081 2082 For modes spanning multiple registers (DFmode in 32-bit GPRs, 2083 32-bit DImode, TImode), indexed addressing cannot be used because 2084 adjacent memory cells are accessed by adding word-sized offsets 2085 during assembly output. */ 2086 2087#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2088{ if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ 2089 goto ADDR; \ 2090} 2091 2092/* Try machine-dependent ways of modifying an illegitimate address 2093 to be legitimate. If we find one, return the new, valid address. 2094 This macro is used in only one place: `memory_address' in explow.c. 2095 2096 OLDX is the address as it was before break_out_memory_refs was called. 2097 In some cases it is useful to look at this to decide what needs to be done. 2098 2099 MODE and WIN are passed so that this macro can use 2100 GO_IF_LEGITIMATE_ADDRESS. 2101 2102 It is always safe for this macro to do nothing. It exists to recognize 2103 opportunities to optimize the output. 2104 2105 On RS/6000, first check for the sum of a register with a constant 2106 integer that is out of range. If so, generate code to add the 2107 constant with the low-order 16 bits masked to the register and force 2108 this result into another register (this can be done with `cau'). 2109 Then generate an address of REG+(CONST&0xffff), allowing for the 2110 possibility of bit 16 being a one. 2111 2112 Then check for the sum of a register and something not constant, try to 2113 load the other things into a register and return the sum. */ 2114 2115#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2116{ rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ 2117 if (result != NULL_RTX) \ 2118 { \ 2119 (X) = result; \ 2120 goto WIN; \ 2121 } \ 2122} 2123 2124/* Try a machine-dependent way of reloading an illegitimate address 2125 operand. If we find one, push the reload and jump to WIN. This 2126 macro is used in only one place: `find_reloads_address' in reload.c. 2127 2128 Implemented on rs6000 by rs6000_legitimize_reload_address. 2129 Note that (X) is evaluated twice; this is safe in current usage. */ 2130 2131#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2132do { \ 2133 int win; \ 2134 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ 2135 (int)(TYPE), (IND_LEVELS), &win); \ 2136 if ( win ) \ 2137 goto WIN; \ 2138} while (0) 2139 2140/* Go to LABEL if ADDR (a legitimate address expression) 2141 has an effect that depends on the machine mode it is used for. */ 2142 2143#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 2144do { \ 2145 if (rs6000_mode_dependent_address (ADDR)) \ 2146 goto LABEL; \ 2147} while (0) 2148 2149/* The register number of the register used to address a table of 2150 static data addresses in memory. In some cases this register is 2151 defined by a processor's "application binary interface" (ABI). 2152 When this macro is defined, RTL is generated for this register 2153 once, as with the stack pointer and frame pointer registers. If 2154 this macro is not defined, it is up to the machine-dependent files 2155 to allocate such a register (if necessary). */ 2156 2157#define RS6000_PIC_OFFSET_TABLE_REGNUM 30 2158#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 2159 2160#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 2161 2162/* Define this macro if the register defined by 2163 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 2164 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 2165 2166/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 2167 2168/* By generating position-independent code, when two different 2169 programs (A and B) share a common library (libC.a), the text of 2170 the library can be shared whether or not the library is linked at 2171 the same address for both programs. In some of these 2172 environments, position-independent code requires not only the use 2173 of different addressing modes, but also special code to enable the 2174 use of these addressing modes. 2175 2176 The `FINALIZE_PIC' macro serves as a hook to emit these special 2177 codes once the function is being compiled into assembly code, but 2178 not before. (It is not done before, because in the case of 2179 compiling an inline function, it would lead to multiple PIC 2180 prologues being included in functions which used inline functions 2181 and were compiled to assembly language.) */ 2182 2183/* #define FINALIZE_PIC */ 2184 2185/* A C expression that is nonzero if X is a legitimate immediate 2186 operand on the target machine when generating position independent 2187 code. You can assume that X satisfies `CONSTANT_P', so you need 2188 not check this. You can also assume FLAG_PIC is true, so you need 2189 not check it either. You need not define this macro if all 2190 constants (including `SYMBOL_REF') can be immediate operands when 2191 generating position independent code. */ 2192 2193/* #define LEGITIMATE_PIC_OPERAND_P (X) */ 2194 2195/* Define this if some processing needs to be done immediately before 2196 emitting code for an insn. */ 2197 2198/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ 2199 2200/* Specify the machine mode that this machine uses 2201 for the index in the tablejump instruction. */ 2202#define CASE_VECTOR_MODE SImode 2203 2204/* Define as C expression which evaluates to nonzero if the tablejump 2205 instruction expects the table to contain offsets from the address of the 2206 table. 2207 Do not define this if the table should contain absolute addresses. */ 2208#define CASE_VECTOR_PC_RELATIVE 1 2209 2210/* Define this as 1 if `char' should by default be signed; else as 0. */ 2211#define DEFAULT_SIGNED_CHAR 0 2212 2213/* This flag, if defined, says the same insns that convert to a signed fixnum 2214 also convert validly to an unsigned one. */ 2215 2216/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ 2217 2218/* Max number of bytes we can move from memory to memory 2219 in one reasonably fast instruction. */ 2220#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 2221#define MAX_MOVE_MAX 8 2222 2223/* Nonzero if access to memory by bytes is no faster than for words. 2224 Also nonzero if doing byte operations (specifically shifts) in registers 2225 is undesirable. */ 2226#define SLOW_BYTE_ACCESS 1 2227 2228/* Define if operations between registers always perform the operation 2229 on the full register even if a narrower mode is specified. */ 2230#define WORD_REGISTER_OPERATIONS 2231 2232/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2233 will either zero-extend or sign-extend. The value of this macro should 2234 be the code that says which one of the two operations is implicitly 2235 done, NIL if none. */ 2236#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2237 2238/* Define if loading short immediate values into registers sign extends. */ 2239#define SHORT_IMMEDIATES_SIGN_EXTEND 2240 2241/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2242 is done just by pretending it is already truncated. */ 2243#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2244 2245/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 2246#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2247 ((VALUE) = ((MODE) == SImode ? 32 : 64)) 2248 2249/* The CTZ patterns return -1 for input of zero. */ 2250#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1) 2251 2252/* Specify the machine mode that pointers have. 2253 After generation of rtl, the compiler makes no further distinction 2254 between pointers and any other objects of this machine mode. */ 2255#define Pmode (TARGET_32BIT ? SImode : DImode) 2256 2257/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 2258#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 2259 2260/* Mode of a function address in a call instruction (for indexing purposes). 2261 Doesn't matter on RS/6000. */ 2262#define FUNCTION_MODE SImode 2263 2264/* Define this if addresses of constant functions 2265 shouldn't be put through pseudo regs where they can be cse'd. 2266 Desirable on machines where ordinary constants are expensive 2267 but a CALL with constant address is cheap. */ 2268#define NO_FUNCTION_CSE 2269 2270/* Define this to be nonzero if shift instructions ignore all but the low-order 2271 few bits. 2272 2273 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2274 have been dropped from the PowerPC architecture. */ 2275 2276#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) 2277 2278/* Adjust the length of an INSN. LENGTH is the currently-computed length and 2279 should be adjusted to reflect any required changes. This macro is used when 2280 there is some systematic length adjustment required that would be difficult 2281 to express in the length attribute. */ 2282 2283/* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2284 2285/* Given a comparison code (EQ, NE, etc.) and the first operand of a 2286 COMPARE, return the mode to be used for the comparison. For 2287 floating-point, CCFPmode should be used. CCUNSmode should be used 2288 for unsigned comparisons. CCEQmode should be used when we are 2289 doing an inequality comparison on the result of a 2290 comparison. CCmode should be used in all other cases. */ 2291 2292#define SELECT_CC_MODE(OP,X,Y) \ 2293 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ 2294 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2295 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \ 2296 ? CCEQmode : CCmode)) 2297 2298/* Can the condition code MODE be safely reversed? This is safe in 2299 all cases on this port, because at present it doesn't use the 2300 trapping FP comparisons (fcmpo). */ 2301#define REVERSIBLE_CC_MODE(MODE) 1 2302 2303/* Given a condition code and a mode, return the inverse condition. */ 2304#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 2305 2306/* Define the information needed to generate branch and scc insns. This is 2307 stored from the compare operation. */ 2308 2309extern GTY(()) rtx rs6000_compare_op0; 2310extern GTY(()) rtx rs6000_compare_op1; 2311extern int rs6000_compare_fp_p; 2312 2313/* Control the assembler format that we output. */ 2314 2315/* A C string constant describing how to begin a comment in the target 2316 assembler language. The compiler assumes that the comment will end at 2317 the end of the line. */ 2318#define ASM_COMMENT_START " #" 2319 2320/* Implicit library calls should use memcpy, not bcopy, etc. */ 2321 2322#define TARGET_MEM_FUNCTIONS 2323 2324/* Flag to say the TOC is initialized */ 2325extern int toc_initialized; 2326 2327/* Macro to output a special constant pool entry. Go to WIN if we output 2328 it. Otherwise, it is written the usual way. 2329 2330 On the RS/6000, toc entries are handled this way. */ 2331 2332#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2333{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2334 { \ 2335 output_toc (FILE, X, LABELNO, MODE); \ 2336 goto WIN; \ 2337 } \ 2338} 2339 2340#ifdef HAVE_GAS_WEAK 2341#define RS6000_WEAK 1 2342#else 2343#define RS6000_WEAK 0 2344#endif 2345 2346#if RS6000_WEAK 2347/* Used in lieu of ASM_WEAKEN_LABEL. */ 2348#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2349 do \ 2350 { \ 2351 fputs ("\t.weak\t", (FILE)); \ 2352 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2353 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2354 && DEFAULT_ABI == ABI_AIX) \ 2355 { \ 2356 if (TARGET_XCOFF) \ 2357 fputs ("[DS]", (FILE)); \ 2358 fputs ("\n\t.weak\t.", (FILE)); \ 2359 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2360 } \ 2361 fputc ('\n', (FILE)); \ 2362 if (VAL) \ 2363 { \ 2364 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2365 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2366 && DEFAULT_ABI == ABI_AIX) \ 2367 { \ 2368 fputs ("\t.set\t.", (FILE)); \ 2369 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2370 fputs (",.", (FILE)); \ 2371 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2372 fputc ('\n', (FILE)); \ 2373 } \ 2374 } \ 2375 } \ 2376 while (0) 2377#endif 2378 2379/* This implements the `alias' attribute. */ 2380#undef ASM_OUTPUT_DEF_FROM_DECLS 2381#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2382 do \ 2383 { \ 2384 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2385 const char *name = IDENTIFIER_POINTER (TARGET); \ 2386 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2387 && DEFAULT_ABI == ABI_AIX) \ 2388 { \ 2389 if (TREE_PUBLIC (DECL)) \ 2390 { \ 2391 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2392 { \ 2393 fputs ("\t.globl\t.", FILE); \ 2394 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2395 putc ('\n', FILE); \ 2396 } \ 2397 } \ 2398 else if (TARGET_XCOFF) \ 2399 { \ 2400 fputs ("\t.lglobl\t.", FILE); \ 2401 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2402 putc ('\n', FILE); \ 2403 } \ 2404 fputs ("\t.set\t.", FILE); \ 2405 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2406 fputs (",.", FILE); \ 2407 RS6000_OUTPUT_BASENAME (FILE, name); \ 2408 fputc ('\n', FILE); \ 2409 } \ 2410 ASM_OUTPUT_DEF (FILE, alias, name); \ 2411 } \ 2412 while (0) 2413 2414#define TARGET_ASM_FILE_START rs6000_file_start 2415 2416/* Output to assembler file text saying following lines 2417 may contain character constants, extra white space, comments, etc. */ 2418 2419#define ASM_APP_ON "" 2420 2421/* Output to assembler file text saying following lines 2422 no longer contain unusual constructs. */ 2423 2424#define ASM_APP_OFF "" 2425 2426/* How to refer to registers in assembler output. 2427 This sequence is indexed by compiler's hard-register-number (see above). */ 2428 2429extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2430 2431#define REGISTER_NAMES \ 2432{ \ 2433 &rs6000_reg_names[ 0][0], /* r0 */ \ 2434 &rs6000_reg_names[ 1][0], /* r1 */ \ 2435 &rs6000_reg_names[ 2][0], /* r2 */ \ 2436 &rs6000_reg_names[ 3][0], /* r3 */ \ 2437 &rs6000_reg_names[ 4][0], /* r4 */ \ 2438 &rs6000_reg_names[ 5][0], /* r5 */ \ 2439 &rs6000_reg_names[ 6][0], /* r6 */ \ 2440 &rs6000_reg_names[ 7][0], /* r7 */ \ 2441 &rs6000_reg_names[ 8][0], /* r8 */ \ 2442 &rs6000_reg_names[ 9][0], /* r9 */ \ 2443 &rs6000_reg_names[10][0], /* r10 */ \ 2444 &rs6000_reg_names[11][0], /* r11 */ \ 2445 &rs6000_reg_names[12][0], /* r12 */ \ 2446 &rs6000_reg_names[13][0], /* r13 */ \ 2447 &rs6000_reg_names[14][0], /* r14 */ \ 2448 &rs6000_reg_names[15][0], /* r15 */ \ 2449 &rs6000_reg_names[16][0], /* r16 */ \ 2450 &rs6000_reg_names[17][0], /* r17 */ \ 2451 &rs6000_reg_names[18][0], /* r18 */ \ 2452 &rs6000_reg_names[19][0], /* r19 */ \ 2453 &rs6000_reg_names[20][0], /* r20 */ \ 2454 &rs6000_reg_names[21][0], /* r21 */ \ 2455 &rs6000_reg_names[22][0], /* r22 */ \ 2456 &rs6000_reg_names[23][0], /* r23 */ \ 2457 &rs6000_reg_names[24][0], /* r24 */ \ 2458 &rs6000_reg_names[25][0], /* r25 */ \ 2459 &rs6000_reg_names[26][0], /* r26 */ \ 2460 &rs6000_reg_names[27][0], /* r27 */ \ 2461 &rs6000_reg_names[28][0], /* r28 */ \ 2462 &rs6000_reg_names[29][0], /* r29 */ \ 2463 &rs6000_reg_names[30][0], /* r30 */ \ 2464 &rs6000_reg_names[31][0], /* r31 */ \ 2465 \ 2466 &rs6000_reg_names[32][0], /* fr0 */ \ 2467 &rs6000_reg_names[33][0], /* fr1 */ \ 2468 &rs6000_reg_names[34][0], /* fr2 */ \ 2469 &rs6000_reg_names[35][0], /* fr3 */ \ 2470 &rs6000_reg_names[36][0], /* fr4 */ \ 2471 &rs6000_reg_names[37][0], /* fr5 */ \ 2472 &rs6000_reg_names[38][0], /* fr6 */ \ 2473 &rs6000_reg_names[39][0], /* fr7 */ \ 2474 &rs6000_reg_names[40][0], /* fr8 */ \ 2475 &rs6000_reg_names[41][0], /* fr9 */ \ 2476 &rs6000_reg_names[42][0], /* fr10 */ \ 2477 &rs6000_reg_names[43][0], /* fr11 */ \ 2478 &rs6000_reg_names[44][0], /* fr12 */ \ 2479 &rs6000_reg_names[45][0], /* fr13 */ \ 2480 &rs6000_reg_names[46][0], /* fr14 */ \ 2481 &rs6000_reg_names[47][0], /* fr15 */ \ 2482 &rs6000_reg_names[48][0], /* fr16 */ \ 2483 &rs6000_reg_names[49][0], /* fr17 */ \ 2484 &rs6000_reg_names[50][0], /* fr18 */ \ 2485 &rs6000_reg_names[51][0], /* fr19 */ \ 2486 &rs6000_reg_names[52][0], /* fr20 */ \ 2487 &rs6000_reg_names[53][0], /* fr21 */ \ 2488 &rs6000_reg_names[54][0], /* fr22 */ \ 2489 &rs6000_reg_names[55][0], /* fr23 */ \ 2490 &rs6000_reg_names[56][0], /* fr24 */ \ 2491 &rs6000_reg_names[57][0], /* fr25 */ \ 2492 &rs6000_reg_names[58][0], /* fr26 */ \ 2493 &rs6000_reg_names[59][0], /* fr27 */ \ 2494 &rs6000_reg_names[60][0], /* fr28 */ \ 2495 &rs6000_reg_names[61][0], /* fr29 */ \ 2496 &rs6000_reg_names[62][0], /* fr30 */ \ 2497 &rs6000_reg_names[63][0], /* fr31 */ \ 2498 \ 2499 &rs6000_reg_names[64][0], /* mq */ \ 2500 &rs6000_reg_names[65][0], /* lr */ \ 2501 &rs6000_reg_names[66][0], /* ctr */ \ 2502 &rs6000_reg_names[67][0], /* ap */ \ 2503 \ 2504 &rs6000_reg_names[68][0], /* cr0 */ \ 2505 &rs6000_reg_names[69][0], /* cr1 */ \ 2506 &rs6000_reg_names[70][0], /* cr2 */ \ 2507 &rs6000_reg_names[71][0], /* cr3 */ \ 2508 &rs6000_reg_names[72][0], /* cr4 */ \ 2509 &rs6000_reg_names[73][0], /* cr5 */ \ 2510 &rs6000_reg_names[74][0], /* cr6 */ \ 2511 &rs6000_reg_names[75][0], /* cr7 */ \ 2512 \ 2513 &rs6000_reg_names[76][0], /* xer */ \ 2514 \ 2515 &rs6000_reg_names[77][0], /* v0 */ \ 2516 &rs6000_reg_names[78][0], /* v1 */ \ 2517 &rs6000_reg_names[79][0], /* v2 */ \ 2518 &rs6000_reg_names[80][0], /* v3 */ \ 2519 &rs6000_reg_names[81][0], /* v4 */ \ 2520 &rs6000_reg_names[82][0], /* v5 */ \ 2521 &rs6000_reg_names[83][0], /* v6 */ \ 2522 &rs6000_reg_names[84][0], /* v7 */ \ 2523 &rs6000_reg_names[85][0], /* v8 */ \ 2524 &rs6000_reg_names[86][0], /* v9 */ \ 2525 &rs6000_reg_names[87][0], /* v10 */ \ 2526 &rs6000_reg_names[88][0], /* v11 */ \ 2527 &rs6000_reg_names[89][0], /* v12 */ \ 2528 &rs6000_reg_names[90][0], /* v13 */ \ 2529 &rs6000_reg_names[91][0], /* v14 */ \ 2530 &rs6000_reg_names[92][0], /* v15 */ \ 2531 &rs6000_reg_names[93][0], /* v16 */ \ 2532 &rs6000_reg_names[94][0], /* v17 */ \ 2533 &rs6000_reg_names[95][0], /* v18 */ \ 2534 &rs6000_reg_names[96][0], /* v19 */ \ 2535 &rs6000_reg_names[97][0], /* v20 */ \ 2536 &rs6000_reg_names[98][0], /* v21 */ \ 2537 &rs6000_reg_names[99][0], /* v22 */ \ 2538 &rs6000_reg_names[100][0], /* v23 */ \ 2539 &rs6000_reg_names[101][0], /* v24 */ \ 2540 &rs6000_reg_names[102][0], /* v25 */ \ 2541 &rs6000_reg_names[103][0], /* v26 */ \ 2542 &rs6000_reg_names[104][0], /* v27 */ \ 2543 &rs6000_reg_names[105][0], /* v28 */ \ 2544 &rs6000_reg_names[106][0], /* v29 */ \ 2545 &rs6000_reg_names[107][0], /* v30 */ \ 2546 &rs6000_reg_names[108][0], /* v31 */ \ 2547 &rs6000_reg_names[109][0], /* vrsave */ \ 2548 &rs6000_reg_names[110][0], /* vscr */ \ 2549 &rs6000_reg_names[111][0], /* spe_acc */ \ 2550 &rs6000_reg_names[112][0], /* spefscr */ \ 2551} 2552 2553/* Table of additional register names to use in user input. */ 2554 2555#define ADDITIONAL_REGISTER_NAMES \ 2556 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2557 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2558 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2559 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2560 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2561 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2562 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2563 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2564 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2565 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2566 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2567 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2568 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2569 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2570 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2571 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2572 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2573 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2574 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2575 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2576 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2577 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2578 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2579 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2580 {"vrsave", 109}, {"vscr", 110}, \ 2581 {"spe_acc", 111}, {"spefscr", 112}, \ 2582 /* no additional names for: mq, lr, ctr, ap */ \ 2583 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2584 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2585 {"cc", 68}, {"sp", 1}, {"toc", 2} } 2586 2587/* Text to write out after a CALL that may be replaced by glue code by 2588 the loader. This depends on the AIX version. */ 2589#define RS6000_CALL_GLUE "cror 31,31,31" 2590 2591/* This is how to output an element of a case-vector that is relative. */ 2592 2593#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2594 do { char buf[100]; \ 2595 fputs ("\t.long ", FILE); \ 2596 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2597 assemble_name (FILE, buf); \ 2598 putc ('-', FILE); \ 2599 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2600 assemble_name (FILE, buf); \ 2601 putc ('\n', FILE); \ 2602 } while (0) 2603 2604/* This is how to output an assembler line 2605 that says to advance the location counter 2606 to a multiple of 2**LOG bytes. */ 2607 2608#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2609 if ((LOG) != 0) \ 2610 fprintf (FILE, "\t.align %d\n", (LOG)) 2611 2612/* Pick up the return address upon entry to a procedure. Used for 2613 dwarf2 unwind information. This also enables the table driven 2614 mechanism. */ 2615 2616#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 2617#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) 2618 2619/* Describe how we implement __builtin_eh_return. */ 2620#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2621#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2622 2623/* Print operand X (an rtx) in assembler syntax to file FILE. 2624 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2625 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2626 2627#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2628 2629/* Define which CODE values are valid. */ 2630 2631#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2632 ((CODE) == '.' || (CODE) == '&') 2633 2634/* Print a memory address as an operand to reference that memory location. */ 2635 2636#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2637 2638/* Define the codes that are matched by predicates in rs6000.c. */ 2639 2640#define PREDICATE_CODES \ 2641 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2642 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ 2643 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2644 LABEL_REF, SUBREG, REG, MEM}}, \ 2645 {"short_cint_operand", {CONST_INT}}, \ 2646 {"u_short_cint_operand", {CONST_INT}}, \ 2647 {"non_short_cint_operand", {CONST_INT}}, \ 2648 {"exact_log2_cint_operand", {CONST_INT}}, \ 2649 {"gpc_reg_operand", {SUBREG, REG}}, \ 2650 {"cc_reg_operand", {SUBREG, REG}}, \ 2651 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ 2652 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ 2653 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ 2654 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \ 2655 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ 2656 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ 2657 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ 2658 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \ 2659 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \ 2660 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2661 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ 2662 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ 2663 {"easy_fp_constant", {CONST_DOUBLE}}, \ 2664 {"easy_vector_constant", {CONST_VECTOR}}, \ 2665 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \ 2666 {"zero_fp_constant", {CONST_DOUBLE}}, \ 2667 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ 2668 {"lwa_operand", {SUBREG, MEM, REG}}, \ 2669 {"volatile_mem_operand", {MEM}}, \ 2670 {"offsettable_mem_operand", {MEM}}, \ 2671 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ 2672 {"add_operand", {SUBREG, REG, CONST_INT}}, \ 2673 {"non_add_cint_operand", {CONST_INT}}, \ 2674 {"and_operand", {SUBREG, REG, CONST_INT}}, \ 2675 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2676 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \ 2677 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2678 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ 2679 {"mask_operand", {CONST_INT}}, \ 2680 {"mask_operand_wrap", {CONST_INT}}, \ 2681 {"mask64_operand", {CONST_INT}}, \ 2682 {"mask64_2_operand", {CONST_INT}}, \ 2683 {"count_register_operand", {REG}}, \ 2684 {"xer_operand", {REG}}, \ 2685 {"symbol_ref_operand", {SYMBOL_REF}}, \ 2686 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \ 2687 {"call_operand", {SYMBOL_REF, REG}}, \ 2688 {"current_file_function_operand", {SYMBOL_REF}}, \ 2689 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ 2690 CONST_DOUBLE, SYMBOL_REF}}, \ 2691 {"load_multiple_operation", {PARALLEL}}, \ 2692 {"store_multiple_operation", {PARALLEL}}, \ 2693 {"vrsave_operation", {PARALLEL}}, \ 2694 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ 2695 GT, LEU, LTU, GEU, GTU, \ 2696 UNORDERED, ORDERED, \ 2697 UNGE, UNLE }}, \ 2698 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \ 2699 UNORDERED }}, \ 2700 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ 2701 GT, LEU, LTU, GEU, GTU, \ 2702 UNORDERED, ORDERED, \ 2703 UNGE, UNLE }}, \ 2704 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ 2705 GT, LEU, LTU, GEU, GTU}}, \ 2706 {"boolean_operator", {AND, IOR, XOR}}, \ 2707 {"boolean_or_operator", {IOR, XOR}}, \ 2708 {"altivec_register_operand", {REG}}, \ 2709 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, 2710 2711/* uncomment for disabling the corresponding default options */ 2712/* #define MACHINE_no_sched_interblock */ 2713/* #define MACHINE_no_sched_speculative */ 2714/* #define MACHINE_no_sched_speculative_load */ 2715 2716/* General flags. */ 2717extern int flag_pic; 2718extern int optimize; 2719extern int flag_expensive_optimizations; 2720extern int frame_pointer_needed; 2721 2722enum rs6000_builtins 2723{ 2724 /* AltiVec builtins. */ 2725 ALTIVEC_BUILTIN_ST_INTERNAL_4si, 2726 ALTIVEC_BUILTIN_LD_INTERNAL_4si, 2727 ALTIVEC_BUILTIN_ST_INTERNAL_8hi, 2728 ALTIVEC_BUILTIN_LD_INTERNAL_8hi, 2729 ALTIVEC_BUILTIN_ST_INTERNAL_16qi, 2730 ALTIVEC_BUILTIN_LD_INTERNAL_16qi, 2731 ALTIVEC_BUILTIN_ST_INTERNAL_4sf, 2732 ALTIVEC_BUILTIN_LD_INTERNAL_4sf, 2733 ALTIVEC_BUILTIN_VADDUBM, 2734 ALTIVEC_BUILTIN_VADDUHM, 2735 ALTIVEC_BUILTIN_VADDUWM, 2736 ALTIVEC_BUILTIN_VADDFP, 2737 ALTIVEC_BUILTIN_VADDCUW, 2738 ALTIVEC_BUILTIN_VADDUBS, 2739 ALTIVEC_BUILTIN_VADDSBS, 2740 ALTIVEC_BUILTIN_VADDUHS, 2741 ALTIVEC_BUILTIN_VADDSHS, 2742 ALTIVEC_BUILTIN_VADDUWS, 2743 ALTIVEC_BUILTIN_VADDSWS, 2744 ALTIVEC_BUILTIN_VAND, 2745 ALTIVEC_BUILTIN_VANDC, 2746 ALTIVEC_BUILTIN_VAVGUB, 2747 ALTIVEC_BUILTIN_VAVGSB, 2748 ALTIVEC_BUILTIN_VAVGUH, 2749 ALTIVEC_BUILTIN_VAVGSH, 2750 ALTIVEC_BUILTIN_VAVGUW, 2751 ALTIVEC_BUILTIN_VAVGSW, 2752 ALTIVEC_BUILTIN_VCFUX, 2753 ALTIVEC_BUILTIN_VCFSX, 2754 ALTIVEC_BUILTIN_VCTSXS, 2755 ALTIVEC_BUILTIN_VCTUXS, 2756 ALTIVEC_BUILTIN_VCMPBFP, 2757 ALTIVEC_BUILTIN_VCMPEQUB, 2758 ALTIVEC_BUILTIN_VCMPEQUH, 2759 ALTIVEC_BUILTIN_VCMPEQUW, 2760 ALTIVEC_BUILTIN_VCMPEQFP, 2761 ALTIVEC_BUILTIN_VCMPGEFP, 2762 ALTIVEC_BUILTIN_VCMPGTUB, 2763 ALTIVEC_BUILTIN_VCMPGTSB, 2764 ALTIVEC_BUILTIN_VCMPGTUH, 2765 ALTIVEC_BUILTIN_VCMPGTSH, 2766 ALTIVEC_BUILTIN_VCMPGTUW, 2767 ALTIVEC_BUILTIN_VCMPGTSW, 2768 ALTIVEC_BUILTIN_VCMPGTFP, 2769 ALTIVEC_BUILTIN_VEXPTEFP, 2770 ALTIVEC_BUILTIN_VLOGEFP, 2771 ALTIVEC_BUILTIN_VMADDFP, 2772 ALTIVEC_BUILTIN_VMAXUB, 2773 ALTIVEC_BUILTIN_VMAXSB, 2774 ALTIVEC_BUILTIN_VMAXUH, 2775 ALTIVEC_BUILTIN_VMAXSH, 2776 ALTIVEC_BUILTIN_VMAXUW, 2777 ALTIVEC_BUILTIN_VMAXSW, 2778 ALTIVEC_BUILTIN_VMAXFP, 2779 ALTIVEC_BUILTIN_VMHADDSHS, 2780 ALTIVEC_BUILTIN_VMHRADDSHS, 2781 ALTIVEC_BUILTIN_VMLADDUHM, 2782 ALTIVEC_BUILTIN_VMRGHB, 2783 ALTIVEC_BUILTIN_VMRGHH, 2784 ALTIVEC_BUILTIN_VMRGHW, 2785 ALTIVEC_BUILTIN_VMRGLB, 2786 ALTIVEC_BUILTIN_VMRGLH, 2787 ALTIVEC_BUILTIN_VMRGLW, 2788 ALTIVEC_BUILTIN_VMSUMUBM, 2789 ALTIVEC_BUILTIN_VMSUMMBM, 2790 ALTIVEC_BUILTIN_VMSUMUHM, 2791 ALTIVEC_BUILTIN_VMSUMSHM, 2792 ALTIVEC_BUILTIN_VMSUMUHS, 2793 ALTIVEC_BUILTIN_VMSUMSHS, 2794 ALTIVEC_BUILTIN_VMINUB, 2795 ALTIVEC_BUILTIN_VMINSB, 2796 ALTIVEC_BUILTIN_VMINUH, 2797 ALTIVEC_BUILTIN_VMINSH, 2798 ALTIVEC_BUILTIN_VMINUW, 2799 ALTIVEC_BUILTIN_VMINSW, 2800 ALTIVEC_BUILTIN_VMINFP, 2801 ALTIVEC_BUILTIN_VMULEUB, 2802 ALTIVEC_BUILTIN_VMULESB, 2803 ALTIVEC_BUILTIN_VMULEUH, 2804 ALTIVEC_BUILTIN_VMULESH, 2805 ALTIVEC_BUILTIN_VMULOUB, 2806 ALTIVEC_BUILTIN_VMULOSB, 2807 ALTIVEC_BUILTIN_VMULOUH, 2808 ALTIVEC_BUILTIN_VMULOSH, 2809 ALTIVEC_BUILTIN_VNMSUBFP, 2810 ALTIVEC_BUILTIN_VNOR, 2811 ALTIVEC_BUILTIN_VOR, 2812 ALTIVEC_BUILTIN_VSEL_4SI, 2813 ALTIVEC_BUILTIN_VSEL_4SF, 2814 ALTIVEC_BUILTIN_VSEL_8HI, 2815 ALTIVEC_BUILTIN_VSEL_16QI, 2816 ALTIVEC_BUILTIN_VPERM_4SI, 2817 ALTIVEC_BUILTIN_VPERM_4SF, 2818 ALTIVEC_BUILTIN_VPERM_8HI, 2819 ALTIVEC_BUILTIN_VPERM_16QI, 2820 ALTIVEC_BUILTIN_VPKUHUM, 2821 ALTIVEC_BUILTIN_VPKUWUM, 2822 ALTIVEC_BUILTIN_VPKPX, 2823 ALTIVEC_BUILTIN_VPKUHSS, 2824 ALTIVEC_BUILTIN_VPKSHSS, 2825 ALTIVEC_BUILTIN_VPKUWSS, 2826 ALTIVEC_BUILTIN_VPKSWSS, 2827 ALTIVEC_BUILTIN_VPKUHUS, 2828 ALTIVEC_BUILTIN_VPKSHUS, 2829 ALTIVEC_BUILTIN_VPKUWUS, 2830 ALTIVEC_BUILTIN_VPKSWUS, 2831 ALTIVEC_BUILTIN_VREFP, 2832 ALTIVEC_BUILTIN_VRFIM, 2833 ALTIVEC_BUILTIN_VRFIN, 2834 ALTIVEC_BUILTIN_VRFIP, 2835 ALTIVEC_BUILTIN_VRFIZ, 2836 ALTIVEC_BUILTIN_VRLB, 2837 ALTIVEC_BUILTIN_VRLH, 2838 ALTIVEC_BUILTIN_VRLW, 2839 ALTIVEC_BUILTIN_VRSQRTEFP, 2840 ALTIVEC_BUILTIN_VSLB, 2841 ALTIVEC_BUILTIN_VSLH, 2842 ALTIVEC_BUILTIN_VSLW, 2843 ALTIVEC_BUILTIN_VSL, 2844 ALTIVEC_BUILTIN_VSLO, 2845 ALTIVEC_BUILTIN_VSPLTB, 2846 ALTIVEC_BUILTIN_VSPLTH, 2847 ALTIVEC_BUILTIN_VSPLTW, 2848 ALTIVEC_BUILTIN_VSPLTISB, 2849 ALTIVEC_BUILTIN_VSPLTISH, 2850 ALTIVEC_BUILTIN_VSPLTISW, 2851 ALTIVEC_BUILTIN_VSRB, 2852 ALTIVEC_BUILTIN_VSRH, 2853 ALTIVEC_BUILTIN_VSRW, 2854 ALTIVEC_BUILTIN_VSRAB, 2855 ALTIVEC_BUILTIN_VSRAH, 2856 ALTIVEC_BUILTIN_VSRAW, 2857 ALTIVEC_BUILTIN_VSR, 2858 ALTIVEC_BUILTIN_VSRO, 2859 ALTIVEC_BUILTIN_VSUBUBM, 2860 ALTIVEC_BUILTIN_VSUBUHM, 2861 ALTIVEC_BUILTIN_VSUBUWM, 2862 ALTIVEC_BUILTIN_VSUBFP, 2863 ALTIVEC_BUILTIN_VSUBCUW, 2864 ALTIVEC_BUILTIN_VSUBUBS, 2865 ALTIVEC_BUILTIN_VSUBSBS, 2866 ALTIVEC_BUILTIN_VSUBUHS, 2867 ALTIVEC_BUILTIN_VSUBSHS, 2868 ALTIVEC_BUILTIN_VSUBUWS, 2869 ALTIVEC_BUILTIN_VSUBSWS, 2870 ALTIVEC_BUILTIN_VSUM4UBS, 2871 ALTIVEC_BUILTIN_VSUM4SBS, 2872 ALTIVEC_BUILTIN_VSUM4SHS, 2873 ALTIVEC_BUILTIN_VSUM2SWS, 2874 ALTIVEC_BUILTIN_VSUMSWS, 2875 ALTIVEC_BUILTIN_VXOR, 2876 ALTIVEC_BUILTIN_VSLDOI_16QI, 2877 ALTIVEC_BUILTIN_VSLDOI_8HI, 2878 ALTIVEC_BUILTIN_VSLDOI_4SI, 2879 ALTIVEC_BUILTIN_VSLDOI_4SF, 2880 ALTIVEC_BUILTIN_VUPKHSB, 2881 ALTIVEC_BUILTIN_VUPKHPX, 2882 ALTIVEC_BUILTIN_VUPKHSH, 2883 ALTIVEC_BUILTIN_VUPKLSB, 2884 ALTIVEC_BUILTIN_VUPKLPX, 2885 ALTIVEC_BUILTIN_VUPKLSH, 2886 ALTIVEC_BUILTIN_MTVSCR, 2887 ALTIVEC_BUILTIN_MFVSCR, 2888 ALTIVEC_BUILTIN_DSSALL, 2889 ALTIVEC_BUILTIN_DSS, 2890 ALTIVEC_BUILTIN_LVSL, 2891 ALTIVEC_BUILTIN_LVSR, 2892 ALTIVEC_BUILTIN_DSTT, 2893 ALTIVEC_BUILTIN_DSTST, 2894 ALTIVEC_BUILTIN_DSTSTT, 2895 ALTIVEC_BUILTIN_DST, 2896 ALTIVEC_BUILTIN_LVEBX, 2897 ALTIVEC_BUILTIN_LVEHX, 2898 ALTIVEC_BUILTIN_LVEWX, 2899 ALTIVEC_BUILTIN_LVXL, 2900 ALTIVEC_BUILTIN_LVX, 2901 ALTIVEC_BUILTIN_STVX, 2902 ALTIVEC_BUILTIN_STVEBX, 2903 ALTIVEC_BUILTIN_STVEHX, 2904 ALTIVEC_BUILTIN_STVEWX, 2905 ALTIVEC_BUILTIN_STVXL, 2906 ALTIVEC_BUILTIN_VCMPBFP_P, 2907 ALTIVEC_BUILTIN_VCMPEQFP_P, 2908 ALTIVEC_BUILTIN_VCMPEQUB_P, 2909 ALTIVEC_BUILTIN_VCMPEQUH_P, 2910 ALTIVEC_BUILTIN_VCMPEQUW_P, 2911 ALTIVEC_BUILTIN_VCMPGEFP_P, 2912 ALTIVEC_BUILTIN_VCMPGTFP_P, 2913 ALTIVEC_BUILTIN_VCMPGTSB_P, 2914 ALTIVEC_BUILTIN_VCMPGTSH_P, 2915 ALTIVEC_BUILTIN_VCMPGTSW_P, 2916 ALTIVEC_BUILTIN_VCMPGTUB_P, 2917 ALTIVEC_BUILTIN_VCMPGTUH_P, 2918 ALTIVEC_BUILTIN_VCMPGTUW_P, 2919 ALTIVEC_BUILTIN_ABSS_V4SI, 2920 ALTIVEC_BUILTIN_ABSS_V8HI, 2921 ALTIVEC_BUILTIN_ABSS_V16QI, 2922 ALTIVEC_BUILTIN_ABS_V4SI, 2923 ALTIVEC_BUILTIN_ABS_V4SF, 2924 ALTIVEC_BUILTIN_ABS_V8HI, 2925 ALTIVEC_BUILTIN_ABS_V16QI, 2926 ALTIVEC_BUILTIN_COMPILETIME_ERROR, 2927 /* SPE builtins. */ 2928 SPE_BUILTIN_EVADDW, 2929 SPE_BUILTIN_EVAND, 2930 SPE_BUILTIN_EVANDC, 2931 SPE_BUILTIN_EVDIVWS, 2932 SPE_BUILTIN_EVDIVWU, 2933 SPE_BUILTIN_EVEQV, 2934 SPE_BUILTIN_EVFSADD, 2935 SPE_BUILTIN_EVFSDIV, 2936 SPE_BUILTIN_EVFSMUL, 2937 SPE_BUILTIN_EVFSSUB, 2938 SPE_BUILTIN_EVLDDX, 2939 SPE_BUILTIN_EVLDHX, 2940 SPE_BUILTIN_EVLDWX, 2941 SPE_BUILTIN_EVLHHESPLATX, 2942 SPE_BUILTIN_EVLHHOSSPLATX, 2943 SPE_BUILTIN_EVLHHOUSPLATX, 2944 SPE_BUILTIN_EVLWHEX, 2945 SPE_BUILTIN_EVLWHOSX, 2946 SPE_BUILTIN_EVLWHOUX, 2947 SPE_BUILTIN_EVLWHSPLATX, 2948 SPE_BUILTIN_EVLWWSPLATX, 2949 SPE_BUILTIN_EVMERGEHI, 2950 SPE_BUILTIN_EVMERGEHILO, 2951 SPE_BUILTIN_EVMERGELO, 2952 SPE_BUILTIN_EVMERGELOHI, 2953 SPE_BUILTIN_EVMHEGSMFAA, 2954 SPE_BUILTIN_EVMHEGSMFAN, 2955 SPE_BUILTIN_EVMHEGSMIAA, 2956 SPE_BUILTIN_EVMHEGSMIAN, 2957 SPE_BUILTIN_EVMHEGUMIAA, 2958 SPE_BUILTIN_EVMHEGUMIAN, 2959 SPE_BUILTIN_EVMHESMF, 2960 SPE_BUILTIN_EVMHESMFA, 2961 SPE_BUILTIN_EVMHESMFAAW, 2962 SPE_BUILTIN_EVMHESMFANW, 2963 SPE_BUILTIN_EVMHESMI, 2964 SPE_BUILTIN_EVMHESMIA, 2965 SPE_BUILTIN_EVMHESMIAAW, 2966 SPE_BUILTIN_EVMHESMIANW, 2967 SPE_BUILTIN_EVMHESSF, 2968 SPE_BUILTIN_EVMHESSFA, 2969 SPE_BUILTIN_EVMHESSFAAW, 2970 SPE_BUILTIN_EVMHESSFANW, 2971 SPE_BUILTIN_EVMHESSIAAW, 2972 SPE_BUILTIN_EVMHESSIANW, 2973 SPE_BUILTIN_EVMHEUMI, 2974 SPE_BUILTIN_EVMHEUMIA, 2975 SPE_BUILTIN_EVMHEUMIAAW, 2976 SPE_BUILTIN_EVMHEUMIANW, 2977 SPE_BUILTIN_EVMHEUSIAAW, 2978 SPE_BUILTIN_EVMHEUSIANW, 2979 SPE_BUILTIN_EVMHOGSMFAA, 2980 SPE_BUILTIN_EVMHOGSMFAN, 2981 SPE_BUILTIN_EVMHOGSMIAA, 2982 SPE_BUILTIN_EVMHOGSMIAN, 2983 SPE_BUILTIN_EVMHOGUMIAA, 2984 SPE_BUILTIN_EVMHOGUMIAN, 2985 SPE_BUILTIN_EVMHOSMF, 2986 SPE_BUILTIN_EVMHOSMFA, 2987 SPE_BUILTIN_EVMHOSMFAAW, 2988 SPE_BUILTIN_EVMHOSMFANW, 2989 SPE_BUILTIN_EVMHOSMI, 2990 SPE_BUILTIN_EVMHOSMIA, 2991 SPE_BUILTIN_EVMHOSMIAAW, 2992 SPE_BUILTIN_EVMHOSMIANW, 2993 SPE_BUILTIN_EVMHOSSF, 2994 SPE_BUILTIN_EVMHOSSFA, 2995 SPE_BUILTIN_EVMHOSSFAAW, 2996 SPE_BUILTIN_EVMHOSSFANW, 2997 SPE_BUILTIN_EVMHOSSIAAW, 2998 SPE_BUILTIN_EVMHOSSIANW, 2999 SPE_BUILTIN_EVMHOUMI, 3000 SPE_BUILTIN_EVMHOUMIA, 3001 SPE_BUILTIN_EVMHOUMIAAW, 3002 SPE_BUILTIN_EVMHOUMIANW, 3003 SPE_BUILTIN_EVMHOUSIAAW, 3004 SPE_BUILTIN_EVMHOUSIANW, 3005 SPE_BUILTIN_EVMWHSMF, 3006 SPE_BUILTIN_EVMWHSMFA, 3007 SPE_BUILTIN_EVMWHSMI, 3008 SPE_BUILTIN_EVMWHSMIA, 3009 SPE_BUILTIN_EVMWHSSF, 3010 SPE_BUILTIN_EVMWHSSFA, 3011 SPE_BUILTIN_EVMWHUMI, 3012 SPE_BUILTIN_EVMWHUMIA, 3013 SPE_BUILTIN_EVMWLSMIAAW, 3014 SPE_BUILTIN_EVMWLSMIANW, 3015 SPE_BUILTIN_EVMWLSSIAAW, 3016 SPE_BUILTIN_EVMWLSSIANW, 3017 SPE_BUILTIN_EVMWLUMI, 3018 SPE_BUILTIN_EVMWLUMIA, 3019 SPE_BUILTIN_EVMWLUMIAAW, 3020 SPE_BUILTIN_EVMWLUMIANW, 3021 SPE_BUILTIN_EVMWLUSIAAW, 3022 SPE_BUILTIN_EVMWLUSIANW, 3023 SPE_BUILTIN_EVMWSMF, 3024 SPE_BUILTIN_EVMWSMFA, 3025 SPE_BUILTIN_EVMWSMFAA, 3026 SPE_BUILTIN_EVMWSMFAN, 3027 SPE_BUILTIN_EVMWSMI, 3028 SPE_BUILTIN_EVMWSMIA, 3029 SPE_BUILTIN_EVMWSMIAA, 3030 SPE_BUILTIN_EVMWSMIAN, 3031 SPE_BUILTIN_EVMWHSSFAA, 3032 SPE_BUILTIN_EVMWSSF, 3033 SPE_BUILTIN_EVMWSSFA, 3034 SPE_BUILTIN_EVMWSSFAA, 3035 SPE_BUILTIN_EVMWSSFAN, 3036 SPE_BUILTIN_EVMWUMI, 3037 SPE_BUILTIN_EVMWUMIA, 3038 SPE_BUILTIN_EVMWUMIAA, 3039 SPE_BUILTIN_EVMWUMIAN, 3040 SPE_BUILTIN_EVNAND, 3041 SPE_BUILTIN_EVNOR, 3042 SPE_BUILTIN_EVOR, 3043 SPE_BUILTIN_EVORC, 3044 SPE_BUILTIN_EVRLW, 3045 SPE_BUILTIN_EVSLW, 3046 SPE_BUILTIN_EVSRWS, 3047 SPE_BUILTIN_EVSRWU, 3048 SPE_BUILTIN_EVSTDDX, 3049 SPE_BUILTIN_EVSTDHX, 3050 SPE_BUILTIN_EVSTDWX, 3051 SPE_BUILTIN_EVSTWHEX, 3052 SPE_BUILTIN_EVSTWHOX, 3053 SPE_BUILTIN_EVSTWWEX, 3054 SPE_BUILTIN_EVSTWWOX, 3055 SPE_BUILTIN_EVSUBFW, 3056 SPE_BUILTIN_EVXOR, 3057 SPE_BUILTIN_EVABS, 3058 SPE_BUILTIN_EVADDSMIAAW, 3059 SPE_BUILTIN_EVADDSSIAAW, 3060 SPE_BUILTIN_EVADDUMIAAW, 3061 SPE_BUILTIN_EVADDUSIAAW, 3062 SPE_BUILTIN_EVCNTLSW, 3063 SPE_BUILTIN_EVCNTLZW, 3064 SPE_BUILTIN_EVEXTSB, 3065 SPE_BUILTIN_EVEXTSH, 3066 SPE_BUILTIN_EVFSABS, 3067 SPE_BUILTIN_EVFSCFSF, 3068 SPE_BUILTIN_EVFSCFSI, 3069 SPE_BUILTIN_EVFSCFUF, 3070 SPE_BUILTIN_EVFSCFUI, 3071 SPE_BUILTIN_EVFSCTSF, 3072 SPE_BUILTIN_EVFSCTSI, 3073 SPE_BUILTIN_EVFSCTSIZ, 3074 SPE_BUILTIN_EVFSCTUF, 3075 SPE_BUILTIN_EVFSCTUI, 3076 SPE_BUILTIN_EVFSCTUIZ, 3077 SPE_BUILTIN_EVFSNABS, 3078 SPE_BUILTIN_EVFSNEG, 3079 SPE_BUILTIN_EVMRA, 3080 SPE_BUILTIN_EVNEG, 3081 SPE_BUILTIN_EVRNDW, 3082 SPE_BUILTIN_EVSUBFSMIAAW, 3083 SPE_BUILTIN_EVSUBFSSIAAW, 3084 SPE_BUILTIN_EVSUBFUMIAAW, 3085 SPE_BUILTIN_EVSUBFUSIAAW, 3086 SPE_BUILTIN_EVADDIW, 3087 SPE_BUILTIN_EVLDD, 3088 SPE_BUILTIN_EVLDH, 3089 SPE_BUILTIN_EVLDW, 3090 SPE_BUILTIN_EVLHHESPLAT, 3091 SPE_BUILTIN_EVLHHOSSPLAT, 3092 SPE_BUILTIN_EVLHHOUSPLAT, 3093 SPE_BUILTIN_EVLWHE, 3094 SPE_BUILTIN_EVLWHOS, 3095 SPE_BUILTIN_EVLWHOU, 3096 SPE_BUILTIN_EVLWHSPLAT, 3097 SPE_BUILTIN_EVLWWSPLAT, 3098 SPE_BUILTIN_EVRLWI, 3099 SPE_BUILTIN_EVSLWI, 3100 SPE_BUILTIN_EVSRWIS, 3101 SPE_BUILTIN_EVSRWIU, 3102 SPE_BUILTIN_EVSTDD, 3103 SPE_BUILTIN_EVSTDH, 3104 SPE_BUILTIN_EVSTDW, 3105 SPE_BUILTIN_EVSTWHE, 3106 SPE_BUILTIN_EVSTWHO, 3107 SPE_BUILTIN_EVSTWWE, 3108 SPE_BUILTIN_EVSTWWO, 3109 SPE_BUILTIN_EVSUBIFW, 3110 3111 /* Compares. */ 3112 SPE_BUILTIN_EVCMPEQ, 3113 SPE_BUILTIN_EVCMPGTS, 3114 SPE_BUILTIN_EVCMPGTU, 3115 SPE_BUILTIN_EVCMPLTS, 3116 SPE_BUILTIN_EVCMPLTU, 3117 SPE_BUILTIN_EVFSCMPEQ, 3118 SPE_BUILTIN_EVFSCMPGT, 3119 SPE_BUILTIN_EVFSCMPLT, 3120 SPE_BUILTIN_EVFSTSTEQ, 3121 SPE_BUILTIN_EVFSTSTGT, 3122 SPE_BUILTIN_EVFSTSTLT, 3123 3124 /* EVSEL compares. */ 3125 SPE_BUILTIN_EVSEL_CMPEQ, 3126 SPE_BUILTIN_EVSEL_CMPGTS, 3127 SPE_BUILTIN_EVSEL_CMPGTU, 3128 SPE_BUILTIN_EVSEL_CMPLTS, 3129 SPE_BUILTIN_EVSEL_CMPLTU, 3130 SPE_BUILTIN_EVSEL_FSCMPEQ, 3131 SPE_BUILTIN_EVSEL_FSCMPGT, 3132 SPE_BUILTIN_EVSEL_FSCMPLT, 3133 SPE_BUILTIN_EVSEL_FSTSTEQ, 3134 SPE_BUILTIN_EVSEL_FSTSTGT, 3135 SPE_BUILTIN_EVSEL_FSTSTLT, 3136 3137 SPE_BUILTIN_EVSPLATFI, 3138 SPE_BUILTIN_EVSPLATI, 3139 SPE_BUILTIN_EVMWHSSMAA, 3140 SPE_BUILTIN_EVMWHSMFAA, 3141 SPE_BUILTIN_EVMWHSMIAA, 3142 SPE_BUILTIN_EVMWHUSIAA, 3143 SPE_BUILTIN_EVMWHUMIAA, 3144 SPE_BUILTIN_EVMWHSSFAN, 3145 SPE_BUILTIN_EVMWHSSIAN, 3146 SPE_BUILTIN_EVMWHSMFAN, 3147 SPE_BUILTIN_EVMWHSMIAN, 3148 SPE_BUILTIN_EVMWHUSIAN, 3149 SPE_BUILTIN_EVMWHUMIAN, 3150 SPE_BUILTIN_EVMWHGSSFAA, 3151 SPE_BUILTIN_EVMWHGSMFAA, 3152 SPE_BUILTIN_EVMWHGSMIAA, 3153 SPE_BUILTIN_EVMWHGUMIAA, 3154 SPE_BUILTIN_EVMWHGSSFAN, 3155 SPE_BUILTIN_EVMWHGSMFAN, 3156 SPE_BUILTIN_EVMWHGSMIAN, 3157 SPE_BUILTIN_EVMWHGUMIAN, 3158 SPE_BUILTIN_MTSPEFSCR, 3159 SPE_BUILTIN_MFSPEFSCR, 3160 SPE_BUILTIN_BRINC 3161}; 3162