1/* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 2, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to the 21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24/* Note that some other tm.h files include this one and then override 25 many of the definitions. */ 26 27/* Definitions for the object file format. These are set at 28 compile-time. */ 29 30#define OBJECT_XCOFF 1 31#define OBJECT_ELF 2 32#define OBJECT_PEF 3 33#define OBJECT_MACHO 4 34 35#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 36#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 37#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 38#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 39 40#ifndef TARGET_AIX 41#define TARGET_AIX 0 42#endif 43 44/* Control whether function entry points use a "dot" symbol when 45 ABI_AIX. */ 46#define DOT_SYMBOLS 1 47 48/* Default string to use for cpu if not specified. */ 49#ifndef TARGET_CPU_DEFAULT 50#define TARGET_CPU_DEFAULT ((char *)0) 51#endif 52 53/* If configured for PPC405, support PPC405CR Erratum77. */ 54#ifdef CONFIG_PPC405CR 55#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 56#else 57#define PPC405_ERRATUM77 0 58#endif 59 60/* Common ASM definitions used by ASM_SPEC among the various targets 61 for handling -mcpu=xxx switches. */ 62#define ASM_CPU_SPEC \ 63"%{!mcpu*: \ 64 %{mpower: %{!mpower2: -mpwr}} \ 65 %{mpower2: -mpwrx} \ 66 %{mpowerpc64*: -mppc64} \ 67 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ 68 %{mno-power: %{!mpowerpc*: -mcom}} \ 69 %{!mno-power: %{!mpower*: %(asm_default)}}} \ 70%{mcpu=common: -mcom} \ 71%{mcpu=power: -mpwr} \ 72%{mcpu=power2: -mpwrx} \ 73%{mcpu=power3: -mppc64} \ 74%{mcpu=power4: -mpower4} \ 75%{mcpu=power5: -mpower4} \ 76%{mcpu=power5+: -mpower4} \ 77%{mcpu=power6: -mpower4 -maltivec} \ 78%{mcpu=powerpc: -mppc} \ 79%{mcpu=rios: -mpwr} \ 80%{mcpu=rios1: -mpwr} \ 81%{mcpu=rios2: -mpwrx} \ 82%{mcpu=rsc: -mpwr} \ 83%{mcpu=rsc1: -mpwr} \ 84%{mcpu=rs64a: -mppc64} \ 85%{mcpu=401: -mppc} \ 86%{mcpu=403: -m403} \ 87%{mcpu=405: -m405} \ 88%{mcpu=405fp: -m405} \ 89%{mcpu=440: -m440} \ 90%{mcpu=440fp: -m440} \ 91%{mcpu=505: -mppc} \ 92%{mcpu=601: -m601} \ 93%{mcpu=602: -mppc} \ 94%{mcpu=603: -mppc} \ 95%{mcpu=603e: -mppc} \ 96%{mcpu=ec603e: -mppc} \ 97%{mcpu=604: -mppc} \ 98%{mcpu=604e: -mppc} \ 99%{mcpu=620: -mppc64} \ 100%{mcpu=630: -mppc64} \ 101%{mcpu=740: -mppc} \ 102%{mcpu=750: -mppc} \ 103%{mcpu=G3: -mppc} \ 104%{mcpu=7400: -mppc -maltivec} \ 105%{mcpu=7450: -mppc -maltivec} \ 106%{mcpu=G4: -mppc -maltivec} \ 107%{mcpu=801: -mppc} \ 108%{mcpu=821: -mppc} \ 109%{mcpu=823: -mppc} \ 110%{mcpu=860: -mppc} \ 111%{mcpu=970: -mpower4 -maltivec} \ 112%{mcpu=G5: -mpower4 -maltivec} \ 113%{mcpu=8540: -me500} \ 114%{maltivec: -maltivec} \ 115-many" 116 117#define CPP_DEFAULT_SPEC "" 118 119#define ASM_DEFAULT_SPEC "" 120 121/* This macro defines names of additional specifications to put in the specs 122 that can be used in various specifications like CC1_SPEC. Its definition 123 is an initializer with a subgrouping for each command option. 124 125 Each subgrouping contains a string constant, that defines the 126 specification name, and a string constant that used by the GCC driver 127 program. 128 129 Do not define this macro if it does not need to do anything. */ 130 131#define SUBTARGET_EXTRA_SPECS 132 133#define EXTRA_SPECS \ 134 { "cpp_default", CPP_DEFAULT_SPEC }, \ 135 { "asm_cpu", ASM_CPU_SPEC }, \ 136 { "asm_default", ASM_DEFAULT_SPEC }, \ 137 SUBTARGET_EXTRA_SPECS 138 139/* Architecture type. */ 140 141/* Define TARGET_MFCRF if the target assembler does not support the 142 optional field operand for mfcr. */ 143 144#ifndef HAVE_AS_MFCRF 145#undef TARGET_MFCRF 146#define TARGET_MFCRF 0 147#endif 148 149/* Define TARGET_POPCNTB if the target assembler does not support the 150 popcount byte instruction. */ 151 152#ifndef HAVE_AS_POPCNTB 153#undef TARGET_POPCNTB 154#define TARGET_POPCNTB 0 155#endif 156 157/* Define TARGET_FPRND if the target assembler does not support the 158 fp rounding instructions. */ 159 160#ifndef HAVE_AS_FPRND 161#undef TARGET_FPRND 162#define TARGET_FPRND 0 163#endif 164 165#ifndef TARGET_SECURE_PLT 166#define TARGET_SECURE_PLT 0 167#endif 168 169#define TARGET_32BIT (! TARGET_64BIT) 170 171#ifndef HAVE_AS_TLS 172#define HAVE_AS_TLS 0 173#endif 174 175/* Return 1 for a symbol ref for a thread-local storage symbol. */ 176#define RS6000_SYMBOL_REF_TLS_P(RTX) \ 177 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 178 179#ifdef IN_LIBGCC2 180/* For libgcc2 we make sure this is a compile time constant */ 181#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 182#undef TARGET_POWERPC64 183#define TARGET_POWERPC64 1 184#else 185#undef TARGET_POWERPC64 186#define TARGET_POWERPC64 0 187#endif 188#else 189 /* The option machinery will define this. */ 190#endif 191 192#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) 193 194/* Processor type. Order must match cpu attribute in MD file. */ 195enum processor_type 196 { 197 PROCESSOR_RIOS1, 198 PROCESSOR_RIOS2, 199 PROCESSOR_RS64A, 200 PROCESSOR_MPCCORE, 201 PROCESSOR_PPC403, 202 PROCESSOR_PPC405, 203 PROCESSOR_PPC440, 204 PROCESSOR_PPC601, 205 PROCESSOR_PPC603, 206 PROCESSOR_PPC604, 207 PROCESSOR_PPC604e, 208 PROCESSOR_PPC620, 209 PROCESSOR_PPC630, 210 PROCESSOR_PPC750, 211 PROCESSOR_PPC7400, 212 PROCESSOR_PPC7450, 213 PROCESSOR_PPC8540, 214 PROCESSOR_POWER4, 215 PROCESSOR_POWER5 216}; 217 218extern enum processor_type rs6000_cpu; 219 220/* Recast the processor type to the cpu attribute. */ 221#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 222 223/* Define generic processor types based upon current deployment. */ 224#define PROCESSOR_COMMON PROCESSOR_PPC601 225#define PROCESSOR_POWER PROCESSOR_RIOS1 226#define PROCESSOR_POWERPC PROCESSOR_PPC604 227#define PROCESSOR_POWERPC64 PROCESSOR_RS64A 228 229/* Define the default processor. This is overridden by other tm.h files. */ 230#define PROCESSOR_DEFAULT PROCESSOR_RIOS1 231#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 232 233/* Specify the dialect of assembler to use. New mnemonics is dialect one 234 and the old mnemonics are dialect zero. */ 235#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) 236 237/* Types of costly dependences. */ 238enum rs6000_dependence_cost 239 { 240 max_dep_latency = 1000, 241 no_dep_costly, 242 all_deps_costly, 243 true_store_to_load_dep_costly, 244 store_to_load_dep_costly 245 }; 246 247/* Types of nop insertion schemes in sched target hook sched_finish. */ 248enum rs6000_nop_insertion 249 { 250 sched_finish_regroup_exact = 1000, 251 sched_finish_pad_groups, 252 sched_finish_none 253 }; 254 255/* Dispatch group termination caused by an insn. */ 256enum group_termination 257 { 258 current_group, 259 previous_group 260 }; 261 262/* Support for a compile-time default CPU, et cetera. The rules are: 263 --with-cpu is ignored if -mcpu is specified. 264 --with-tune is ignored if -mtune is specified. 265 --with-float is ignored if -mhard-float or -msoft-float are 266 specified. */ 267#define OPTION_DEFAULT_SPECS \ 268 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 269 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 270 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } 271 272/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ 273struct rs6000_cpu_select 274{ 275 const char *string; 276 const char *name; 277 int set_tune_p; 278 int set_arch_p; 279}; 280 281extern struct rs6000_cpu_select rs6000_select[]; 282 283/* Debug support */ 284extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ 285extern int rs6000_debug_stack; /* debug stack applications */ 286extern int rs6000_debug_arg; /* debug argument handling */ 287 288#define TARGET_DEBUG_STACK rs6000_debug_stack 289#define TARGET_DEBUG_ARG rs6000_debug_arg 290 291extern const char *rs6000_traceback_name; /* Type of traceback table. */ 292 293/* These are separate from target_flags because we've run out of bits 294 there. */ 295extern int rs6000_long_double_type_size; 296extern int rs6000_ieeequad; 297extern int rs6000_altivec_abi; 298extern int rs6000_spe_abi; 299extern int rs6000_float_gprs; 300extern int rs6000_alignment_flags; 301extern const char *rs6000_sched_insert_nops_str; 302extern enum rs6000_nop_insertion rs6000_sched_insert_nops; 303 304/* Alignment options for fields in structures for sub-targets following 305 AIX-like ABI. 306 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 307 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 308 309 Override the macro definitions when compiling libobjc to avoid undefined 310 reference to rs6000_alignment_flags due to library's use of GCC alignment 311 macros which use the macros below. */ 312 313#ifndef IN_TARGET_LIBS 314#define MASK_ALIGN_POWER 0x00000000 315#define MASK_ALIGN_NATURAL 0x00000001 316#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 317#else 318#define TARGET_ALIGN_NATURAL 0 319#endif 320 321#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 322#define TARGET_IEEEQUAD rs6000_ieeequad 323#define TARGET_ALTIVEC_ABI rs6000_altivec_abi 324 325#define TARGET_SPE_ABI 0 326#define TARGET_SPE 0 327#define TARGET_E500 0 328#define TARGET_ISEL 0 329#define TARGET_FPRS 1 330#define TARGET_E500_SINGLE 0 331#define TARGET_E500_DOUBLE 0 332 333/* E500 processors only support plain "sync", not lwsync. */ 334#define TARGET_NO_LWSYNC TARGET_E500 335 336/* Sometimes certain combinations of command options do not make sense 337 on a particular target machine. You can define a macro 338 `OVERRIDE_OPTIONS' to take account of this. This macro, if 339 defined, is executed once just after all the command options have 340 been parsed. 341 342 Do not use this macro to turn on various extra optimizations for 343 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. 344 345 On the RS/6000 this is used to define the target cpu type. */ 346 347#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) 348 349/* Define this to change the optimizations performed by default. */ 350#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) 351 352/* Show we can debug even without a frame pointer. */ 353#define CAN_DEBUG_WITHOUT_FP 354 355/* Target pragma. */ 356#define REGISTER_TARGET_PRAGMAS() do { \ 357 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 358 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 359} while (0) 360 361/* Target #defines. */ 362#define TARGET_CPU_CPP_BUILTINS() \ 363 rs6000_cpu_cpp_builtins (pfile) 364 365/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 366 we're compiling for. Some configurations may need to override it. */ 367#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 368 do \ 369 { \ 370 if (BYTES_BIG_ENDIAN) \ 371 { \ 372 builtin_define ("__BIG_ENDIAN__"); \ 373 builtin_define ("_BIG_ENDIAN"); \ 374 builtin_assert ("machine=bigendian"); \ 375 } \ 376 else \ 377 { \ 378 builtin_define ("__LITTLE_ENDIAN__"); \ 379 builtin_define ("_LITTLE_ENDIAN"); \ 380 builtin_assert ("machine=littleendian"); \ 381 } \ 382 } \ 383 while (0) 384 385/* Target machine storage layout. */ 386 387/* Define this macro if it is advisable to hold scalars in registers 388 in a wider mode than that declared by the program. In such cases, 389 the value is constrained to be within the bounds of the declared 390 type, but kept valid in the wider mode. The signedness of the 391 extension may differ from that of the type. */ 392 393#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 394 if (GET_MODE_CLASS (MODE) == MODE_INT \ 395 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 396 (MODE) = TARGET_32BIT ? SImode : DImode; 397 398/* Define this if most significant bit is lowest numbered 399 in instructions that operate on numbered bit-fields. */ 400/* That is true on RS/6000. */ 401#define BITS_BIG_ENDIAN 1 402 403/* Define this if most significant byte of a word is the lowest numbered. */ 404/* That is true on RS/6000. */ 405#define BYTES_BIG_ENDIAN 1 406 407/* Define this if most significant word of a multiword number is lowest 408 numbered. 409 410 For RS/6000 we can decide arbitrarily since there are no machine 411 instructions for them. Might as well be consistent with bits and bytes. */ 412#define WORDS_BIG_ENDIAN 1 413 414#define MAX_BITS_PER_WORD 64 415 416/* Width of a word, in units (bytes). */ 417#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 418#ifdef IN_LIBGCC2 419#define MIN_UNITS_PER_WORD UNITS_PER_WORD 420#else 421#define MIN_UNITS_PER_WORD 4 422#endif 423#define UNITS_PER_FP_WORD 8 424#define UNITS_PER_ALTIVEC_WORD 16 425#define UNITS_PER_SPE_WORD 8 426 427/* Type used for ptrdiff_t, as a string used in a declaration. */ 428#define PTRDIFF_TYPE "int" 429 430/* Type used for size_t, as a string used in a declaration. */ 431#define SIZE_TYPE "long unsigned int" 432 433/* Type used for wchar_t, as a string used in a declaration. */ 434#define WCHAR_TYPE "short unsigned int" 435 436/* Width of wchar_t in bits. */ 437#define WCHAR_TYPE_SIZE 16 438 439/* A C expression for the size in bits of the type `short' on the 440 target machine. If you don't define this, the default is half a 441 word. (If this would be less than one storage unit, it is 442 rounded up to one unit.) */ 443#define SHORT_TYPE_SIZE 16 444 445/* A C expression for the size in bits of the type `int' on the 446 target machine. If you don't define this, the default is one 447 word. */ 448#define INT_TYPE_SIZE 32 449 450/* A C expression for the size in bits of the type `long' on the 451 target machine. If you don't define this, the default is one 452 word. */ 453#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 454 455/* A C expression for the size in bits of the type `long long' on the 456 target machine. If you don't define this, the default is two 457 words. */ 458#define LONG_LONG_TYPE_SIZE 64 459 460/* A C expression for the size in bits of the type `float' on the 461 target machine. If you don't define this, the default is one 462 word. */ 463#define FLOAT_TYPE_SIZE 32 464 465/* A C expression for the size in bits of the type `double' on the 466 target machine. If you don't define this, the default is two 467 words. */ 468#define DOUBLE_TYPE_SIZE 64 469 470/* A C expression for the size in bits of the type `long double' on 471 the target machine. If you don't define this, the default is two 472 words. */ 473#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 474 475/* Define this to set long double type size to use in libgcc2.c, which can 476 not depend on target_flags. */ 477#ifdef __LONG_DOUBLE_128__ 478#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 479#else 480#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 481#endif 482 483/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 484#define WIDEST_HARDWARE_FP_SIZE 64 485 486/* Width in bits of a pointer. 487 See also the macro `Pmode' defined below. */ 488#define POINTER_SIZE (TARGET_32BIT ? 32 : 64) 489 490/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 491#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 492 493/* Boundary (in *bits*) on which stack pointer should be aligned. */ 494#define STACK_BOUNDARY \ 495 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128) 496 497/* Allocation boundary (in *bits*) for the code of a function. */ 498#define FUNCTION_BOUNDARY 32 499 500/* No data type wants to be aligned rounder than this. */ 501#define BIGGEST_ALIGNMENT 128 502 503/* A C expression to compute the alignment for a variables in the 504 local store. TYPE is the data type, and ALIGN is the alignment 505 that the object would ordinarily have. */ 506#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 507 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ 508 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \ 509 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \ 510 && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) ? 64 : ALIGN) 511 512/* Alignment of field after `int : 0' in a structure. */ 513#define EMPTY_FIELD_BOUNDARY 32 514 515/* Every structure's size must be a multiple of this. */ 516#define STRUCTURE_SIZE_BOUNDARY 8 517 518/* Return 1 if a structure or array containing FIELD should be 519 accessed using `BLKMODE'. 520 521 For the SPE, simd types are V2SI, and gcc can be tempted to put the 522 entire thing in a DI and use subregs to access the internals. 523 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the 524 back-end. Because a single GPR can hold a V2SI, but not a DI, the 525 best thing to do is set structs to BLKmode and avoid Severe Tire 526 Damage. 527 528 On e500 v2, DF and DI modes suffer from the same anomaly. DF can 529 fit into 1, whereas DI still needs two. */ 530#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 531 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ 532 || (TARGET_E500_DOUBLE && (MODE) == DFmode)) 533 534/* A bit-field declared as `int' forces `int' alignment for the struct. */ 535#define PCC_BITFIELD_TYPE_MATTERS 1 536 537/* Make strings word-aligned so strcpy from constants will be faster. 538 Make vector constants quadword aligned. */ 539#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 540 (TREE_CODE (EXP) == STRING_CST \ 541 && (ALIGN) < BITS_PER_WORD \ 542 ? BITS_PER_WORD \ 543 : (ALIGN)) 544 545/* Make arrays of chars word-aligned for the same reasons. 546 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 547 64 bits. */ 548#define DATA_ALIGNMENT(TYPE, ALIGN) \ 549 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ 550 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \ 551 : TREE_CODE (TYPE) == ARRAY_TYPE \ 552 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 553 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 554 555/* Nonzero if move instructions will actually fail to work 556 when given unaligned data. */ 557#define STRICT_ALIGNMENT 0 558 559/* Define this macro to be the value 1 if unaligned accesses have a cost 560 many times greater than aligned accesses, for example if they are 561 emulated in a trap handler. */ 562#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 563 (STRICT_ALIGNMENT \ 564 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 565 || (MODE) == DImode) \ 566 && (ALIGN) < 32)) 567 568/* Standard register usage. */ 569 570/* Number of actual hardware registers. 571 The hardware registers are assigned numbers for the compiler 572 from 0 to just below FIRST_PSEUDO_REGISTER. 573 All registers that the compiler knows about must be given numbers, 574 even those that are not normally considered general registers. 575 576 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 577 an MQ register, a count register, a link register, and 8 condition 578 register fields, which we view here as separate registers. AltiVec 579 adds 32 vector registers and a VRsave register. 580 581 In addition, the difference between the frame and argument pointers is 582 a function of the number of registers saved, so we need to have a 583 register for AP that will later be eliminated in favor of SP or FP. 584 This is a normal register, but it is fixed. 585 586 We also create a pseudo register for float/int conversions, that will 587 really represent the memory location used. It is represented here as 588 a register, in order to work around problems in allocating stack storage 589 in inline functions. 590 591 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 592 pointer, which is eventually eliminated in favor of SP or FP. */ 593 594#define FIRST_PSEUDO_REGISTER 114 595 596/* This must be included for pre gcc 3.0 glibc compatibility. */ 597#define PRE_GCC3_DWARF_FRAME_REGISTERS 77 598 599/* Add 32 dwarf columns for synthetic SPE registers. */ 600#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) 601 602/* The SPE has an additional 32 synthetic registers, with DWARF debug 603 info numbering for these registers starting at 1200. While eh_frame 604 register numbering need not be the same as the debug info numbering, 605 we choose to number these regs for eh_frame at 1200 too. This allows 606 future versions of the rs6000 backend to add hard registers and 607 continue to use the gcc hard register numbering for eh_frame. If the 608 extra SPE registers in eh_frame were numbered starting from the 609 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER 610 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to 611 avoid invalidating older SPE eh_frame info. 612 613 We must map them here to avoid huge unwinder tables mostly consisting 614 of unused space. */ 615#define DWARF_REG_TO_UNWIND_COLUMN(r) \ 616 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) 617 618/* Use standard DWARF numbering for DWARF debugging information. */ 619#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) 620 621/* Use gcc hard register numbering for eh_frame. */ 622#define DWARF_FRAME_REGNUM(REGNO) (REGNO) 623 624/* Map register numbers held in the call frame info that gcc has 625 collected using DWARF_FRAME_REGNUM to those that should be output in 626 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers 627 for .eh_frame, but use the numbers mandated by the various ABIs for 628 .debug_frame. rs6000_emit_prologue has translated any combination of 629 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves 630 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ 631#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 632 ((FOR_EH) ? (REGNO) \ 633 : (REGNO) == CR2_REGNO ? 64 \ 634 : DBX_REGISTER_NUMBER (REGNO)) 635 636/* 1 for registers that have pervasive standard uses 637 and are not available for the register allocator. 638 639 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 640 as a local register; for all other OS's r2 is the TOC pointer. 641 642 cr5 is not supposed to be used. 643 644 On System V implementations, r13 is fixed and not available for use. */ 645 646#define FIXED_REGISTERS \ 647 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 651 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 652 /* AltiVec registers. */ \ 653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 655 1, 1 \ 656 , 1, 1, 1 \ 657} 658 659/* 1 for registers not available across function calls. 660 These must include the FIXED_REGISTERS and also any 661 registers that can be used without being saved. 662 The latter must include the registers where values are returned 663 and the register where structure-value addresses are passed. 664 Aside from that, you can include as many other registers as you like. */ 665 666#define CALL_USED_REGISTERS \ 667 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 669 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 670 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 671 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 672 /* AltiVec registers. */ \ 673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 675 1, 1 \ 676 , 1, 1, 1 \ 677} 678 679/* Like `CALL_USED_REGISTERS' except this macro doesn't require that 680 the entire set of `FIXED_REGISTERS' be included. 681 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 682 This macro is optional. If not specified, it defaults to the value 683 of `CALL_USED_REGISTERS'. */ 684 685#define CALL_REALLY_USED_REGISTERS \ 686 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 688 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 690 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 691 /* AltiVec registers. */ \ 692 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 693 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 694 0, 0 \ 695 , 0, 0, 0 \ 696} 697 698#define MQ_REGNO 64 699#define CR0_REGNO 68 700#define CR1_REGNO 69 701#define CR2_REGNO 70 702#define CR3_REGNO 71 703#define CR4_REGNO 72 704#define MAX_CR_REGNO 75 705#define XER_REGNO 76 706#define FIRST_ALTIVEC_REGNO 77 707#define LAST_ALTIVEC_REGNO 108 708#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 709#define VRSAVE_REGNO 109 710#define VSCR_REGNO 110 711#define SPE_ACC_REGNO 111 712#define SPEFSCR_REGNO 112 713 714#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 715#define FIRST_SAVED_FP_REGNO (14+32) 716#define FIRST_SAVED_GP_REGNO 13 717 718/* List the order in which to allocate registers. Each register must be 719 listed once, even those in FIXED_REGISTERS. 720 721 We allocate in the following order: 722 fp0 (not saved or used for anything) 723 fp13 - fp2 (not saved; incoming fp arg registers) 724 fp1 (not saved; return value) 725 fp31 - fp14 (saved; order given to save least number) 726 cr7, cr6 (not saved or special) 727 cr1 (not saved, but used for FP operations) 728 cr0 (not saved, but used for arithmetic operations) 729 cr4, cr3, cr2 (saved) 730 r0 (not saved; cannot be base reg) 731 r9 (not saved; best for TImode) 732 r11, r10, r8-r4 (not saved; highest used first to make less conflict) 733 r3 (not saved; return value register) 734 r31 - r13 (saved; order given to save least number) 735 r12 (not saved; if used for DImode or DFmode would use r13) 736 mq (not saved; best to use it if we can) 737 ctr (not saved; when we have the choice ctr is better) 738 lr (saved) 739 cr5, r1, r2, ap, xer (fixed) 740 v0 - v1 (not saved or used for anything) 741 v13 - v3 (not saved; incoming vector arg registers) 742 v2 (not saved; incoming vector arg reg; return value) 743 v19 - v14 (not saved or used for anything) 744 v31 - v20 (saved; order given to save least number) 745 vrsave, vscr (fixed) 746 spe_acc, spefscr (fixed) 747 sfp (fixed) 748*/ 749 750#if FIXED_R2 == 1 751#define MAYBE_R2_AVAILABLE 752#define MAYBE_R2_FIXED 2, 753#else 754#define MAYBE_R2_AVAILABLE 2, 755#define MAYBE_R2_FIXED 756#endif 757 758#define REG_ALLOC_ORDER \ 759 {32, \ 760 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 761 33, \ 762 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 763 50, 49, 48, 47, 46, \ 764 75, 74, 69, 68, 72, 71, 70, \ 765 0, MAYBE_R2_AVAILABLE \ 766 9, 11, 10, 8, 7, 6, 5, 4, \ 767 3, \ 768 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 769 18, 17, 16, 15, 14, 13, 12, \ 770 64, 66, 65, \ 771 73, 1, MAYBE_R2_FIXED 67, 76, \ 772 /* AltiVec registers. */ \ 773 77, 78, \ 774 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 775 79, \ 776 96, 95, 94, 93, 92, 91, \ 777 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 778 109, 110, \ 779 111, 112, 113 \ 780} 781 782/* True if register is floating-point. */ 783#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 784 785/* True if register is a condition register. */ 786#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) 787 788/* True if register is a condition register, but not cr0. */ 789#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) 790 791/* True if register is an integer register. */ 792#define INT_REGNO_P(N) \ 793 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 794 795/* SPE SIMD registers are just the GPRs. */ 796#define SPE_SIMD_REGNO_P(N) ((N) <= 31) 797 798/* True if register is the XER register. */ 799#define XER_REGNO_P(N) ((N) == XER_REGNO) 800 801/* True if register is an AltiVec register. */ 802#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 803 804/* Return number of consecutive hard regs needed starting at reg REGNO 805 to hold something of mode MODE. */ 806 807#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE)) 808 809#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 810 ((TARGET_32BIT && TARGET_POWERPC64 \ 811 && (GET_MODE_SIZE (MODE) > 4) \ 812 && INT_REGNO_P (REGNO)) ? 1 : 0) 813 814#define ALTIVEC_VECTOR_MODE(MODE) \ 815 ((MODE) == V16QImode \ 816 || (MODE) == V8HImode \ 817 || (MODE) == V4SFmode \ 818 || (MODE) == V4SImode) 819 820#define SPE_VECTOR_MODE(MODE) \ 821 ((MODE) == V4HImode \ 822 || (MODE) == V2SFmode \ 823 || (MODE) == V1DImode \ 824 || (MODE) == V2SImode) 825 826#define UNITS_PER_SIMD_WORD \ 827 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \ 828 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD)) 829 830/* Value is TRUE if hard register REGNO can hold a value of 831 machine-mode MODE. */ 832#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 833 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 834 835/* Value is 1 if it is a good idea to tie two pseudo registers 836 when one has mode MODE1 and one has mode MODE2. 837 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 838 for any hard reg, then this must be 0 for correct output. */ 839#define MODES_TIEABLE_P(MODE1, MODE2) \ 840 (SCALAR_FLOAT_MODE_P (MODE1) \ 841 ? SCALAR_FLOAT_MODE_P (MODE2) \ 842 : SCALAR_FLOAT_MODE_P (MODE2) \ 843 ? SCALAR_FLOAT_MODE_P (MODE1) \ 844 : GET_MODE_CLASS (MODE1) == MODE_CC \ 845 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 846 : GET_MODE_CLASS (MODE2) == MODE_CC \ 847 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 848 : SPE_VECTOR_MODE (MODE1) \ 849 ? SPE_VECTOR_MODE (MODE2) \ 850 : SPE_VECTOR_MODE (MODE2) \ 851 ? SPE_VECTOR_MODE (MODE1) \ 852 : ALTIVEC_VECTOR_MODE (MODE1) \ 853 ? ALTIVEC_VECTOR_MODE (MODE2) \ 854 : ALTIVEC_VECTOR_MODE (MODE2) \ 855 ? ALTIVEC_VECTOR_MODE (MODE1) \ 856 : 1) 857 858/* Post-reload, we can't use any new AltiVec registers, as we already 859 emitted the vrsave mask. */ 860 861#define HARD_REGNO_RENAME_OK(SRC, DST) \ 862 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST]) 863 864/* A C expression returning the cost of moving data from a register of class 865 CLASS1 to one of CLASS2. */ 866 867#define REGISTER_MOVE_COST rs6000_register_move_cost 868 869/* A C expressions returning the cost of moving data of MODE from a register to 870 or from memory. */ 871 872#define MEMORY_MOVE_COST rs6000_memory_move_cost 873 874/* Specify the cost of a branch insn; roughly the number of extra insns that 875 should be added to avoid a branch. 876 877 Set this to 3 on the RS/6000 since that is roughly the average cost of an 878 unscheduled conditional branch. */ 879 880#define BRANCH_COST 3 881 882/* Override BRANCH_COST heuristic which empirically produces worse 883 performance for removing short circuiting from the logical ops. */ 884 885#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 886 887/* A fixed register used at prologue and epilogue generation to fix 888 addressing modes. The SPE needs heavy addressing fixes at the last 889 minute, and it's best to save a register for it. 890 891 AltiVec also needs fixes, but we've gotten around using r11, which 892 is actually wrong because when use_backchain_to_restore_sp is true, 893 we end up clobbering r11. 894 895 The AltiVec case needs to be fixed. Dunno if we should break ABI 896 compatibility and reserve a register for it as well.. */ 897 898#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) 899 900/* Define this macro to change register usage conditional on target 901 flags. */ 902 903#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage () 904 905/* Specify the registers used for certain standard purposes. 906 The values of these macros are register numbers. */ 907 908/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 909/* #define PC_REGNUM */ 910 911/* Register to use for pushing function arguments. */ 912#define STACK_POINTER_REGNUM 1 913 914/* Base register for access to local variables of the function. */ 915#define HARD_FRAME_POINTER_REGNUM 31 916 917/* Base register for access to local variables of the function. */ 918#define FRAME_POINTER_REGNUM 113 919 920/* Value should be nonzero if functions must have frame pointers. 921 Zero means the frame pointer need not be set up (and parms 922 may be accessed via the stack pointer) in functions that seem suitable. 923 This is computed in `reload', in reload1.c. */ 924#define FRAME_POINTER_REQUIRED 0 925 926/* Base register for access to arguments of the function. */ 927#define ARG_POINTER_REGNUM 67 928 929/* Place to put static chain when calling a function that requires it. */ 930#define STATIC_CHAIN_REGNUM 11 931 932/* Link register number. */ 933#define LINK_REGISTER_REGNUM 65 934 935/* Count register number. */ 936#define COUNT_REGISTER_REGNUM 66 937 938/* Define the classes of registers for register constraints in the 939 machine description. Also define ranges of constants. 940 941 One of the classes must always be named ALL_REGS and include all hard regs. 942 If there is more than one class, another class must be named NO_REGS 943 and contain no registers. 944 945 The name GENERAL_REGS must be the name of a class (or an alias for 946 another name such as ALL_REGS). This is the class of registers 947 that is allowed by "g" or "r" in a register constraint. 948 Also, registers outside this class are allocated only when 949 instructions express preferences for them. 950 951 The classes must be numbered in nondecreasing order; that is, 952 a larger-numbered class must never be contained completely 953 in a smaller-numbered class. 954 955 For any two classes, it is very desirable that there be another 956 class that represents their union. */ 957 958/* The RS/6000 has three types of registers, fixed-point, floating-point, 959 and condition registers, plus three special registers, MQ, CTR, and the 960 link register. AltiVec adds a vector register class. 961 962 However, r0 is special in that it cannot be used as a base register. 963 So make a class for registers valid as base registers. 964 965 Also, cr0 is the only condition code register that can be used in 966 arithmetic insns, so make a separate class for it. */ 967 968enum reg_class 969{ 970 NO_REGS, 971 BASE_REGS, 972 GENERAL_REGS, 973 FLOAT_REGS, 974 ALTIVEC_REGS, 975 VRSAVE_REGS, 976 VSCR_REGS, 977 SPE_ACC_REGS, 978 SPEFSCR_REGS, 979 NON_SPECIAL_REGS, 980 MQ_REGS, 981 LINK_REGS, 982 CTR_REGS, 983 LINK_OR_CTR_REGS, 984 SPECIAL_REGS, 985 SPEC_OR_GEN_REGS, 986 CR0_REGS, 987 CR_REGS, 988 NON_FLOAT_REGS, 989 XER_REGS, 990 ALL_REGS, 991 LIM_REG_CLASSES 992}; 993 994#define N_REG_CLASSES (int) LIM_REG_CLASSES 995 996/* Give names of register classes as strings for dump file. */ 997 998#define REG_CLASS_NAMES \ 999{ \ 1000 "NO_REGS", \ 1001 "BASE_REGS", \ 1002 "GENERAL_REGS", \ 1003 "FLOAT_REGS", \ 1004 "ALTIVEC_REGS", \ 1005 "VRSAVE_REGS", \ 1006 "VSCR_REGS", \ 1007 "SPE_ACC_REGS", \ 1008 "SPEFSCR_REGS", \ 1009 "NON_SPECIAL_REGS", \ 1010 "MQ_REGS", \ 1011 "LINK_REGS", \ 1012 "CTR_REGS", \ 1013 "LINK_OR_CTR_REGS", \ 1014 "SPECIAL_REGS", \ 1015 "SPEC_OR_GEN_REGS", \ 1016 "CR0_REGS", \ 1017 "CR_REGS", \ 1018 "NON_FLOAT_REGS", \ 1019 "XER_REGS", \ 1020 "ALL_REGS" \ 1021} 1022 1023/* Define which registers fit in which classes. 1024 This is an initializer for a vector of HARD_REG_SET 1025 of length N_REG_CLASSES. */ 1026 1027#define REG_CLASS_CONTENTS \ 1028{ \ 1029 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1030 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ 1031 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ 1032 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1033 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1034 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1035 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1036 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1037 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1038 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ 1039 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ 1040 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1041 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1042 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1043 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ 1044 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ 1045 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1046 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1047 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \ 1048 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ 1049 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ 1050} 1051 1052/* The same information, inverted: 1053 Return the class number of the smallest class containing 1054 reg number REGNO. This could be a conditional expression 1055 or could index an array. */ 1056 1057#define REGNO_REG_CLASS(REGNO) \ 1058 ((REGNO) == 0 ? GENERAL_REGS \ 1059 : (REGNO) < 32 ? BASE_REGS \ 1060 : FP_REGNO_P (REGNO) ? FLOAT_REGS \ 1061 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ 1062 : (REGNO) == CR0_REGNO ? CR0_REGS \ 1063 : CR_REGNO_P (REGNO) ? CR_REGS \ 1064 : (REGNO) == MQ_REGNO ? MQ_REGS \ 1065 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ 1066 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ 1067 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ 1068 : (REGNO) == XER_REGNO ? XER_REGS \ 1069 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ 1070 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ 1071 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ 1072 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ 1073 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \ 1074 : NO_REGS) 1075 1076/* The class value for index registers, and the one for base regs. */ 1077#define INDEX_REG_CLASS GENERAL_REGS 1078#define BASE_REG_CLASS BASE_REGS 1079 1080/* Given an rtx X being reloaded into a reg required to be 1081 in class CLASS, return the class of reg to actually use. 1082 In general this is just CLASS; but on some machines 1083 in some cases it is preferable to use a more restrictive class. 1084 1085 On the RS/6000, we have to return NO_REGS when we want to reload a 1086 floating-point CONST_DOUBLE to force it to be copied to memory. 1087 1088 We also don't want to reload integer values into floating-point 1089 registers if we can at all help it. In fact, this can 1090 cause reload to die, if it tries to generate a reload of CTR 1091 into a FP register and discovers it doesn't have the memory location 1092 required. 1093 1094 ??? Would it be a good idea to have reload do the converse, that is 1095 try to reload floating modes into FP registers if possible? 1096 */ 1097 1098#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1099 ((CONSTANT_P (X) \ 1100 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \ 1101 ? NO_REGS \ 1102 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 1103 && (CLASS) == NON_SPECIAL_REGS) \ 1104 ? GENERAL_REGS \ 1105 : (CLASS)) 1106 1107/* Return the register class of a scratch register needed to copy IN into 1108 or out of a register in CLASS in MODE. If it can be done directly, 1109 NO_REGS is returned. */ 1110 1111#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1112 rs6000_secondary_reload_class (CLASS, MODE, IN) 1113 1114/* If we are copying between FP or AltiVec registers and anything 1115 else, we need a memory location. */ 1116 1117#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1118 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ 1119 || (CLASS2) == FLOAT_REGS \ 1120 || (CLASS1) == ALTIVEC_REGS \ 1121 || (CLASS2) == ALTIVEC_REGS)) 1122 1123/* Return the maximum number of consecutive registers 1124 needed to represent mode MODE in a register of class CLASS. 1125 1126 On RS/6000, this is the size of MODE in words, 1127 except in the FP regs, where a single reg is enough for two words. */ 1128#define CLASS_MAX_NREGS(CLASS, MODE) \ 1129 (((CLASS) == FLOAT_REGS) \ 1130 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 1131 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \ 1132 ? 1 \ 1133 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1134 1135/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1136 1137#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1138 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1139 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \ 1140 || TARGET_IEEEQUAD) \ 1141 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \ 1142 : (((TARGET_E500_DOUBLE \ 1143 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \ 1144 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \ 1145 || (TARGET_SPE \ 1146 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \ 1147 && reg_classes_intersect_p (GENERAL_REGS, CLASS))) 1148 1149/* Stack layout; function entry, exit and calling. */ 1150 1151/* Enumeration to give which calling sequence to use. */ 1152enum rs6000_abi { 1153 ABI_NONE, 1154 ABI_AIX, /* IBM's AIX */ 1155 ABI_V4, /* System V.4/eabi */ 1156 ABI_DARWIN /* Apple's Darwin (OS X kernel) */ 1157}; 1158 1159extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ 1160 1161/* Define this if pushing a word on the stack 1162 makes the stack pointer a smaller address. */ 1163#define STACK_GROWS_DOWNWARD 1164 1165/* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1166#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1167 1168/* Define this to nonzero if the nominal address of the stack frame 1169 is at the high-address end of the local variables; 1170 that is, each additional local variable allocated 1171 goes at a more negative offset in the frame. 1172 1173 On the RS/6000, we grow upwards, from the area after the outgoing 1174 arguments. */ 1175#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0) 1176 1177/* Size of the outgoing register save area */ 1178#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1179 || DEFAULT_ABI == ABI_DARWIN) \ 1180 ? (TARGET_64BIT ? 64 : 32) \ 1181 : 0) 1182 1183/* Size of the fixed area on the stack */ 1184#define RS6000_SAVE_AREA \ 1185 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1186 << (TARGET_64BIT ? 1 : 0)) 1187 1188/* MEM representing address to save the TOC register */ 1189#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1190 plus_constant (stack_pointer_rtx, \ 1191 (TARGET_32BIT ? 20 : 40))) 1192 1193/* Align an address */ 1194#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1195 1196/* Offset within stack frame to start allocating local variables at. 1197 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1198 first local allocated. Otherwise, it is the offset to the BEGINNING 1199 of the first local allocated. 1200 1201 On the RS/6000, the frame pointer is the same as the stack pointer, 1202 except for dynamic allocations. So we start after the fixed area and 1203 outgoing parameter area. */ 1204 1205#define STARTING_FRAME_OFFSET \ 1206 (FRAME_GROWS_DOWNWARD \ 1207 ? 0 \ 1208 : (RS6000_ALIGN (current_function_outgoing_args_size, \ 1209 TARGET_ALTIVEC ? 16 : 8) \ 1210 + RS6000_SAVE_AREA)) 1211 1212/* Offset from the stack pointer register to an item dynamically 1213 allocated on the stack, e.g., by `alloca'. 1214 1215 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1216 length of the outgoing arguments. The default is correct for most 1217 machines. See `function.c' for details. */ 1218#define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1219 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1220 TARGET_ALTIVEC ? 16 : 8) \ 1221 + (STACK_POINTER_OFFSET)) 1222 1223/* If we generate an insn to push BYTES bytes, 1224 this says how many the stack pointer really advances by. 1225 On RS/6000, don't define this because there are no push insns. */ 1226/* #define PUSH_ROUNDING(BYTES) */ 1227 1228/* Offset of first parameter from the argument pointer register value. 1229 On the RS/6000, we define the argument pointer to the start of the fixed 1230 area. */ 1231#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1232 1233/* Offset from the argument pointer register value to the top of 1234 stack. This is different from FIRST_PARM_OFFSET because of the 1235 register save area. */ 1236#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1237 1238/* Define this if stack space is still allocated for a parameter passed 1239 in a register. The value is the number of bytes allocated to this 1240 area. */ 1241#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1242 1243/* Define this if the above stack space is to be considered part of the 1244 space allocated by the caller. */ 1245#define OUTGOING_REG_PARM_STACK_SPACE 1246 1247/* This is the difference between the logical top of stack and the actual sp. 1248 1249 For the RS/6000, sp points past the fixed area. */ 1250#define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1251 1252/* Define this if the maximum size of all the outgoing args is to be 1253 accumulated and pushed during the prologue. The amount can be 1254 found in the variable current_function_outgoing_args_size. */ 1255#define ACCUMULATE_OUTGOING_ARGS 1 1256 1257/* Value is the number of bytes of arguments automatically 1258 popped when returning from a subroutine call. 1259 FUNDECL is the declaration node of the function (as a tree), 1260 FUNTYPE is the data type of the function (as a tree), 1261 or for a library call it is an identifier node for the subroutine name. 1262 SIZE is the number of bytes of arguments passed on the stack. */ 1263 1264#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1265 1266/* Define how to find the value returned by a function. 1267 VALTYPE is the data type of the value (as a tree). 1268 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1269 otherwise, FUNC is 0. */ 1270 1271#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC)) 1272 1273/* Define how to find the value returned by a library function 1274 assuming the value has mode MODE. */ 1275 1276#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1277 1278/* DRAFT_V4_STRUCT_RET defaults off. */ 1279#define DRAFT_V4_STRUCT_RET 0 1280 1281/* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1282#define DEFAULT_PCC_STRUCT_RETURN 0 1283 1284/* Mode of stack savearea. 1285 FUNCTION is VOIDmode because calling convention maintains SP. 1286 BLOCK needs Pmode for SP. 1287 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1288#define STACK_SAVEAREA_MODE(LEVEL) \ 1289 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1290 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1291 1292/* Minimum and maximum general purpose registers used to hold arguments. */ 1293#define GP_ARG_MIN_REG 3 1294#define GP_ARG_MAX_REG 10 1295#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1296 1297/* Minimum and maximum floating point registers used to hold arguments. */ 1298#define FP_ARG_MIN_REG 33 1299#define FP_ARG_AIX_MAX_REG 45 1300#define FP_ARG_V4_MAX_REG 40 1301#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1302 || DEFAULT_ABI == ABI_DARWIN) \ 1303 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1304#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1305 1306/* Minimum and maximum AltiVec registers used to hold arguments. */ 1307#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1308#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1309#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1310 1311/* Return registers */ 1312#define GP_ARG_RETURN GP_ARG_MIN_REG 1313#define FP_ARG_RETURN FP_ARG_MIN_REG 1314#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1315 1316/* Flags for the call/call_value rtl operations set up by function_arg */ 1317#define CALL_NORMAL 0x00000000 /* no special processing */ 1318/* Bits in 0x00000001 are unused. */ 1319#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1320#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1321#define CALL_LONG 0x00000008 /* always call indirect */ 1322#define CALL_LIBCALL 0x00000010 /* libcall */ 1323 1324/* We don't have prologue and epilogue functions to save/restore 1325 everything for most ABIs. */ 1326#define WORLD_SAVE_P(INFO) 0 1327 1328/* 1 if N is a possible register number for a function value 1329 as seen by the caller. 1330 1331 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1332#define FUNCTION_VALUE_REGNO_P(N) \ 1333 ((N) == GP_ARG_RETURN \ 1334 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1335 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1336 1337/* 1 if N is a possible register number for function argument passing. 1338 On RS/6000, these are r3-r10 and fp1-fp13. 1339 On AltiVec, v2 - v13 are used for passing vectors. */ 1340#define FUNCTION_ARG_REGNO_P(N) \ 1341 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1342 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1343 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1344 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1345 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1346 1347/* Define a data type for recording info about an argument list 1348 during the scan of that argument list. This data type should 1349 hold all necessary information about the function itself 1350 and about the args processed so far, enough to enable macros 1351 such as FUNCTION_ARG to determine where the next arg should go. 1352 1353 On the RS/6000, this is a structure. The first element is the number of 1354 total argument words, the second is used to store the next 1355 floating-point register number, and the third says how many more args we 1356 have prototype types for. 1357 1358 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1359 the next available GP register, `fregno' is the next available FP 1360 register, and `words' is the number of words used on the stack. 1361 1362 The varargs/stdarg support requires that this structure's size 1363 be a multiple of sizeof(int). */ 1364 1365typedef struct rs6000_args 1366{ 1367 int words; /* # words used for passing GP registers */ 1368 int fregno; /* next available FP register */ 1369 int vregno; /* next available AltiVec register */ 1370 int nargs_prototype; /* # args left in the current prototype */ 1371 int prototype; /* Whether a prototype was defined */ 1372 int stdarg; /* Whether function is a stdarg function. */ 1373 int call_cookie; /* Do special things for this call */ 1374 int sysv_gregno; /* next available GP register */ 1375 int intoffset; /* running offset in struct (darwin64) */ 1376 int use_stack; /* any part of struct on stack (darwin64) */ 1377 int named; /* false for varargs params */ 1378} CUMULATIVE_ARGS; 1379 1380/* Initialize a variable CUM of type CUMULATIVE_ARGS 1381 for a call to a function whose data type is FNTYPE. 1382 For a library call, FNTYPE is 0. */ 1383 1384#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1385 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS) 1386 1387/* Similar, but when scanning the definition of a procedure. We always 1388 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1389 1390#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1391 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000) 1392 1393/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1394 1395#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1396 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0) 1397 1398/* Update the data in CUM to advance over an argument 1399 of mode MODE and data type TYPE. 1400 (TYPE is null for libcalls where that information may not be available.) */ 1401 1402#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1403 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0) 1404 1405/* Determine where to put an argument to a function. 1406 Value is zero to push the argument on the stack, 1407 or a hard register in which to store the argument. 1408 1409 MODE is the argument's machine mode. 1410 TYPE is the data type of the argument (as a tree). 1411 This is null for libcalls where that information may 1412 not be available. 1413 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1414 the preceding args and about the function being called. 1415 NAMED is nonzero if this argument is a named parameter 1416 (otherwise it is an extra parameter matching an ellipsis). 1417 1418 On RS/6000 the first eight words of non-FP are normally in registers 1419 and the rest are pushed. The first 13 FP args are in registers. 1420 1421 If this is floating-point and no prototype is specified, we use 1422 both an FP and integer register (or possibly FP reg and stack). Library 1423 functions (when TYPE is zero) always have the proper types for args, 1424 so we can pass the FP value just in one register. emit_library_function 1425 doesn't support EXPR_LIST anyway. */ 1426 1427#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1428 function_arg (&CUM, MODE, TYPE, NAMED) 1429 1430/* If defined, a C expression which determines whether, and in which 1431 direction, to pad out an argument with extra space. The value 1432 should be of type `enum direction': either `upward' to pad above 1433 the argument, `downward' to pad below, or `none' to inhibit 1434 padding. */ 1435 1436#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1437 1438/* If defined, a C expression that gives the alignment boundary, in bits, 1439 of an argument with the specified mode and type. If it is not defined, 1440 PARM_BOUNDARY is used for all arguments. */ 1441 1442#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1443 function_arg_boundary (MODE, TYPE) 1444 1445/* Implement `va_start' for varargs and stdarg. */ 1446#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1447 rs6000_va_start (valist, nextarg) 1448 1449#define PAD_VARARGS_DOWN \ 1450 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1451 1452/* Output assembler code to FILE to increment profiler label # LABELNO 1453 for profiling a function entry. */ 1454 1455#define FUNCTION_PROFILER(FILE, LABELNO) \ 1456 output_function_profiler ((FILE), (LABELNO)); 1457 1458/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1459 the stack pointer does not matter. No definition is equivalent to 1460 always zero. 1461 1462 On the RS/6000, this is nonzero because we can restore the stack from 1463 its backpointer, which we maintain. */ 1464#define EXIT_IGNORE_STACK 1 1465 1466/* Define this macro as a C expression that is nonzero for registers 1467 that are used by the epilogue or the return' pattern. The stack 1468 and frame pointer registers are already be assumed to be used as 1469 needed. */ 1470 1471#define EPILOGUE_USES(REGNO) \ 1472 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ 1473 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1474 || (current_function_calls_eh_return \ 1475 && TARGET_AIX \ 1476 && (REGNO) == 2)) 1477 1478 1479/* TRAMPOLINE_TEMPLATE deleted */ 1480 1481/* Length in units of the trampoline for entering a nested function. */ 1482 1483#define TRAMPOLINE_SIZE rs6000_trampoline_size () 1484 1485/* Emit RTL insns to initialize the variable parts of a trampoline. 1486 FNADDR is an RTX for the address of the function's pure code. 1487 CXT is an RTX for the static chain value for the function. */ 1488 1489#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ 1490 rs6000_initialize_trampoline (ADDR, FNADDR, CXT) 1491 1492/* Definitions for __builtin_return_address and __builtin_frame_address. 1493 __builtin_return_address (0) should give link register (65), enable 1494 this. */ 1495/* This should be uncommented, so that the link register is used, but 1496 currently this would result in unmatched insns and spilling fixed 1497 registers so we'll leave it for another day. When these problems are 1498 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1499 (mrs) */ 1500/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1501 1502/* Number of bytes into the frame return addresses can be found. See 1503 rs6000_stack_info in rs6000.c for more information on how the different 1504 abi's store the return address. */ 1505#define RETURN_ADDRESS_OFFSET \ 1506 ((DEFAULT_ABI == ABI_AIX \ 1507 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ 1508 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1509 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1510 1511/* The current return address is in link register (65). The return address 1512 of anything farther back is accessed normally at an offset of 8 from the 1513 frame pointer. */ 1514#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1515 (rs6000_return_addr (COUNT, FRAME)) 1516 1517 1518/* Definitions for register eliminations. 1519 1520 We have two registers that can be eliminated on the RS/6000. First, the 1521 frame pointer register can often be eliminated in favor of the stack 1522 pointer register. Secondly, the argument pointer register can always be 1523 eliminated; it is replaced with either the stack or frame pointer. 1524 1525 In addition, we use the elimination mechanism to see if r30 is needed 1526 Initially we assume that it isn't. If it is, we spill it. This is done 1527 by making it an eliminable register. We replace it with itself so that 1528 if it isn't needed, then existing uses won't be modified. */ 1529 1530/* This is an array of structures. Each structure initializes one pair 1531 of eliminable registers. The "from" register number is given first, 1532 followed by "to". Eliminations of the same "from" register are listed 1533 in order of preference. */ 1534#define ELIMINABLE_REGS \ 1535{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1536 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1537 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1538 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1539 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1540 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1541 1542/* Given FROM and TO register numbers, say whether this elimination is allowed. 1543 Frame pointer elimination is automatically handled. 1544 1545 For the RS/6000, if frame pointer elimination is being done, we would like 1546 to convert ap into fp, not sp. 1547 1548 We need r30 if -mminimal-toc was specified, and there are constant pool 1549 references. */ 1550 1551#define CAN_ELIMINATE(FROM, TO) \ 1552 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 1553 ? ! frame_pointer_needed \ 1554 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ 1555 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ 1556 : 1) 1557 1558/* Define the offset between two registers, one to be eliminated, and the other 1559 its replacement, at the start of a routine. */ 1560#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1561 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1562 1563/* Addressing modes, and classification of registers for them. */ 1564 1565#define HAVE_PRE_DECREMENT 1 1566#define HAVE_PRE_INCREMENT 1 1567 1568/* Macros to check register numbers against specific register classes. */ 1569 1570/* These assume that REGNO is a hard or pseudo reg number. 1571 They give nonzero only if REGNO is a hard reg of the suitable class 1572 or a pseudo reg currently allocated to a suitable hard reg. 1573 Since they use reg_renumber, they are safe only once reg_renumber 1574 has been allocated, which happens in local-alloc.c. */ 1575 1576#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1577((REGNO) < FIRST_PSEUDO_REGISTER \ 1578 ? (REGNO) <= 31 || (REGNO) == 67 \ 1579 || (REGNO) == FRAME_POINTER_REGNUM \ 1580 : (reg_renumber[REGNO] >= 0 \ 1581 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1582 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1583 1584#define REGNO_OK_FOR_BASE_P(REGNO) \ 1585((REGNO) < FIRST_PSEUDO_REGISTER \ 1586 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1587 || (REGNO) == FRAME_POINTER_REGNUM \ 1588 : (reg_renumber[REGNO] > 0 \ 1589 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1590 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1591 1592/* Maximum number of registers that can appear in a valid memory address. */ 1593 1594#define MAX_REGS_PER_ADDRESS 2 1595 1596/* Recognize any constant value that is a valid address. */ 1597 1598#define CONSTANT_ADDRESS_P(X) \ 1599 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1600 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1601 || GET_CODE (X) == HIGH) 1602 1603/* Nonzero if the constant value X is a legitimate general operand. 1604 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1605 1606 On the RS/6000, all integer constants are acceptable, most won't be valid 1607 for particular insns, though. Only easy FP constants are 1608 acceptable. */ 1609 1610#define LEGITIMATE_CONSTANT_P(X) \ 1611 (((GET_CODE (X) != CONST_DOUBLE \ 1612 && GET_CODE (X) != CONST_VECTOR) \ 1613 || GET_MODE (X) == VOIDmode \ 1614 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ 1615 || easy_fp_constant (X, GET_MODE (X)) \ 1616 || easy_vector_constant (X, GET_MODE (X))) \ 1617 && !rs6000_tls_referenced_p (X)) 1618 1619#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1620#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1621 && EASY_VECTOR_15((n) >> 1) \ 1622 && ((n) & 1) == 0) 1623 1624/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1625 and check its validity for a certain class. 1626 We have two alternate definitions for each of them. 1627 The usual definition accepts all pseudo regs; the other rejects 1628 them unless they have been allocated suitable hard regs. 1629 The symbol REG_OK_STRICT causes the latter definition to be used. 1630 1631 Most source files want to accept pseudo regs in the hope that 1632 they will get allocated to the class that the insn wants them to be in. 1633 Source files for reload pass need to be strict. 1634 After reload, it makes no difference, since pseudo regs have 1635 been eliminated by then. */ 1636 1637#ifdef REG_OK_STRICT 1638# define REG_OK_STRICT_FLAG 1 1639#else 1640# define REG_OK_STRICT_FLAG 0 1641#endif 1642 1643/* Nonzero if X is a hard reg that can be used as an index 1644 or if it is a pseudo reg in the non-strict case. */ 1645#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1646 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1647 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1648 1649/* Nonzero if X is a hard reg that can be used as a base reg 1650 or if it is a pseudo reg in the non-strict case. */ 1651#define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1652 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1653 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1654 1655#define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) 1656#define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) 1657 1658/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1659 that is a valid memory address for an instruction. 1660 The MODE argument is the machine mode for the MEM expression 1661 that wants to use this address. 1662 1663 On the RS/6000, there are four valid addresses: a SYMBOL_REF that 1664 refers to a constant pool entry of an address (or the sum of it 1665 plus a constant), a short (16-bit signed) constant plus a register, 1666 the sum of two registers, or a register indirect, possibly with an 1667 auto-increment. For DFmode and DImode with a constant plus register, 1668 we must ensure that both words are addressable or PowerPC64 with offset 1669 word aligned. 1670 1671 For modes spanning multiple registers (DFmode in 32-bit GPRs, 1672 32-bit DImode, TImode), indexed addressing cannot be used because 1673 adjacent memory cells are accessed by adding word-sized offsets 1674 during assembly output. */ 1675 1676#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1677{ if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ 1678 goto ADDR; \ 1679} 1680 1681/* Try machine-dependent ways of modifying an illegitimate address 1682 to be legitimate. If we find one, return the new, valid address. 1683 This macro is used in only one place: `memory_address' in explow.c. 1684 1685 OLDX is the address as it was before break_out_memory_refs was called. 1686 In some cases it is useful to look at this to decide what needs to be done. 1687 1688 MODE and WIN are passed so that this macro can use 1689 GO_IF_LEGITIMATE_ADDRESS. 1690 1691 It is always safe for this macro to do nothing. It exists to recognize 1692 opportunities to optimize the output. 1693 1694 On RS/6000, first check for the sum of a register with a constant 1695 integer that is out of range. If so, generate code to add the 1696 constant with the low-order 16 bits masked to the register and force 1697 this result into another register (this can be done with `cau'). 1698 Then generate an address of REG+(CONST&0xffff), allowing for the 1699 possibility of bit 16 being a one. 1700 1701 Then check for the sum of a register and something not constant, try to 1702 load the other things into a register and return the sum. */ 1703 1704#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1705{ rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ 1706 if (result != NULL_RTX) \ 1707 { \ 1708 (X) = result; \ 1709 goto WIN; \ 1710 } \ 1711} 1712 1713/* Try a machine-dependent way of reloading an illegitimate address 1714 operand. If we find one, push the reload and jump to WIN. This 1715 macro is used in only one place: `find_reloads_address' in reload.c. 1716 1717 Implemented on rs6000 by rs6000_legitimize_reload_address. 1718 Note that (X) is evaluated twice; this is safe in current usage. */ 1719 1720#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1721do { \ 1722 int win; \ 1723 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1724 (int)(TYPE), (IND_LEVELS), &win); \ 1725 if ( win ) \ 1726 goto WIN; \ 1727} while (0) 1728 1729/* Go to LABEL if ADDR (a legitimate address expression) 1730 has an effect that depends on the machine mode it is used for. */ 1731 1732#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1733do { \ 1734 if (rs6000_mode_dependent_address (ADDR)) \ 1735 goto LABEL; \ 1736} while (0) 1737 1738/* The register number of the register used to address a table of 1739 static data addresses in memory. In some cases this register is 1740 defined by a processor's "application binary interface" (ABI). 1741 When this macro is defined, RTL is generated for this register 1742 once, as with the stack pointer and frame pointer registers. If 1743 this macro is not defined, it is up to the machine-dependent files 1744 to allocate such a register (if necessary). */ 1745 1746#define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1747#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 1748 1749#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1750 1751/* Define this macro if the register defined by 1752 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1753 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1754 1755/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1756 1757/* A C expression that is nonzero if X is a legitimate immediate 1758 operand on the target machine when generating position independent 1759 code. You can assume that X satisfies `CONSTANT_P', so you need 1760 not check this. You can also assume FLAG_PIC is true, so you need 1761 not check it either. You need not define this macro if all 1762 constants (including `SYMBOL_REF') can be immediate operands when 1763 generating position independent code. */ 1764 1765/* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1766 1767/* Define this if some processing needs to be done immediately before 1768 emitting code for an insn. */ 1769 1770/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ 1771 1772/* Specify the machine mode that this machine uses 1773 for the index in the tablejump instruction. */ 1774#define CASE_VECTOR_MODE SImode 1775 1776/* Define as C expression which evaluates to nonzero if the tablejump 1777 instruction expects the table to contain offsets from the address of the 1778 table. 1779 Do not define this if the table should contain absolute addresses. */ 1780#define CASE_VECTOR_PC_RELATIVE 1 1781 1782/* Define this as 1 if `char' should by default be signed; else as 0. */ 1783#define DEFAULT_SIGNED_CHAR 0 1784 1785/* This flag, if defined, says the same insns that convert to a signed fixnum 1786 also convert validly to an unsigned one. */ 1787 1788/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ 1789 1790/* An integer expression for the size in bits of the largest integer machine 1791 mode that should actually be used. */ 1792 1793/* Allow pairs of registers to be used, which is the intent of the default. */ 1794#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1795 1796/* Max number of bytes we can move from memory to memory 1797 in one reasonably fast instruction. */ 1798#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1799#define MAX_MOVE_MAX 8 1800 1801/* Nonzero if access to memory by bytes is no faster than for words. 1802 Also nonzero if doing byte operations (specifically shifts) in registers 1803 is undesirable. */ 1804#define SLOW_BYTE_ACCESS 1 1805 1806/* Define if operations between registers always perform the operation 1807 on the full register even if a narrower mode is specified. */ 1808#define WORD_REGISTER_OPERATIONS 1809 1810/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1811 will either zero-extend or sign-extend. The value of this macro should 1812 be the code that says which one of the two operations is implicitly 1813 done, UNKNOWN if none. */ 1814#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1815 1816/* Define if loading short immediate values into registers sign extends. */ 1817#define SHORT_IMMEDIATES_SIGN_EXTEND 1818 1819/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1820 is done just by pretending it is already truncated. */ 1821#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1822 1823/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1824#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1825 ((VALUE) = ((MODE) == SImode ? 32 : 64)) 1826 1827/* The CTZ patterns return -1 for input of zero. */ 1828#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1) 1829 1830/* Specify the machine mode that pointers have. 1831 After generation of rtl, the compiler makes no further distinction 1832 between pointers and any other objects of this machine mode. */ 1833#define Pmode (TARGET_32BIT ? SImode : DImode) 1834 1835/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1836#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1837 1838/* Mode of a function address in a call instruction (for indexing purposes). 1839 Doesn't matter on RS/6000. */ 1840#define FUNCTION_MODE SImode 1841 1842/* Define this if addresses of constant functions 1843 shouldn't be put through pseudo regs where they can be cse'd. 1844 Desirable on machines where ordinary constants are expensive 1845 but a CALL with constant address is cheap. */ 1846#define NO_FUNCTION_CSE 1847 1848/* Define this to be nonzero if shift instructions ignore all but the low-order 1849 few bits. 1850 1851 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1852 have been dropped from the PowerPC architecture. */ 1853 1854#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) 1855 1856/* Adjust the length of an INSN. LENGTH is the currently-computed length and 1857 should be adjusted to reflect any required changes. This macro is used when 1858 there is some systematic length adjustment required that would be difficult 1859 to express in the length attribute. */ 1860 1861/* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 1862 1863/* Given a comparison code (EQ, NE, etc.) and the first operand of a 1864 COMPARE, return the mode to be used for the comparison. For 1865 floating-point, CCFPmode should be used. CCUNSmode should be used 1866 for unsigned comparisons. CCEQmode should be used when we are 1867 doing an inequality comparison on the result of a 1868 comparison. CCmode should be used in all other cases. */ 1869 1870#define SELECT_CC_MODE(OP,X,Y) \ 1871 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1872 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1873 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1874 ? CCEQmode : CCmode)) 1875 1876/* Can the condition code MODE be safely reversed? This is safe in 1877 all cases on this port, because at present it doesn't use the 1878 trapping FP comparisons (fcmpo). */ 1879#define REVERSIBLE_CC_MODE(MODE) 1 1880 1881/* Given a condition code and a mode, return the inverse condition. */ 1882#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1883 1884/* Define the information needed to generate branch and scc insns. This is 1885 stored from the compare operation. */ 1886 1887extern GTY(()) rtx rs6000_compare_op0; 1888extern GTY(()) rtx rs6000_compare_op1; 1889extern int rs6000_compare_fp_p; 1890 1891/* Control the assembler format that we output. */ 1892 1893/* A C string constant describing how to begin a comment in the target 1894 assembler language. The compiler assumes that the comment will end at 1895 the end of the line. */ 1896#define ASM_COMMENT_START " #" 1897 1898/* Flag to say the TOC is initialized */ 1899extern int toc_initialized; 1900 1901/* Macro to output a special constant pool entry. Go to WIN if we output 1902 it. Otherwise, it is written the usual way. 1903 1904 On the RS/6000, toc entries are handled this way. */ 1905 1906#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1907{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1908 { \ 1909 output_toc (FILE, X, LABELNO, MODE); \ 1910 goto WIN; \ 1911 } \ 1912} 1913 1914#ifdef HAVE_GAS_WEAK 1915#define RS6000_WEAK 1 1916#else 1917#define RS6000_WEAK 0 1918#endif 1919 1920#if RS6000_WEAK 1921/* Used in lieu of ASM_WEAKEN_LABEL. */ 1922#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1923 do \ 1924 { \ 1925 fputs ("\t.weak\t", (FILE)); \ 1926 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1927 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1928 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1929 { \ 1930 if (TARGET_XCOFF) \ 1931 fputs ("[DS]", (FILE)); \ 1932 fputs ("\n\t.weak\t.", (FILE)); \ 1933 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1934 } \ 1935 fputc ('\n', (FILE)); \ 1936 if (VAL) \ 1937 { \ 1938 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 1939 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1940 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1941 { \ 1942 fputs ("\t.set\t.", (FILE)); \ 1943 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1944 fputs (",.", (FILE)); \ 1945 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 1946 fputc ('\n', (FILE)); \ 1947 } \ 1948 } \ 1949 } \ 1950 while (0) 1951#endif 1952 1953#if HAVE_GAS_WEAKREF 1954#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 1955 do \ 1956 { \ 1957 fputs ("\t.weakref\t", (FILE)); \ 1958 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1959 fputs (", ", (FILE)); \ 1960 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1961 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1962 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1963 { \ 1964 fputs ("\n\t.weakref\t.", (FILE)); \ 1965 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1966 fputs (", .", (FILE)); \ 1967 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1968 } \ 1969 fputc ('\n', (FILE)); \ 1970 } while (0) 1971#endif 1972 1973/* This implements the `alias' attribute. */ 1974#undef ASM_OUTPUT_DEF_FROM_DECLS 1975#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 1976 do \ 1977 { \ 1978 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 1979 const char *name = IDENTIFIER_POINTER (TARGET); \ 1980 if (TREE_CODE (DECL) == FUNCTION_DECL \ 1981 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1982 { \ 1983 if (TREE_PUBLIC (DECL)) \ 1984 { \ 1985 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1986 { \ 1987 fputs ("\t.globl\t.", FILE); \ 1988 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1989 putc ('\n', FILE); \ 1990 } \ 1991 } \ 1992 else if (TARGET_XCOFF) \ 1993 { \ 1994 fputs ("\t.lglobl\t.", FILE); \ 1995 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1996 putc ('\n', FILE); \ 1997 } \ 1998 fputs ("\t.set\t.", FILE); \ 1999 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2000 fputs (",.", FILE); \ 2001 RS6000_OUTPUT_BASENAME (FILE, name); \ 2002 fputc ('\n', FILE); \ 2003 } \ 2004 ASM_OUTPUT_DEF (FILE, alias, name); \ 2005 } \ 2006 while (0) 2007 2008#define TARGET_ASM_FILE_START rs6000_file_start 2009 2010/* Output to assembler file text saying following lines 2011 may contain character constants, extra white space, comments, etc. */ 2012 2013#define ASM_APP_ON "" 2014 2015/* Output to assembler file text saying following lines 2016 no longer contain unusual constructs. */ 2017 2018#define ASM_APP_OFF "" 2019 2020/* How to refer to registers in assembler output. 2021 This sequence is indexed by compiler's hard-register-number (see above). */ 2022 2023extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2024 2025#define REGISTER_NAMES \ 2026{ \ 2027 &rs6000_reg_names[ 0][0], /* r0 */ \ 2028 &rs6000_reg_names[ 1][0], /* r1 */ \ 2029 &rs6000_reg_names[ 2][0], /* r2 */ \ 2030 &rs6000_reg_names[ 3][0], /* r3 */ \ 2031 &rs6000_reg_names[ 4][0], /* r4 */ \ 2032 &rs6000_reg_names[ 5][0], /* r5 */ \ 2033 &rs6000_reg_names[ 6][0], /* r6 */ \ 2034 &rs6000_reg_names[ 7][0], /* r7 */ \ 2035 &rs6000_reg_names[ 8][0], /* r8 */ \ 2036 &rs6000_reg_names[ 9][0], /* r9 */ \ 2037 &rs6000_reg_names[10][0], /* r10 */ \ 2038 &rs6000_reg_names[11][0], /* r11 */ \ 2039 &rs6000_reg_names[12][0], /* r12 */ \ 2040 &rs6000_reg_names[13][0], /* r13 */ \ 2041 &rs6000_reg_names[14][0], /* r14 */ \ 2042 &rs6000_reg_names[15][0], /* r15 */ \ 2043 &rs6000_reg_names[16][0], /* r16 */ \ 2044 &rs6000_reg_names[17][0], /* r17 */ \ 2045 &rs6000_reg_names[18][0], /* r18 */ \ 2046 &rs6000_reg_names[19][0], /* r19 */ \ 2047 &rs6000_reg_names[20][0], /* r20 */ \ 2048 &rs6000_reg_names[21][0], /* r21 */ \ 2049 &rs6000_reg_names[22][0], /* r22 */ \ 2050 &rs6000_reg_names[23][0], /* r23 */ \ 2051 &rs6000_reg_names[24][0], /* r24 */ \ 2052 &rs6000_reg_names[25][0], /* r25 */ \ 2053 &rs6000_reg_names[26][0], /* r26 */ \ 2054 &rs6000_reg_names[27][0], /* r27 */ \ 2055 &rs6000_reg_names[28][0], /* r28 */ \ 2056 &rs6000_reg_names[29][0], /* r29 */ \ 2057 &rs6000_reg_names[30][0], /* r30 */ \ 2058 &rs6000_reg_names[31][0], /* r31 */ \ 2059 \ 2060 &rs6000_reg_names[32][0], /* fr0 */ \ 2061 &rs6000_reg_names[33][0], /* fr1 */ \ 2062 &rs6000_reg_names[34][0], /* fr2 */ \ 2063 &rs6000_reg_names[35][0], /* fr3 */ \ 2064 &rs6000_reg_names[36][0], /* fr4 */ \ 2065 &rs6000_reg_names[37][0], /* fr5 */ \ 2066 &rs6000_reg_names[38][0], /* fr6 */ \ 2067 &rs6000_reg_names[39][0], /* fr7 */ \ 2068 &rs6000_reg_names[40][0], /* fr8 */ \ 2069 &rs6000_reg_names[41][0], /* fr9 */ \ 2070 &rs6000_reg_names[42][0], /* fr10 */ \ 2071 &rs6000_reg_names[43][0], /* fr11 */ \ 2072 &rs6000_reg_names[44][0], /* fr12 */ \ 2073 &rs6000_reg_names[45][0], /* fr13 */ \ 2074 &rs6000_reg_names[46][0], /* fr14 */ \ 2075 &rs6000_reg_names[47][0], /* fr15 */ \ 2076 &rs6000_reg_names[48][0], /* fr16 */ \ 2077 &rs6000_reg_names[49][0], /* fr17 */ \ 2078 &rs6000_reg_names[50][0], /* fr18 */ \ 2079 &rs6000_reg_names[51][0], /* fr19 */ \ 2080 &rs6000_reg_names[52][0], /* fr20 */ \ 2081 &rs6000_reg_names[53][0], /* fr21 */ \ 2082 &rs6000_reg_names[54][0], /* fr22 */ \ 2083 &rs6000_reg_names[55][0], /* fr23 */ \ 2084 &rs6000_reg_names[56][0], /* fr24 */ \ 2085 &rs6000_reg_names[57][0], /* fr25 */ \ 2086 &rs6000_reg_names[58][0], /* fr26 */ \ 2087 &rs6000_reg_names[59][0], /* fr27 */ \ 2088 &rs6000_reg_names[60][0], /* fr28 */ \ 2089 &rs6000_reg_names[61][0], /* fr29 */ \ 2090 &rs6000_reg_names[62][0], /* fr30 */ \ 2091 &rs6000_reg_names[63][0], /* fr31 */ \ 2092 \ 2093 &rs6000_reg_names[64][0], /* mq */ \ 2094 &rs6000_reg_names[65][0], /* lr */ \ 2095 &rs6000_reg_names[66][0], /* ctr */ \ 2096 &rs6000_reg_names[67][0], /* ap */ \ 2097 \ 2098 &rs6000_reg_names[68][0], /* cr0 */ \ 2099 &rs6000_reg_names[69][0], /* cr1 */ \ 2100 &rs6000_reg_names[70][0], /* cr2 */ \ 2101 &rs6000_reg_names[71][0], /* cr3 */ \ 2102 &rs6000_reg_names[72][0], /* cr4 */ \ 2103 &rs6000_reg_names[73][0], /* cr5 */ \ 2104 &rs6000_reg_names[74][0], /* cr6 */ \ 2105 &rs6000_reg_names[75][0], /* cr7 */ \ 2106 \ 2107 &rs6000_reg_names[76][0], /* xer */ \ 2108 \ 2109 &rs6000_reg_names[77][0], /* v0 */ \ 2110 &rs6000_reg_names[78][0], /* v1 */ \ 2111 &rs6000_reg_names[79][0], /* v2 */ \ 2112 &rs6000_reg_names[80][0], /* v3 */ \ 2113 &rs6000_reg_names[81][0], /* v4 */ \ 2114 &rs6000_reg_names[82][0], /* v5 */ \ 2115 &rs6000_reg_names[83][0], /* v6 */ \ 2116 &rs6000_reg_names[84][0], /* v7 */ \ 2117 &rs6000_reg_names[85][0], /* v8 */ \ 2118 &rs6000_reg_names[86][0], /* v9 */ \ 2119 &rs6000_reg_names[87][0], /* v10 */ \ 2120 &rs6000_reg_names[88][0], /* v11 */ \ 2121 &rs6000_reg_names[89][0], /* v12 */ \ 2122 &rs6000_reg_names[90][0], /* v13 */ \ 2123 &rs6000_reg_names[91][0], /* v14 */ \ 2124 &rs6000_reg_names[92][0], /* v15 */ \ 2125 &rs6000_reg_names[93][0], /* v16 */ \ 2126 &rs6000_reg_names[94][0], /* v17 */ \ 2127 &rs6000_reg_names[95][0], /* v18 */ \ 2128 &rs6000_reg_names[96][0], /* v19 */ \ 2129 &rs6000_reg_names[97][0], /* v20 */ \ 2130 &rs6000_reg_names[98][0], /* v21 */ \ 2131 &rs6000_reg_names[99][0], /* v22 */ \ 2132 &rs6000_reg_names[100][0], /* v23 */ \ 2133 &rs6000_reg_names[101][0], /* v24 */ \ 2134 &rs6000_reg_names[102][0], /* v25 */ \ 2135 &rs6000_reg_names[103][0], /* v26 */ \ 2136 &rs6000_reg_names[104][0], /* v27 */ \ 2137 &rs6000_reg_names[105][0], /* v28 */ \ 2138 &rs6000_reg_names[106][0], /* v29 */ \ 2139 &rs6000_reg_names[107][0], /* v30 */ \ 2140 &rs6000_reg_names[108][0], /* v31 */ \ 2141 &rs6000_reg_names[109][0], /* vrsave */ \ 2142 &rs6000_reg_names[110][0], /* vscr */ \ 2143 &rs6000_reg_names[111][0], /* spe_acc */ \ 2144 &rs6000_reg_names[112][0], /* spefscr */ \ 2145 &rs6000_reg_names[113][0], /* sfp */ \ 2146} 2147 2148/* Table of additional register names to use in user input. */ 2149 2150#define ADDITIONAL_REGISTER_NAMES \ 2151 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2152 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2153 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2154 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2155 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2156 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2157 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2158 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2159 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2160 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2161 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2162 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2163 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2164 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2165 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2166 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2167 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2168 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2169 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2170 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2171 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2172 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2173 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2174 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2175 {"vrsave", 109}, {"vscr", 110}, \ 2176 {"spe_acc", 111}, {"spefscr", 112}, \ 2177 /* no additional names for: mq, lr, ctr, ap */ \ 2178 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2179 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2180 {"cc", 68}, {"sp", 1}, {"toc", 2} } 2181 2182/* Text to write out after a CALL that may be replaced by glue code by 2183 the loader. This depends on the AIX version. */ 2184#define RS6000_CALL_GLUE "cror 31,31,31" 2185 2186/* This is how to output an element of a case-vector that is relative. */ 2187 2188#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2189 do { char buf[100]; \ 2190 fputs ("\t.long ", FILE); \ 2191 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2192 assemble_name (FILE, buf); \ 2193 putc ('-', FILE); \ 2194 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2195 assemble_name (FILE, buf); \ 2196 putc ('\n', FILE); \ 2197 } while (0) 2198 2199/* This is how to output an assembler line 2200 that says to advance the location counter 2201 to a multiple of 2**LOG bytes. */ 2202 2203#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2204 if ((LOG) != 0) \ 2205 fprintf (FILE, "\t.align %d\n", (LOG)) 2206 2207/* Pick up the return address upon entry to a procedure. Used for 2208 dwarf2 unwind information. This also enables the table driven 2209 mechanism. */ 2210 2211#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 2212#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) 2213 2214/* Describe how we implement __builtin_eh_return. */ 2215#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2216#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2217 2218/* Print operand X (an rtx) in assembler syntax to file FILE. 2219 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2220 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2221 2222#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2223 2224/* Define which CODE values are valid. */ 2225 2226#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2227 ((CODE) == '.' || (CODE) == '&') 2228 2229/* Print a memory address as an operand to reference that memory location. */ 2230 2231#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2232 2233/* uncomment for disabling the corresponding default options */ 2234/* #define MACHINE_no_sched_interblock */ 2235/* #define MACHINE_no_sched_speculative */ 2236/* #define MACHINE_no_sched_speculative_load */ 2237 2238/* General flags. */ 2239extern int flag_pic; 2240extern int optimize; 2241extern int flag_expensive_optimizations; 2242extern int frame_pointer_needed; 2243 2244enum rs6000_builtins 2245{ 2246 /* AltiVec builtins. */ 2247 ALTIVEC_BUILTIN_ST_INTERNAL_4si, 2248 ALTIVEC_BUILTIN_LD_INTERNAL_4si, 2249 ALTIVEC_BUILTIN_ST_INTERNAL_8hi, 2250 ALTIVEC_BUILTIN_LD_INTERNAL_8hi, 2251 ALTIVEC_BUILTIN_ST_INTERNAL_16qi, 2252 ALTIVEC_BUILTIN_LD_INTERNAL_16qi, 2253 ALTIVEC_BUILTIN_ST_INTERNAL_4sf, 2254 ALTIVEC_BUILTIN_LD_INTERNAL_4sf, 2255 ALTIVEC_BUILTIN_VADDUBM, 2256 ALTIVEC_BUILTIN_VADDUHM, 2257 ALTIVEC_BUILTIN_VADDUWM, 2258 ALTIVEC_BUILTIN_VADDFP, 2259 ALTIVEC_BUILTIN_VADDCUW, 2260 ALTIVEC_BUILTIN_VADDUBS, 2261 ALTIVEC_BUILTIN_VADDSBS, 2262 ALTIVEC_BUILTIN_VADDUHS, 2263 ALTIVEC_BUILTIN_VADDSHS, 2264 ALTIVEC_BUILTIN_VADDUWS, 2265 ALTIVEC_BUILTIN_VADDSWS, 2266 ALTIVEC_BUILTIN_VAND, 2267 ALTIVEC_BUILTIN_VANDC, 2268 ALTIVEC_BUILTIN_VAVGUB, 2269 ALTIVEC_BUILTIN_VAVGSB, 2270 ALTIVEC_BUILTIN_VAVGUH, 2271 ALTIVEC_BUILTIN_VAVGSH, 2272 ALTIVEC_BUILTIN_VAVGUW, 2273 ALTIVEC_BUILTIN_VAVGSW, 2274 ALTIVEC_BUILTIN_VCFUX, 2275 ALTIVEC_BUILTIN_VCFSX, 2276 ALTIVEC_BUILTIN_VCTSXS, 2277 ALTIVEC_BUILTIN_VCTUXS, 2278 ALTIVEC_BUILTIN_VCMPBFP, 2279 ALTIVEC_BUILTIN_VCMPEQUB, 2280 ALTIVEC_BUILTIN_VCMPEQUH, 2281 ALTIVEC_BUILTIN_VCMPEQUW, 2282 ALTIVEC_BUILTIN_VCMPEQFP, 2283 ALTIVEC_BUILTIN_VCMPGEFP, 2284 ALTIVEC_BUILTIN_VCMPGTUB, 2285 ALTIVEC_BUILTIN_VCMPGTSB, 2286 ALTIVEC_BUILTIN_VCMPGTUH, 2287 ALTIVEC_BUILTIN_VCMPGTSH, 2288 ALTIVEC_BUILTIN_VCMPGTUW, 2289 ALTIVEC_BUILTIN_VCMPGTSW, 2290 ALTIVEC_BUILTIN_VCMPGTFP, 2291 ALTIVEC_BUILTIN_VEXPTEFP, 2292 ALTIVEC_BUILTIN_VLOGEFP, 2293 ALTIVEC_BUILTIN_VMADDFP, 2294 ALTIVEC_BUILTIN_VMAXUB, 2295 ALTIVEC_BUILTIN_VMAXSB, 2296 ALTIVEC_BUILTIN_VMAXUH, 2297 ALTIVEC_BUILTIN_VMAXSH, 2298 ALTIVEC_BUILTIN_VMAXUW, 2299 ALTIVEC_BUILTIN_VMAXSW, 2300 ALTIVEC_BUILTIN_VMAXFP, 2301 ALTIVEC_BUILTIN_VMHADDSHS, 2302 ALTIVEC_BUILTIN_VMHRADDSHS, 2303 ALTIVEC_BUILTIN_VMLADDUHM, 2304 ALTIVEC_BUILTIN_VMRGHB, 2305 ALTIVEC_BUILTIN_VMRGHH, 2306 ALTIVEC_BUILTIN_VMRGHW, 2307 ALTIVEC_BUILTIN_VMRGLB, 2308 ALTIVEC_BUILTIN_VMRGLH, 2309 ALTIVEC_BUILTIN_VMRGLW, 2310 ALTIVEC_BUILTIN_VMSUMUBM, 2311 ALTIVEC_BUILTIN_VMSUMMBM, 2312 ALTIVEC_BUILTIN_VMSUMUHM, 2313 ALTIVEC_BUILTIN_VMSUMSHM, 2314 ALTIVEC_BUILTIN_VMSUMUHS, 2315 ALTIVEC_BUILTIN_VMSUMSHS, 2316 ALTIVEC_BUILTIN_VMINUB, 2317 ALTIVEC_BUILTIN_VMINSB, 2318 ALTIVEC_BUILTIN_VMINUH, 2319 ALTIVEC_BUILTIN_VMINSH, 2320 ALTIVEC_BUILTIN_VMINUW, 2321 ALTIVEC_BUILTIN_VMINSW, 2322 ALTIVEC_BUILTIN_VMINFP, 2323 ALTIVEC_BUILTIN_VMULEUB, 2324 ALTIVEC_BUILTIN_VMULESB, 2325 ALTIVEC_BUILTIN_VMULEUH, 2326 ALTIVEC_BUILTIN_VMULESH, 2327 ALTIVEC_BUILTIN_VMULOUB, 2328 ALTIVEC_BUILTIN_VMULOSB, 2329 ALTIVEC_BUILTIN_VMULOUH, 2330 ALTIVEC_BUILTIN_VMULOSH, 2331 ALTIVEC_BUILTIN_VNMSUBFP, 2332 ALTIVEC_BUILTIN_VNOR, 2333 ALTIVEC_BUILTIN_VOR, 2334 ALTIVEC_BUILTIN_VSEL_4SI, 2335 ALTIVEC_BUILTIN_VSEL_4SF, 2336 ALTIVEC_BUILTIN_VSEL_8HI, 2337 ALTIVEC_BUILTIN_VSEL_16QI, 2338 ALTIVEC_BUILTIN_VPERM_4SI, 2339 ALTIVEC_BUILTIN_VPERM_4SF, 2340 ALTIVEC_BUILTIN_VPERM_8HI, 2341 ALTIVEC_BUILTIN_VPERM_16QI, 2342 ALTIVEC_BUILTIN_VPKUHUM, 2343 ALTIVEC_BUILTIN_VPKUWUM, 2344 ALTIVEC_BUILTIN_VPKPX, 2345 ALTIVEC_BUILTIN_VPKUHSS, 2346 ALTIVEC_BUILTIN_VPKSHSS, 2347 ALTIVEC_BUILTIN_VPKUWSS, 2348 ALTIVEC_BUILTIN_VPKSWSS, 2349 ALTIVEC_BUILTIN_VPKUHUS, 2350 ALTIVEC_BUILTIN_VPKSHUS, 2351 ALTIVEC_BUILTIN_VPKUWUS, 2352 ALTIVEC_BUILTIN_VPKSWUS, 2353 ALTIVEC_BUILTIN_VREFP, 2354 ALTIVEC_BUILTIN_VRFIM, 2355 ALTIVEC_BUILTIN_VRFIN, 2356 ALTIVEC_BUILTIN_VRFIP, 2357 ALTIVEC_BUILTIN_VRFIZ, 2358 ALTIVEC_BUILTIN_VRLB, 2359 ALTIVEC_BUILTIN_VRLH, 2360 ALTIVEC_BUILTIN_VRLW, 2361 ALTIVEC_BUILTIN_VRSQRTEFP, 2362 ALTIVEC_BUILTIN_VSLB, 2363 ALTIVEC_BUILTIN_VSLH, 2364 ALTIVEC_BUILTIN_VSLW, 2365 ALTIVEC_BUILTIN_VSL, 2366 ALTIVEC_BUILTIN_VSLO, 2367 ALTIVEC_BUILTIN_VSPLTB, 2368 ALTIVEC_BUILTIN_VSPLTH, 2369 ALTIVEC_BUILTIN_VSPLTW, 2370 ALTIVEC_BUILTIN_VSPLTISB, 2371 ALTIVEC_BUILTIN_VSPLTISH, 2372 ALTIVEC_BUILTIN_VSPLTISW, 2373 ALTIVEC_BUILTIN_VSRB, 2374 ALTIVEC_BUILTIN_VSRH, 2375 ALTIVEC_BUILTIN_VSRW, 2376 ALTIVEC_BUILTIN_VSRAB, 2377 ALTIVEC_BUILTIN_VSRAH, 2378 ALTIVEC_BUILTIN_VSRAW, 2379 ALTIVEC_BUILTIN_VSR, 2380 ALTIVEC_BUILTIN_VSRO, 2381 ALTIVEC_BUILTIN_VSUBUBM, 2382 ALTIVEC_BUILTIN_VSUBUHM, 2383 ALTIVEC_BUILTIN_VSUBUWM, 2384 ALTIVEC_BUILTIN_VSUBFP, 2385 ALTIVEC_BUILTIN_VSUBCUW, 2386 ALTIVEC_BUILTIN_VSUBUBS, 2387 ALTIVEC_BUILTIN_VSUBSBS, 2388 ALTIVEC_BUILTIN_VSUBUHS, 2389 ALTIVEC_BUILTIN_VSUBSHS, 2390 ALTIVEC_BUILTIN_VSUBUWS, 2391 ALTIVEC_BUILTIN_VSUBSWS, 2392 ALTIVEC_BUILTIN_VSUM4UBS, 2393 ALTIVEC_BUILTIN_VSUM4SBS, 2394 ALTIVEC_BUILTIN_VSUM4SHS, 2395 ALTIVEC_BUILTIN_VSUM2SWS, 2396 ALTIVEC_BUILTIN_VSUMSWS, 2397 ALTIVEC_BUILTIN_VXOR, 2398 ALTIVEC_BUILTIN_VSLDOI_16QI, 2399 ALTIVEC_BUILTIN_VSLDOI_8HI, 2400 ALTIVEC_BUILTIN_VSLDOI_4SI, 2401 ALTIVEC_BUILTIN_VSLDOI_4SF, 2402 ALTIVEC_BUILTIN_VUPKHSB, 2403 ALTIVEC_BUILTIN_VUPKHPX, 2404 ALTIVEC_BUILTIN_VUPKHSH, 2405 ALTIVEC_BUILTIN_VUPKLSB, 2406 ALTIVEC_BUILTIN_VUPKLPX, 2407 ALTIVEC_BUILTIN_VUPKLSH, 2408 ALTIVEC_BUILTIN_MTVSCR, 2409 ALTIVEC_BUILTIN_MFVSCR, 2410 ALTIVEC_BUILTIN_DSSALL, 2411 ALTIVEC_BUILTIN_DSS, 2412 ALTIVEC_BUILTIN_LVSL, 2413 ALTIVEC_BUILTIN_LVSR, 2414 ALTIVEC_BUILTIN_DSTT, 2415 ALTIVEC_BUILTIN_DSTST, 2416 ALTIVEC_BUILTIN_DSTSTT, 2417 ALTIVEC_BUILTIN_DST, 2418 ALTIVEC_BUILTIN_LVEBX, 2419 ALTIVEC_BUILTIN_LVEHX, 2420 ALTIVEC_BUILTIN_LVEWX, 2421 ALTIVEC_BUILTIN_LVXL, 2422 ALTIVEC_BUILTIN_LVX, 2423 ALTIVEC_BUILTIN_STVX, 2424 ALTIVEC_BUILTIN_STVEBX, 2425 ALTIVEC_BUILTIN_STVEHX, 2426 ALTIVEC_BUILTIN_STVEWX, 2427 ALTIVEC_BUILTIN_STVXL, 2428 ALTIVEC_BUILTIN_VCMPBFP_P, 2429 ALTIVEC_BUILTIN_VCMPEQFP_P, 2430 ALTIVEC_BUILTIN_VCMPEQUB_P, 2431 ALTIVEC_BUILTIN_VCMPEQUH_P, 2432 ALTIVEC_BUILTIN_VCMPEQUW_P, 2433 ALTIVEC_BUILTIN_VCMPGEFP_P, 2434 ALTIVEC_BUILTIN_VCMPGTFP_P, 2435 ALTIVEC_BUILTIN_VCMPGTSB_P, 2436 ALTIVEC_BUILTIN_VCMPGTSH_P, 2437 ALTIVEC_BUILTIN_VCMPGTSW_P, 2438 ALTIVEC_BUILTIN_VCMPGTUB_P, 2439 ALTIVEC_BUILTIN_VCMPGTUH_P, 2440 ALTIVEC_BUILTIN_VCMPGTUW_P, 2441 ALTIVEC_BUILTIN_ABSS_V4SI, 2442 ALTIVEC_BUILTIN_ABSS_V8HI, 2443 ALTIVEC_BUILTIN_ABSS_V16QI, 2444 ALTIVEC_BUILTIN_ABS_V4SI, 2445 ALTIVEC_BUILTIN_ABS_V4SF, 2446 ALTIVEC_BUILTIN_ABS_V8HI, 2447 ALTIVEC_BUILTIN_ABS_V16QI, 2448 ALTIVEC_BUILTIN_MASK_FOR_LOAD, 2449 ALTIVEC_BUILTIN_MASK_FOR_STORE, 2450 ALTIVEC_BUILTIN_VEC_INIT_V4SI, 2451 ALTIVEC_BUILTIN_VEC_INIT_V8HI, 2452 ALTIVEC_BUILTIN_VEC_INIT_V16QI, 2453 ALTIVEC_BUILTIN_VEC_INIT_V4SF, 2454 ALTIVEC_BUILTIN_VEC_SET_V4SI, 2455 ALTIVEC_BUILTIN_VEC_SET_V8HI, 2456 ALTIVEC_BUILTIN_VEC_SET_V16QI, 2457 ALTIVEC_BUILTIN_VEC_SET_V4SF, 2458 ALTIVEC_BUILTIN_VEC_EXT_V4SI, 2459 ALTIVEC_BUILTIN_VEC_EXT_V8HI, 2460 ALTIVEC_BUILTIN_VEC_EXT_V16QI, 2461 ALTIVEC_BUILTIN_VEC_EXT_V4SF, 2462 2463 /* Altivec overloaded builtins. */ 2464 ALTIVEC_BUILTIN_VCMPEQ_P, 2465 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P, 2466 ALTIVEC_BUILTIN_VCMPGT_P, 2467 ALTIVEC_BUILTIN_VCMPGE_P, 2468 ALTIVEC_BUILTIN_VEC_ABS, 2469 ALTIVEC_BUILTIN_VEC_ABSS, 2470 ALTIVEC_BUILTIN_VEC_ADD, 2471 ALTIVEC_BUILTIN_VEC_ADDC, 2472 ALTIVEC_BUILTIN_VEC_ADDS, 2473 ALTIVEC_BUILTIN_VEC_AND, 2474 ALTIVEC_BUILTIN_VEC_ANDC, 2475 ALTIVEC_BUILTIN_VEC_AVG, 2476 ALTIVEC_BUILTIN_VEC_CEIL, 2477 ALTIVEC_BUILTIN_VEC_CMPB, 2478 ALTIVEC_BUILTIN_VEC_CMPEQ, 2479 ALTIVEC_BUILTIN_VEC_CMPEQUB, 2480 ALTIVEC_BUILTIN_VEC_CMPEQUH, 2481 ALTIVEC_BUILTIN_VEC_CMPEQUW, 2482 ALTIVEC_BUILTIN_VEC_CMPGE, 2483 ALTIVEC_BUILTIN_VEC_CMPGT, 2484 ALTIVEC_BUILTIN_VEC_CMPLE, 2485 ALTIVEC_BUILTIN_VEC_CMPLT, 2486 ALTIVEC_BUILTIN_VEC_CTF, 2487 ALTIVEC_BUILTIN_VEC_CTS, 2488 ALTIVEC_BUILTIN_VEC_CTU, 2489 ALTIVEC_BUILTIN_VEC_DST, 2490 ALTIVEC_BUILTIN_VEC_DSTST, 2491 ALTIVEC_BUILTIN_VEC_DSTSTT, 2492 ALTIVEC_BUILTIN_VEC_DSTT, 2493 ALTIVEC_BUILTIN_VEC_EXPTE, 2494 ALTIVEC_BUILTIN_VEC_FLOOR, 2495 ALTIVEC_BUILTIN_VEC_LD, 2496 ALTIVEC_BUILTIN_VEC_LDE, 2497 ALTIVEC_BUILTIN_VEC_LDL, 2498 ALTIVEC_BUILTIN_VEC_LOGE, 2499 ALTIVEC_BUILTIN_VEC_LVEBX, 2500 ALTIVEC_BUILTIN_VEC_LVEHX, 2501 ALTIVEC_BUILTIN_VEC_LVEWX, 2502 ALTIVEC_BUILTIN_VEC_LVSL, 2503 ALTIVEC_BUILTIN_VEC_LVSR, 2504 ALTIVEC_BUILTIN_VEC_MADD, 2505 ALTIVEC_BUILTIN_VEC_MADDS, 2506 ALTIVEC_BUILTIN_VEC_MAX, 2507 ALTIVEC_BUILTIN_VEC_MERGEH, 2508 ALTIVEC_BUILTIN_VEC_MERGEL, 2509 ALTIVEC_BUILTIN_VEC_MIN, 2510 ALTIVEC_BUILTIN_VEC_MLADD, 2511 ALTIVEC_BUILTIN_VEC_MPERM, 2512 ALTIVEC_BUILTIN_VEC_MRADDS, 2513 ALTIVEC_BUILTIN_VEC_MRGHB, 2514 ALTIVEC_BUILTIN_VEC_MRGHH, 2515 ALTIVEC_BUILTIN_VEC_MRGHW, 2516 ALTIVEC_BUILTIN_VEC_MRGLB, 2517 ALTIVEC_BUILTIN_VEC_MRGLH, 2518 ALTIVEC_BUILTIN_VEC_MRGLW, 2519 ALTIVEC_BUILTIN_VEC_MSUM, 2520 ALTIVEC_BUILTIN_VEC_MSUMS, 2521 ALTIVEC_BUILTIN_VEC_MTVSCR, 2522 ALTIVEC_BUILTIN_VEC_MULE, 2523 ALTIVEC_BUILTIN_VEC_MULO, 2524 ALTIVEC_BUILTIN_VEC_NMSUB, 2525 ALTIVEC_BUILTIN_VEC_NOR, 2526 ALTIVEC_BUILTIN_VEC_OR, 2527 ALTIVEC_BUILTIN_VEC_PACK, 2528 ALTIVEC_BUILTIN_VEC_PACKPX, 2529 ALTIVEC_BUILTIN_VEC_PACKS, 2530 ALTIVEC_BUILTIN_VEC_PACKSU, 2531 ALTIVEC_BUILTIN_VEC_PERM, 2532 ALTIVEC_BUILTIN_VEC_RE, 2533 ALTIVEC_BUILTIN_VEC_RL, 2534 ALTIVEC_BUILTIN_VEC_ROUND, 2535 ALTIVEC_BUILTIN_VEC_RSQRTE, 2536 ALTIVEC_BUILTIN_VEC_SEL, 2537 ALTIVEC_BUILTIN_VEC_SL, 2538 ALTIVEC_BUILTIN_VEC_SLD, 2539 ALTIVEC_BUILTIN_VEC_SLL, 2540 ALTIVEC_BUILTIN_VEC_SLO, 2541 ALTIVEC_BUILTIN_VEC_SPLAT, 2542 ALTIVEC_BUILTIN_VEC_SPLAT_S16, 2543 ALTIVEC_BUILTIN_VEC_SPLAT_S32, 2544 ALTIVEC_BUILTIN_VEC_SPLAT_S8, 2545 ALTIVEC_BUILTIN_VEC_SPLAT_U16, 2546 ALTIVEC_BUILTIN_VEC_SPLAT_U32, 2547 ALTIVEC_BUILTIN_VEC_SPLAT_U8, 2548 ALTIVEC_BUILTIN_VEC_SPLTB, 2549 ALTIVEC_BUILTIN_VEC_SPLTH, 2550 ALTIVEC_BUILTIN_VEC_SPLTW, 2551 ALTIVEC_BUILTIN_VEC_SR, 2552 ALTIVEC_BUILTIN_VEC_SRA, 2553 ALTIVEC_BUILTIN_VEC_SRL, 2554 ALTIVEC_BUILTIN_VEC_SRO, 2555 ALTIVEC_BUILTIN_VEC_ST, 2556 ALTIVEC_BUILTIN_VEC_STE, 2557 ALTIVEC_BUILTIN_VEC_STL, 2558 ALTIVEC_BUILTIN_VEC_STVEBX, 2559 ALTIVEC_BUILTIN_VEC_STVEHX, 2560 ALTIVEC_BUILTIN_VEC_STVEWX, 2561 ALTIVEC_BUILTIN_VEC_SUB, 2562 ALTIVEC_BUILTIN_VEC_SUBC, 2563 ALTIVEC_BUILTIN_VEC_SUBS, 2564 ALTIVEC_BUILTIN_VEC_SUM2S, 2565 ALTIVEC_BUILTIN_VEC_SUM4S, 2566 ALTIVEC_BUILTIN_VEC_SUMS, 2567 ALTIVEC_BUILTIN_VEC_TRUNC, 2568 ALTIVEC_BUILTIN_VEC_UNPACKH, 2569 ALTIVEC_BUILTIN_VEC_UNPACKL, 2570 ALTIVEC_BUILTIN_VEC_VADDFP, 2571 ALTIVEC_BUILTIN_VEC_VADDSBS, 2572 ALTIVEC_BUILTIN_VEC_VADDSHS, 2573 ALTIVEC_BUILTIN_VEC_VADDSWS, 2574 ALTIVEC_BUILTIN_VEC_VADDUBM, 2575 ALTIVEC_BUILTIN_VEC_VADDUBS, 2576 ALTIVEC_BUILTIN_VEC_VADDUHM, 2577 ALTIVEC_BUILTIN_VEC_VADDUHS, 2578 ALTIVEC_BUILTIN_VEC_VADDUWM, 2579 ALTIVEC_BUILTIN_VEC_VADDUWS, 2580 ALTIVEC_BUILTIN_VEC_VAVGSB, 2581 ALTIVEC_BUILTIN_VEC_VAVGSH, 2582 ALTIVEC_BUILTIN_VEC_VAVGSW, 2583 ALTIVEC_BUILTIN_VEC_VAVGUB, 2584 ALTIVEC_BUILTIN_VEC_VAVGUH, 2585 ALTIVEC_BUILTIN_VEC_VAVGUW, 2586 ALTIVEC_BUILTIN_VEC_VCFSX, 2587 ALTIVEC_BUILTIN_VEC_VCFUX, 2588 ALTIVEC_BUILTIN_VEC_VCMPEQFP, 2589 ALTIVEC_BUILTIN_VEC_VCMPEQUB, 2590 ALTIVEC_BUILTIN_VEC_VCMPEQUH, 2591 ALTIVEC_BUILTIN_VEC_VCMPEQUW, 2592 ALTIVEC_BUILTIN_VEC_VCMPGTFP, 2593 ALTIVEC_BUILTIN_VEC_VCMPGTSB, 2594 ALTIVEC_BUILTIN_VEC_VCMPGTSH, 2595 ALTIVEC_BUILTIN_VEC_VCMPGTSW, 2596 ALTIVEC_BUILTIN_VEC_VCMPGTUB, 2597 ALTIVEC_BUILTIN_VEC_VCMPGTUH, 2598 ALTIVEC_BUILTIN_VEC_VCMPGTUW, 2599 ALTIVEC_BUILTIN_VEC_VMAXFP, 2600 ALTIVEC_BUILTIN_VEC_VMAXSB, 2601 ALTIVEC_BUILTIN_VEC_VMAXSH, 2602 ALTIVEC_BUILTIN_VEC_VMAXSW, 2603 ALTIVEC_BUILTIN_VEC_VMAXUB, 2604 ALTIVEC_BUILTIN_VEC_VMAXUH, 2605 ALTIVEC_BUILTIN_VEC_VMAXUW, 2606 ALTIVEC_BUILTIN_VEC_VMINFP, 2607 ALTIVEC_BUILTIN_VEC_VMINSB, 2608 ALTIVEC_BUILTIN_VEC_VMINSH, 2609 ALTIVEC_BUILTIN_VEC_VMINSW, 2610 ALTIVEC_BUILTIN_VEC_VMINUB, 2611 ALTIVEC_BUILTIN_VEC_VMINUH, 2612 ALTIVEC_BUILTIN_VEC_VMINUW, 2613 ALTIVEC_BUILTIN_VEC_VMRGHB, 2614 ALTIVEC_BUILTIN_VEC_VMRGHH, 2615 ALTIVEC_BUILTIN_VEC_VMRGHW, 2616 ALTIVEC_BUILTIN_VEC_VMRGLB, 2617 ALTIVEC_BUILTIN_VEC_VMRGLH, 2618 ALTIVEC_BUILTIN_VEC_VMRGLW, 2619 ALTIVEC_BUILTIN_VEC_VMSUMMBM, 2620 ALTIVEC_BUILTIN_VEC_VMSUMSHM, 2621 ALTIVEC_BUILTIN_VEC_VMSUMSHS, 2622 ALTIVEC_BUILTIN_VEC_VMSUMUBM, 2623 ALTIVEC_BUILTIN_VEC_VMSUMUHM, 2624 ALTIVEC_BUILTIN_VEC_VMSUMUHS, 2625 ALTIVEC_BUILTIN_VEC_VMULESB, 2626 ALTIVEC_BUILTIN_VEC_VMULESH, 2627 ALTIVEC_BUILTIN_VEC_VMULEUB, 2628 ALTIVEC_BUILTIN_VEC_VMULEUH, 2629 ALTIVEC_BUILTIN_VEC_VMULOSB, 2630 ALTIVEC_BUILTIN_VEC_VMULOSH, 2631 ALTIVEC_BUILTIN_VEC_VMULOUB, 2632 ALTIVEC_BUILTIN_VEC_VMULOUH, 2633 ALTIVEC_BUILTIN_VEC_VPKSHSS, 2634 ALTIVEC_BUILTIN_VEC_VPKSHUS, 2635 ALTIVEC_BUILTIN_VEC_VPKSWSS, 2636 ALTIVEC_BUILTIN_VEC_VPKSWUS, 2637 ALTIVEC_BUILTIN_VEC_VPKUHUM, 2638 ALTIVEC_BUILTIN_VEC_VPKUHUS, 2639 ALTIVEC_BUILTIN_VEC_VPKUWUM, 2640 ALTIVEC_BUILTIN_VEC_VPKUWUS, 2641 ALTIVEC_BUILTIN_VEC_VRLB, 2642 ALTIVEC_BUILTIN_VEC_VRLH, 2643 ALTIVEC_BUILTIN_VEC_VRLW, 2644 ALTIVEC_BUILTIN_VEC_VSLB, 2645 ALTIVEC_BUILTIN_VEC_VSLH, 2646 ALTIVEC_BUILTIN_VEC_VSLW, 2647 ALTIVEC_BUILTIN_VEC_VSPLTB, 2648 ALTIVEC_BUILTIN_VEC_VSPLTH, 2649 ALTIVEC_BUILTIN_VEC_VSPLTW, 2650 ALTIVEC_BUILTIN_VEC_VSRAB, 2651 ALTIVEC_BUILTIN_VEC_VSRAH, 2652 ALTIVEC_BUILTIN_VEC_VSRAW, 2653 ALTIVEC_BUILTIN_VEC_VSRB, 2654 ALTIVEC_BUILTIN_VEC_VSRH, 2655 ALTIVEC_BUILTIN_VEC_VSRW, 2656 ALTIVEC_BUILTIN_VEC_VSUBFP, 2657 ALTIVEC_BUILTIN_VEC_VSUBSBS, 2658 ALTIVEC_BUILTIN_VEC_VSUBSHS, 2659 ALTIVEC_BUILTIN_VEC_VSUBSWS, 2660 ALTIVEC_BUILTIN_VEC_VSUBUBM, 2661 ALTIVEC_BUILTIN_VEC_VSUBUBS, 2662 ALTIVEC_BUILTIN_VEC_VSUBUHM, 2663 ALTIVEC_BUILTIN_VEC_VSUBUHS, 2664 ALTIVEC_BUILTIN_VEC_VSUBUWM, 2665 ALTIVEC_BUILTIN_VEC_VSUBUWS, 2666 ALTIVEC_BUILTIN_VEC_VSUM4SBS, 2667 ALTIVEC_BUILTIN_VEC_VSUM4SHS, 2668 ALTIVEC_BUILTIN_VEC_VSUM4UBS, 2669 ALTIVEC_BUILTIN_VEC_VUPKHPX, 2670 ALTIVEC_BUILTIN_VEC_VUPKHSB, 2671 ALTIVEC_BUILTIN_VEC_VUPKHSH, 2672 ALTIVEC_BUILTIN_VEC_VUPKLPX, 2673 ALTIVEC_BUILTIN_VEC_VUPKLSB, 2674 ALTIVEC_BUILTIN_VEC_VUPKLSH, 2675 ALTIVEC_BUILTIN_VEC_XOR, 2676 ALTIVEC_BUILTIN_VEC_STEP, 2677 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP, 2678 2679 /* SPE builtins. */ 2680 SPE_BUILTIN_EVADDW, 2681 SPE_BUILTIN_EVAND, 2682 SPE_BUILTIN_EVANDC, 2683 SPE_BUILTIN_EVDIVWS, 2684 SPE_BUILTIN_EVDIVWU, 2685 SPE_BUILTIN_EVEQV, 2686 SPE_BUILTIN_EVFSADD, 2687 SPE_BUILTIN_EVFSDIV, 2688 SPE_BUILTIN_EVFSMUL, 2689 SPE_BUILTIN_EVFSSUB, 2690 SPE_BUILTIN_EVLDDX, 2691 SPE_BUILTIN_EVLDHX, 2692 SPE_BUILTIN_EVLDWX, 2693 SPE_BUILTIN_EVLHHESPLATX, 2694 SPE_BUILTIN_EVLHHOSSPLATX, 2695 SPE_BUILTIN_EVLHHOUSPLATX, 2696 SPE_BUILTIN_EVLWHEX, 2697 SPE_BUILTIN_EVLWHOSX, 2698 SPE_BUILTIN_EVLWHOUX, 2699 SPE_BUILTIN_EVLWHSPLATX, 2700 SPE_BUILTIN_EVLWWSPLATX, 2701 SPE_BUILTIN_EVMERGEHI, 2702 SPE_BUILTIN_EVMERGEHILO, 2703 SPE_BUILTIN_EVMERGELO, 2704 SPE_BUILTIN_EVMERGELOHI, 2705 SPE_BUILTIN_EVMHEGSMFAA, 2706 SPE_BUILTIN_EVMHEGSMFAN, 2707 SPE_BUILTIN_EVMHEGSMIAA, 2708 SPE_BUILTIN_EVMHEGSMIAN, 2709 SPE_BUILTIN_EVMHEGUMIAA, 2710 SPE_BUILTIN_EVMHEGUMIAN, 2711 SPE_BUILTIN_EVMHESMF, 2712 SPE_BUILTIN_EVMHESMFA, 2713 SPE_BUILTIN_EVMHESMFAAW, 2714 SPE_BUILTIN_EVMHESMFANW, 2715 SPE_BUILTIN_EVMHESMI, 2716 SPE_BUILTIN_EVMHESMIA, 2717 SPE_BUILTIN_EVMHESMIAAW, 2718 SPE_BUILTIN_EVMHESMIANW, 2719 SPE_BUILTIN_EVMHESSF, 2720 SPE_BUILTIN_EVMHESSFA, 2721 SPE_BUILTIN_EVMHESSFAAW, 2722 SPE_BUILTIN_EVMHESSFANW, 2723 SPE_BUILTIN_EVMHESSIAAW, 2724 SPE_BUILTIN_EVMHESSIANW, 2725 SPE_BUILTIN_EVMHEUMI, 2726 SPE_BUILTIN_EVMHEUMIA, 2727 SPE_BUILTIN_EVMHEUMIAAW, 2728 SPE_BUILTIN_EVMHEUMIANW, 2729 SPE_BUILTIN_EVMHEUSIAAW, 2730 SPE_BUILTIN_EVMHEUSIANW, 2731 SPE_BUILTIN_EVMHOGSMFAA, 2732 SPE_BUILTIN_EVMHOGSMFAN, 2733 SPE_BUILTIN_EVMHOGSMIAA, 2734 SPE_BUILTIN_EVMHOGSMIAN, 2735 SPE_BUILTIN_EVMHOGUMIAA, 2736 SPE_BUILTIN_EVMHOGUMIAN, 2737 SPE_BUILTIN_EVMHOSMF, 2738 SPE_BUILTIN_EVMHOSMFA, 2739 SPE_BUILTIN_EVMHOSMFAAW, 2740 SPE_BUILTIN_EVMHOSMFANW, 2741 SPE_BUILTIN_EVMHOSMI, 2742 SPE_BUILTIN_EVMHOSMIA, 2743 SPE_BUILTIN_EVMHOSMIAAW, 2744 SPE_BUILTIN_EVMHOSMIANW, 2745 SPE_BUILTIN_EVMHOSSF, 2746 SPE_BUILTIN_EVMHOSSFA, 2747 SPE_BUILTIN_EVMHOSSFAAW, 2748 SPE_BUILTIN_EVMHOSSFANW, 2749 SPE_BUILTIN_EVMHOSSIAAW, 2750 SPE_BUILTIN_EVMHOSSIANW, 2751 SPE_BUILTIN_EVMHOUMI, 2752 SPE_BUILTIN_EVMHOUMIA, 2753 SPE_BUILTIN_EVMHOUMIAAW, 2754 SPE_BUILTIN_EVMHOUMIANW, 2755 SPE_BUILTIN_EVMHOUSIAAW, 2756 SPE_BUILTIN_EVMHOUSIANW, 2757 SPE_BUILTIN_EVMWHSMF, 2758 SPE_BUILTIN_EVMWHSMFA, 2759 SPE_BUILTIN_EVMWHSMI, 2760 SPE_BUILTIN_EVMWHSMIA, 2761 SPE_BUILTIN_EVMWHSSF, 2762 SPE_BUILTIN_EVMWHSSFA, 2763 SPE_BUILTIN_EVMWHUMI, 2764 SPE_BUILTIN_EVMWHUMIA, 2765 SPE_BUILTIN_EVMWLSMIAAW, 2766 SPE_BUILTIN_EVMWLSMIANW, 2767 SPE_BUILTIN_EVMWLSSIAAW, 2768 SPE_BUILTIN_EVMWLSSIANW, 2769 SPE_BUILTIN_EVMWLUMI, 2770 SPE_BUILTIN_EVMWLUMIA, 2771 SPE_BUILTIN_EVMWLUMIAAW, 2772 SPE_BUILTIN_EVMWLUMIANW, 2773 SPE_BUILTIN_EVMWLUSIAAW, 2774 SPE_BUILTIN_EVMWLUSIANW, 2775 SPE_BUILTIN_EVMWSMF, 2776 SPE_BUILTIN_EVMWSMFA, 2777 SPE_BUILTIN_EVMWSMFAA, 2778 SPE_BUILTIN_EVMWSMFAN, 2779 SPE_BUILTIN_EVMWSMI, 2780 SPE_BUILTIN_EVMWSMIA, 2781 SPE_BUILTIN_EVMWSMIAA, 2782 SPE_BUILTIN_EVMWSMIAN, 2783 SPE_BUILTIN_EVMWHSSFAA, 2784 SPE_BUILTIN_EVMWSSF, 2785 SPE_BUILTIN_EVMWSSFA, 2786 SPE_BUILTIN_EVMWSSFAA, 2787 SPE_BUILTIN_EVMWSSFAN, 2788 SPE_BUILTIN_EVMWUMI, 2789 SPE_BUILTIN_EVMWUMIA, 2790 SPE_BUILTIN_EVMWUMIAA, 2791 SPE_BUILTIN_EVMWUMIAN, 2792 SPE_BUILTIN_EVNAND, 2793 SPE_BUILTIN_EVNOR, 2794 SPE_BUILTIN_EVOR, 2795 SPE_BUILTIN_EVORC, 2796 SPE_BUILTIN_EVRLW, 2797 SPE_BUILTIN_EVSLW, 2798 SPE_BUILTIN_EVSRWS, 2799 SPE_BUILTIN_EVSRWU, 2800 SPE_BUILTIN_EVSTDDX, 2801 SPE_BUILTIN_EVSTDHX, 2802 SPE_BUILTIN_EVSTDWX, 2803 SPE_BUILTIN_EVSTWHEX, 2804 SPE_BUILTIN_EVSTWHOX, 2805 SPE_BUILTIN_EVSTWWEX, 2806 SPE_BUILTIN_EVSTWWOX, 2807 SPE_BUILTIN_EVSUBFW, 2808 SPE_BUILTIN_EVXOR, 2809 SPE_BUILTIN_EVABS, 2810 SPE_BUILTIN_EVADDSMIAAW, 2811 SPE_BUILTIN_EVADDSSIAAW, 2812 SPE_BUILTIN_EVADDUMIAAW, 2813 SPE_BUILTIN_EVADDUSIAAW, 2814 SPE_BUILTIN_EVCNTLSW, 2815 SPE_BUILTIN_EVCNTLZW, 2816 SPE_BUILTIN_EVEXTSB, 2817 SPE_BUILTIN_EVEXTSH, 2818 SPE_BUILTIN_EVFSABS, 2819 SPE_BUILTIN_EVFSCFSF, 2820 SPE_BUILTIN_EVFSCFSI, 2821 SPE_BUILTIN_EVFSCFUF, 2822 SPE_BUILTIN_EVFSCFUI, 2823 SPE_BUILTIN_EVFSCTSF, 2824 SPE_BUILTIN_EVFSCTSI, 2825 SPE_BUILTIN_EVFSCTSIZ, 2826 SPE_BUILTIN_EVFSCTUF, 2827 SPE_BUILTIN_EVFSCTUI, 2828 SPE_BUILTIN_EVFSCTUIZ, 2829 SPE_BUILTIN_EVFSNABS, 2830 SPE_BUILTIN_EVFSNEG, 2831 SPE_BUILTIN_EVMRA, 2832 SPE_BUILTIN_EVNEG, 2833 SPE_BUILTIN_EVRNDW, 2834 SPE_BUILTIN_EVSUBFSMIAAW, 2835 SPE_BUILTIN_EVSUBFSSIAAW, 2836 SPE_BUILTIN_EVSUBFUMIAAW, 2837 SPE_BUILTIN_EVSUBFUSIAAW, 2838 SPE_BUILTIN_EVADDIW, 2839 SPE_BUILTIN_EVLDD, 2840 SPE_BUILTIN_EVLDH, 2841 SPE_BUILTIN_EVLDW, 2842 SPE_BUILTIN_EVLHHESPLAT, 2843 SPE_BUILTIN_EVLHHOSSPLAT, 2844 SPE_BUILTIN_EVLHHOUSPLAT, 2845 SPE_BUILTIN_EVLWHE, 2846 SPE_BUILTIN_EVLWHOS, 2847 SPE_BUILTIN_EVLWHOU, 2848 SPE_BUILTIN_EVLWHSPLAT, 2849 SPE_BUILTIN_EVLWWSPLAT, 2850 SPE_BUILTIN_EVRLWI, 2851 SPE_BUILTIN_EVSLWI, 2852 SPE_BUILTIN_EVSRWIS, 2853 SPE_BUILTIN_EVSRWIU, 2854 SPE_BUILTIN_EVSTDD, 2855 SPE_BUILTIN_EVSTDH, 2856 SPE_BUILTIN_EVSTDW, 2857 SPE_BUILTIN_EVSTWHE, 2858 SPE_BUILTIN_EVSTWHO, 2859 SPE_BUILTIN_EVSTWWE, 2860 SPE_BUILTIN_EVSTWWO, 2861 SPE_BUILTIN_EVSUBIFW, 2862 2863 /* Compares. */ 2864 SPE_BUILTIN_EVCMPEQ, 2865 SPE_BUILTIN_EVCMPGTS, 2866 SPE_BUILTIN_EVCMPGTU, 2867 SPE_BUILTIN_EVCMPLTS, 2868 SPE_BUILTIN_EVCMPLTU, 2869 SPE_BUILTIN_EVFSCMPEQ, 2870 SPE_BUILTIN_EVFSCMPGT, 2871 SPE_BUILTIN_EVFSCMPLT, 2872 SPE_BUILTIN_EVFSTSTEQ, 2873 SPE_BUILTIN_EVFSTSTGT, 2874 SPE_BUILTIN_EVFSTSTLT, 2875 2876 /* EVSEL compares. */ 2877 SPE_BUILTIN_EVSEL_CMPEQ, 2878 SPE_BUILTIN_EVSEL_CMPGTS, 2879 SPE_BUILTIN_EVSEL_CMPGTU, 2880 SPE_BUILTIN_EVSEL_CMPLTS, 2881 SPE_BUILTIN_EVSEL_CMPLTU, 2882 SPE_BUILTIN_EVSEL_FSCMPEQ, 2883 SPE_BUILTIN_EVSEL_FSCMPGT, 2884 SPE_BUILTIN_EVSEL_FSCMPLT, 2885 SPE_BUILTIN_EVSEL_FSTSTEQ, 2886 SPE_BUILTIN_EVSEL_FSTSTGT, 2887 SPE_BUILTIN_EVSEL_FSTSTLT, 2888 2889 SPE_BUILTIN_EVSPLATFI, 2890 SPE_BUILTIN_EVSPLATI, 2891 SPE_BUILTIN_EVMWHSSMAA, 2892 SPE_BUILTIN_EVMWHSMFAA, 2893 SPE_BUILTIN_EVMWHSMIAA, 2894 SPE_BUILTIN_EVMWHUSIAA, 2895 SPE_BUILTIN_EVMWHUMIAA, 2896 SPE_BUILTIN_EVMWHSSFAN, 2897 SPE_BUILTIN_EVMWHSSIAN, 2898 SPE_BUILTIN_EVMWHSMFAN, 2899 SPE_BUILTIN_EVMWHSMIAN, 2900 SPE_BUILTIN_EVMWHUSIAN, 2901 SPE_BUILTIN_EVMWHUMIAN, 2902 SPE_BUILTIN_EVMWHGSSFAA, 2903 SPE_BUILTIN_EVMWHGSMFAA, 2904 SPE_BUILTIN_EVMWHGSMIAA, 2905 SPE_BUILTIN_EVMWHGUMIAA, 2906 SPE_BUILTIN_EVMWHGSSFAN, 2907 SPE_BUILTIN_EVMWHGSMFAN, 2908 SPE_BUILTIN_EVMWHGSMIAN, 2909 SPE_BUILTIN_EVMWHGUMIAN, 2910 SPE_BUILTIN_MTSPEFSCR, 2911 SPE_BUILTIN_MFSPEFSCR, 2912 SPE_BUILTIN_BRINC, 2913 2914 RS6000_BUILTIN_COUNT 2915}; 2916 2917enum rs6000_builtin_type_index 2918{ 2919 RS6000_BTI_NOT_OPAQUE, 2920 RS6000_BTI_opaque_V2SI, 2921 RS6000_BTI_opaque_V2SF, 2922 RS6000_BTI_opaque_p_V2SI, 2923 RS6000_BTI_opaque_V4SI, 2924 RS6000_BTI_V16QI, 2925 RS6000_BTI_V2SI, 2926 RS6000_BTI_V2SF, 2927 RS6000_BTI_V4HI, 2928 RS6000_BTI_V4SI, 2929 RS6000_BTI_V4SF, 2930 RS6000_BTI_V8HI, 2931 RS6000_BTI_unsigned_V16QI, 2932 RS6000_BTI_unsigned_V8HI, 2933 RS6000_BTI_unsigned_V4SI, 2934 RS6000_BTI_bool_char, /* __bool char */ 2935 RS6000_BTI_bool_short, /* __bool short */ 2936 RS6000_BTI_bool_int, /* __bool int */ 2937 RS6000_BTI_pixel, /* __pixel */ 2938 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2939 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2940 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2941 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2942 RS6000_BTI_long, /* long_integer_type_node */ 2943 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2944 RS6000_BTI_INTQI, /* intQI_type_node */ 2945 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2946 RS6000_BTI_INTHI, /* intHI_type_node */ 2947 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2948 RS6000_BTI_INTSI, /* intSI_type_node */ 2949 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2950 RS6000_BTI_float, /* float_type_node */ 2951 RS6000_BTI_void, /* void_type_node */ 2952 RS6000_BTI_MAX 2953}; 2954 2955 2956#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2957#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2958#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2959#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2960#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2961#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2962#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2963#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2964#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2965#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2966#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2967#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2968#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2969#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2970#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2971#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2972#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2973#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2974#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2975#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2976#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2977#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2978 2979#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2980#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2981#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2982#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2983#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2984#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2985#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2986#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2987#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2988#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2989 2990extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2991extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2992 2993