if_rlreg.h revision 41243
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3241243Swpaul * $Id: if_rlreg.h,v 1.13 1998/11/18 20:27:28 wpaul Exp $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 7940516Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 10240516Swpaul 10340516Swpaul/* 10440516Swpaul * TX config register bits 10540516Swpaul */ 10640516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 10740516Swpaul#define RL_TXCFG_MXDMA0 0x00000100 /* max DMA burst size */ 10840516Swpaul#define RL_TXCFG_MXDMA1 0x00000200 10940516Swpaul#define RL_TXCFG_MXDMA2 0x00000400 11040516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 11140516Swpaul#define RL_TXCFG_LOOPBKTST0 0x00020000 /* loopback test */ 11240516Swpaul#define RL_TXCFG_LOOPBKTST1 0x00040000 /* loopback test */ 11340516Swpaul#define RL_TXCFG_IFG0 0x01000000 /* interframe gap */ 11440516Swpaul#define RL_TXCFG_IFG1 0x02000000 /* interframe gap */ 11540516Swpaul 11640516Swpaul/* 11740516Swpaul * Transmit descriptor status register bits. 11840516Swpaul */ 11940516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 12040516Swpaul#define RL_TXSTAT_OWN 0x00002000 12140516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 12240516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 12340516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 12440516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 12540516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 12640516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 12740516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 12840516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 12940516Swpaul 13040516Swpaul/* 13140516Swpaul * Interrupt status register bits. 13240516Swpaul */ 13340516Swpaul#define RL_ISR_RX_OK 0x0001 13440516Swpaul#define RL_ISR_RX_ERR 0x0002 13540516Swpaul#define RL_ISR_TX_OK 0x0004 13640516Swpaul#define RL_ISR_TX_ERR 0x0008 13740516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 13840516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 13940516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 14040516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 14140516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 14240516Swpaul 14340516Swpaul#define RL_INTRS \ 14440516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 14540516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 14640516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 14740516Swpaul 14840516Swpaul/* 14940516Swpaul * Media status register. (8139 only) 15040516Swpaul */ 15140516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 15240516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 15340516Swpaul#define RL_MEDIASTAT_LINK 0x04 15440516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 15540516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 15640516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 15740516Swpaul 15840516Swpaul/* 15940516Swpaul * Receive config register. 16040516Swpaul */ 16140516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 16240516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 16340516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 16440516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 16540516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 16640516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 16740516Swpaul#define RL_RXCFG_WRAP 0x00000080 16840516Swpaul#define RL_RXCFG_MAXDMA (0x00000100|0x00000200|0x00000400) 16940516Swpaul#define RL_RXCFG_BUFSZ (0x00000800|0x00001000) 17040516Swpaul#define RL_RXCFG_FIFOTHRESH (0x00002000|0x00004000|0x00008000) 17140516Swpaul#define RL_RXCFG_EARLYTHRESH (0x01000000|0x02000000|0x04000000) 17240516Swpaul 17340516Swpaul#define RL_RXBUF_8 0x00000000 17440516Swpaul#define RL_RXBUF_16 0x00000800 17540516Swpaul#define RL_RXBUF_32 0x00001000 17640516Swpaul#define RL_RXBUF_64 (0x00001000|0x00000800) 17740516Swpaul 17840516Swpaul/* 17940516Swpaul * Bits in RX status header (included with RX'ed packet 18040516Swpaul * in ring buffer). 18140516Swpaul */ 18240516Swpaul#define RL_RXSTAT_RXOK 0x00000001 18340516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 18440516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 18540516Swpaul#define RL_RXSTAT_GIANT 0x00000008 18640516Swpaul#define RL_RXSTAT_RUNT 0x00000010 18740516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 18840516Swpaul#define RL_RXSTAT_BROAD 0x00002000 18940516Swpaul#define RL_RXSTAT_INDIV 0x00004000 19040516Swpaul#define RL_RXSTAT_MULTI 0x00008000 19140516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 19240516Swpaul 19340516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 19440516Swpaul/* 19540516Swpaul * Command register. 19640516Swpaul */ 19740516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 19840516Swpaul#define RL_CMD_TX_ENB 0x0004 19940516Swpaul#define RL_CMD_RX_ENB 0x0008 20040516Swpaul#define RL_CMD_RESET 0x0010 20140516Swpaul 20240516Swpaul/* 20340516Swpaul * EEPROM control register 20440516Swpaul */ 20540516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 20640516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 20740516Swpaul#define RL_EE_CLK 0x04 /* clock */ 20840516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 20940516Swpaul#define RL_EE_MODE (0x40|0x80) 21040516Swpaul 21140516Swpaul#define RL_EEMODE_OFF 0x00 21240516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 21340516Swpaul#define RL_EEMODE_PROGRAM 0x80 21440516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 21540516Swpaul 21640516Swpaul/* 9346 EEPROM commands */ 21740516Swpaul#define RL_EECMD_WRITE 0x140 21840516Swpaul#define RL_EECMD_READ 0x180 21940516Swpaul#define RL_EECMD_ERASE 0x1c0 22040516Swpaul 22140516Swpaul#define RL_EE_ID 0x00 22240516Swpaul#define RL_EE_PCI_VID 0x01 22340516Swpaul#define RL_EE_PCI_DID 0x02 22440516Swpaul/* Location of station address inside EEPROM */ 22540516Swpaul#define RL_EE_EADDR 0x07 22640516Swpaul 22740516Swpaul/* 22840516Swpaul * MII register (8129 only) 22940516Swpaul */ 23040516Swpaul#define RL_MII_CLK 0x01 23140516Swpaul#define RL_MII_DATAIN 0x02 23240516Swpaul#define RL_MII_DATAOUT 0x04 23340516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 23440516Swpaul 23540516Swpaul/* 23640516Swpaul * Config 0 register 23740516Swpaul */ 23840516Swpaul#define RL_CFG0_ROM0 0x01 23940516Swpaul#define RL_CFG0_ROM1 0x02 24040516Swpaul#define RL_CFG0_ROM2 0x04 24140516Swpaul#define RL_CFG0_PL0 0x08 24240516Swpaul#define RL_CFG0_PL1 0x10 24340516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 24440516Swpaul#define RL_CFG0_PCS 0x40 24540516Swpaul#define RL_CFG0_SCR 0x80 24640516Swpaul 24740516Swpaul/* 24840516Swpaul * Config 1 register 24940516Swpaul */ 25040516Swpaul#define RL_CFG1_PWRDWN 0x01 25140516Swpaul#define RL_CFG1_SLEEP 0x02 25240516Swpaul#define RL_CFG1_IOMAP 0x04 25340516Swpaul#define RL_CFG1_MEMMAP 0x08 25440516Swpaul#define RL_CFG1_RSVD 0x10 25540516Swpaul#define RL_CFG1_DRVLOAD 0x20 25640516Swpaul#define RL_CFG1_LED0 0x40 25740516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 25840516Swpaul#define RL_CFG1_LED1 0x80 25940516Swpaul 26040516Swpaul/* 26140516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 26240516Swpaul * Instead, there are only four register sets, each or which represents 26340516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 26440516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 26540516Swpaul * the registers so the chip knows where they are. 26640516Swpaul * 26740516Swpaul * We can sort of kludge together the same kind of buffer management 26840516Swpaul * used in previous drivers, but we have to do buffer copies almost all 26940516Swpaul * the time, so it doesn't really buy us much. 27040516Swpaul * 27140516Swpaul * For reception, there's just one large buffer where the chip stores 27240516Swpaul * all received packets. 27340516Swpaul */ 27440516Swpaul 27540516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 27640516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 27740516Swpaul#define RL_TX_LIST_CNT 4 27840516Swpaul#define RL_MIN_FRAMELEN 60 27940516Swpaul#define RL_TX_EARLYTHRESH 0x80000 /* 256 << 11 */ 28040516Swpaul#define RL_RX_FIFOTHRESH 0x8000 /* 4 << 13 */ 28140516Swpaul#define RL_RX_MAXDMA 0x00000400 28240516Swpaul 28340516Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_BUF_SZ) 28440516Swpaul 28540516Swpaulstruct rl_chain { 28640516Swpaul char rl_desc; /* descriptor register idx */ 28740516Swpaul struct mbuf *rl_mbuf; 28840516Swpaul struct rl_chain *rl_next; 28940516Swpaul}; 29040516Swpaul 29140516Swpaulstruct rl_chain_data { 29240516Swpaul u_int16_t cur_rx; 29340516Swpaul caddr_t rl_rx_buf; 29440516Swpaul struct rl_chain rl_tx_chain[RL_TX_LIST_CNT]; 29540516Swpaul 29640516Swpaul int rl_tx_cnt; 29740516Swpaul struct rl_chain *rl_tx_cur; 29840516Swpaul struct rl_chain *rl_tx_free; 29940516Swpaul}; 30040516Swpaul 30140516Swpaulstruct rl_type { 30240516Swpaul u_int16_t rl_vid; 30340516Swpaul u_int16_t rl_did; 30440516Swpaul char *rl_name; 30540516Swpaul}; 30640516Swpaul 30740516Swpaulstruct rl_mii_frame { 30840516Swpaul u_int8_t mii_stdelim; 30940516Swpaul u_int8_t mii_opcode; 31040516Swpaul u_int8_t mii_phyaddr; 31140516Swpaul u_int8_t mii_regaddr; 31240516Swpaul u_int8_t mii_turnaround; 31340516Swpaul u_int16_t mii_data; 31440516Swpaul}; 31540516Swpaul 31640516Swpaul/* 31740516Swpaul * MII constants 31840516Swpaul */ 31940516Swpaul#define RL_MII_STARTDELIM 0x01 32040516Swpaul#define RL_MII_READOP 0x02 32140516Swpaul#define RL_MII_WRITEOP 0x01 32240516Swpaul#define RL_MII_TURNAROUND 0x02 32340516Swpaul 32440516Swpaul#define RL_FLAG_FORCEDELAY 1 32540516Swpaul#define RL_FLAG_SCHEDDELAY 2 32640516Swpaul#define RL_FLAG_DELAYTIMEO 3 32740516Swpaul 32840516Swpaul#define RL_8129 1 32940516Swpaul#define RL_8139 2 33040516Swpaul 33140516Swpaulstruct rl_softc { 33240516Swpaul struct arpcom arpcom; /* interface info */ 33340516Swpaul struct ifmedia ifmedia; /* media info */ 33440516Swpaul u_int32_t iobase; /* pointer to PIO space */ 33540516Swpaul#ifndef RL_USEIOSPACE 33640516Swpaul volatile caddr_t csr; /* pointer to register map */ 33740516Swpaul#endif 33840516Swpaul struct rl_type *rl_pinfo; /* phy info */ 33940516Swpaul u_int8_t rl_unit; /* interface number */ 34040516Swpaul u_int8_t rl_type; 34140516Swpaul u_int8_t rl_phy_addr; /* PHY address */ 34240516Swpaul u_int8_t rl_tx_pend; /* TX pending */ 34340516Swpaul u_int8_t rl_want_auto; 34440516Swpaul u_int8_t rl_autoneg; 34540516Swpaul u_int8_t rl_stats_no_timeout; 34640516Swpaul struct rl_chain_data rl_cdata; 34740516Swpaul}; 34840516Swpaul 34940516Swpaul/* 35040516Swpaul * register space access macros 35140516Swpaul */ 35240516Swpaul#ifdef RL_USEIOSPACE 35340516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 35440516Swpaul outl(sc->iobase + (u_int32_t)(reg), val) 35540516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 35640516Swpaul outw(sc->iobase + (u_int32_t)(reg), val) 35740516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 35840516Swpaul outb(sc->iobase + (u_int32_t)(reg), val) 35940516Swpaul 36040516Swpaul#define CSR_READ_4(sc, reg) \ 36140516Swpaul inl(sc->iobase + (u_int32_t)(reg)) 36240516Swpaul#define CSR_READ_2(sc, reg) \ 36340516Swpaul inw(sc->iobase + (u_int32_t)(reg)) 36440516Swpaul#define CSR_READ_1(sc, reg) \ 36540516Swpaul inb(sc->iobase + (u_int32_t)(reg)) 36640516Swpaul#else 36740516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 36840516Swpaul ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 36940516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 37040516Swpaul ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 37140516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 37240516Swpaul ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 37340516Swpaul 37440516Swpaul#define CSR_READ_4(sc, reg) \ 37540516Swpaul (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 37640516Swpaul#define CSR_READ_2(sc, reg) \ 37740516Swpaul (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 37840516Swpaul#define CSR_READ_1(sc, reg) \ 37940516Swpaul (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 38040516Swpaul#endif 38140516Swpaul 38240516Swpaul#define RL_TIMEOUT 1000 38340516Swpaul 38440516Swpaul/* 38540516Swpaul * General constants that are fun to know. 38640516Swpaul * 38740516Swpaul * RealTek PCI vendor ID 38840516Swpaul */ 38940516Swpaul#define RT_VENDORID 0x10EC 39040516Swpaul 39140516Swpaul/* 39241243Swpaul * Accton PCI vendor ID 39341243Swpaul */ 39441243Swpaul#define ACCTON_VENDORID 0x1113 39541243Swpaul 39641243Swpaul/* 39740516Swpaul * RealTek chip device IDs. 39840516Swpaul */ 39940516Swpaul#define RT_DEVICEID_8129 0x8129 40040516Swpaul#define RT_DEVICEID_8139 0x8139 40140516Swpaul 40240516Swpaul/* 40341243Swpaul * Accton MPX 5030/5038 device ID. 40441243Swpaul */ 40541243Swpaul#define ACCTON_DEVICEID_5030 0x1211 40641243Swpaul 40741243Swpaul/* 40840516Swpaul * Texas Instruments PHY identifiers 40940516Swpaul */ 41040516Swpaul#define TI_PHY_VENDORID 0x4000 41140516Swpaul#define TI_PHY_10BT 0x501F 41240516Swpaul#define TI_PHY_100VGPMI 0x502F 41340516Swpaul 41440516Swpaul/* 41540516Swpaul * These ID values are for the NS DP83840A 10/100 PHY 41640516Swpaul */ 41740516Swpaul#define NS_PHY_VENDORID 0x2000 41840516Swpaul#define NS_PHY_83840A 0x5C0F 41940516Swpaul 42040516Swpaul/* 42140516Swpaul * Level 1 10/100 PHY 42240516Swpaul */ 42340516Swpaul#define LEVEL1_PHY_VENDORID 0x7810 42440516Swpaul#define LEVEL1_PHY_LXT970 0x000F 42540516Swpaul 42640516Swpaul/* 42740516Swpaul * Intel 82555 10/100 PHY 42840516Swpaul */ 42940516Swpaul#define INTEL_PHY_VENDORID 0x0A28 43040516Swpaul#define INTEL_PHY_82555 0x015F 43140516Swpaul 43240516Swpaul/* 43340516Swpaul * SEEQ 80220 10/100 PHY 43440516Swpaul */ 43540516Swpaul#define SEEQ_PHY_VENDORID 0x0016 43640516Swpaul#define SEEQ_PHY_80220 0xF83F 43740516Swpaul 43840516Swpaul 43940516Swpaul/* 44040516Swpaul * PCI low memory base and low I/O base register, and 44140516Swpaul * other PCI registers. Note: some are only available on 44240516Swpaul * the 3c905B, in particular those that related to power management. 44340516Swpaul */ 44440516Swpaul 44540516Swpaul#define RL_PCI_VENDOR_ID 0x00 44640516Swpaul#define RL_PCI_DEVICE_ID 0x02 44740516Swpaul#define RL_PCI_COMMAND 0x04 44840516Swpaul#define RL_PCI_STATUS 0x06 44940516Swpaul#define RL_PCI_CLASSCODE 0x09 45040516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 45140516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 45240516Swpaul#define RL_PCI_LOIO 0x10 45340516Swpaul#define RL_PCI_LOMEM 0x14 45440516Swpaul#define RL_PCI_BIOSROM 0x30 45540516Swpaul#define RL_PCI_INTLINE 0x3C 45640516Swpaul#define RL_PCI_INTPIN 0x3D 45740516Swpaul#define RL_PCI_MINGNT 0x3E 45840516Swpaul#define RL_PCI_MINLAT 0x0F 45940516Swpaul#define RL_PCI_RESETOPT 0x48 46040516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 46140516Swpaul 46240516Swpaul#define RL_PCI_CAPID 0xDC /* 8 bits */ 46340516Swpaul#define RL_PCI_NEXTPTR 0xDD /* 8 bits */ 46440516Swpaul#define RL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 46540516Swpaul#define RL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 46640516Swpaul 46740516Swpaul#define RL_PSTATE_MASK 0x0003 46840516Swpaul#define RL_PSTATE_D0 0x0000 46940516Swpaul#define RL_PSTATE_D1 0x0002 47040516Swpaul#define RL_PSTATE_D2 0x0002 47140516Swpaul#define RL_PSTATE_D3 0x0003 47240516Swpaul#define RL_PME_EN 0x0010 47340516Swpaul#define RL_PME_STATUS 0x8000 47440516Swpaul 47540516Swpaul#define PHY_UNKNOWN 6 47640516Swpaul 47740516Swpaul#define RL_PHYADDR_MIN 0x00 47840516Swpaul#define RL_PHYADDR_MAX 0x1F 47940516Swpaul 48040516Swpaul#define PHY_BMCR 0x00 48140516Swpaul#define PHY_BMSR 0x01 48240516Swpaul#define PHY_VENID 0x02 48340516Swpaul#define PHY_DEVID 0x03 48440516Swpaul#define PHY_ANAR 0x04 48540516Swpaul#define PHY_LPAR 0x05 48640516Swpaul#define PHY_ANEXP 0x06 48740516Swpaul 48840516Swpaul#define PHY_ANAR_NEXTPAGE 0x8000 48940516Swpaul#define PHY_ANAR_RSVD0 0x4000 49040516Swpaul#define PHY_ANAR_TLRFLT 0x2000 49140516Swpaul#define PHY_ANAR_RSVD1 0x1000 49240516Swpaul#define PHY_ANAR_RSVD2 0x0800 49340516Swpaul#define PHY_ANAR_RSVD3 0x0400 49440516Swpaul#define PHY_ANAR_100BT4 0x0200 49540516Swpaul#define PHY_ANAR_100BTXFULL 0x0100 49640516Swpaul#define PHY_ANAR_100BTXHALF 0x0080 49740516Swpaul#define PHY_ANAR_10BTFULL 0x0040 49840516Swpaul#define PHY_ANAR_10BTHALF 0x0020 49940516Swpaul#define PHY_ANAR_PROTO4 0x0010 50040516Swpaul#define PHY_ANAR_PROTO3 0x0008 50140516Swpaul#define PHY_ANAR_PROTO2 0x0004 50240516Swpaul#define PHY_ANAR_PROTO1 0x0002 50340516Swpaul#define PHY_ANAR_PROTO0 0x0001 50440516Swpaul 50540516Swpaul/* 50640516Swpaul * These are the register definitions for the PHY (physical layer 50740516Swpaul * interface chip). 50840516Swpaul */ 50940516Swpaul/* 51040516Swpaul * PHY BMCR Basic Mode Control Register 51140516Swpaul */ 51240516Swpaul#define PHY_BMCR_RESET 0x8000 51340516Swpaul#define PHY_BMCR_LOOPBK 0x4000 51440516Swpaul#define PHY_BMCR_SPEEDSEL 0x2000 51540516Swpaul#define PHY_BMCR_AUTONEGENBL 0x1000 51640516Swpaul#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 51740516Swpaul#define PHY_BMCR_ISOLATE 0x0400 51840516Swpaul#define PHY_BMCR_AUTONEGRSTR 0x0200 51940516Swpaul#define PHY_BMCR_DUPLEX 0x0100 52040516Swpaul#define PHY_BMCR_COLLTEST 0x0080 52140516Swpaul#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 52240516Swpaul#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 52340516Swpaul#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 52440516Swpaul#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 52540516Swpaul#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 52640516Swpaul#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 52740516Swpaul#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 52840516Swpaul/* 52940516Swpaul * RESET: 1 == software reset, 0 == normal operation 53040516Swpaul * Resets status and control registers to default values. 53140516Swpaul * Relatches all hardware config values. 53240516Swpaul * 53340516Swpaul * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 53440516Swpaul * 53540516Swpaul * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 53640516Swpaul * Link speed is selected byt his bit or if auto-negotiation if bit 53740516Swpaul * 12 (AUTONEGENBL) is set (in which case the value of this register 53840516Swpaul * is ignored). 53940516Swpaul * 54040516Swpaul * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 54140516Swpaul * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 54240516Swpaul * determine speed and mode. Should be cleared and then set if PHY configured 54340516Swpaul * for no autoneg on startup. 54440516Swpaul * 54540516Swpaul * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 54640516Swpaul * 54740516Swpaul * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 54840516Swpaul * 54940516Swpaul * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 55040516Swpaul * 55140516Swpaul * COLLTEST: 1 == collision test enabled, 0 == normal operation 55240516Swpaul */ 55340516Swpaul 55440516Swpaul/* 55540516Swpaul * PHY, BMSR Basic Mode Status Register 55640516Swpaul */ 55740516Swpaul#define PHY_BMSR_100BT4 0x8000 55840516Swpaul#define PHY_BMSR_100BTXFULL 0x4000 55940516Swpaul#define PHY_BMSR_100BTXHALF 0x2000 56040516Swpaul#define PHY_BMSR_10BTFULL 0x1000 56140516Swpaul#define PHY_BMSR_10BTHALF 0x0800 56240516Swpaul#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 56340516Swpaul#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 56440516Swpaul#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 56540516Swpaul#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 56640516Swpaul#define PHY_BMSR_MFPRESUP 0x0040 56740516Swpaul#define PHY_BMSR_AUTONEGCOMP 0x0020 56840516Swpaul#define PHY_BMSR_REMFAULT 0x0010 56940516Swpaul#define PHY_BMSR_CANAUTONEG 0x0008 57040516Swpaul#define PHY_BMSR_LINKSTAT 0x0004 57140516Swpaul#define PHY_BMSR_JABBER 0x0002 57240516Swpaul#define PHY_BMSR_EXTENDED 0x0001 573