if_rlreg.h revision 41243
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_rlreg.h,v 1.13 1998/11/18 20:27:28 wpaul Exp $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102 103/* 104 * TX config register bits 105 */ 106#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 107#define RL_TXCFG_MXDMA0 0x00000100 /* max DMA burst size */ 108#define RL_TXCFG_MXDMA1 0x00000200 109#define RL_TXCFG_MXDMA2 0x00000400 110#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 111#define RL_TXCFG_LOOPBKTST0 0x00020000 /* loopback test */ 112#define RL_TXCFG_LOOPBKTST1 0x00040000 /* loopback test */ 113#define RL_TXCFG_IFG0 0x01000000 /* interframe gap */ 114#define RL_TXCFG_IFG1 0x02000000 /* interframe gap */ 115 116/* 117 * Transmit descriptor status register bits. 118 */ 119#define RL_TXSTAT_LENMASK 0x00001FFF 120#define RL_TXSTAT_OWN 0x00002000 121#define RL_TXSTAT_TX_UNDERRUN 0x00004000 122#define RL_TXSTAT_TX_OK 0x00008000 123#define RL_TXSTAT_EARLY_THRESH 0x003F0000 124#define RL_TXSTAT_COLLCNT 0x0F000000 125#define RL_TXSTAT_CARR_HBEAT 0x10000000 126#define RL_TXSTAT_OUTOFWIN 0x20000000 127#define RL_TXSTAT_TXABRT 0x40000000 128#define RL_TXSTAT_CARRLOSS 0x80000000 129 130/* 131 * Interrupt status register bits. 132 */ 133#define RL_ISR_RX_OK 0x0001 134#define RL_ISR_RX_ERR 0x0002 135#define RL_ISR_TX_OK 0x0004 136#define RL_ISR_TX_ERR 0x0008 137#define RL_ISR_RX_OVERRUN 0x0010 138#define RL_ISR_PKT_UNDERRUN 0x0020 139#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 140#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 141#define RL_ISR_SYSTEM_ERR 0x8000 142 143#define RL_INTRS \ 144 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 145 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 146 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 147 148/* 149 * Media status register. (8139 only) 150 */ 151#define RL_MEDIASTAT_RXPAUSE 0x01 152#define RL_MEDIASTAT_TXPAUSE 0x02 153#define RL_MEDIASTAT_LINK 0x04 154#define RL_MEDIASTAT_SPEED10 0x08 155#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 156#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 157 158/* 159 * Receive config register. 160 */ 161#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 162#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 163#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 164#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 165#define RL_RXCFG_RX_RUNT 0x00000010 166#define RL_RXCFG_RX_ERRPKT 0x00000020 167#define RL_RXCFG_WRAP 0x00000080 168#define RL_RXCFG_MAXDMA (0x00000100|0x00000200|0x00000400) 169#define RL_RXCFG_BUFSZ (0x00000800|0x00001000) 170#define RL_RXCFG_FIFOTHRESH (0x00002000|0x00004000|0x00008000) 171#define RL_RXCFG_EARLYTHRESH (0x01000000|0x02000000|0x04000000) 172 173#define RL_RXBUF_8 0x00000000 174#define RL_RXBUF_16 0x00000800 175#define RL_RXBUF_32 0x00001000 176#define RL_RXBUF_64 (0x00001000|0x00000800) 177 178/* 179 * Bits in RX status header (included with RX'ed packet 180 * in ring buffer). 181 */ 182#define RL_RXSTAT_RXOK 0x00000001 183#define RL_RXSTAT_ALIGNERR 0x00000002 184#define RL_RXSTAT_CRCERR 0x00000004 185#define RL_RXSTAT_GIANT 0x00000008 186#define RL_RXSTAT_RUNT 0x00000010 187#define RL_RXSTAT_BADSYM 0x00000020 188#define RL_RXSTAT_BROAD 0x00002000 189#define RL_RXSTAT_INDIV 0x00004000 190#define RL_RXSTAT_MULTI 0x00008000 191#define RL_RXSTAT_LENMASK 0xFFFF0000 192 193#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 194/* 195 * Command register. 196 */ 197#define RL_CMD_EMPTY_RXBUF 0x0001 198#define RL_CMD_TX_ENB 0x0004 199#define RL_CMD_RX_ENB 0x0008 200#define RL_CMD_RESET 0x0010 201 202/* 203 * EEPROM control register 204 */ 205#define RL_EE_DATAOUT 0x01 /* Data out */ 206#define RL_EE_DATAIN 0x02 /* Data in */ 207#define RL_EE_CLK 0x04 /* clock */ 208#define RL_EE_SEL 0x08 /* chip select */ 209#define RL_EE_MODE (0x40|0x80) 210 211#define RL_EEMODE_OFF 0x00 212#define RL_EEMODE_AUTOLOAD 0x40 213#define RL_EEMODE_PROGRAM 0x80 214#define RL_EEMODE_WRITECFG (0x80|0x40) 215 216/* 9346 EEPROM commands */ 217#define RL_EECMD_WRITE 0x140 218#define RL_EECMD_READ 0x180 219#define RL_EECMD_ERASE 0x1c0 220 221#define RL_EE_ID 0x00 222#define RL_EE_PCI_VID 0x01 223#define RL_EE_PCI_DID 0x02 224/* Location of station address inside EEPROM */ 225#define RL_EE_EADDR 0x07 226 227/* 228 * MII register (8129 only) 229 */ 230#define RL_MII_CLK 0x01 231#define RL_MII_DATAIN 0x02 232#define RL_MII_DATAOUT 0x04 233#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 234 235/* 236 * Config 0 register 237 */ 238#define RL_CFG0_ROM0 0x01 239#define RL_CFG0_ROM1 0x02 240#define RL_CFG0_ROM2 0x04 241#define RL_CFG0_PL0 0x08 242#define RL_CFG0_PL1 0x10 243#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 244#define RL_CFG0_PCS 0x40 245#define RL_CFG0_SCR 0x80 246 247/* 248 * Config 1 register 249 */ 250#define RL_CFG1_PWRDWN 0x01 251#define RL_CFG1_SLEEP 0x02 252#define RL_CFG1_IOMAP 0x04 253#define RL_CFG1_MEMMAP 0x08 254#define RL_CFG1_RSVD 0x10 255#define RL_CFG1_DRVLOAD 0x20 256#define RL_CFG1_LED0 0x40 257#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 258#define RL_CFG1_LED1 0x80 259 260/* 261 * The RealTek doesn't use a fragment-based descriptor mechanism. 262 * Instead, there are only four register sets, each or which represents 263 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 264 * packet buffer (32-bit aligned!) and we place the buffer addresses in 265 * the registers so the chip knows where they are. 266 * 267 * We can sort of kludge together the same kind of buffer management 268 * used in previous drivers, but we have to do buffer copies almost all 269 * the time, so it doesn't really buy us much. 270 * 271 * For reception, there's just one large buffer where the chip stores 272 * all received packets. 273 */ 274 275#define RL_RX_BUF_SZ RL_RXBUF_64 276#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 277#define RL_TX_LIST_CNT 4 278#define RL_MIN_FRAMELEN 60 279#define RL_TX_EARLYTHRESH 0x80000 /* 256 << 11 */ 280#define RL_RX_FIFOTHRESH 0x8000 /* 4 << 13 */ 281#define RL_RX_MAXDMA 0x00000400 282 283#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_BUF_SZ) 284 285struct rl_chain { 286 char rl_desc; /* descriptor register idx */ 287 struct mbuf *rl_mbuf; 288 struct rl_chain *rl_next; 289}; 290 291struct rl_chain_data { 292 u_int16_t cur_rx; 293 caddr_t rl_rx_buf; 294 struct rl_chain rl_tx_chain[RL_TX_LIST_CNT]; 295 296 int rl_tx_cnt; 297 struct rl_chain *rl_tx_cur; 298 struct rl_chain *rl_tx_free; 299}; 300 301struct rl_type { 302 u_int16_t rl_vid; 303 u_int16_t rl_did; 304 char *rl_name; 305}; 306 307struct rl_mii_frame { 308 u_int8_t mii_stdelim; 309 u_int8_t mii_opcode; 310 u_int8_t mii_phyaddr; 311 u_int8_t mii_regaddr; 312 u_int8_t mii_turnaround; 313 u_int16_t mii_data; 314}; 315 316/* 317 * MII constants 318 */ 319#define RL_MII_STARTDELIM 0x01 320#define RL_MII_READOP 0x02 321#define RL_MII_WRITEOP 0x01 322#define RL_MII_TURNAROUND 0x02 323 324#define RL_FLAG_FORCEDELAY 1 325#define RL_FLAG_SCHEDDELAY 2 326#define RL_FLAG_DELAYTIMEO 3 327 328#define RL_8129 1 329#define RL_8139 2 330 331struct rl_softc { 332 struct arpcom arpcom; /* interface info */ 333 struct ifmedia ifmedia; /* media info */ 334 u_int32_t iobase; /* pointer to PIO space */ 335#ifndef RL_USEIOSPACE 336 volatile caddr_t csr; /* pointer to register map */ 337#endif 338 struct rl_type *rl_pinfo; /* phy info */ 339 u_int8_t rl_unit; /* interface number */ 340 u_int8_t rl_type; 341 u_int8_t rl_phy_addr; /* PHY address */ 342 u_int8_t rl_tx_pend; /* TX pending */ 343 u_int8_t rl_want_auto; 344 u_int8_t rl_autoneg; 345 u_int8_t rl_stats_no_timeout; 346 struct rl_chain_data rl_cdata; 347}; 348 349/* 350 * register space access macros 351 */ 352#ifdef RL_USEIOSPACE 353#define CSR_WRITE_4(sc, reg, val) \ 354 outl(sc->iobase + (u_int32_t)(reg), val) 355#define CSR_WRITE_2(sc, reg, val) \ 356 outw(sc->iobase + (u_int32_t)(reg), val) 357#define CSR_WRITE_1(sc, reg, val) \ 358 outb(sc->iobase + (u_int32_t)(reg), val) 359 360#define CSR_READ_4(sc, reg) \ 361 inl(sc->iobase + (u_int32_t)(reg)) 362#define CSR_READ_2(sc, reg) \ 363 inw(sc->iobase + (u_int32_t)(reg)) 364#define CSR_READ_1(sc, reg) \ 365 inb(sc->iobase + (u_int32_t)(reg)) 366#else 367#define CSR_WRITE_4(sc, reg, val) \ 368 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 369#define CSR_WRITE_2(sc, reg, val) \ 370 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 371#define CSR_WRITE_1(sc, reg, val) \ 372 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 373 374#define CSR_READ_4(sc, reg) \ 375 (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 376#define CSR_READ_2(sc, reg) \ 377 (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 378#define CSR_READ_1(sc, reg) \ 379 (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 380#endif 381 382#define RL_TIMEOUT 1000 383 384/* 385 * General constants that are fun to know. 386 * 387 * RealTek PCI vendor ID 388 */ 389#define RT_VENDORID 0x10EC 390 391/* 392 * Accton PCI vendor ID 393 */ 394#define ACCTON_VENDORID 0x1113 395 396/* 397 * RealTek chip device IDs. 398 */ 399#define RT_DEVICEID_8129 0x8129 400#define RT_DEVICEID_8139 0x8139 401 402/* 403 * Accton MPX 5030/5038 device ID. 404 */ 405#define ACCTON_DEVICEID_5030 0x1211 406 407/* 408 * Texas Instruments PHY identifiers 409 */ 410#define TI_PHY_VENDORID 0x4000 411#define TI_PHY_10BT 0x501F 412#define TI_PHY_100VGPMI 0x502F 413 414/* 415 * These ID values are for the NS DP83840A 10/100 PHY 416 */ 417#define NS_PHY_VENDORID 0x2000 418#define NS_PHY_83840A 0x5C0F 419 420/* 421 * Level 1 10/100 PHY 422 */ 423#define LEVEL1_PHY_VENDORID 0x7810 424#define LEVEL1_PHY_LXT970 0x000F 425 426/* 427 * Intel 82555 10/100 PHY 428 */ 429#define INTEL_PHY_VENDORID 0x0A28 430#define INTEL_PHY_82555 0x015F 431 432/* 433 * SEEQ 80220 10/100 PHY 434 */ 435#define SEEQ_PHY_VENDORID 0x0016 436#define SEEQ_PHY_80220 0xF83F 437 438 439/* 440 * PCI low memory base and low I/O base register, and 441 * other PCI registers. Note: some are only available on 442 * the 3c905B, in particular those that related to power management. 443 */ 444 445#define RL_PCI_VENDOR_ID 0x00 446#define RL_PCI_DEVICE_ID 0x02 447#define RL_PCI_COMMAND 0x04 448#define RL_PCI_STATUS 0x06 449#define RL_PCI_CLASSCODE 0x09 450#define RL_PCI_LATENCY_TIMER 0x0D 451#define RL_PCI_HEADER_TYPE 0x0E 452#define RL_PCI_LOIO 0x10 453#define RL_PCI_LOMEM 0x14 454#define RL_PCI_BIOSROM 0x30 455#define RL_PCI_INTLINE 0x3C 456#define RL_PCI_INTPIN 0x3D 457#define RL_PCI_MINGNT 0x3E 458#define RL_PCI_MINLAT 0x0F 459#define RL_PCI_RESETOPT 0x48 460#define RL_PCI_EEPROM_DATA 0x4C 461 462#define RL_PCI_CAPID 0xDC /* 8 bits */ 463#define RL_PCI_NEXTPTR 0xDD /* 8 bits */ 464#define RL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 465#define RL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 466 467#define RL_PSTATE_MASK 0x0003 468#define RL_PSTATE_D0 0x0000 469#define RL_PSTATE_D1 0x0002 470#define RL_PSTATE_D2 0x0002 471#define RL_PSTATE_D3 0x0003 472#define RL_PME_EN 0x0010 473#define RL_PME_STATUS 0x8000 474 475#define PHY_UNKNOWN 6 476 477#define RL_PHYADDR_MIN 0x00 478#define RL_PHYADDR_MAX 0x1F 479 480#define PHY_BMCR 0x00 481#define PHY_BMSR 0x01 482#define PHY_VENID 0x02 483#define PHY_DEVID 0x03 484#define PHY_ANAR 0x04 485#define PHY_LPAR 0x05 486#define PHY_ANEXP 0x06 487 488#define PHY_ANAR_NEXTPAGE 0x8000 489#define PHY_ANAR_RSVD0 0x4000 490#define PHY_ANAR_TLRFLT 0x2000 491#define PHY_ANAR_RSVD1 0x1000 492#define PHY_ANAR_RSVD2 0x0800 493#define PHY_ANAR_RSVD3 0x0400 494#define PHY_ANAR_100BT4 0x0200 495#define PHY_ANAR_100BTXFULL 0x0100 496#define PHY_ANAR_100BTXHALF 0x0080 497#define PHY_ANAR_10BTFULL 0x0040 498#define PHY_ANAR_10BTHALF 0x0020 499#define PHY_ANAR_PROTO4 0x0010 500#define PHY_ANAR_PROTO3 0x0008 501#define PHY_ANAR_PROTO2 0x0004 502#define PHY_ANAR_PROTO1 0x0002 503#define PHY_ANAR_PROTO0 0x0001 504 505/* 506 * These are the register definitions for the PHY (physical layer 507 * interface chip). 508 */ 509/* 510 * PHY BMCR Basic Mode Control Register 511 */ 512#define PHY_BMCR_RESET 0x8000 513#define PHY_BMCR_LOOPBK 0x4000 514#define PHY_BMCR_SPEEDSEL 0x2000 515#define PHY_BMCR_AUTONEGENBL 0x1000 516#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 517#define PHY_BMCR_ISOLATE 0x0400 518#define PHY_BMCR_AUTONEGRSTR 0x0200 519#define PHY_BMCR_DUPLEX 0x0100 520#define PHY_BMCR_COLLTEST 0x0080 521#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 522#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 523#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 524#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 525#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 526#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 527#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 528/* 529 * RESET: 1 == software reset, 0 == normal operation 530 * Resets status and control registers to default values. 531 * Relatches all hardware config values. 532 * 533 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 534 * 535 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 536 * Link speed is selected byt his bit or if auto-negotiation if bit 537 * 12 (AUTONEGENBL) is set (in which case the value of this register 538 * is ignored). 539 * 540 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 541 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 542 * determine speed and mode. Should be cleared and then set if PHY configured 543 * for no autoneg on startup. 544 * 545 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 546 * 547 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 548 * 549 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 550 * 551 * COLLTEST: 1 == collision test enabled, 0 == normal operation 552 */ 553 554/* 555 * PHY, BMSR Basic Mode Status Register 556 */ 557#define PHY_BMSR_100BT4 0x8000 558#define PHY_BMSR_100BTXFULL 0x4000 559#define PHY_BMSR_100BTXHALF 0x2000 560#define PHY_BMSR_10BTFULL 0x1000 561#define PHY_BMSR_10BTHALF 0x0800 562#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 563#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 564#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 565#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 566#define PHY_BMSR_MFPRESUP 0x0040 567#define PHY_BMSR_AUTONEGCOMP 0x0020 568#define PHY_BMSR_REMFAULT 0x0010 569#define PHY_BMSR_CANAUTONEG 0x0008 570#define PHY_BMSR_LINKSTAT 0x0004 571#define PHY_BMSR_JABBER 0x0002 572#define PHY_BMSR_EXTENDED 0x0001 573