if_rlreg.h revision 159962
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 159962 2006-06-26 20:31:32Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79120043Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113120043Swpaul#define RL_CFG2 0x0053 114117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 116117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12040516Swpaul 12140516Swpaul/* 122117388Swpaul * Registers specific to the 8169 gigE chip 123117388Swpaul */ 124118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125117388Swpaul#define RL_PHYAR 0x0060 126117388Swpaul#define RL_TBICSR 0x0064 127117388Swpaul#define RL_TBI_ANAR 0x0068 128117388Swpaul#define RL_TBI_LPAR 0x006A 129117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 132117388Swpaul 133117388Swpaul/* 13440516Swpaul * TX config register bits 13540516Swpaul */ 13640516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13745633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13840516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13945633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14145633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14340516Swpaul 144119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 145119868Swpaul#define RL_LOOPTEST_ON 0x00020000 146119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 147119868Swpaul 148159962Swpaul/* Known revision codes. */ 149117388Swpaul 150159962Swpaul#define RL_HWREV_8169 0x00000000 151159962Swpaul#define RL_HWREV_8110S 0x00800000 152159962Swpaul#define RL_HWREV_8169S 0x04000000 153159962Swpaul#define RL_HWREV_8169_8110SB 0x10000000 154159962Swpaul#define RL_HWREV_8169_8110SC 0x18000000 155159962Swpaul#define RL_HWREV_8100E 0x30800000 156159962Swpaul#define RL_HWREV_8101E 0x34000000 157159962Swpaul#define RL_HWREV_8168 0x38000000 158159962Swpaul#define RL_HWREV_8139 0x60000000 159159962Swpaul#define RL_HWREV_8139A 0x70000000 160159962Swpaul#define RL_HWREV_8139AG 0x70800000 161159962Swpaul#define RL_HWREV_8139B 0x78000000 162159962Swpaul#define RL_HWREV_8130 0x7C000000 163159962Swpaul#define RL_HWREV_8139C 0x74000000 164159962Swpaul#define RL_HWREV_8139D 0x74400000 165159962Swpaul#define RL_HWREV_8139CPLUS 0x74800000 166159962Swpaul#define RL_HWREV_8101 0x74c00000 167159962Swpaul#define RL_HWREV_8100 0x78800000 168159962Swpaul 16945633Swpaul#define RL_TXDMA_16BYTES 0x00000000 17045633Swpaul#define RL_TXDMA_32BYTES 0x00000100 17145633Swpaul#define RL_TXDMA_64BYTES 0x00000200 17245633Swpaul#define RL_TXDMA_128BYTES 0x00000300 17345633Swpaul#define RL_TXDMA_256BYTES 0x00000400 17445633Swpaul#define RL_TXDMA_512BYTES 0x00000500 17545633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 17645633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 17745633Swpaul 17840516Swpaul/* 17940516Swpaul * Transmit descriptor status register bits. 18040516Swpaul */ 18140516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 18240516Swpaul#define RL_TXSTAT_OWN 0x00002000 18340516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 18440516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 18540516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 18640516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 18740516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 18840516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 18940516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 19040516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 19140516Swpaul 19240516Swpaul/* 19340516Swpaul * Interrupt status register bits. 19440516Swpaul */ 19540516Swpaul#define RL_ISR_RX_OK 0x0001 19640516Swpaul#define RL_ISR_RX_ERR 0x0002 19740516Swpaul#define RL_ISR_TX_OK 0x0004 19840516Swpaul#define RL_ISR_TX_ERR 0x0008 19940516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 20040516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 201119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 20240516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 203117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 204117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 205117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 20640516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 207117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 20840516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 20940516Swpaul 21040516Swpaul#define RL_INTRS \ 21140516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 21240516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 21340516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 21440516Swpaul 215159962Swpaul#ifdef RE_TX_MODERATION 216117388Swpaul#define RL_INTRS_CPLUS \ 217119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 218117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 219117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 220159962Swpaul#else 221159962Swpaul#define RL_INTRS_CPLUS \ 222159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 223159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 224159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 225159962Swpaul#endif 226117388Swpaul 22740516Swpaul/* 22840516Swpaul * Media status register. (8139 only) 22940516Swpaul */ 23040516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 23140516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 23240516Swpaul#define RL_MEDIASTAT_LINK 0x04 23340516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 23440516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 23540516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 23640516Swpaul 23740516Swpaul/* 23840516Swpaul * Receive config register. 23940516Swpaul */ 24040516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 24140516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 24240516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 24340516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 24440516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 24540516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 24640516Swpaul#define RL_RXCFG_WRAP 0x00000080 24745633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 24845633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 24945633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 25045633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 25140516Swpaul 25245633Swpaul#define RL_RXDMA_16BYTES 0x00000000 25345633Swpaul#define RL_RXDMA_32BYTES 0x00000100 25445633Swpaul#define RL_RXDMA_64BYTES 0x00000200 25545633Swpaul#define RL_RXDMA_128BYTES 0x00000300 25645633Swpaul#define RL_RXDMA_256BYTES 0x00000400 25745633Swpaul#define RL_RXDMA_512BYTES 0x00000500 25845633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 25945633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 26045633Swpaul 26140516Swpaul#define RL_RXBUF_8 0x00000000 26240516Swpaul#define RL_RXBUF_16 0x00000800 26340516Swpaul#define RL_RXBUF_32 0x00001000 26445633Swpaul#define RL_RXBUF_64 0x00001800 26540516Swpaul 26645633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 26745633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 26845633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 26945633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 27045633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 27145633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 27245633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 27345633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 27445633Swpaul 27540516Swpaul/* 27640516Swpaul * Bits in RX status header (included with RX'ed packet 27740516Swpaul * in ring buffer). 27840516Swpaul */ 27940516Swpaul#define RL_RXSTAT_RXOK 0x00000001 28040516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 28140516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 28240516Swpaul#define RL_RXSTAT_GIANT 0x00000008 28340516Swpaul#define RL_RXSTAT_RUNT 0x00000010 28440516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 28540516Swpaul#define RL_RXSTAT_BROAD 0x00002000 28640516Swpaul#define RL_RXSTAT_INDIV 0x00004000 28740516Swpaul#define RL_RXSTAT_MULTI 0x00008000 28840516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 28940516Swpaul 29040516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 29140516Swpaul/* 29240516Swpaul * Command register. 29340516Swpaul */ 29440516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 29540516Swpaul#define RL_CMD_TX_ENB 0x0004 29640516Swpaul#define RL_CMD_RX_ENB 0x0008 29740516Swpaul#define RL_CMD_RESET 0x0010 29840516Swpaul 29940516Swpaul/* 30040516Swpaul * EEPROM control register 30140516Swpaul */ 30240516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 30340516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 30440516Swpaul#define RL_EE_CLK 0x04 /* clock */ 30540516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 30640516Swpaul#define RL_EE_MODE (0x40|0x80) 30740516Swpaul 30840516Swpaul#define RL_EEMODE_OFF 0x00 30940516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 31040516Swpaul#define RL_EEMODE_PROGRAM 0x80 31140516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 31240516Swpaul 31340516Swpaul/* 9346 EEPROM commands */ 314159962Swpaul 315159962Swpaul#define RL_9346_WRITE 0x5 316159962Swpaul#define RL_9346_READ 0x6 317159962Swpaul#define RL_9346_ERASE 0x7 318159962Swpaul#define RL_9346_EWEN 0x4 319159962Swpaul#define RL_9346_EWEN_ADDR 0x30 320159962Swpaul#define RL_9456_EWDS 0x4 321159962Swpaul#define RL_9346_EWDS_ADDR 0x00 322159962Swpaul 32340516Swpaul#define RL_EECMD_WRITE 0x140 32467931Swpaul#define RL_EECMD_READ_6BIT 0x180 32567931Swpaul#define RL_EECMD_READ_8BIT 0x600 32640516Swpaul#define RL_EECMD_ERASE 0x1c0 32740516Swpaul 32840516Swpaul#define RL_EE_ID 0x00 32940516Swpaul#define RL_EE_PCI_VID 0x01 33040516Swpaul#define RL_EE_PCI_DID 0x02 33140516Swpaul/* Location of station address inside EEPROM */ 33240516Swpaul#define RL_EE_EADDR 0x07 33340516Swpaul 33440516Swpaul/* 33540516Swpaul * MII register (8129 only) 33640516Swpaul */ 33740516Swpaul#define RL_MII_CLK 0x01 33840516Swpaul#define RL_MII_DATAIN 0x02 33940516Swpaul#define RL_MII_DATAOUT 0x04 34040516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 34140516Swpaul 34240516Swpaul/* 34340516Swpaul * Config 0 register 34440516Swpaul */ 34540516Swpaul#define RL_CFG0_ROM0 0x01 34640516Swpaul#define RL_CFG0_ROM1 0x02 34740516Swpaul#define RL_CFG0_ROM2 0x04 34840516Swpaul#define RL_CFG0_PL0 0x08 34940516Swpaul#define RL_CFG0_PL1 0x10 35040516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 35140516Swpaul#define RL_CFG0_PCS 0x40 35240516Swpaul#define RL_CFG0_SCR 0x80 35340516Swpaul 35440516Swpaul/* 35540516Swpaul * Config 1 register 35640516Swpaul */ 35740516Swpaul#define RL_CFG1_PWRDWN 0x01 35840516Swpaul#define RL_CFG1_SLEEP 0x02 35940516Swpaul#define RL_CFG1_IOMAP 0x04 36040516Swpaul#define RL_CFG1_MEMMAP 0x08 36140516Swpaul#define RL_CFG1_RSVD 0x10 36240516Swpaul#define RL_CFG1_DRVLOAD 0x20 36340516Swpaul#define RL_CFG1_LED0 0x40 36440516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 36540516Swpaul#define RL_CFG1_LED1 0x80 36640516Swpaul 36740516Swpaul/* 368117388Swpaul * 8139C+ register definitions 369117388Swpaul */ 370117388Swpaul 371117388Swpaul/* RL_DUMPSTATS_LO register */ 372117388Swpaul 373117388Swpaul#define RL_DUMPSTATS_START 0x00000008 374117388Swpaul 375117388Swpaul/* Transmit start register */ 376117388Swpaul 377117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 378117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 379117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 380117388Swpaul 381120043Swpaul/* 382120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 383120043Swpaul */ 384120043Swpaul#define RL_CFG2_BUSFREQ 0x07 385120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 386120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 387120043Swpaul 388120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 389120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 390120043Swpaul 391120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 392120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 393120043Swpaul 394117388Swpaul/* C+ mode command register */ 395117388Swpaul 396117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 397117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 398117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 399117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 400117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 401117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 402117388Swpaul 403117388Swpaul/* C+ early transmit threshold */ 404117388Swpaul 405117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 406117388Swpaul 407117388Swpaul/* 408117388Swpaul * Gigabit PHY access register (8169 only) 409117388Swpaul */ 410117388Swpaul 411117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 412117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 413117388Swpaul#define RL_PHYAR_BUSY 0x80000000 414117388Swpaul 415117388Swpaul/* 416117388Swpaul * Gigabit media status (8169 only) 417117388Swpaul */ 418117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 419117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 420117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 421117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 422119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 423117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 424117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 425117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 426117388Swpaul 427117388Swpaul/* 42840516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 42940516Swpaul * Instead, there are only four register sets, each or which represents 43040516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 43140516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 43240516Swpaul * the registers so the chip knows where they are. 43340516Swpaul * 43440516Swpaul * We can sort of kludge together the same kind of buffer management 43540516Swpaul * used in previous drivers, but we have to do buffer copies almost all 43640516Swpaul * the time, so it doesn't really buy us much. 43740516Swpaul * 43840516Swpaul * For reception, there's just one large buffer where the chip stores 43940516Swpaul * all received packets. 44040516Swpaul */ 44140516Swpaul 44240516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 44340516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 44440516Swpaul#define RL_TX_LIST_CNT 4 44540516Swpaul#define RL_MIN_FRAMELEN 60 44652426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 44752426Swpaul#define RL_TX_THRESH_INIT 96 448119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 449119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 45050703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 45140516Swpaul 45245633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 45345633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 45440516Swpaul 45548028Swpaul#define RL_ETHER_ALIGN 2 45648028Swpaul 45740516Swpaulstruct rl_chain_data { 458131605Sbms uint16_t cur_rx; 459131605Sbms uint8_t *rl_rx_buf; 460131605Sbms uint8_t *rl_rx_buf_ptr; 46181713Swpaul bus_dmamap_t rl_rx_dmamap; 46240516Swpaul 46345633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 46481713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 465131605Sbms uint8_t last_tx; 466131605Sbms uint8_t cur_tx; 46740516Swpaul}; 46840516Swpaul 46945633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 47045633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 47145633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 47245633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 47381713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 47445633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 47545633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 47645633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 47781713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 47845633Swpaul 47940516Swpaulstruct rl_type { 480131605Sbms uint16_t rl_vid; 481131605Sbms uint16_t rl_did; 482117388Swpaul int rl_basetype; 48340516Swpaul char *rl_name; 48440516Swpaul}; 48540516Swpaul 486117388Swpaulstruct rl_hwrev { 487131605Sbms uint32_t rl_rev; 488117388Swpaul int rl_type; 489117388Swpaul char *rl_desc; 490117388Swpaul}; 491117388Swpaul 49240516Swpaulstruct rl_mii_frame { 493131605Sbms uint8_t mii_stdelim; 494131605Sbms uint8_t mii_opcode; 495131605Sbms uint8_t mii_phyaddr; 496131605Sbms uint8_t mii_regaddr; 497131605Sbms uint8_t mii_turnaround; 498131605Sbms uint16_t mii_data; 49940516Swpaul}; 50040516Swpaul 50140516Swpaul/* 50240516Swpaul * MII constants 50340516Swpaul */ 50440516Swpaul#define RL_MII_STARTDELIM 0x01 50540516Swpaul#define RL_MII_READOP 0x02 50640516Swpaul#define RL_MII_WRITEOP 0x01 50740516Swpaul#define RL_MII_TURNAROUND 0x02 50840516Swpaul 50940516Swpaul#define RL_8129 1 51040516Swpaul#define RL_8139 2 511117388Swpaul#define RL_8139CPLUS 3 512117388Swpaul#define RL_8169 4 51340516Swpaul 514117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 515117388Swpaul (x)->rl_type == RL_8169) 516117388Swpaul 517117388Swpaul/* 518117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 519117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 520117388Swpaul * must be allocated in contiguous blocks that are aligned on a 521117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 522117388Swpaul */ 523117388Swpaul 524117388Swpaul/* 525117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 526117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 527117388Swpaul * the checksum offload bits are disabled. The structure layout is 528117388Swpaul * the same for RX and TX descriptors 529117388Swpaul */ 530117388Swpaul 531117388Swpaulstruct rl_desc { 532131605Sbms uint32_t rl_cmdstat; 533131605Sbms uint32_t rl_vlanctl; 534131605Sbms uint32_t rl_bufaddr_lo; 535131605Sbms uint32_t rl_bufaddr_hi; 536117388Swpaul}; 537117388Swpaul 538117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 539117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 540117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 541117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 542117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 543117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 544117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 545117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 546117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 547117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 548117388Swpaul 549117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 550117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 551117388Swpaul 552117388Swpaul/* 553117388Swpaul * Error bits are valid only on the last descriptor of a frame 554117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 555117388Swpaul */ 556117388Swpaul 557117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 558117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 559117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 560117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 561117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 562117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 563117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 564117388Swpaul 565117388Swpaul/* 566117388Swpaul * RX descriptor cmd/vlan definitions 567117388Swpaul */ 568117388Swpaul 569117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 570117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 571119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 572117388Swpaul 573117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 574117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 575117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 576117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 577117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 578117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 579117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 580117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 581117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 582117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 583117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 584117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 585117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 586117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 587117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 588117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 589117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 590117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 591119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 592119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 593135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 594135896Sjmg RL_RDESC_STAT_CRCERR) 595117388Swpaul 596117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 597117388Swpaul (rl_vlandata valid)*/ 598117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 599117388Swpaul 600117388Swpaul#define RL_PROTOID_NONIP 0x00000000 601117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 602117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 603117388Swpaul#define RL_PROTOID_IP 0x00030000 604117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 605117388Swpaul RL_PROTOID_TCPIP) 606117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 607117388Swpaul RL_PROTOID_UDPIP) 608117388Swpaul 609117388Swpaul/* 610117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 611117388Swpaul */ 612117388Swpaulstruct rl_stats { 613131605Sbms uint32_t rl_tx_pkts_lo; 614131605Sbms uint32_t rl_tx_pkts_hi; 615131605Sbms uint32_t rl_tx_errs_lo; 616131605Sbms uint32_t rl_tx_errs_hi; 617131605Sbms uint32_t rl_tx_errs; 618131605Sbms uint16_t rl_missed_pkts; 619131605Sbms uint16_t rl_rx_framealign_errs; 620131605Sbms uint32_t rl_tx_onecoll; 621131605Sbms uint32_t rl_tx_multicolls; 622131605Sbms uint32_t rl_rx_ucasts_hi; 623131605Sbms uint32_t rl_rx_ucasts_lo; 624131605Sbms uint32_t rl_rx_bcasts_lo; 625131605Sbms uint32_t rl_rx_bcasts_hi; 626131605Sbms uint32_t rl_rx_mcasts; 627131605Sbms uint16_t rl_tx_aborts; 628131605Sbms uint16_t rl_rx_underruns; 629117388Swpaul}; 630117388Swpaul 631135467Sjmg/* 632135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 633135467Sjmg * 634135467Sjmg * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 635135896Sjmg * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 636135896Sjmg * due to the 8139C+. We need to put the number of descriptors in the ring 637135896Sjmg * structure and use that value instead. 638135467Sjmg */ 639135896Sjmg#if !defined(__i386__) && !defined(__amd64__) 640135896Sjmg#define RE_FIXUP_RX 1 641135896Sjmg#endif 642135896Sjmg 643117388Swpaul#define RL_TX_DESC_CNT 64 644135469Sjmg#define RL_RX_DESC_CNT RL_TX_DESC_CNT 645159962Swpaul 646117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 647117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 648117388Swpaul#define RL_RING_ALIGN 256 649117388Swpaul#define RL_IFQ_MAXLEN 512 650117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 651117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 652119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 653119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 654135896Sjmg#ifdef RE_FIXUP_RX 655135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 656135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 657135896Sjmg#else 658135896Sjmg#define RE_ETHER_ALIGN 0 659135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 660135896Sjmg#endif 661117388Swpaul 662135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 663135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 664118712Swpaul 665135896Sjmg/* see comment in dev/re/if_re.c */ 666135896Sjmg#define RL_JUMBO_FRAMELEN 7440 667119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 668119868Swpaul 669117388Swpaulstruct rl_softc; 670117388Swpaul 671117388Swpaulstruct rl_dmaload_arg { 672117388Swpaul struct rl_softc *sc; 673117388Swpaul int rl_idx; 674117388Swpaul int rl_maxsegs; 675131605Sbms uint32_t rl_flags; 676117388Swpaul struct rl_desc *rl_ring; 677117388Swpaul}; 678117388Swpaul 679117388Swpaulstruct rl_list_data { 680117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 681159962Swpaul struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 682117388Swpaul int rl_tx_prodidx; 683117388Swpaul int rl_rx_prodidx; 684117388Swpaul int rl_tx_considx; 685117388Swpaul int rl_tx_free; 686117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 687117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 688117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 689117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 690117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 691117388Swpaul struct rl_stats *rl_stats; 692118712Swpaul bus_addr_t rl_stats_addr; 693117388Swpaul bus_dma_tag_t rl_rx_list_tag; 694117388Swpaul bus_dmamap_t rl_rx_list_map; 695117388Swpaul struct rl_desc *rl_rx_list; 696118712Swpaul bus_addr_t rl_rx_list_addr; 697117388Swpaul bus_dma_tag_t rl_tx_list_tag; 698117388Swpaul bus_dmamap_t rl_tx_list_map; 699117388Swpaul struct rl_desc *rl_tx_list; 700118712Swpaul bus_addr_t rl_tx_list_addr; 701117388Swpaul}; 702117388Swpaul 70340516Swpaulstruct rl_softc { 704147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 70541569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 70641569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 707159962Swpaul device_t rl_dev; 70850703Swpaul struct resource *rl_res; 70950703Swpaul struct resource *rl_irq; 71050703Swpaul void *rl_intrhand; 71150703Swpaul device_t rl_miibus; 71281713Swpaul bus_dma_tag_t rl_parent_tag; 71381713Swpaul bus_dma_tag_t rl_tag; 714131605Sbms uint8_t rl_type; 71567931Swpaul int rl_eecmd_read; 716159962Swpaul int rl_eewidth; 717131605Sbms uint8_t rl_stats_no_timeout; 71852426Swpaul int rl_txthresh; 71940516Swpaul struct rl_chain_data rl_cdata; 720117388Swpaul struct rl_list_data rl_ldata; 721150720Sjhb struct callout rl_stat_callout; 72267087Swpaul struct mtx rl_mtx; 723119868Swpaul struct mbuf *rl_head; 724119868Swpaul struct mbuf *rl_tail; 725131605Sbms uint32_t rl_hwrev; 726131605Sbms uint32_t rl_rxlenmask; 727119868Swpaul int rl_testmode; 72886822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 72994883Sluigi#ifdef DEVICE_POLLING 73094883Sluigi int rxcycles; 73194883Sluigi#endif 732159962Swpaul 733159962Swpaul struct task rl_txtask; 734159962Swpaul struct task rl_inttask; 735159962Swpaul 736159962Swpaul struct mtx rl_intlock; 737159962Swpaul int rl_txstart; 738159962Swpaul int rl_link; 73940516Swpaul}; 74040516Swpaul 74172200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 74272200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 743122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 74467087Swpaul 74540516Swpaul/* 74640516Swpaul * register space access macros 74740516Swpaul */ 748119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 749119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 75040516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 75141569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 75240516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 75341569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 75440516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 75541569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 75640516Swpaul 75741569Swpaul#define CSR_READ_4(sc, reg) \ 75841569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 75941569Swpaul#define CSR_READ_2(sc, reg) \ 76041569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 76141569Swpaul#define CSR_READ_1(sc, reg) \ 76241569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 76340516Swpaul 764159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 765159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 766159962Swpaul 767159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 768159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 769159962Swpaul 770159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 771159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 772159962Swpaul 773159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 774159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 775159962Swpaul 776159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 777159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 778159962Swpaul 779159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 780159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 781159962Swpaul 78240516Swpaul#define RL_TIMEOUT 1000 78340516Swpaul 78440516Swpaul/* 78540516Swpaul * General constants that are fun to know. 78640516Swpaul * 78740516Swpaul * RealTek PCI vendor ID 78840516Swpaul */ 78940516Swpaul#define RT_VENDORID 0x10EC 79040516Swpaul 79140516Swpaul/* 79240516Swpaul * RealTek chip device IDs. 79340516Swpaul */ 79440516Swpaul#define RT_DEVICEID_8129 0x8129 795159962Swpaul#define RT_DEVICEID_8101E 0x8136 79667771Swpaul#define RT_DEVICEID_8138 0x8138 79740516Swpaul#define RT_DEVICEID_8139 0x8139 798159962Swpaul#define RT_DEVICEID_8169SC 0x8167 799159962Swpaul#define RT_DEVICEID_8168 0x8168 800117388Swpaul#define RT_DEVICEID_8169 0x8169 801118978Swpaul#define RT_DEVICEID_8100 0x8100 80240516Swpaul 803117388Swpaul#define RT_REVID_8139CPLUS 0x20 804117388Swpaul 80540516Swpaul/* 80644238Swpaul * Accton PCI vendor ID 80744238Swpaul */ 80844238Swpaul#define ACCTON_VENDORID 0x1113 80944238Swpaul 81044238Swpaul/* 81141243Swpaul * Accton MPX 5030/5038 device ID. 81241243Swpaul */ 81341243Swpaul#define ACCTON_DEVICEID_5030 0x1211 81441243Swpaul 81541243Swpaul/* 81694400Swpaul * Nortel PCI vendor ID 81794400Swpaul */ 81894400Swpaul#define NORTEL_VENDORID 0x126C 81994400Swpaul 82094400Swpaul/* 82144238Swpaul * Delta Electronics Vendor ID. 82244238Swpaul */ 82344238Swpaul#define DELTA_VENDORID 0x1500 82444238Swpaul 82544238Swpaul/* 82644238Swpaul * Delta device IDs. 82744238Swpaul */ 82844238Swpaul#define DELTA_DEVICEID_8139 0x1360 82944238Swpaul 83044238Swpaul/* 83144238Swpaul * Addtron vendor ID. 83244238Swpaul */ 83344238Swpaul#define ADDTRON_VENDORID 0x4033 83444238Swpaul 83544238Swpaul/* 83644238Swpaul * Addtron device IDs. 83744238Swpaul */ 83844238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 83944238Swpaul 84044238Swpaul/* 84172813Swpaul * D-Link vendor ID. 84272813Swpaul */ 84372813Swpaul#define DLINK_VENDORID 0x1186 84472813Swpaul 84572813Swpaul/* 84672813Swpaul * D-Link DFE-530TX+ device ID 84772813Swpaul */ 84872813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 84972813Swpaul 85072813Swpaul/* 851148722Stobez * D-Link DFE-5280T device ID 852148722Stobez */ 853148722Stobez#define DLINK_DEVICEID_528T 0x4300 854148722Stobez 855148722Stobez/* 85696112Sjhb * D-Link DFE-690TXD device ID 85796112Sjhb */ 85896112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 85996112Sjhb 86096112Sjhb/* 861103020Siwasaki * Corega K.K vendor ID 862103020Siwasaki */ 863103020Siwasaki#define COREGA_VENDORID 0x1259 864103020Siwasaki 865103020Siwasaki/* 866109095Ssanpei * Corega FEther CB-TXD device ID 867103020Siwasaki */ 868151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 869103020Siwasaki 870103020Siwasaki/* 871109095Ssanpei * Corega FEtherII CB-TXD device ID 872109095Ssanpei */ 873151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 874109095Ssanpei 875111381Sdan/* 876134433Ssanpei * Corega CG-LAPCIGT device ID 877134433Ssanpei */ 878134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 879134433Ssanpei 880134433Ssanpei/* 881151341Sjhb * Linksys vendor ID 882151341Sjhb */ 883151341Sjhb#define LINKSYS_VENDORID 0x1737 884151341Sjhb 885151341Sjhb/* 886151341Sjhb * Linksys EG1032 device ID 887151341Sjhb */ 888151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 889151341Sjhb 890151341Sjhb/* 891151341Sjhb * Linksys EG1032 rev 3 sub-device ID 892151341Sjhb */ 893151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 894151341Sjhb 895151341Sjhb/* 896111381Sdan * Peppercon vendor ID 897111381Sdan */ 898111381Sdan#define PEPPERCON_VENDORID 0x1743 899109095Ssanpei 900111381Sdan/* 901111381Sdan * Peppercon ROL-F device ID 902111381Sdan */ 903111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 904109095Ssanpei 905109095Ssanpei/* 906112379Ssanpei * Planex Communications, Inc. vendor ID 907112379Ssanpei */ 908117388Swpaul#define PLANEX_VENDORID 0x14ea 909112379Ssanpei 910112379Ssanpei/* 911112379Ssanpei * Planex FNW-3800-TX device ID 912112379Ssanpei */ 913117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 914112379Ssanpei 915112379Ssanpei/* 916117388Swpaul * LevelOne vendor ID 917117388Swpaul */ 918117388Swpaul#define LEVEL1_VENDORID 0x018A 919117388Swpaul 920117388Swpaul/* 921117388Swpaul * LevelOne FPC-0106TX devide ID 922117388Swpaul */ 923117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 924117388Swpaul 925117388Swpaul/* 926117388Swpaul * Compaq vendor ID 927117388Swpaul */ 928117388Swpaul#define CP_VENDORID 0x021B 929117388Swpaul 930117388Swpaul/* 931117388Swpaul * Edimax vendor ID 932117388Swpaul */ 933117388Swpaul#define EDIMAX_VENDORID 0x13D1 934117388Swpaul 935117388Swpaul/* 936117388Swpaul * Edimax EP-4103DL cardbus device ID 937117388Swpaul */ 938117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 939117388Swpaul 940117388Swpaul/* 94140516Swpaul * PCI low memory base and low I/O base register, and 94250703Swpaul * other PCI registers. 94340516Swpaul */ 94440516Swpaul 94540516Swpaul#define RL_PCI_VENDOR_ID 0x00 94640516Swpaul#define RL_PCI_DEVICE_ID 0x02 94740516Swpaul#define RL_PCI_COMMAND 0x04 94840516Swpaul#define RL_PCI_STATUS 0x06 94940516Swpaul#define RL_PCI_CLASSCODE 0x09 95040516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 95140516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 95240516Swpaul#define RL_PCI_LOIO 0x10 95340516Swpaul#define RL_PCI_LOMEM 0x14 95440516Swpaul#define RL_PCI_BIOSROM 0x30 95540516Swpaul#define RL_PCI_INTLINE 0x3C 95640516Swpaul#define RL_PCI_INTPIN 0x3D 95740516Swpaul#define RL_PCI_MINGNT 0x3E 95840516Swpaul#define RL_PCI_MINLAT 0x0F 95940516Swpaul#define RL_PCI_RESETOPT 0x48 96040516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 96140516Swpaul 96250097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 96350097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 96450097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 96550097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 96640516Swpaul 96740516Swpaul#define RL_PSTATE_MASK 0x0003 96840516Swpaul#define RL_PSTATE_D0 0x0000 96940516Swpaul#define RL_PSTATE_D1 0x0002 97040516Swpaul#define RL_PSTATE_D2 0x0002 97140516Swpaul#define RL_PSTATE_D3 0x0003 97240516Swpaul#define RL_PME_EN 0x0010 97340516Swpaul#define RL_PME_STATUS 0x8000 974