if_rlreg.h revision 159962
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 159962 2006-06-26 20:31:32Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102/* 103 * When operating in special C+ mode, some of the registers in an 104 * 8139C+ chip have different definitions. These are also used for 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113#define RL_CFG2 0x0053 114#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115#define RL_TXSTART 0x00D9 /* 8 bits */ 116#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 120 121/* 122 * Registers specific to the 8169 gigE chip 123 */ 124#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125#define RL_PHYAR 0x0060 126#define RL_TBICSR 0x0064 127#define RL_TBI_ANAR 0x0068 128#define RL_TBI_LPAR 0x006A 129#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131#define RL_GTXSTART 0x0038 /* 16 bits */ 132 133/* 134 * TX config register bits 135 */ 136#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 137#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 138#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 139#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 141#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142#define RL_TXCFG_HWREV 0x7CC00000 143 144#define RL_LOOPTEST_OFF 0x00000000 145#define RL_LOOPTEST_ON 0x00020000 146#define RL_LOOPTEST_ON_CPLUS 0x00060000 147 148/* Known revision codes. */ 149 150#define RL_HWREV_8169 0x00000000 151#define RL_HWREV_8110S 0x00800000 152#define RL_HWREV_8169S 0x04000000 153#define RL_HWREV_8169_8110SB 0x10000000 154#define RL_HWREV_8169_8110SC 0x18000000 155#define RL_HWREV_8100E 0x30800000 156#define RL_HWREV_8101E 0x34000000 157#define RL_HWREV_8168 0x38000000 158#define RL_HWREV_8139 0x60000000 159#define RL_HWREV_8139A 0x70000000 160#define RL_HWREV_8139AG 0x70800000 161#define RL_HWREV_8139B 0x78000000 162#define RL_HWREV_8130 0x7C000000 163#define RL_HWREV_8139C 0x74000000 164#define RL_HWREV_8139D 0x74400000 165#define RL_HWREV_8139CPLUS 0x74800000 166#define RL_HWREV_8101 0x74c00000 167#define RL_HWREV_8100 0x78800000 168 169#define RL_TXDMA_16BYTES 0x00000000 170#define RL_TXDMA_32BYTES 0x00000100 171#define RL_TXDMA_64BYTES 0x00000200 172#define RL_TXDMA_128BYTES 0x00000300 173#define RL_TXDMA_256BYTES 0x00000400 174#define RL_TXDMA_512BYTES 0x00000500 175#define RL_TXDMA_1024BYTES 0x00000600 176#define RL_TXDMA_2048BYTES 0x00000700 177 178/* 179 * Transmit descriptor status register bits. 180 */ 181#define RL_TXSTAT_LENMASK 0x00001FFF 182#define RL_TXSTAT_OWN 0x00002000 183#define RL_TXSTAT_TX_UNDERRUN 0x00004000 184#define RL_TXSTAT_TX_OK 0x00008000 185#define RL_TXSTAT_EARLY_THRESH 0x003F0000 186#define RL_TXSTAT_COLLCNT 0x0F000000 187#define RL_TXSTAT_CARR_HBEAT 0x10000000 188#define RL_TXSTAT_OUTOFWIN 0x20000000 189#define RL_TXSTAT_TXABRT 0x40000000 190#define RL_TXSTAT_CARRLOSS 0x80000000 191 192/* 193 * Interrupt status register bits. 194 */ 195#define RL_ISR_RX_OK 0x0001 196#define RL_ISR_RX_ERR 0x0002 197#define RL_ISR_TX_OK 0x0004 198#define RL_ISR_TX_ERR 0x0008 199#define RL_ISR_RX_OVERRUN 0x0010 200#define RL_ISR_PKT_UNDERRUN 0x0020 201#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 202#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 203#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 204#define RL_ISR_SWI 0x0100 /* C+ only */ 205#define RL_ISR_CABLE_LEN_CHGD 0x2000 206#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 207#define RL_ISR_TIMEOUT_EXPIRED 0x4000 208#define RL_ISR_SYSTEM_ERR 0x8000 209 210#define RL_INTRS \ 211 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 212 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 213 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 214 215#ifdef RE_TX_MODERATION 216#define RL_INTRS_CPLUS \ 217 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 220#else 221#define RL_INTRS_CPLUS \ 222 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 223 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 224 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 225#endif 226 227/* 228 * Media status register. (8139 only) 229 */ 230#define RL_MEDIASTAT_RXPAUSE 0x01 231#define RL_MEDIASTAT_TXPAUSE 0x02 232#define RL_MEDIASTAT_LINK 0x04 233#define RL_MEDIASTAT_SPEED10 0x08 234#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 235#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 236 237/* 238 * Receive config register. 239 */ 240#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 241#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 242#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 243#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 244#define RL_RXCFG_RX_RUNT 0x00000010 245#define RL_RXCFG_RX_ERRPKT 0x00000020 246#define RL_RXCFG_WRAP 0x00000080 247#define RL_RXCFG_MAXDMA 0x00000700 248#define RL_RXCFG_BUFSZ 0x00001800 249#define RL_RXCFG_FIFOTHRESH 0x0000E000 250#define RL_RXCFG_EARLYTHRESH 0x07000000 251 252#define RL_RXDMA_16BYTES 0x00000000 253#define RL_RXDMA_32BYTES 0x00000100 254#define RL_RXDMA_64BYTES 0x00000200 255#define RL_RXDMA_128BYTES 0x00000300 256#define RL_RXDMA_256BYTES 0x00000400 257#define RL_RXDMA_512BYTES 0x00000500 258#define RL_RXDMA_1024BYTES 0x00000600 259#define RL_RXDMA_UNLIMITED 0x00000700 260 261#define RL_RXBUF_8 0x00000000 262#define RL_RXBUF_16 0x00000800 263#define RL_RXBUF_32 0x00001000 264#define RL_RXBUF_64 0x00001800 265 266#define RL_RXFIFO_16BYTES 0x00000000 267#define RL_RXFIFO_32BYTES 0x00002000 268#define RL_RXFIFO_64BYTES 0x00004000 269#define RL_RXFIFO_128BYTES 0x00006000 270#define RL_RXFIFO_256BYTES 0x00008000 271#define RL_RXFIFO_512BYTES 0x0000A000 272#define RL_RXFIFO_1024BYTES 0x0000C000 273#define RL_RXFIFO_NOTHRESH 0x0000E000 274 275/* 276 * Bits in RX status header (included with RX'ed packet 277 * in ring buffer). 278 */ 279#define RL_RXSTAT_RXOK 0x00000001 280#define RL_RXSTAT_ALIGNERR 0x00000002 281#define RL_RXSTAT_CRCERR 0x00000004 282#define RL_RXSTAT_GIANT 0x00000008 283#define RL_RXSTAT_RUNT 0x00000010 284#define RL_RXSTAT_BADSYM 0x00000020 285#define RL_RXSTAT_BROAD 0x00002000 286#define RL_RXSTAT_INDIV 0x00004000 287#define RL_RXSTAT_MULTI 0x00008000 288#define RL_RXSTAT_LENMASK 0xFFFF0000 289 290#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 291/* 292 * Command register. 293 */ 294#define RL_CMD_EMPTY_RXBUF 0x0001 295#define RL_CMD_TX_ENB 0x0004 296#define RL_CMD_RX_ENB 0x0008 297#define RL_CMD_RESET 0x0010 298 299/* 300 * EEPROM control register 301 */ 302#define RL_EE_DATAOUT 0x01 /* Data out */ 303#define RL_EE_DATAIN 0x02 /* Data in */ 304#define RL_EE_CLK 0x04 /* clock */ 305#define RL_EE_SEL 0x08 /* chip select */ 306#define RL_EE_MODE (0x40|0x80) 307 308#define RL_EEMODE_OFF 0x00 309#define RL_EEMODE_AUTOLOAD 0x40 310#define RL_EEMODE_PROGRAM 0x80 311#define RL_EEMODE_WRITECFG (0x80|0x40) 312 313/* 9346 EEPROM commands */ 314 315#define RL_9346_WRITE 0x5 316#define RL_9346_READ 0x6 317#define RL_9346_ERASE 0x7 318#define RL_9346_EWEN 0x4 319#define RL_9346_EWEN_ADDR 0x30 320#define RL_9456_EWDS 0x4 321#define RL_9346_EWDS_ADDR 0x00 322 323#define RL_EECMD_WRITE 0x140 324#define RL_EECMD_READ_6BIT 0x180 325#define RL_EECMD_READ_8BIT 0x600 326#define RL_EECMD_ERASE 0x1c0 327 328#define RL_EE_ID 0x00 329#define RL_EE_PCI_VID 0x01 330#define RL_EE_PCI_DID 0x02 331/* Location of station address inside EEPROM */ 332#define RL_EE_EADDR 0x07 333 334/* 335 * MII register (8129 only) 336 */ 337#define RL_MII_CLK 0x01 338#define RL_MII_DATAIN 0x02 339#define RL_MII_DATAOUT 0x04 340#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 341 342/* 343 * Config 0 register 344 */ 345#define RL_CFG0_ROM0 0x01 346#define RL_CFG0_ROM1 0x02 347#define RL_CFG0_ROM2 0x04 348#define RL_CFG0_PL0 0x08 349#define RL_CFG0_PL1 0x10 350#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 351#define RL_CFG0_PCS 0x40 352#define RL_CFG0_SCR 0x80 353 354/* 355 * Config 1 register 356 */ 357#define RL_CFG1_PWRDWN 0x01 358#define RL_CFG1_SLEEP 0x02 359#define RL_CFG1_IOMAP 0x04 360#define RL_CFG1_MEMMAP 0x08 361#define RL_CFG1_RSVD 0x10 362#define RL_CFG1_DRVLOAD 0x20 363#define RL_CFG1_LED0 0x40 364#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 365#define RL_CFG1_LED1 0x80 366 367/* 368 * 8139C+ register definitions 369 */ 370 371/* RL_DUMPSTATS_LO register */ 372 373#define RL_DUMPSTATS_START 0x00000008 374 375/* Transmit start register */ 376 377#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 378#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 379#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 380 381/* 382 * Config 2 register, 8139C+/8169/8169S/8110S only 383 */ 384#define RL_CFG2_BUSFREQ 0x07 385#define RL_CFG2_BUSWIDTH 0x08 386#define RL_CFG2_AUXPWRSTS 0x10 387 388#define RL_BUSFREQ_33MHZ 0x00 389#define RL_BUSFREQ_66MHZ 0x01 390 391#define RL_BUSWIDTH_32BITS 0x00 392#define RL_BUSWIDTH_64BITS 0x08 393 394/* C+ mode command register */ 395 396#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 397#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 398#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 399#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 400#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 401#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 402 403/* C+ early transmit threshold */ 404 405#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 406 407/* 408 * Gigabit PHY access register (8169 only) 409 */ 410 411#define RL_PHYAR_PHYDATA 0x0000FFFF 412#define RL_PHYAR_PHYREG 0x001F0000 413#define RL_PHYAR_BUSY 0x80000000 414 415/* 416 * Gigabit media status (8169 only) 417 */ 418#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 419#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 420#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 421#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 422#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 423#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 424#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 425#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 426 427/* 428 * The RealTek doesn't use a fragment-based descriptor mechanism. 429 * Instead, there are only four register sets, each or which represents 430 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 431 * packet buffer (32-bit aligned!) and we place the buffer addresses in 432 * the registers so the chip knows where they are. 433 * 434 * We can sort of kludge together the same kind of buffer management 435 * used in previous drivers, but we have to do buffer copies almost all 436 * the time, so it doesn't really buy us much. 437 * 438 * For reception, there's just one large buffer where the chip stores 439 * all received packets. 440 */ 441 442#define RL_RX_BUF_SZ RL_RXBUF_64 443#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 444#define RL_TX_LIST_CNT 4 445#define RL_MIN_FRAMELEN 60 446#define RL_TXTHRESH(x) ((x) << 11) 447#define RL_TX_THRESH_INIT 96 448#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 449#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 450#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 451 452#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 453#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 454 455#define RL_ETHER_ALIGN 2 456 457struct rl_chain_data { 458 uint16_t cur_rx; 459 uint8_t *rl_rx_buf; 460 uint8_t *rl_rx_buf_ptr; 461 bus_dmamap_t rl_rx_dmamap; 462 463 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 464 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 465 uint8_t last_tx; 466 uint8_t cur_tx; 467}; 468 469#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 470#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 471#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 472#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 473#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 474#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 475#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 476#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 477#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 478 479struct rl_type { 480 uint16_t rl_vid; 481 uint16_t rl_did; 482 int rl_basetype; 483 char *rl_name; 484}; 485 486struct rl_hwrev { 487 uint32_t rl_rev; 488 int rl_type; 489 char *rl_desc; 490}; 491 492struct rl_mii_frame { 493 uint8_t mii_stdelim; 494 uint8_t mii_opcode; 495 uint8_t mii_phyaddr; 496 uint8_t mii_regaddr; 497 uint8_t mii_turnaround; 498 uint16_t mii_data; 499}; 500 501/* 502 * MII constants 503 */ 504#define RL_MII_STARTDELIM 0x01 505#define RL_MII_READOP 0x02 506#define RL_MII_WRITEOP 0x01 507#define RL_MII_TURNAROUND 0x02 508 509#define RL_8129 1 510#define RL_8139 2 511#define RL_8139CPLUS 3 512#define RL_8169 4 513 514#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 515 (x)->rl_type == RL_8169) 516 517/* 518 * The 8139C+ and 8160 gigE chips support descriptor-based TX 519 * and RX. In fact, they even support TCP large send. Descriptors 520 * must be allocated in contiguous blocks that are aligned on a 521 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 522 */ 523 524/* 525 * RX/TX descriptor definition. When large send mode is enabled, the 526 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 527 * the checksum offload bits are disabled. The structure layout is 528 * the same for RX and TX descriptors 529 */ 530 531struct rl_desc { 532 uint32_t rl_cmdstat; 533 uint32_t rl_vlanctl; 534 uint32_t rl_bufaddr_lo; 535 uint32_t rl_bufaddr_hi; 536}; 537 538#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 539#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 540#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 541#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 542#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 543#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 544#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 545#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 546#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 547#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 548 549#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 550#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 551 552/* 553 * Error bits are valid only on the last descriptor of a frame 554 * (i.e. RL_TDESC_CMD_EOF == 1) 555 */ 556 557#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 558#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 559#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 560#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 561#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 562#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 563#define RL_TDESC_STAT_OWN 0x80000000 564 565/* 566 * RX descriptor cmd/vlan definitions 567 */ 568 569#define RL_RDESC_CMD_EOR 0x40000000 570#define RL_RDESC_CMD_OWN 0x80000000 571#define RL_RDESC_CMD_BUFLEN 0x00001FFF 572 573#define RL_RDESC_STAT_OWN 0x80000000 574#define RL_RDESC_STAT_EOR 0x40000000 575#define RL_RDESC_STAT_SOF 0x20000000 576#define RL_RDESC_STAT_EOF 0x10000000 577#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 578#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 579#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 580#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 581#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 582#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 583#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 584#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 585#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 586#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 587#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 588#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 589#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 590#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 591#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 592#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 593#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 594 RL_RDESC_STAT_CRCERR) 595 596#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 597 (rl_vlandata valid)*/ 598#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 599 600#define RL_PROTOID_NONIP 0x00000000 601#define RL_PROTOID_TCPIP 0x00010000 602#define RL_PROTOID_UDPIP 0x00020000 603#define RL_PROTOID_IP 0x00030000 604#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 605 RL_PROTOID_TCPIP) 606#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 607 RL_PROTOID_UDPIP) 608 609/* 610 * Statistics counter structure (8139C+ and 8169 only) 611 */ 612struct rl_stats { 613 uint32_t rl_tx_pkts_lo; 614 uint32_t rl_tx_pkts_hi; 615 uint32_t rl_tx_errs_lo; 616 uint32_t rl_tx_errs_hi; 617 uint32_t rl_tx_errs; 618 uint16_t rl_missed_pkts; 619 uint16_t rl_rx_framealign_errs; 620 uint32_t rl_tx_onecoll; 621 uint32_t rl_tx_multicolls; 622 uint32_t rl_rx_ucasts_hi; 623 uint32_t rl_rx_ucasts_lo; 624 uint32_t rl_rx_bcasts_lo; 625 uint32_t rl_rx_bcasts_hi; 626 uint32_t rl_rx_mcasts; 627 uint16_t rl_tx_aborts; 628 uint16_t rl_rx_underruns; 629}; 630 631/* 632 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 633 * 634 * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 635 * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 636 * due to the 8139C+. We need to put the number of descriptors in the ring 637 * structure and use that value instead. 638 */ 639#if !defined(__i386__) && !defined(__amd64__) 640#define RE_FIXUP_RX 1 641#endif 642 643#define RL_TX_DESC_CNT 64 644#define RL_RX_DESC_CNT RL_TX_DESC_CNT 645 646#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 647#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 648#define RL_RING_ALIGN 256 649#define RL_IFQ_MAXLEN 512 650#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 651#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 652#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 653#define RL_PKTSZ(x) ((x)/* >> 3*/) 654#ifdef RE_FIXUP_RX 655#define RE_ETHER_ALIGN sizeof(uint64_t) 656#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 657#else 658#define RE_ETHER_ALIGN 0 659#define RE_RX_DESC_BUFLEN MCLBYTES 660#endif 661 662#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 663#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 664 665/* see comment in dev/re/if_re.c */ 666#define RL_JUMBO_FRAMELEN 7440 667#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 668 669struct rl_softc; 670 671struct rl_dmaload_arg { 672 struct rl_softc *sc; 673 int rl_idx; 674 int rl_maxsegs; 675 uint32_t rl_flags; 676 struct rl_desc *rl_ring; 677}; 678 679struct rl_list_data { 680 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 681 struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 682 int rl_tx_prodidx; 683 int rl_rx_prodidx; 684 int rl_tx_considx; 685 int rl_tx_free; 686 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 687 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 688 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 689 bus_dma_tag_t rl_stag; /* stats mapping tag */ 690 bus_dmamap_t rl_smap; /* stats map */ 691 struct rl_stats *rl_stats; 692 bus_addr_t rl_stats_addr; 693 bus_dma_tag_t rl_rx_list_tag; 694 bus_dmamap_t rl_rx_list_map; 695 struct rl_desc *rl_rx_list; 696 bus_addr_t rl_rx_list_addr; 697 bus_dma_tag_t rl_tx_list_tag; 698 bus_dmamap_t rl_tx_list_map; 699 struct rl_desc *rl_tx_list; 700 bus_addr_t rl_tx_list_addr; 701}; 702 703struct rl_softc { 704 struct ifnet *rl_ifp; /* interface info */ 705 bus_space_handle_t rl_bhandle; /* bus space handle */ 706 bus_space_tag_t rl_btag; /* bus space tag */ 707 device_t rl_dev; 708 struct resource *rl_res; 709 struct resource *rl_irq; 710 void *rl_intrhand; 711 device_t rl_miibus; 712 bus_dma_tag_t rl_parent_tag; 713 bus_dma_tag_t rl_tag; 714 uint8_t rl_type; 715 int rl_eecmd_read; 716 int rl_eewidth; 717 uint8_t rl_stats_no_timeout; 718 int rl_txthresh; 719 struct rl_chain_data rl_cdata; 720 struct rl_list_data rl_ldata; 721 struct callout rl_stat_callout; 722 struct mtx rl_mtx; 723 struct mbuf *rl_head; 724 struct mbuf *rl_tail; 725 uint32_t rl_hwrev; 726 uint32_t rl_rxlenmask; 727 int rl_testmode; 728 int suspended; /* 0 = normal 1 = suspended */ 729#ifdef DEVICE_POLLING 730 int rxcycles; 731#endif 732 733 struct task rl_txtask; 734 struct task rl_inttask; 735 736 struct mtx rl_intlock; 737 int rl_txstart; 738 int rl_link; 739}; 740 741#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 742#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 743#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 744 745/* 746 * register space access macros 747 */ 748#define CSR_WRITE_STREAM_4(sc, reg, val) \ 749 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 750#define CSR_WRITE_4(sc, reg, val) \ 751 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 752#define CSR_WRITE_2(sc, reg, val) \ 753 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 754#define CSR_WRITE_1(sc, reg, val) \ 755 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 756 757#define CSR_READ_4(sc, reg) \ 758 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 759#define CSR_READ_2(sc, reg) \ 760 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 761#define CSR_READ_1(sc, reg) \ 762 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 763 764#define CSR_SETBIT_1(sc, offset, val) \ 765 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 766 767#define CSR_CLRBIT_1(sc, offset, val) \ 768 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 769 770#define CSR_SETBIT_2(sc, offset, val) \ 771 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 772 773#define CSR_CLRBIT_2(sc, offset, val) \ 774 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 775 776#define CSR_SETBIT_4(sc, offset, val) \ 777 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 778 779#define CSR_CLRBIT_4(sc, offset, val) \ 780 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 781 782#define RL_TIMEOUT 1000 783 784/* 785 * General constants that are fun to know. 786 * 787 * RealTek PCI vendor ID 788 */ 789#define RT_VENDORID 0x10EC 790 791/* 792 * RealTek chip device IDs. 793 */ 794#define RT_DEVICEID_8129 0x8129 795#define RT_DEVICEID_8101E 0x8136 796#define RT_DEVICEID_8138 0x8138 797#define RT_DEVICEID_8139 0x8139 798#define RT_DEVICEID_8169SC 0x8167 799#define RT_DEVICEID_8168 0x8168 800#define RT_DEVICEID_8169 0x8169 801#define RT_DEVICEID_8100 0x8100 802 803#define RT_REVID_8139CPLUS 0x20 804 805/* 806 * Accton PCI vendor ID 807 */ 808#define ACCTON_VENDORID 0x1113 809 810/* 811 * Accton MPX 5030/5038 device ID. 812 */ 813#define ACCTON_DEVICEID_5030 0x1211 814 815/* 816 * Nortel PCI vendor ID 817 */ 818#define NORTEL_VENDORID 0x126C 819 820/* 821 * Delta Electronics Vendor ID. 822 */ 823#define DELTA_VENDORID 0x1500 824 825/* 826 * Delta device IDs. 827 */ 828#define DELTA_DEVICEID_8139 0x1360 829 830/* 831 * Addtron vendor ID. 832 */ 833#define ADDTRON_VENDORID 0x4033 834 835/* 836 * Addtron device IDs. 837 */ 838#define ADDTRON_DEVICEID_8139 0x1360 839 840/* 841 * D-Link vendor ID. 842 */ 843#define DLINK_VENDORID 0x1186 844 845/* 846 * D-Link DFE-530TX+ device ID 847 */ 848#define DLINK_DEVICEID_530TXPLUS 0x1300 849 850/* 851 * D-Link DFE-5280T device ID 852 */ 853#define DLINK_DEVICEID_528T 0x4300 854 855/* 856 * D-Link DFE-690TXD device ID 857 */ 858#define DLINK_DEVICEID_690TXD 0x1340 859 860/* 861 * Corega K.K vendor ID 862 */ 863#define COREGA_VENDORID 0x1259 864 865/* 866 * Corega FEther CB-TXD device ID 867 */ 868#define COREGA_DEVICEID_FETHERCBTXD 0xa117 869 870/* 871 * Corega FEtherII CB-TXD device ID 872 */ 873#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 874 875/* 876 * Corega CG-LAPCIGT device ID 877 */ 878#define COREGA_DEVICEID_CGLAPCIGT 0xc107 879 880/* 881 * Linksys vendor ID 882 */ 883#define LINKSYS_VENDORID 0x1737 884 885/* 886 * Linksys EG1032 device ID 887 */ 888#define LINKSYS_DEVICEID_EG1032 0x1032 889 890/* 891 * Linksys EG1032 rev 3 sub-device ID 892 */ 893#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 894 895/* 896 * Peppercon vendor ID 897 */ 898#define PEPPERCON_VENDORID 0x1743 899 900/* 901 * Peppercon ROL-F device ID 902 */ 903#define PEPPERCON_DEVICEID_ROLF 0x8139 904 905/* 906 * Planex Communications, Inc. vendor ID 907 */ 908#define PLANEX_VENDORID 0x14ea 909 910/* 911 * Planex FNW-3800-TX device ID 912 */ 913#define PLANEX_DEVICEID_FNW3800TX 0xab07 914 915/* 916 * LevelOne vendor ID 917 */ 918#define LEVEL1_VENDORID 0x018A 919 920/* 921 * LevelOne FPC-0106TX devide ID 922 */ 923#define LEVEL1_DEVICEID_FPC0106TX 0x0106 924 925/* 926 * Compaq vendor ID 927 */ 928#define CP_VENDORID 0x021B 929 930/* 931 * Edimax vendor ID 932 */ 933#define EDIMAX_VENDORID 0x13D1 934 935/* 936 * Edimax EP-4103DL cardbus device ID 937 */ 938#define EDIMAX_DEVICEID_EP4103DL 0xAB06 939 940/* 941 * PCI low memory base and low I/O base register, and 942 * other PCI registers. 943 */ 944 945#define RL_PCI_VENDOR_ID 0x00 946#define RL_PCI_DEVICE_ID 0x02 947#define RL_PCI_COMMAND 0x04 948#define RL_PCI_STATUS 0x06 949#define RL_PCI_CLASSCODE 0x09 950#define RL_PCI_LATENCY_TIMER 0x0D 951#define RL_PCI_HEADER_TYPE 0x0E 952#define RL_PCI_LOIO 0x10 953#define RL_PCI_LOMEM 0x14 954#define RL_PCI_BIOSROM 0x30 955#define RL_PCI_INTLINE 0x3C 956#define RL_PCI_INTPIN 0x3D 957#define RL_PCI_MINGNT 0x3E 958#define RL_PCI_MINLAT 0x0F 959#define RL_PCI_RESETOPT 0x48 960#define RL_PCI_EEPROM_DATA 0x4C 961 962#define RL_PCI_CAPID 0x50 /* 8 bits */ 963#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 964#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 965#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 966 967#define RL_PSTATE_MASK 0x0003 968#define RL_PSTATE_D0 0x0000 969#define RL_PSTATE_D1 0x0002 970#define RL_PSTATE_D2 0x0002 971#define RL_PSTATE_D3 0x0003 972#define RL_PME_EN 0x0010 973#define RL_PME_STATUS 0x8000 974