1/* 2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#ifndef _MLX4_EN_H_ 35#define _MLX4_EN_H_ 36 37#include <linux/bitops.h> 38#include <linux/compiler.h> 39#include <linux/list.h> 40#include <linux/mutex.h> 41#include <linux/kobject.h> 42#include <linux/netdevice.h> 43#include <linux/if_vlan.h> 44#include <linux/if_ether.h> 45#ifdef CONFIG_MLX4_EN_DCB 46#include <linux/dcbnl.h> 47#endif 48 49#include <linux/mlx4/device.h> 50#include <linux/mlx4/qp.h> 51#include <linux/mlx4/cq.h> 52#include <linux/mlx4/srq.h> 53#include <linux/mlx4/doorbell.h> 54#include <linux/mlx4/cmd.h> 55 56#include <netinet/tcp_lro.h> 57 58#include "en_port.h" 59#include "mlx4_stats.h" 60 61#define DRV_NAME "mlx4_en" 62#define DRV_VERSION "2.1" 63#define DRV_RELDATE __DATE__ 64 65#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 66 67/* 68 * Device constants 69 */ 70 71 72#define MLX4_EN_PAGE_SHIFT 12 73#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 74#define DEF_RX_RINGS 16 75#define MAX_RX_RINGS 128 76#define MIN_RX_RINGS 4 77#define TXBB_SIZE 64 78#define HEADROOM (2048 / TXBB_SIZE + 1) 79#define STAMP_STRIDE 64 80#define STAMP_DWORDS (STAMP_STRIDE / 4) 81#define STAMP_SHIFT 31 82#define STAMP_VAL 0x7fffffff 83#define STATS_DELAY (HZ / 4) 84#define SERVICE_TASK_DELAY (HZ / 4) 85#define MAX_NUM_OF_FS_RULES 256 86 87#define MLX4_EN_FILTER_HASH_SHIFT 4 88#define MLX4_EN_FILTER_EXPIRY_QUOTA 60 89 90#ifdef CONFIG_NET_RX_BUSY_POLL 91#define LL_EXTENDED_STATS 92#endif 93 94/* vlan valid range */ 95#define VLAN_MIN_VALUE 1 96#define VLAN_MAX_VALUE 4094 97 98/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 99#define MAX_DESC_SIZE 512 100#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 101 102/* 103 * OS related constants and tunables 104 */ 105 106#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 107 108#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE) 109#define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 110 111enum mlx4_en_alloc_type { 112 MLX4_EN_ALLOC_NEW = 0, 113 MLX4_EN_ALLOC_REPLACEMENT = 1, 114}; 115 116/* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 117 * and 4K allocations) */ 118#if MJUMPAGESIZE == 4096 119enum { 120 FRAG_SZ0 = MCLBYTES, 121 FRAG_SZ1 = MJUMPAGESIZE, 122 FRAG_SZ2 = MJUMPAGESIZE, 123}; 124#define MLX4_EN_MAX_RX_FRAGS 3 125#elif MJUMPAGESIZE == 8192 126enum { 127 FRAG_SZ0 = MCLBYTES, 128 FRAG_SZ1 = MJUMPAGESIZE, 129}; 130#define MLX4_EN_MAX_RX_FRAGS 2 131#elif MJUMPAGESIZE == 8192 132#else 133#error "Unknown PAGE_SIZE" 134#endif 135 136/* Maximum ring sizes */ 137#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 138 139/* Minimum packet number till arming the CQ */ 140#define MLX4_EN_MIN_RX_ARM 2048 141#define MLX4_EN_MIN_TX_ARM 2048 142 143/* Maximum ring sizes */ 144#define MLX4_EN_MAX_TX_SIZE 8192 145#define MLX4_EN_MAX_RX_SIZE 8192 146 147/* Minimum ring sizes */ 148#define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE) 149#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 150 151#define MLX4_EN_SMALL_PKT_SIZE 64 152 153#define MLX4_EN_MAX_TX_RING_P_UP 32 154#define MLX4_EN_NUM_UP 1 155 156#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 157 MLX4_EN_NUM_UP) 158 159#define MLX4_EN_DEF_TX_RING_SIZE 1024 160#define MLX4_EN_DEF_RX_RING_SIZE 1024 161 162/* Target number of bytes to coalesce with interrupt moderation */ 163#define MLX4_EN_RX_COAL_TARGET 0x20000 164#define MLX4_EN_RX_COAL_TIME 0x10 165 166#define MLX4_EN_TX_COAL_PKTS 64 167#define MLX4_EN_TX_COAL_TIME 64 168 169#define MLX4_EN_RX_RATE_LOW 400000 170#define MLX4_EN_RX_COAL_TIME_LOW 0 171#define MLX4_EN_RX_RATE_HIGH 450000 172#define MLX4_EN_RX_COAL_TIME_HIGH 128 173#define MLX4_EN_RX_SIZE_THRESH 1024 174#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 175#define MLX4_EN_SAMPLE_INTERVAL 0 176#define MLX4_EN_AVG_PKT_SMALL 256 177 178#define MLX4_EN_AUTO_CONF 0xffff 179 180#define MLX4_EN_DEF_RX_PAUSE 1 181#define MLX4_EN_DEF_TX_PAUSE 1 182 183/* Interval between successive polls in the Tx routine when polling is used 184 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 185#define MLX4_EN_TX_POLL_MODER 16 186#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 187 188#define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD) 189#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 190#define HEADER_COPY_SIZE (128) 191#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 192 193#define MLX4_EN_MIN_MTU 46 194#define ETH_BCAST 0xffffffffffffULL 195 196#define MLX4_EN_LOOPBACK_RETRIES 5 197#define MLX4_EN_LOOPBACK_TIMEOUT 100 198 199#ifdef MLX4_EN_PERF_STAT 200/* Number of samples to 'average' */ 201#define AVG_SIZE 128 202#define AVG_FACTOR 1024 203 204#define INC_PERF_COUNTER(cnt) (++(cnt)) 205#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 206#define AVG_PERF_COUNTER(cnt, sample) \ 207 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 208#define GET_PERF_COUNTER(cnt) (cnt) 209#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 210 211#else 212 213#define INC_PERF_COUNTER(cnt) do {} while (0) 214#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 215#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 216#define GET_PERF_COUNTER(cnt) (0) 217#define GET_AVG_PERF_COUNTER(cnt) (0) 218#endif /* MLX4_EN_PERF_STAT */ 219 220/* 221 * Configurables 222 */ 223 224enum cq_type { 225 RX = 0, 226 TX = 1, 227}; 228 229 230/* 231 * Useful macros 232 */ 233#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 234#define XNOR(x, y) (!(x) == !(y)) 235#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 236 237struct mlx4_en_tx_info { 238 struct mbuf *mb; 239 u32 nr_txbb; 240 u32 nr_bytes; 241 u8 linear; 242 u8 nr_segs; 243 u8 data_offset; 244 u8 inl; 245#if 0 246 u8 ts_requested; 247#endif 248}; 249 250 251#define MLX4_EN_BIT_DESC_OWN 0x80000000 252#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 253#define MLX4_EN_MEMTYPE_PAD 0x100 254#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 255 256 257struct mlx4_en_tx_desc { 258 struct mlx4_wqe_ctrl_seg ctrl; 259 union { 260 struct mlx4_wqe_data_seg data; /* at least one data segment */ 261 struct mlx4_wqe_lso_seg lso; 262 struct mlx4_wqe_inline_seg inl; 263 }; 264}; 265 266#define MLX4_EN_USE_SRQ 0x01000000 267 268#define MLX4_EN_TX_BUDGET 64*4 //Compensate for no NAPI in freeBSD - might need some fine tunning in the future. 269#define MLX4_EN_RX_BUDGET 64 270 271#define MLX4_EN_CX3_LOW_ID 0x1000 272#define MLX4_EN_CX3_HIGH_ID 0x1005 273 274struct mlx4_en_tx_ring { 275 spinlock_t tx_lock; 276 struct mlx4_hwq_resources wqres; 277 u32 size ; /* number of TXBBs */ 278 u32 size_mask; 279 u16 stride; 280 u16 cqn; /* index of port CQ associated with this ring */ 281 u32 prod; 282 u32 cons; 283 u32 buf_size; 284 u32 doorbell_qpn; 285 void *buf; 286 u16 poll_cnt; 287 int blocked; 288 struct mlx4_en_tx_info *tx_info; 289 u8 *bounce_buf; 290 u8 queue_index; 291 cpuset_t affinity_mask; 292 struct buf_ring *br; 293 u32 last_nr_txbb; 294 struct mlx4_qp qp; 295 struct mlx4_qp_context context; 296 int qpn; 297 enum mlx4_qp_state qp_state; 298 struct mlx4_srq dummy; 299 unsigned long bytes; 300 unsigned long packets; 301 unsigned long tx_csum; 302 unsigned long queue_stopped; 303 unsigned long wake_queue; 304 struct mlx4_bf bf; 305 bool bf_enabled; 306 struct netdev_queue *tx_queue; 307 int hwtstamp_tx_type; 308 spinlock_t comp_lock; 309 int full_size; 310 int inline_thold; 311 u64 watchdog_time; 312}; 313 314struct mlx4_en_rx_desc { 315 /* actual number of entries depends on rx ring stride */ 316 struct mlx4_wqe_data_seg data[0]; 317}; 318 319struct mlx4_en_rx_buf { 320 dma_addr_t dma; 321 struct page *page; 322 unsigned int page_offset; 323}; 324 325struct mlx4_en_rx_ring { 326 struct mlx4_hwq_resources wqres; 327 u32 size ; /* number of Rx descs*/ 328 u32 actual_size; 329 u32 size_mask; 330 u16 stride; 331 u16 log_stride; 332 u16 cqn; /* index of port CQ associated with this ring */ 333 u32 prod; 334 u32 cons; 335 u32 buf_size; 336 u8 fcs_del; 337 u16 rx_alloc_order; 338 u32 rx_alloc_size; 339 u32 rx_buf_size; 340 u32 rx_mb_size; 341 int qpn; 342 void *buf; 343 void *rx_info; 344 unsigned long errors; 345 unsigned long bytes; 346 unsigned long packets; 347#ifdef LL_EXTENDED_STATS 348 unsigned long yields; 349 unsigned long misses; 350 unsigned long cleaned; 351#endif 352 unsigned long csum_ok; 353 unsigned long csum_none; 354 int hwtstamp_rx_filter; 355 int numa_node; 356 struct lro_ctrl lro; 357}; 358 359static inline int mlx4_en_can_lro(__be16 status) 360{ 361 const __be16 status_all = cpu_to_be16( 362 MLX4_CQE_STATUS_IPV4 | 363 MLX4_CQE_STATUS_IPV4F | 364 MLX4_CQE_STATUS_IPV6 | 365 MLX4_CQE_STATUS_IPV4OPT | 366 MLX4_CQE_STATUS_TCP | 367 MLX4_CQE_STATUS_UDP | 368 MLX4_CQE_STATUS_IPOK); 369 const __be16 status_ipv4_ipok_tcp = cpu_to_be16( 370 MLX4_CQE_STATUS_IPV4 | 371 MLX4_CQE_STATUS_IPOK | 372 MLX4_CQE_STATUS_TCP); 373 const __be16 status_ipv6_ipok_tcp = cpu_to_be16( 374 MLX4_CQE_STATUS_IPV6 | 375 MLX4_CQE_STATUS_IPOK | 376 MLX4_CQE_STATUS_TCP); 377 378 status &= status_all; 379 return (status == status_ipv4_ipok_tcp || 380 status == status_ipv6_ipok_tcp); 381} 382 383struct mlx4_en_cq { 384 struct mlx4_cq mcq; 385 struct mlx4_hwq_resources wqres; 386 int ring; 387 spinlock_t lock; 388 struct net_device *dev; 389 /* Per-core Tx cq processing support */ 390 struct timer_list timer; 391 int size; 392 int buf_size; 393 unsigned vector; 394 enum cq_type is_tx; 395 u16 moder_time; 396 u16 moder_cnt; 397 struct mlx4_cqe *buf; 398 struct task cq_task; 399 struct taskqueue *tq; 400#define MLX4_EN_OPCODE_ERROR 0x1e 401 u32 tot_rx; 402 u32 tot_tx; 403 404#ifdef CONFIG_NET_RX_BUSY_POLL 405 unsigned int state; 406#define MLX4_EN_CQ_STATEIDLE 0 407#define MLX4_EN_CQ_STATENAPI 1 /* NAPI owns this CQ */ 408#define MLX4_EN_CQ_STATEPOLL 2 /* poll owns this CQ */ 409#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATENAPI | MLX4_EN_CQ_STATEPOLL) 410#define MLX4_EN_CQ_STATENAPI_YIELD 4 /* NAPI yielded this CQ */ 411#define MLX4_EN_CQ_STATEPOLL_YIELD 8 /* poll yielded this CQ */ 412#define CQ_YIELD (MLX4_EN_CQ_STATENAPI_YIELD | MLX4_EN_CQ_STATEPOLL_YIELD) 413#define CQ_USER_PEND (MLX4_EN_CQ_STATEPOLL | MLX4_EN_CQ_STATEPOLL_YIELD) 414 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 415#endif /* CONFIG_NET_RX_BUSY_POLL */ 416}; 417 418struct mlx4_en_port_profile { 419 u32 flags; 420 u32 tx_ring_num; 421 u32 rx_ring_num; 422 u32 tx_ring_size; 423 u32 rx_ring_size; 424 u8 rx_pause; 425 u8 rx_ppp; 426 u8 tx_pause; 427 u8 tx_ppp; 428 int rss_rings; 429}; 430 431struct mlx4_en_profile { 432 int rss_xor; 433 int udp_rss; 434 u8 rss_mask; 435 u32 active_ports; 436 u32 small_pkt_int; 437 u8 no_reset; 438 u8 num_tx_rings_p_up; 439 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 440}; 441 442struct mlx4_en_dev { 443 struct mlx4_dev *dev; 444 struct pci_dev *pdev; 445 struct mutex state_lock; 446 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 447 u32 port_cnt; 448 bool device_up; 449 struct mlx4_en_profile profile; 450 u32 LSO_support; 451 struct workqueue_struct *workqueue; 452 struct device *dma_device; 453 void __iomem *uar_map; 454 struct mlx4_uar priv_uar; 455 struct mlx4_mr mr; 456 u32 priv_pdn; 457 spinlock_t uar_lock; 458 u8 mac_removed[MLX4_MAX_PORTS + 1]; 459 unsigned long last_overflow_check; 460 unsigned long overflow_period; 461}; 462 463 464struct mlx4_en_rss_map { 465 int base_qpn; 466 struct mlx4_qp qps[MAX_RX_RINGS]; 467 enum mlx4_qp_state state[MAX_RX_RINGS]; 468 struct mlx4_qp indir_qp; 469 enum mlx4_qp_state indir_state; 470}; 471 472struct mlx4_en_port_state { 473 int link_state; 474 int link_speed; 475 int transciver; 476 int autoneg; 477}; 478 479enum mlx4_en_mclist_act { 480 MCLIST_NONE, 481 MCLIST_REM, 482 MCLIST_ADD, 483}; 484 485struct mlx4_en_mc_list { 486 struct list_head list; 487 enum mlx4_en_mclist_act action; 488 u8 addr[ETH_ALEN]; 489 u64 reg_id; 490}; 491 492#ifdef CONFIG_MLX4_EN_DCB 493/* Minimal TC BW - setting to 0 will block traffic */ 494#define MLX4_EN_BW_MIN 1 495#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 496 497#define MLX4_EN_TC_ETS 7 498 499#endif 500 501 502enum { 503 MLX4_EN_FLAG_PROMISC = (1 << 0), 504 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 505 /* whether we need to enable hardware loopback by putting dmac 506 * in Tx WQE 507 */ 508 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 509 /* whether we need to drop packets that hardware loopback-ed */ 510 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 511 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 512#ifdef CONFIG_MLX4_EN_DCB 513 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5) 514#endif 515}; 516 517#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 518#define MLX4_EN_MAC_HASH_IDX 5 519 520struct en_port { 521 struct kobject kobj; 522 struct mlx4_dev *dev; 523 u8 port_num; 524 u8 vport_num; 525}; 526 527struct mlx4_en_frag_info { 528 u16 frag_size; 529 u16 frag_prefix_size; 530}; 531 532 533struct mlx4_en_priv { 534 struct mlx4_en_dev *mdev; 535 struct mlx4_en_port_profile *prof; 536 struct net_device *dev; 537 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 538 struct mlx4_en_port_state port_state; 539 spinlock_t stats_lock; 540 /* To allow rules removal while port is going down */ 541 struct list_head ethtool_list; 542 543 unsigned long last_moder_packets[MAX_RX_RINGS]; 544 unsigned long last_moder_tx_packets; 545 unsigned long last_moder_bytes[MAX_RX_RINGS]; 546 unsigned long last_moder_jiffies; 547 int last_moder_time[MAX_RX_RINGS]; 548 u16 rx_usecs; 549 u16 rx_frames; 550 u16 tx_usecs; 551 u16 tx_frames; 552 u32 pkt_rate_low; 553 u32 rx_usecs_low; 554 u32 pkt_rate_high; 555 u32 rx_usecs_high; 556 u32 sample_interval; 557 u32 adaptive_rx_coal; 558 u32 msg_enable; 559 u32 loopback_ok; 560 u32 validate_loopback; 561 562 struct mlx4_hwq_resources res; 563 int link_state; 564 int last_link_state; 565 bool port_up; 566 int port; 567 int registered; 568 int allocated; 569 int stride; 570 unsigned char current_mac[ETH_ALEN + 2]; 571 u64 mac; 572 int mac_index; 573 unsigned max_mtu; 574 int base_qpn; 575 int cqe_factor; 576 577 struct mlx4_en_rss_map rss_map; 578 __be32 ctrl_flags; 579 u32 flags; 580 u8 num_tx_rings_p_up; 581 u32 tx_ring_num; 582 u32 rx_ring_num; 583 u32 rx_mb_size; 584 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 585 u16 rx_alloc_order; 586 u32 rx_alloc_size; 587 u32 rx_buf_size; 588 u16 num_frags; 589 u16 log_rx_info; 590 591 struct mlx4_en_tx_ring **tx_ring; 592 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 593 struct mlx4_en_cq **tx_cq; 594 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 595 struct mlx4_qp drop_qp; 596 struct work_struct rx_mode_task; 597 struct work_struct watchdog_task; 598 struct work_struct linkstate_task; 599 struct delayed_work stats_task; 600 struct delayed_work service_task; 601 struct mlx4_en_perf_stats pstats; 602 struct mlx4_en_pkt_stats pkstats; 603 struct mlx4_en_flow_stats flowstats[MLX4_NUM_PRIORITIES]; 604 struct mlx4_en_port_stats port_stats; 605 struct mlx4_en_vport_stats vport_stats; 606 struct mlx4_en_vf_stats vf_stats; 607 DECLARE_BITMAP(stats_bitmap, NUM_ALL_STATS); 608 struct list_head mc_list; 609 struct list_head curr_list; 610 u64 broadcast_id; 611 struct mlx4_en_stat_out_mbox hw_stats; 612 int vids[128]; 613 bool wol; 614 struct device *ddev; 615 struct dentry *dev_root; 616 u32 counter_index; 617 eventhandler_tag vlan_attach; 618 eventhandler_tag vlan_detach; 619 struct callout watchdog_timer; 620 struct ifmedia media; 621 volatile int blocked; 622 struct sysctl_oid *sysctl; 623 struct sysctl_ctx_list conf_ctx; 624 struct sysctl_ctx_list stat_ctx; 625#define MLX4_EN_MAC_HASH_IDX 5 626 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 627 628#ifdef CONFIG_MLX4_EN_DCB 629 struct ieee_ets ets; 630 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 631 u8 dcbx_cap; 632#endif 633#ifdef CONFIG_RFS_ACCEL 634 spinlock_t filters_lock; 635 int last_filter_id; 636 struct list_head filters; 637 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 638#endif 639 struct en_port *vf_ports[MLX4_MAX_NUM_VF]; 640 unsigned long last_ifq_jiffies; 641 u64 if_counters_rx_errors; 642 u64 if_counters_rx_no_buffer; 643 644}; 645 646enum mlx4_en_wol { 647 MLX4_EN_WOL_MAGIC = (1ULL << 61), 648 MLX4_EN_WOL_ENABLED = (1ULL << 62), 649}; 650 651struct mlx4_mac_entry { 652 struct hlist_node hlist; 653 unsigned char mac[ETH_ALEN + 2]; 654 u64 reg_id; 655}; 656 657#ifdef CONFIG_NET_RX_BUSY_POLL 658static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 659{ 660 spin_lock_init(&cq->poll_lock); 661 cq->state = MLX4_EN_CQ_STATEIDLE; 662} 663 664/* called from the device poll rutine to get ownership of a cq */ 665static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 666{ 667 int rc = true; 668 spin_lock(&cq->poll_lock); 669 if (cq->state & MLX4_CQ_LOCKED) { 670 WARN_ON(cq->state & MLX4_EN_CQ_STATENAPI); 671 cq->state |= MLX4_EN_CQ_STATENAPI_YIELD; 672 rc = false; 673 } else 674 /* we don't care if someone yielded */ 675 cq->state = MLX4_EN_CQ_STATENAPI; 676 spin_unlock(&cq->poll_lock); 677 return rc; 678} 679 680/* returns true is someone tried to get the cq while napi had it */ 681static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 682{ 683 int rc = false; 684 spin_lock(&cq->poll_lock); 685 WARN_ON(cq->state & (MLX4_EN_CQ_STATEPOLL | 686 MLX4_EN_CQ_STATENAPI_YIELD)); 687 688 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 689 rc = true; 690 cq->state = MLX4_EN_CQ_STATEIDLE; 691 spin_unlock(&cq->poll_lock); 692 return rc; 693} 694 695/* called from mlx4_en_low_latency_poll() */ 696static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 697{ 698 int rc = true; 699 spin_lock_bh(&cq->poll_lock); 700 if ((cq->state & MLX4_CQ_LOCKED)) { 701 struct net_device *dev = cq->dev; 702 struct mlx4_en_priv *priv = netdev_priv(dev); 703 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 704 705 cq->state |= MLX4_EN_CQ_STATEPOLL_YIELD; 706 rc = false; 707#ifdef LL_EXTENDED_STATS 708 rx_ring->yields++; 709#endif 710 } else 711 /* preserve yield marks */ 712 cq->state |= MLX4_EN_CQ_STATEPOLL; 713 spin_unlock_bh(&cq->poll_lock); 714 return rc; 715} 716 717/* returns true if someone tried to get the cq while it was locked */ 718static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 719{ 720 int rc = false; 721 spin_lock_bh(&cq->poll_lock); 722 WARN_ON(cq->state & (MLX4_EN_CQ_STATENAPI)); 723 724 if (cq->state & MLX4_EN_CQ_STATEPOLL_YIELD) 725 rc = true; 726 cq->state = MLX4_EN_CQ_STATEIDLE; 727 spin_unlock_bh(&cq->poll_lock); 728 return rc; 729} 730 731/* true if a socket is polling, even if it did not get the lock */ 732static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 733{ 734 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 735 return cq->state & CQ_USER_PEND; 736} 737#else 738static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 739{ 740} 741 742static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 743{ 744 return true; 745} 746 747static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 748{ 749 return false; 750} 751 752static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 753{ 754 return false; 755} 756 757static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 758{ 759 return false; 760} 761 762static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 763{ 764 return false; 765} 766#endif /* CONFIG_NET_RX_BUSY_POLL */ 767 768#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 769 770void mlx4_en_destroy_netdev(struct net_device *dev); 771int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 772 struct mlx4_en_port_profile *prof); 773 774int mlx4_en_start_port(struct net_device *dev); 775void mlx4_en_stop_port(struct net_device *dev); 776 777void mlx4_en_free_resources(struct mlx4_en_priv *priv); 778int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 779 780int mlx4_en_pre_config(struct mlx4_en_priv *priv); 781int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 782 int entries, int ring, enum cq_type mode, int node); 783void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 784int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 785 int cq_idx); 786void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 787int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 788int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 789 790void mlx4_en_tx_irq(struct mlx4_cq *mcq); 791u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 792 793int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m); 794int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 795 struct mlx4_en_tx_ring **pring, 796 u32 size, u16 stride, int node, int queue_idx); 797void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 798 struct mlx4_en_tx_ring **pring); 799int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 800 struct mlx4_en_tx_ring *ring, 801 int cq, int user_prio); 802void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 803 struct mlx4_en_tx_ring *ring); 804void mlx4_en_qflush(struct ifnet *dev); 805 806int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 807 struct mlx4_en_rx_ring **pring, 808 u32 size, int node); 809void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 810 struct mlx4_en_rx_ring **pring, 811 u32 size, u16 stride); 812void mlx4_en_tx_que(void *context, int pending); 813void mlx4_en_rx_que(void *context, int pending); 814int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 815void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 816 struct mlx4_en_rx_ring *ring); 817int mlx4_en_process_rx_cq(struct net_device *dev, 818 struct mlx4_en_cq *cq, 819 int budget); 820void mlx4_en_poll_tx_cq(unsigned long data); 821void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 822 int is_tx, int rss, int qpn, int cqn, int user_prio, 823 struct mlx4_qp_context *context); 824void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 825int mlx4_en_map_buffer(struct mlx4_buf *buf); 826void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 827void mlx4_en_calc_rx_buf(struct net_device *dev); 828 829int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 830void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 831int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 832void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 833int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 834void mlx4_en_rx_irq(struct mlx4_cq *mcq); 835 836int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 837int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 838 839int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 840int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 841int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port); 842void mlx4_en_create_debug_files(struct mlx4_en_priv *priv); 843void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv); 844int mlx4_en_register_debugfs(void); 845void mlx4_en_unregister_debugfs(void); 846 847#ifdef CONFIG_MLX4_EN_DCB 848extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 849extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 850#endif 851 852int mlx4_en_setup_tc(struct net_device *dev, u8 up); 853 854#ifdef CONFIG_RFS_ACCEL 855void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, 856 struct mlx4_en_rx_ring *rx_ring); 857#endif 858 859#define MLX4_EN_NUM_SELF_TEST 5 860void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 861void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 862 863/* 864 * Functions for time stamping 865 */ 866#define SKBTX_HW_TSTAMP (1 << 0) 867#define SKBTX_IN_PROGRESS (1 << 2) 868 869u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 870 871/* Functions for caching and restoring statistics */ 872int mlx4_en_get_sset_count(struct net_device *dev, int sset); 873void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv, 874 u64 *data); 875 876/* 877 * Globals 878 */ 879extern const struct ethtool_ops mlx4_en_ethtool_ops; 880 881/* 882 * Defines for link speed - needed by selftest 883 */ 884#define MLX4_EN_LINK_SPEED_1G 1000 885#define MLX4_EN_LINK_SPEED_10G 10000 886#define MLX4_EN_LINK_SPEED_40G 40000 887 888enum { 889 NETIF_MSG_DRV = 0x0001, 890 NETIF_MSG_PROBE = 0x0002, 891 NETIF_MSG_LINK = 0x0004, 892 NETIF_MSG_TIMER = 0x0008, 893 NETIF_MSG_IFDOWN = 0x0010, 894 NETIF_MSG_IFUP = 0x0020, 895 NETIF_MSG_RX_ERR = 0x0040, 896 NETIF_MSG_TX_ERR = 0x0080, 897 NETIF_MSG_TX_QUEUED = 0x0100, 898 NETIF_MSG_INTR = 0x0200, 899 NETIF_MSG_TX_DONE = 0x0400, 900 NETIF_MSG_RX_STATUS = 0x0800, 901 NETIF_MSG_PKTDATA = 0x1000, 902 NETIF_MSG_HW = 0x2000, 903 NETIF_MSG_WOL = 0x4000, 904}; 905 906 907/* 908 * printk / logging functions 909 */ 910 911#define en_print(level, priv, format, arg...) \ 912 { \ 913 if ((priv)->registered) \ 914 printk(level "%s: %s: " format, DRV_NAME, \ 915 (priv->dev)->if_xname, ## arg); \ 916 else \ 917 printk(level "%s: %s: Port %d: " format, \ 918 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 919 (priv)->port, ## arg); \ 920 } 921 922 923#define en_dbg(mlevel, priv, format, arg...) \ 924do { \ 925 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 926 en_print(KERN_DEBUG, priv, format, ##arg); \ 927} while (0) 928#define en_warn(priv, format, arg...) \ 929 en_print(KERN_WARNING, priv, format, ##arg) 930#define en_err(priv, format, arg...) \ 931 en_print(KERN_ERR, priv, format, ##arg) 932#define en_info(priv, format, arg...) \ 933 en_print(KERN_INFO, priv, format, ## arg) 934 935#define mlx4_err(mdev, format, arg...) \ 936 pr_err("%s %s: " format, DRV_NAME, \ 937 dev_name(&mdev->pdev->dev), ##arg) 938#define mlx4_info(mdev, format, arg...) \ 939 pr_info("%s %s: " format, DRV_NAME, \ 940 dev_name(&mdev->pdev->dev), ##arg) 941#define mlx4_warn(mdev, format, arg...) \ 942 pr_warning("%s %s: " format, DRV_NAME, \ 943 dev_name(&mdev->pdev->dev), ##arg) 944 945#endif 946