1/*- 2 * Copyright (c) 2009 M. Warner Losh <imp@FreeBSD.org> 3 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $Id$ 28 */ 29#include "opt_uart.h" 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: releng/10.2/sys/mips/cavium/uart_cpu_octeonusart.c 242345 2012-10-30 06:29:17Z jmallett $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/cons.h> 38 39#include <machine/bus.h> 40 41#include <dev/uart/uart.h> 42#include <dev/uart/uart_cpu.h> 43 44#include <mips/cavium/octeon_pcmap_regs.h> 45 46#include <contrib/octeon-sdk/cvmx.h> 47 48bus_space_tag_t uart_bus_space_io; 49bus_space_tag_t uart_bus_space_mem; 50 51/* 52 * Specailized uart bus space. We present a 1 apart byte oriented 53 * bus to the outside world, but internally translate to/from the 8-apart 54 * 64-bit word bus that's on the octeon. We only support simple read/write 55 * in this space. Everything else is undefined. 56 */ 57static uint8_t 58ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset) 59{ 60 61 return (cvmx_read64_uint64(handle + offset)); 62} 63 64static uint16_t 65ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset) 66{ 67 68 return (cvmx_read64_uint64(handle + offset)); 69} 70 71static uint32_t 72ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset) 73{ 74 75 return (cvmx_read64_uint64(handle + offset)); 76} 77 78static uint64_t 79ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset) 80{ 81 82 return (cvmx_read64_uint64(handle + offset)); 83} 84 85static void 86ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value) 87{ 88 89 cvmx_write64_uint64(bsh + offset, value); 90} 91 92static void 93ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value) 94{ 95 96 cvmx_write64_uint64(bsh + offset, value); 97} 98 99static void 100ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value) 101{ 102 103 cvmx_write64_uint64(bsh + offset, value); 104} 105 106static void 107ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value) 108{ 109 110 cvmx_write64_uint64(bsh + offset, value); 111} 112 113struct bus_space octeon_uart_tag = { 114 .bs_map = generic_bs_map, 115 .bs_unmap = generic_bs_unmap, 116 .bs_subregion = generic_bs_subregion, 117 .bs_barrier = generic_bs_barrier, 118 .bs_r_1 = ou_bs_r_1, 119 .bs_r_2 = ou_bs_r_2, 120 .bs_r_4 = ou_bs_r_4, 121 .bs_r_8 = ou_bs_r_8, 122 .bs_w_1 = ou_bs_w_1, 123 .bs_w_2 = ou_bs_w_2, 124 .bs_w_4 = ou_bs_w_4, 125 .bs_w_8 = ou_bs_w_8, 126}; 127 128extern struct uart_class uart_oct16550_class; 129 130int 131uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) 132{ 133 134 return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); 135} 136 137int 138uart_cpu_getdev(int devtype, struct uart_devinfo *di) 139{ 140 struct uart_class *class = &uart_oct16550_class; 141 142 /* 143 * These fields need to be setup corretly for uart_getenv to 144 * work in all cases. 145 */ 146 uart_bus_space_io = NULL; /* No io map for this device */ 147 uart_bus_space_mem = &octeon_uart_tag; 148 di->bas.bst = uart_bus_space_mem; 149 150 /* 151 * If env specification for UART exists it takes precedence: 152 * hw.uart.console="mm:0xf1012000" or similar 153 */ 154 if (uart_getenv(devtype, di, class) == 0) 155 return (0); 156 157 /* 158 * Fallback to UART0 for console. 159 */ 160 di->ops = uart_getops(class); 161 di->bas.chan = 0; 162 /* XXX */ 163 if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0), 164 uart_getrange(class), 0, &di->bas.bsh) != 0) 165 return (ENXIO); 166 di->bas.regshft = 3; 167 di->bas.rclk = 0; 168 di->baudrate = 115200; 169 di->databits = 8; 170 di->stopbits = 1; 171 di->parity = UART_PARITY_NONE; 172 173 return (0); 174} 175