1279377Simp/* 2279377Simp * Copyright 2013 Maxime Ripard 3279377Simp * 4279377Simp * Maxime Ripard <maxime.ripard@free-electrons.com> 5279377Simp * 6279377Simp * This file is dual-licensed: you can use it either under the terms 7279377Simp * of the GPL or the X11 license, at your option. Note that this dual 8279377Simp * licensing only applies to this file, and not this project as a 9279377Simp * whole. 10279377Simp * 11279377Simp * a) This file is free software; you can redistribute it and/or 12279377Simp * modify it under the terms of the GNU General Public License as 13279377Simp * published by the Free Software Foundation; either version 2 of the 14279377Simp * License, or (at your option) any later version. 15279377Simp * 16279377Simp * This file is distributed in the hope that it will be useful, 17279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 18279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19279377Simp * GNU General Public License for more details. 20279377Simp * 21279377Simp * You should have received a copy of the GNU General Public 22279377Simp * License along with this file; if not, write to the Free 23279377Simp * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24279377Simp * MA 02110-1301 USA 25279377Simp * 26279377Simp * Or, alternatively, 27279377Simp * 28279377Simp * b) Permission is hereby granted, free of charge, to any person 29279377Simp * obtaining a copy of this software and associated documentation 30279377Simp * files (the "Software"), to deal in the Software without 31279377Simp * restriction, including without limitation the rights to use, 32279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 33279377Simp * sell copies of the Software, and to permit persons to whom the 34279377Simp * Software is furnished to do so, subject to the following 35279377Simp * conditions: 36279377Simp * 37279377Simp * The above copyright notice and this permission notice shall be 38279377Simp * included in all copies or substantial portions of the Software. 39279377Simp * 40279377Simp * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47279377Simp * OTHER DEALINGS IN THE SOFTWARE. 48279377Simp */ 49279377Simp 50279377Simp#include "skeleton.dtsi" 51279377Simp 52279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 53279377Simp#include <dt-bindings/thermal/thermal.h> 54279377Simp 55279377Simp#include <dt-bindings/dma/sun4i-a10.h> 56279377Simp#include <dt-bindings/pinctrl/sun4i-a10.h> 57279377Simp 58279377Simp/ { 59279377Simp interrupt-parent = <&gic>; 60279377Simp 61279377Simp aliases { 62279377Simp ethernet0 = &gmac; 63279377Simp }; 64279377Simp 65279377Simp chosen { 66279377Simp #address-cells = <1>; 67279377Simp #size-cells = <1>; 68279377Simp ranges; 69279377Simp 70279377Simp framebuffer@0 { 71279377Simp compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; 72279377Simp allwinner,pipeline = "de_be0-lcd0-hdmi"; 73279377Simp clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 74279377Simp <&ahb_gates 44>; 75279377Simp status = "disabled"; 76279377Simp }; 77279377Simp 78279377Simp framebuffer@1 { 79279377Simp compatible = "allwinner,simple-framebuffer", 80279377Simp "simple-framebuffer"; 81279377Simp allwinner,pipeline = "de_be0-lcd0"; 82279377Simp clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; 83279377Simp status = "disabled"; 84279377Simp }; 85279377Simp 86279377Simp framebuffer@2 { 87279377Simp compatible = "allwinner,simple-framebuffer", 88279377Simp "simple-framebuffer"; 89279377Simp allwinner,pipeline = "de_be0-lcd0-tve0"; 90279377Simp clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, 91279377Simp <&ahb_gates 44>; 92279377Simp status = "disabled"; 93279377Simp }; 94279377Simp }; 95279377Simp 96279377Simp cpus { 97279377Simp #address-cells = <1>; 98279377Simp #size-cells = <0>; 99279377Simp 100279377Simp cpu0: cpu@0 { 101279377Simp compatible = "arm,cortex-a7"; 102279377Simp device_type = "cpu"; 103279377Simp reg = <0>; 104279377Simp clocks = <&cpu>; 105279377Simp clock-latency = <244144>; /* 8 32k periods */ 106279377Simp operating-points = < 107279377Simp /* kHz uV */ 108279377Simp 1008000 1450000 109279377Simp 960000 1400000 110279377Simp 912000 1400000 111279377Simp 864000 1300000 112279377Simp 720000 1200000 113279377Simp 528000 1100000 114279377Simp 312000 1000000 115279377Simp 144000 900000 116279377Simp >; 117279377Simp #cooling-cells = <2>; 118279377Simp cooling-min-level = <0>; 119279377Simp cooling-max-level = <7>; 120279377Simp }; 121279377Simp 122279377Simp cpu@1 { 123279377Simp compatible = "arm,cortex-a7"; 124279377Simp device_type = "cpu"; 125279377Simp reg = <1>; 126279377Simp }; 127279377Simp }; 128279377Simp 129279377Simp thermal-zones { 130279377Simp cpu_thermal { 131279377Simp /* milliseconds */ 132279377Simp polling-delay-passive = <250>; 133279377Simp polling-delay = <1000>; 134279377Simp thermal-sensors = <&rtp>; 135279377Simp 136279377Simp cooling-maps { 137279377Simp map0 { 138279377Simp trip = <&cpu_alert0>; 139279377Simp cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 140279377Simp }; 141279377Simp }; 142279377Simp 143279377Simp trips { 144279377Simp cpu_alert0: cpu_alert0 { 145279377Simp /* milliCelsius */ 146279377Simp temperature = <75000>; 147279377Simp hysteresis = <2000>; 148279377Simp type = "passive"; 149279377Simp }; 150279377Simp 151279377Simp cpu_crit: cpu_crit { 152279377Simp /* milliCelsius */ 153279377Simp temperature = <100000>; 154279377Simp hysteresis = <2000>; 155279377Simp type = "critical"; 156279377Simp }; 157279377Simp }; 158279377Simp }; 159279377Simp }; 160279377Simp 161279377Simp memory { 162279377Simp reg = <0x40000000 0x80000000>; 163279377Simp }; 164279377Simp 165279377Simp timer { 166279377Simp compatible = "arm,armv7-timer"; 167279377Simp interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168279377Simp <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 169279377Simp <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 170279377Simp <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 171279377Simp }; 172279377Simp 173279377Simp pmu { 174279377Simp compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 175279377Simp interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 176279377Simp <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 177279377Simp }; 178279377Simp 179279377Simp clocks { 180279377Simp #address-cells = <1>; 181279377Simp #size-cells = <1>; 182279377Simp ranges; 183279377Simp 184279377Simp osc24M: clk@01c20050 { 185279377Simp #clock-cells = <0>; 186279377Simp compatible = "allwinner,sun4i-a10-osc-clk"; 187279377Simp reg = <0x01c20050 0x4>; 188279377Simp clock-frequency = <24000000>; 189279377Simp clock-output-names = "osc24M"; 190279377Simp }; 191279377Simp 192279377Simp osc32k: clk@0 { 193279377Simp #clock-cells = <0>; 194279377Simp compatible = "fixed-clock"; 195279377Simp clock-frequency = <32768>; 196279377Simp clock-output-names = "osc32k"; 197279377Simp }; 198279377Simp 199279377Simp pll1: clk@01c20000 { 200279377Simp #clock-cells = <0>; 201279377Simp compatible = "allwinner,sun4i-a10-pll1-clk"; 202279377Simp reg = <0x01c20000 0x4>; 203279377Simp clocks = <&osc24M>; 204279377Simp clock-output-names = "pll1"; 205279377Simp }; 206279377Simp 207279377Simp pll4: clk@01c20018 { 208279377Simp #clock-cells = <0>; 209279377Simp compatible = "allwinner,sun7i-a20-pll4-clk"; 210279377Simp reg = <0x01c20018 0x4>; 211279377Simp clocks = <&osc24M>; 212279377Simp clock-output-names = "pll4"; 213279377Simp }; 214279377Simp 215279377Simp pll5: clk@01c20020 { 216279377Simp #clock-cells = <1>; 217279377Simp compatible = "allwinner,sun4i-a10-pll5-clk"; 218279377Simp reg = <0x01c20020 0x4>; 219279377Simp clocks = <&osc24M>; 220279377Simp clock-output-names = "pll5_ddr", "pll5_other"; 221279377Simp }; 222279377Simp 223279377Simp pll6: clk@01c20028 { 224279377Simp #clock-cells = <1>; 225279377Simp compatible = "allwinner,sun4i-a10-pll6-clk"; 226279377Simp reg = <0x01c20028 0x4>; 227279377Simp clocks = <&osc24M>; 228279377Simp clock-output-names = "pll6_sata", "pll6_other", "pll6"; 229279377Simp }; 230279377Simp 231279377Simp pll8: clk@01c20040 { 232279377Simp #clock-cells = <0>; 233279377Simp compatible = "allwinner,sun7i-a20-pll4-clk"; 234279377Simp reg = <0x01c20040 0x4>; 235279377Simp clocks = <&osc24M>; 236279377Simp clock-output-names = "pll8"; 237279377Simp }; 238279377Simp 239279377Simp cpu: cpu@01c20054 { 240279377Simp #clock-cells = <0>; 241279377Simp compatible = "allwinner,sun4i-a10-cpu-clk"; 242279377Simp reg = <0x01c20054 0x4>; 243279377Simp clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 244279377Simp clock-output-names = "cpu"; 245279377Simp }; 246279377Simp 247279377Simp axi: axi@01c20054 { 248279377Simp #clock-cells = <0>; 249279377Simp compatible = "allwinner,sun4i-a10-axi-clk"; 250279377Simp reg = <0x01c20054 0x4>; 251279377Simp clocks = <&cpu>; 252279377Simp clock-output-names = "axi"; 253279377Simp }; 254279377Simp 255279377Simp ahb: ahb@01c20054 { 256279377Simp #clock-cells = <0>; 257279377Simp compatible = "allwinner,sun4i-a10-ahb-clk"; 258279377Simp reg = <0x01c20054 0x4>; 259279377Simp clocks = <&axi>; 260279377Simp clock-output-names = "ahb"; 261279377Simp }; 262279377Simp 263279377Simp ahb_gates: clk@01c20060 { 264279377Simp #clock-cells = <1>; 265279377Simp compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 266279377Simp reg = <0x01c20060 0x8>; 267279377Simp clocks = <&ahb>; 268279377Simp clock-output-names = "ahb_usb0", "ahb_ehci0", 269279377Simp "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", 270279377Simp "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", 271279377Simp "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", 272279377Simp "ahb_nand", "ahb_sdram", "ahb_ace", 273279377Simp "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", 274279377Simp "ahb_spi2", "ahb_spi3", "ahb_sata", 275279377Simp "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", 276279377Simp "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", 277279377Simp "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", 278279377Simp "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", 279279377Simp "ahb_de_fe1", "ahb_gmac", "ahb_mp", 280279377Simp "ahb_mali"; 281279377Simp }; 282279377Simp 283279377Simp apb0: apb0@01c20054 { 284279377Simp #clock-cells = <0>; 285279377Simp compatible = "allwinner,sun4i-a10-apb0-clk"; 286279377Simp reg = <0x01c20054 0x4>; 287279377Simp clocks = <&ahb>; 288279377Simp clock-output-names = "apb0"; 289279377Simp }; 290279377Simp 291279377Simp apb0_gates: clk@01c20068 { 292279377Simp #clock-cells = <1>; 293279377Simp compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 294279377Simp reg = <0x01c20068 0x4>; 295279377Simp clocks = <&apb0>; 296279377Simp clock-output-names = "apb0_codec", "apb0_spdif", 297279377Simp "apb0_ac97", "apb0_iis0", "apb0_iis1", 298279377Simp "apb0_pio", "apb0_ir0", "apb0_ir1", 299279377Simp "apb0_iis2", "apb0_keypad"; 300279377Simp }; 301279377Simp 302279377Simp apb1: clk@01c20058 { 303279377Simp #clock-cells = <0>; 304279377Simp compatible = "allwinner,sun4i-a10-apb1-clk"; 305279377Simp reg = <0x01c20058 0x4>; 306279377Simp clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 307279377Simp clock-output-names = "apb1"; 308279377Simp }; 309279377Simp 310279377Simp apb1_gates: clk@01c2006c { 311279377Simp #clock-cells = <1>; 312279377Simp compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 313279377Simp reg = <0x01c2006c 0x4>; 314279377Simp clocks = <&apb1>; 315279377Simp clock-output-names = "apb1_i2c0", "apb1_i2c1", 316279377Simp "apb1_i2c2", "apb1_i2c3", "apb1_can", 317279377Simp "apb1_scr", "apb1_ps20", "apb1_ps21", 318279377Simp "apb1_i2c4", "apb1_uart0", "apb1_uart1", 319279377Simp "apb1_uart2", "apb1_uart3", "apb1_uart4", 320279377Simp "apb1_uart5", "apb1_uart6", "apb1_uart7"; 321279377Simp }; 322279377Simp 323279377Simp nand_clk: clk@01c20080 { 324279377Simp #clock-cells = <0>; 325279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 326279377Simp reg = <0x01c20080 0x4>; 327279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 328279377Simp clock-output-names = "nand"; 329279377Simp }; 330279377Simp 331279377Simp ms_clk: clk@01c20084 { 332279377Simp #clock-cells = <0>; 333279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 334279377Simp reg = <0x01c20084 0x4>; 335279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 336279377Simp clock-output-names = "ms"; 337279377Simp }; 338279377Simp 339279377Simp mmc0_clk: clk@01c20088 { 340279377Simp #clock-cells = <1>; 341279377Simp compatible = "allwinner,sun4i-a10-mmc-clk"; 342279377Simp reg = <0x01c20088 0x4>; 343279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 344279377Simp clock-output-names = "mmc0", 345279377Simp "mmc0_output", 346279377Simp "mmc0_sample"; 347279377Simp }; 348279377Simp 349279377Simp mmc1_clk: clk@01c2008c { 350279377Simp #clock-cells = <1>; 351279377Simp compatible = "allwinner,sun4i-a10-mmc-clk"; 352279377Simp reg = <0x01c2008c 0x4>; 353279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 354279377Simp clock-output-names = "mmc1", 355279377Simp "mmc1_output", 356279377Simp "mmc1_sample"; 357279377Simp }; 358279377Simp 359279377Simp mmc2_clk: clk@01c20090 { 360279377Simp #clock-cells = <1>; 361279377Simp compatible = "allwinner,sun4i-a10-mmc-clk"; 362279377Simp reg = <0x01c20090 0x4>; 363279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 364279377Simp clock-output-names = "mmc2", 365279377Simp "mmc2_output", 366279377Simp "mmc2_sample"; 367279377Simp }; 368279377Simp 369279377Simp mmc3_clk: clk@01c20094 { 370279377Simp #clock-cells = <1>; 371279377Simp compatible = "allwinner,sun4i-a10-mmc-clk"; 372279377Simp reg = <0x01c20094 0x4>; 373279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 374279377Simp clock-output-names = "mmc3", 375279377Simp "mmc3_output", 376279377Simp "mmc3_sample"; 377279377Simp }; 378279377Simp 379279377Simp ts_clk: clk@01c20098 { 380279377Simp #clock-cells = <0>; 381279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 382279377Simp reg = <0x01c20098 0x4>; 383279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 384279377Simp clock-output-names = "ts"; 385279377Simp }; 386279377Simp 387279377Simp ss_clk: clk@01c2009c { 388279377Simp #clock-cells = <0>; 389279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 390279377Simp reg = <0x01c2009c 0x4>; 391279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 392279377Simp clock-output-names = "ss"; 393279377Simp }; 394279377Simp 395279377Simp spi0_clk: clk@01c200a0 { 396279377Simp #clock-cells = <0>; 397279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 398279377Simp reg = <0x01c200a0 0x4>; 399279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 400279377Simp clock-output-names = "spi0"; 401279377Simp }; 402279377Simp 403279377Simp spi1_clk: clk@01c200a4 { 404279377Simp #clock-cells = <0>; 405279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 406279377Simp reg = <0x01c200a4 0x4>; 407279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 408279377Simp clock-output-names = "spi1"; 409279377Simp }; 410279377Simp 411279377Simp spi2_clk: clk@01c200a8 { 412279377Simp #clock-cells = <0>; 413279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 414279377Simp reg = <0x01c200a8 0x4>; 415279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 416279377Simp clock-output-names = "spi2"; 417279377Simp }; 418279377Simp 419279377Simp pata_clk: clk@01c200ac { 420279377Simp #clock-cells = <0>; 421279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 422279377Simp reg = <0x01c200ac 0x4>; 423279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 424279377Simp clock-output-names = "pata"; 425279377Simp }; 426279377Simp 427279377Simp ir0_clk: clk@01c200b0 { 428279377Simp #clock-cells = <0>; 429279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 430279377Simp reg = <0x01c200b0 0x4>; 431279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 432279377Simp clock-output-names = "ir0"; 433279377Simp }; 434279377Simp 435279377Simp ir1_clk: clk@01c200b4 { 436279377Simp #clock-cells = <0>; 437279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 438279377Simp reg = <0x01c200b4 0x4>; 439279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 440279377Simp clock-output-names = "ir1"; 441279377Simp }; 442279377Simp 443279377Simp usb_clk: clk@01c200cc { 444279377Simp #clock-cells = <1>; 445279377Simp #reset-cells = <1>; 446279377Simp compatible = "allwinner,sun4i-a10-usb-clk"; 447279377Simp reg = <0x01c200cc 0x4>; 448279377Simp clocks = <&pll6 1>; 449279377Simp clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; 450279377Simp }; 451279377Simp 452279377Simp spi3_clk: clk@01c200d4 { 453279377Simp #clock-cells = <0>; 454279377Simp compatible = "allwinner,sun4i-a10-mod0-clk"; 455279377Simp reg = <0x01c200d4 0x4>; 456279377Simp clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 457279377Simp clock-output-names = "spi3"; 458279377Simp }; 459279377Simp 460279377Simp mbus_clk: clk@01c2015c { 461279377Simp #clock-cells = <0>; 462279377Simp compatible = "allwinner,sun5i-a13-mbus-clk"; 463279377Simp reg = <0x01c2015c 0x4>; 464279377Simp clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 465279377Simp clock-output-names = "mbus"; 466279377Simp }; 467279377Simp 468279377Simp /* 469279377Simp * The following two are dummy clocks, placeholders used in the gmac_tx 470279377Simp * clock. The gmac driver will choose one parent depending on the PHY 471279377Simp * interface mode, using clk_set_rate auto-reparenting. 472279377Simp * The actual TX clock rate is not controlled by the gmac_tx clock. 473279377Simp */ 474279377Simp mii_phy_tx_clk: clk@2 { 475279377Simp #clock-cells = <0>; 476279377Simp compatible = "fixed-clock"; 477279377Simp clock-frequency = <25000000>; 478279377Simp clock-output-names = "mii_phy_tx"; 479279377Simp }; 480279377Simp 481279377Simp gmac_int_tx_clk: clk@3 { 482279377Simp #clock-cells = <0>; 483279377Simp compatible = "fixed-clock"; 484279377Simp clock-frequency = <125000000>; 485279377Simp clock-output-names = "gmac_int_tx"; 486279377Simp }; 487279377Simp 488279377Simp gmac_tx_clk: clk@01c20164 { 489279377Simp #clock-cells = <0>; 490279377Simp compatible = "allwinner,sun7i-a20-gmac-clk"; 491279377Simp reg = <0x01c20164 0x4>; 492279377Simp clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 493279377Simp clock-output-names = "gmac_tx"; 494279377Simp }; 495279377Simp 496279377Simp /* 497279377Simp * Dummy clock used by output clocks 498279377Simp */ 499279377Simp osc24M_32k: clk@1 { 500279377Simp #clock-cells = <0>; 501279377Simp compatible = "fixed-factor-clock"; 502279377Simp clock-div = <750>; 503279377Simp clock-mult = <1>; 504279377Simp clocks = <&osc24M>; 505279377Simp clock-output-names = "osc24M_32k"; 506279377Simp }; 507279377Simp 508279377Simp clk_out_a: clk@01c201f0 { 509279377Simp #clock-cells = <0>; 510279377Simp compatible = "allwinner,sun7i-a20-out-clk"; 511279377Simp reg = <0x01c201f0 0x4>; 512279377Simp clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 513279377Simp clock-output-names = "clk_out_a"; 514279377Simp }; 515279377Simp 516279377Simp clk_out_b: clk@01c201f4 { 517279377Simp #clock-cells = <0>; 518279377Simp compatible = "allwinner,sun7i-a20-out-clk"; 519279377Simp reg = <0x01c201f4 0x4>; 520279377Simp clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 521279377Simp clock-output-names = "clk_out_b"; 522279377Simp }; 523279377Simp }; 524279377Simp 525279377Simp soc@01c00000 { 526279377Simp compatible = "simple-bus"; 527279377Simp #address-cells = <1>; 528279377Simp #size-cells = <1>; 529279377Simp ranges; 530279377Simp 531279377Simp nmi_intc: interrupt-controller@01c00030 { 532279377Simp compatible = "allwinner,sun7i-a20-sc-nmi"; 533279377Simp interrupt-controller; 534279377Simp #interrupt-cells = <2>; 535279377Simp reg = <0x01c00030 0x0c>; 536279377Simp interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 537279377Simp }; 538279377Simp 539279377Simp dma: dma-controller@01c02000 { 540279377Simp compatible = "allwinner,sun4i-a10-dma"; 541279377Simp reg = <0x01c02000 0x1000>; 542279377Simp interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 543279377Simp clocks = <&ahb_gates 6>; 544279377Simp #dma-cells = <2>; 545279377Simp }; 546279377Simp 547279377Simp spi0: spi@01c05000 { 548279377Simp compatible = "allwinner,sun4i-a10-spi"; 549279377Simp reg = <0x01c05000 0x1000>; 550279377Simp interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 551279377Simp clocks = <&ahb_gates 20>, <&spi0_clk>; 552279377Simp clock-names = "ahb", "mod"; 553279377Simp dmas = <&dma SUN4I_DMA_DEDICATED 27>, 554279377Simp <&dma SUN4I_DMA_DEDICATED 26>; 555279377Simp dma-names = "rx", "tx"; 556279377Simp status = "disabled"; 557279377Simp #address-cells = <1>; 558279377Simp #size-cells = <0>; 559279377Simp }; 560279377Simp 561279377Simp spi1: spi@01c06000 { 562279377Simp compatible = "allwinner,sun4i-a10-spi"; 563279377Simp reg = <0x01c06000 0x1000>; 564279377Simp interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 565279377Simp clocks = <&ahb_gates 21>, <&spi1_clk>; 566279377Simp clock-names = "ahb", "mod"; 567279377Simp dmas = <&dma SUN4I_DMA_DEDICATED 9>, 568279377Simp <&dma SUN4I_DMA_DEDICATED 8>; 569279377Simp dma-names = "rx", "tx"; 570279377Simp status = "disabled"; 571279377Simp #address-cells = <1>; 572279377Simp #size-cells = <0>; 573279377Simp }; 574279377Simp 575279377Simp emac: ethernet@01c0b000 { 576279377Simp compatible = "allwinner,sun4i-a10-emac"; 577279377Simp reg = <0x01c0b000 0x1000>; 578279377Simp interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 579279377Simp clocks = <&ahb_gates 17>; 580279377Simp status = "disabled"; 581279377Simp }; 582279377Simp 583279377Simp mdio: mdio@01c0b080 { 584279377Simp compatible = "allwinner,sun4i-a10-mdio"; 585279377Simp reg = <0x01c0b080 0x14>; 586279377Simp status = "disabled"; 587279377Simp #address-cells = <1>; 588279377Simp #size-cells = <0>; 589279377Simp }; 590279377Simp 591279377Simp mmc0: mmc@01c0f000 { 592279377Simp compatible = "allwinner,sun5i-a13-mmc"; 593279377Simp reg = <0x01c0f000 0x1000>; 594279377Simp clocks = <&ahb_gates 8>, 595279377Simp <&mmc0_clk 0>, 596279377Simp <&mmc0_clk 1>, 597279377Simp <&mmc0_clk 2>; 598279377Simp clock-names = "ahb", 599279377Simp "mmc", 600279377Simp "output", 601279377Simp "sample"; 602279377Simp interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 603279377Simp status = "disabled"; 604279377Simp }; 605279377Simp 606279377Simp mmc1: mmc@01c10000 { 607279377Simp compatible = "allwinner,sun5i-a13-mmc"; 608279377Simp reg = <0x01c10000 0x1000>; 609279377Simp clocks = <&ahb_gates 9>, 610279377Simp <&mmc1_clk 0>, 611279377Simp <&mmc1_clk 1>, 612279377Simp <&mmc1_clk 2>; 613279377Simp clock-names = "ahb", 614279377Simp "mmc", 615279377Simp "output", 616279377Simp "sample"; 617279377Simp interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 618279377Simp status = "disabled"; 619279377Simp }; 620279377Simp 621279377Simp mmc2: mmc@01c11000 { 622279377Simp compatible = "allwinner,sun5i-a13-mmc"; 623279377Simp reg = <0x01c11000 0x1000>; 624279377Simp clocks = <&ahb_gates 10>, 625279377Simp <&mmc2_clk 0>, 626279377Simp <&mmc2_clk 1>, 627279377Simp <&mmc2_clk 2>; 628279377Simp clock-names = "ahb", 629279377Simp "mmc", 630279377Simp "output", 631279377Simp "sample"; 632279377Simp interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 633279377Simp status = "disabled"; 634279377Simp }; 635279377Simp 636279377Simp mmc3: mmc@01c12000 { 637279377Simp compatible = "allwinner,sun5i-a13-mmc"; 638279377Simp reg = <0x01c12000 0x1000>; 639279377Simp clocks = <&ahb_gates 11>, 640279377Simp <&mmc3_clk 0>, 641279377Simp <&mmc3_clk 1>, 642279377Simp <&mmc3_clk 2>; 643279377Simp clock-names = "ahb", 644279377Simp "mmc", 645279377Simp "output", 646279377Simp "sample"; 647279377Simp interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 648279377Simp status = "disabled"; 649279377Simp }; 650279377Simp 651279377Simp usbphy: phy@01c13400 { 652279377Simp #phy-cells = <1>; 653279377Simp compatible = "allwinner,sun7i-a20-usb-phy"; 654279377Simp reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 655279377Simp reg-names = "phy_ctrl", "pmu1", "pmu2"; 656279377Simp clocks = <&usb_clk 8>; 657279377Simp clock-names = "usb_phy"; 658279377Simp resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; 659279377Simp reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 660279377Simp status = "disabled"; 661279377Simp }; 662279377Simp 663279377Simp ehci0: usb@01c14000 { 664279377Simp compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 665279377Simp reg = <0x01c14000 0x100>; 666279377Simp interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 667279377Simp clocks = <&ahb_gates 1>; 668279377Simp phys = <&usbphy 1>; 669279377Simp phy-names = "usb"; 670279377Simp status = "disabled"; 671279377Simp }; 672279377Simp 673279377Simp ohci0: usb@01c14400 { 674279377Simp compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 675279377Simp reg = <0x01c14400 0x100>; 676279377Simp interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 677279377Simp clocks = <&usb_clk 6>, <&ahb_gates 2>; 678279377Simp phys = <&usbphy 1>; 679279377Simp phy-names = "usb"; 680279377Simp status = "disabled"; 681279377Simp }; 682279377Simp 683279377Simp spi2: spi@01c17000 { 684279377Simp compatible = "allwinner,sun4i-a10-spi"; 685279377Simp reg = <0x01c17000 0x1000>; 686279377Simp interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 687279377Simp clocks = <&ahb_gates 22>, <&spi2_clk>; 688279377Simp clock-names = "ahb", "mod"; 689279377Simp dmas = <&dma SUN4I_DMA_DEDICATED 29>, 690279377Simp <&dma SUN4I_DMA_DEDICATED 28>; 691279377Simp dma-names = "rx", "tx"; 692279377Simp status = "disabled"; 693279377Simp #address-cells = <1>; 694279377Simp #size-cells = <0>; 695279377Simp }; 696279377Simp 697279377Simp ahci: sata@01c18000 { 698279377Simp compatible = "allwinner,sun4i-a10-ahci"; 699279377Simp reg = <0x01c18000 0x1000>; 700279377Simp interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 701279377Simp clocks = <&pll6 0>, <&ahb_gates 25>; 702279377Simp status = "disabled"; 703279377Simp }; 704279377Simp 705279377Simp ehci1: usb@01c1c000 { 706279377Simp compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 707279377Simp reg = <0x01c1c000 0x100>; 708279377Simp interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 709279377Simp clocks = <&ahb_gates 3>; 710279377Simp phys = <&usbphy 2>; 711279377Simp phy-names = "usb"; 712279377Simp status = "disabled"; 713279377Simp }; 714279377Simp 715279377Simp ohci1: usb@01c1c400 { 716279377Simp compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 717279377Simp reg = <0x01c1c400 0x100>; 718279377Simp interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 719279377Simp clocks = <&usb_clk 7>, <&ahb_gates 4>; 720279377Simp phys = <&usbphy 2>; 721279377Simp phy-names = "usb"; 722279377Simp status = "disabled"; 723279377Simp }; 724279377Simp 725279377Simp spi3: spi@01c1f000 { 726279377Simp compatible = "allwinner,sun4i-a10-spi"; 727279377Simp reg = <0x01c1f000 0x1000>; 728279377Simp interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 729279377Simp clocks = <&ahb_gates 23>, <&spi3_clk>; 730279377Simp clock-names = "ahb", "mod"; 731279377Simp dmas = <&dma SUN4I_DMA_DEDICATED 31>, 732279377Simp <&dma SUN4I_DMA_DEDICATED 30>; 733279377Simp dma-names = "rx", "tx"; 734279377Simp status = "disabled"; 735279377Simp #address-cells = <1>; 736279377Simp #size-cells = <0>; 737279377Simp }; 738279377Simp 739279377Simp pio: pinctrl@01c20800 { 740279377Simp compatible = "allwinner,sun7i-a20-pinctrl"; 741279377Simp reg = <0x01c20800 0x400>; 742279377Simp interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 743279377Simp clocks = <&apb0_gates 5>; 744279377Simp gpio-controller; 745279377Simp interrupt-controller; 746279377Simp #interrupt-cells = <2>; 747279377Simp #size-cells = <0>; 748279377Simp #gpio-cells = <3>; 749279377Simp 750279377Simp pwm0_pins_a: pwm0@0 { 751279377Simp allwinner,pins = "PB2"; 752279377Simp allwinner,function = "pwm"; 753279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 754279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 755279377Simp }; 756279377Simp 757279377Simp pwm1_pins_a: pwm1@0 { 758279377Simp allwinner,pins = "PI3"; 759279377Simp allwinner,function = "pwm"; 760279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 761279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 762279377Simp }; 763279377Simp 764279377Simp uart0_pins_a: uart0@0 { 765279377Simp allwinner,pins = "PB22", "PB23"; 766279377Simp allwinner,function = "uart0"; 767279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 768279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 769279377Simp }; 770279377Simp 771279377Simp uart2_pins_a: uart2@0 { 772279377Simp allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 773279377Simp allwinner,function = "uart2"; 774279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 775279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 776279377Simp }; 777279377Simp 778279377Simp uart3_pins_a: uart3@0 { 779279377Simp allwinner,pins = "PG6", "PG7", "PG8", "PG9"; 780279377Simp allwinner,function = "uart3"; 781279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 782279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 783279377Simp }; 784279377Simp 785279377Simp uart3_pins_b: uart3@1 { 786279377Simp allwinner,pins = "PH0", "PH1"; 787279377Simp allwinner,function = "uart3"; 788279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 789279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 790279377Simp }; 791279377Simp 792279377Simp uart4_pins_a: uart4@0 { 793279377Simp allwinner,pins = "PG10", "PG11"; 794279377Simp allwinner,function = "uart4"; 795279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 796279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 797279377Simp }; 798279377Simp 799279377Simp uart5_pins_a: uart5@0 { 800279377Simp allwinner,pins = "PI10", "PI11"; 801279377Simp allwinner,function = "uart5"; 802279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 803279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 804279377Simp }; 805279377Simp 806279377Simp uart6_pins_a: uart6@0 { 807279377Simp allwinner,pins = "PI12", "PI13"; 808279377Simp allwinner,function = "uart6"; 809279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 810279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 811279377Simp }; 812279377Simp 813279377Simp uart7_pins_a: uart7@0 { 814279377Simp allwinner,pins = "PI20", "PI21"; 815279377Simp allwinner,function = "uart7"; 816279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 817279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 818279377Simp }; 819279377Simp 820279377Simp i2c0_pins_a: i2c0@0 { 821279377Simp allwinner,pins = "PB0", "PB1"; 822279377Simp allwinner,function = "i2c0"; 823279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 824279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 825279377Simp }; 826279377Simp 827279377Simp i2c1_pins_a: i2c1@0 { 828279377Simp allwinner,pins = "PB18", "PB19"; 829279377Simp allwinner,function = "i2c1"; 830279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 831279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 832279377Simp }; 833279377Simp 834279377Simp i2c2_pins_a: i2c2@0 { 835279377Simp allwinner,pins = "PB20", "PB21"; 836279377Simp allwinner,function = "i2c2"; 837279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 838279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 839279377Simp }; 840279377Simp 841279377Simp i2c3_pins_a: i2c3@0 { 842279377Simp allwinner,pins = "PI0", "PI1"; 843279377Simp allwinner,function = "i2c3"; 844279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 845279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 846279377Simp }; 847279377Simp 848279377Simp emac_pins_a: emac0@0 { 849279377Simp allwinner,pins = "PA0", "PA1", "PA2", 850279377Simp "PA3", "PA4", "PA5", "PA6", 851279377Simp "PA7", "PA8", "PA9", "PA10", 852279377Simp "PA11", "PA12", "PA13", "PA14", 853279377Simp "PA15", "PA16"; 854279377Simp allwinner,function = "emac"; 855279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 856279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 857279377Simp }; 858279377Simp 859279377Simp clk_out_a_pins_a: clk_out_a@0 { 860279377Simp allwinner,pins = "PI12"; 861279377Simp allwinner,function = "clk_out_a"; 862279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 863279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 864279377Simp }; 865279377Simp 866279377Simp clk_out_b_pins_a: clk_out_b@0 { 867279377Simp allwinner,pins = "PI13"; 868279377Simp allwinner,function = "clk_out_b"; 869279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 870279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 871279377Simp }; 872279377Simp 873279377Simp gmac_pins_mii_a: gmac_mii@0 { 874279377Simp allwinner,pins = "PA0", "PA1", "PA2", 875279377Simp "PA3", "PA4", "PA5", "PA6", 876279377Simp "PA7", "PA8", "PA9", "PA10", 877279377Simp "PA11", "PA12", "PA13", "PA14", 878279377Simp "PA15", "PA16"; 879279377Simp allwinner,function = "gmac"; 880279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 881279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 882279377Simp }; 883279377Simp 884279377Simp gmac_pins_rgmii_a: gmac_rgmii@0 { 885279377Simp allwinner,pins = "PA0", "PA1", "PA2", 886279377Simp "PA3", "PA4", "PA5", "PA6", 887279377Simp "PA7", "PA8", "PA10", 888279377Simp "PA11", "PA12", "PA13", 889279377Simp "PA15", "PA16"; 890279377Simp allwinner,function = "gmac"; 891279377Simp /* 892279377Simp * data lines in RGMII mode use DDR mode 893279377Simp * and need a higher signal drive strength 894279377Simp */ 895279377Simp allwinner,drive = <SUN4I_PINCTRL_40_MA>; 896279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 897279377Simp }; 898279377Simp 899279377Simp spi0_pins_a: spi0@0 { 900279377Simp allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; 901279377Simp allwinner,function = "spi0"; 902279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 903279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 904279377Simp }; 905279377Simp 906279377Simp spi1_pins_a: spi1@0 { 907279377Simp allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 908279377Simp allwinner,function = "spi1"; 909279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 910279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 911279377Simp }; 912279377Simp 913279377Simp spi2_pins_a: spi2@0 { 914279377Simp allwinner,pins = "PC19", "PC20", "PC21", "PC22"; 915279377Simp allwinner,function = "spi2"; 916279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 917279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 918279377Simp }; 919279377Simp 920279377Simp spi2_pins_b: spi2@1 { 921279377Simp allwinner,pins = "PB14", "PB15", "PB16", "PB17"; 922279377Simp allwinner,function = "spi2"; 923279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 924279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 925279377Simp }; 926279377Simp 927279377Simp mmc0_pins_a: mmc0@0 { 928279377Simp allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 929279377Simp allwinner,function = "mmc0"; 930279377Simp allwinner,drive = <SUN4I_PINCTRL_30_MA>; 931279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 932279377Simp }; 933279377Simp 934279377Simp mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 935279377Simp allwinner,pins = "PH1"; 936279377Simp allwinner,function = "gpio_in"; 937279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 938279377Simp allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 939279377Simp }; 940279377Simp 941279377Simp mmc2_pins_a: mmc2@0 { 942279377Simp allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; 943279377Simp allwinner,function = "mmc2"; 944279377Simp allwinner,drive = <SUN4I_PINCTRL_30_MA>; 945279377Simp allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 946279377Simp }; 947279377Simp 948279377Simp mmc3_pins_a: mmc3@0 { 949279377Simp allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 950279377Simp allwinner,function = "mmc3"; 951279377Simp allwinner,drive = <SUN4I_PINCTRL_30_MA>; 952279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 953279377Simp }; 954279377Simp 955279377Simp ir0_pins_a: ir0@0 { 956279377Simp allwinner,pins = "PB3","PB4"; 957279377Simp allwinner,function = "ir0"; 958279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 959279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 960279377Simp }; 961279377Simp 962279377Simp ir1_pins_a: ir1@0 { 963279377Simp allwinner,pins = "PB22","PB23"; 964279377Simp allwinner,function = "ir1"; 965279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 966279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 967279377Simp }; 968279377Simp 969279377Simp ps20_pins_a: ps20@0 { 970279377Simp allwinner,pins = "PI20", "PI21"; 971279377Simp allwinner,function = "ps2"; 972279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 973279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 974279377Simp }; 975279377Simp 976279377Simp ps21_pins_a: ps21@0 { 977279377Simp allwinner,pins = "PH12", "PH13"; 978279377Simp allwinner,function = "ps2"; 979279377Simp allwinner,drive = <SUN4I_PINCTRL_10_MA>; 980279377Simp allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 981279377Simp }; 982279377Simp }; 983279377Simp 984279377Simp timer@01c20c00 { 985279377Simp compatible = "allwinner,sun4i-a10-timer"; 986279377Simp reg = <0x01c20c00 0x90>; 987279377Simp interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 988279377Simp <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 989279377Simp <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 990279377Simp <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 991279377Simp <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 992279377Simp <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 993279377Simp clocks = <&osc24M>; 994279377Simp }; 995279377Simp 996279377Simp wdt: watchdog@01c20c90 { 997279377Simp compatible = "allwinner,sun4i-a10-wdt"; 998279377Simp reg = <0x01c20c90 0x10>; 999279377Simp }; 1000279377Simp 1001279377Simp rtc: rtc@01c20d00 { 1002279377Simp compatible = "allwinner,sun7i-a20-rtc"; 1003279377Simp reg = <0x01c20d00 0x20>; 1004279377Simp interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1005279377Simp }; 1006279377Simp 1007279377Simp pwm: pwm@01c20e00 { 1008279377Simp compatible = "allwinner,sun7i-a20-pwm"; 1009279377Simp reg = <0x01c20e00 0xc>; 1010279377Simp clocks = <&osc24M>; 1011279377Simp #pwm-cells = <3>; 1012279377Simp status = "disabled"; 1013279377Simp }; 1014279377Simp 1015279377Simp ir0: ir@01c21800 { 1016279377Simp compatible = "allwinner,sun4i-a10-ir"; 1017279377Simp clocks = <&apb0_gates 6>, <&ir0_clk>; 1018279377Simp clock-names = "apb", "ir"; 1019279377Simp interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1020279377Simp reg = <0x01c21800 0x40>; 1021279377Simp status = "disabled"; 1022279377Simp }; 1023279377Simp 1024279377Simp ir1: ir@01c21c00 { 1025279377Simp compatible = "allwinner,sun4i-a10-ir"; 1026279377Simp clocks = <&apb0_gates 7>, <&ir1_clk>; 1027279377Simp clock-names = "apb", "ir"; 1028279377Simp interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1029279377Simp reg = <0x01c21c00 0x40>; 1030279377Simp status = "disabled"; 1031279377Simp }; 1032279377Simp 1033279377Simp lradc: lradc@01c22800 { 1034279377Simp compatible = "allwinner,sun4i-a10-lradc-keys"; 1035279377Simp reg = <0x01c22800 0x100>; 1036279377Simp interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1037279377Simp status = "disabled"; 1038279377Simp }; 1039279377Simp 1040279377Simp sid: eeprom@01c23800 { 1041279377Simp compatible = "allwinner,sun7i-a20-sid"; 1042279377Simp reg = <0x01c23800 0x200>; 1043279377Simp }; 1044279377Simp 1045279377Simp rtp: rtp@01c25000 { 1046279377Simp compatible = "allwinner,sun4i-a10-ts"; 1047279377Simp reg = <0x01c25000 0x100>; 1048279377Simp interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1049279377Simp #thermal-sensor-cells = <0>; 1050279377Simp }; 1051279377Simp 1052279377Simp uart0: serial@01c28000 { 1053279377Simp compatible = "snps,dw-apb-uart"; 1054279377Simp reg = <0x01c28000 0x400>; 1055279377Simp interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1056279377Simp reg-shift = <2>; 1057279377Simp reg-io-width = <4>; 1058279377Simp clocks = <&apb1_gates 16>; 1059279377Simp status = "disabled"; 1060279377Simp }; 1061279377Simp 1062279377Simp uart1: serial@01c28400 { 1063279377Simp compatible = "snps,dw-apb-uart"; 1064279377Simp reg = <0x01c28400 0x400>; 1065279377Simp interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1066279377Simp reg-shift = <2>; 1067279377Simp reg-io-width = <4>; 1068279377Simp clocks = <&apb1_gates 17>; 1069279377Simp status = "disabled"; 1070279377Simp }; 1071279377Simp 1072279377Simp uart2: serial@01c28800 { 1073279377Simp compatible = "snps,dw-apb-uart"; 1074279377Simp reg = <0x01c28800 0x400>; 1075279377Simp interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1076279377Simp reg-shift = <2>; 1077279377Simp reg-io-width = <4>; 1078279377Simp clocks = <&apb1_gates 18>; 1079279377Simp status = "disabled"; 1080279377Simp }; 1081279377Simp 1082279377Simp uart3: serial@01c28c00 { 1083279377Simp compatible = "snps,dw-apb-uart"; 1084279377Simp reg = <0x01c28c00 0x400>; 1085279377Simp interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1086279377Simp reg-shift = <2>; 1087279377Simp reg-io-width = <4>; 1088279377Simp clocks = <&apb1_gates 19>; 1089279377Simp status = "disabled"; 1090279377Simp }; 1091279377Simp 1092279377Simp uart4: serial@01c29000 { 1093279377Simp compatible = "snps,dw-apb-uart"; 1094279377Simp reg = <0x01c29000 0x400>; 1095279377Simp interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1096279377Simp reg-shift = <2>; 1097279377Simp reg-io-width = <4>; 1098279377Simp clocks = <&apb1_gates 20>; 1099279377Simp status = "disabled"; 1100279377Simp }; 1101279377Simp 1102279377Simp uart5: serial@01c29400 { 1103279377Simp compatible = "snps,dw-apb-uart"; 1104279377Simp reg = <0x01c29400 0x400>; 1105279377Simp interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1106279377Simp reg-shift = <2>; 1107279377Simp reg-io-width = <4>; 1108279377Simp clocks = <&apb1_gates 21>; 1109279377Simp status = "disabled"; 1110279377Simp }; 1111279377Simp 1112279377Simp uart6: serial@01c29800 { 1113279377Simp compatible = "snps,dw-apb-uart"; 1114279377Simp reg = <0x01c29800 0x400>; 1115279377Simp interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1116279377Simp reg-shift = <2>; 1117279377Simp reg-io-width = <4>; 1118279377Simp clocks = <&apb1_gates 22>; 1119279377Simp status = "disabled"; 1120279377Simp }; 1121279377Simp 1122279377Simp uart7: serial@01c29c00 { 1123279377Simp compatible = "snps,dw-apb-uart"; 1124279377Simp reg = <0x01c29c00 0x400>; 1125279377Simp interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1126279377Simp reg-shift = <2>; 1127279377Simp reg-io-width = <4>; 1128279377Simp clocks = <&apb1_gates 23>; 1129279377Simp status = "disabled"; 1130279377Simp }; 1131279377Simp 1132279377Simp i2c0: i2c@01c2ac00 { 1133279377Simp compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1134279377Simp reg = <0x01c2ac00 0x400>; 1135279377Simp interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1136279377Simp clocks = <&apb1_gates 0>; 1137279377Simp status = "disabled"; 1138279377Simp #address-cells = <1>; 1139279377Simp #size-cells = <0>; 1140279377Simp }; 1141279377Simp 1142279377Simp i2c1: i2c@01c2b000 { 1143279377Simp compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1144279377Simp reg = <0x01c2b000 0x400>; 1145279377Simp interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1146279377Simp clocks = <&apb1_gates 1>; 1147279377Simp status = "disabled"; 1148279377Simp #address-cells = <1>; 1149279377Simp #size-cells = <0>; 1150279377Simp }; 1151279377Simp 1152279377Simp i2c2: i2c@01c2b400 { 1153279377Simp compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1154279377Simp reg = <0x01c2b400 0x400>; 1155279377Simp interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1156279377Simp clocks = <&apb1_gates 2>; 1157279377Simp status = "disabled"; 1158279377Simp #address-cells = <1>; 1159279377Simp #size-cells = <0>; 1160279377Simp }; 1161279377Simp 1162279377Simp i2c3: i2c@01c2b800 { 1163279377Simp compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1164279377Simp reg = <0x01c2b800 0x400>; 1165279377Simp interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1166279377Simp clocks = <&apb1_gates 3>; 1167279377Simp status = "disabled"; 1168279377Simp #address-cells = <1>; 1169279377Simp #size-cells = <0>; 1170279377Simp }; 1171279377Simp 1172279377Simp i2c4: i2c@01c2c000 { 1173279377Simp compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1174279377Simp reg = <0x01c2c000 0x400>; 1175279377Simp interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1176279377Simp clocks = <&apb1_gates 15>; 1177279377Simp status = "disabled"; 1178279377Simp #address-cells = <1>; 1179279377Simp #size-cells = <0>; 1180279377Simp }; 1181279377Simp 1182279377Simp gmac: ethernet@01c50000 { 1183279377Simp compatible = "allwinner,sun7i-a20-gmac"; 1184279377Simp reg = <0x01c50000 0x10000>; 1185279377Simp interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1186279377Simp interrupt-names = "macirq"; 1187279377Simp clocks = <&ahb_gates 49>, <&gmac_tx_clk>; 1188279377Simp clock-names = "stmmaceth", "allwinner_gmac_tx"; 1189279377Simp snps,pbl = <2>; 1190279377Simp snps,fixed-burst; 1191279377Simp snps,force_sf_dma_mode; 1192279377Simp status = "disabled"; 1193279377Simp #address-cells = <1>; 1194279377Simp #size-cells = <0>; 1195279377Simp }; 1196279377Simp 1197279377Simp hstimer@01c60000 { 1198279377Simp compatible = "allwinner,sun7i-a20-hstimer"; 1199279377Simp reg = <0x01c60000 0x1000>; 1200279377Simp interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1201279377Simp <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1202279377Simp <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1203279377Simp <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1204279377Simp clocks = <&ahb_gates 28>; 1205279377Simp }; 1206279377Simp 1207279377Simp gic: interrupt-controller@01c81000 { 1208279377Simp compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1209279377Simp reg = <0x01c81000 0x1000>, 1210279377Simp <0x01c82000 0x1000>, 1211279377Simp <0x01c84000 0x2000>, 1212279377Simp <0x01c86000 0x2000>; 1213279377Simp interrupt-controller; 1214279377Simp #interrupt-cells = <3>; 1215279377Simp interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1216279377Simp }; 1217279377Simp 1218279377Simp ps20: ps2@01c2a000 { 1219279377Simp compatible = "allwinner,sun4i-a10-ps2"; 1220279377Simp reg = <0x01c2a000 0x400>; 1221279377Simp interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1222279377Simp clocks = <&apb1_gates 6>; 1223279377Simp status = "disabled"; 1224279377Simp }; 1225279377Simp 1226279377Simp ps21: ps2@01c2a400 { 1227279377Simp compatible = "allwinner,sun4i-a10-ps2"; 1228279377Simp reg = <0x01c2a400 0x400>; 1229279377Simp interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1230279377Simp clocks = <&apb1_gates 7>; 1231279377Simp status = "disabled"; 1232279377Simp }; 1233279377Simp }; 1234279377Simp}; 1235