1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public 22 * License along with this file; if not, write to the Free 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 * 26 * Or, alternatively, 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use, 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50#include "skeleton.dtsi" 51 52#include <dt-bindings/interrupt-controller/arm-gic.h> 53#include <dt-bindings/thermal/thermal.h> 54 55#include <dt-bindings/dma/sun4i-a10.h> 56#include <dt-bindings/pinctrl/sun4i-a10.h> 57 58/ { 59 interrupt-parent = <&gic>; 60 61 aliases { 62 ethernet0 = &gmac; 63 }; 64 65 chosen { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges; 69 70 framebuffer@0 { 71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; 72 allwinner,pipeline = "de_be0-lcd0-hdmi"; 73 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 74 <&ahb_gates 44>; 75 status = "disabled"; 76 }; 77 78 framebuffer@1 { 79 compatible = "allwinner,simple-framebuffer", 80 "simple-framebuffer"; 81 allwinner,pipeline = "de_be0-lcd0"; 82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; 83 status = "disabled"; 84 }; 85 86 framebuffer@2 { 87 compatible = "allwinner,simple-framebuffer", 88 "simple-framebuffer"; 89 allwinner,pipeline = "de_be0-lcd0-tve0"; 90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, 91 <&ahb_gates 44>; 92 status = "disabled"; 93 }; 94 }; 95 96 cpus { 97 #address-cells = <1>; 98 #size-cells = <0>; 99 100 cpu0: cpu@0 { 101 compatible = "arm,cortex-a7"; 102 device_type = "cpu"; 103 reg = <0>; 104 clocks = <&cpu>; 105 clock-latency = <244144>; /* 8 32k periods */ 106 operating-points = < 107 /* kHz uV */ 108 1008000 1450000 109 960000 1400000 110 912000 1400000 111 864000 1300000 112 720000 1200000 113 528000 1100000 114 312000 1000000 115 144000 900000 116 >; 117 #cooling-cells = <2>; 118 cooling-min-level = <0>; 119 cooling-max-level = <7>; 120 }; 121 122 cpu@1 { 123 compatible = "arm,cortex-a7"; 124 device_type = "cpu"; 125 reg = <1>; 126 }; 127 }; 128 129 thermal-zones { 130 cpu_thermal { 131 /* milliseconds */ 132 polling-delay-passive = <250>; 133 polling-delay = <1000>; 134 thermal-sensors = <&rtp>; 135 136 cooling-maps { 137 map0 { 138 trip = <&cpu_alert0>; 139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 140 }; 141 }; 142 143 trips { 144 cpu_alert0: cpu_alert0 { 145 /* milliCelsius */ 146 temperature = <75000>; 147 hysteresis = <2000>; 148 type = "passive"; 149 }; 150 151 cpu_crit: cpu_crit { 152 /* milliCelsius */ 153 temperature = <100000>; 154 hysteresis = <2000>; 155 type = "critical"; 156 }; 157 }; 158 }; 159 }; 160 161 memory { 162 reg = <0x40000000 0x80000000>; 163 }; 164 165 timer { 166 compatible = "arm,armv7-timer"; 167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 177 }; 178 179 clocks { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 osc24M: clk@01c20050 { 185 #clock-cells = <0>; 186 compatible = "allwinner,sun4i-a10-osc-clk"; 187 reg = <0x01c20050 0x4>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc24M"; 190 }; 191 192 osc32k: clk@0 { 193 #clock-cells = <0>; 194 compatible = "fixed-clock"; 195 clock-frequency = <32768>; 196 clock-output-names = "osc32k"; 197 }; 198 199 pll1: clk@01c20000 { 200 #clock-cells = <0>; 201 compatible = "allwinner,sun4i-a10-pll1-clk"; 202 reg = <0x01c20000 0x4>; 203 clocks = <&osc24M>; 204 clock-output-names = "pll1"; 205 }; 206 207 pll4: clk@01c20018 { 208 #clock-cells = <0>; 209 compatible = "allwinner,sun7i-a20-pll4-clk"; 210 reg = <0x01c20018 0x4>; 211 clocks = <&osc24M>; 212 clock-output-names = "pll4"; 213 }; 214 215 pll5: clk@01c20020 { 216 #clock-cells = <1>; 217 compatible = "allwinner,sun4i-a10-pll5-clk"; 218 reg = <0x01c20020 0x4>; 219 clocks = <&osc24M>; 220 clock-output-names = "pll5_ddr", "pll5_other"; 221 }; 222 223 pll6: clk@01c20028 { 224 #clock-cells = <1>; 225 compatible = "allwinner,sun4i-a10-pll6-clk"; 226 reg = <0x01c20028 0x4>; 227 clocks = <&osc24M>; 228 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 229 }; 230 231 pll8: clk@01c20040 { 232 #clock-cells = <0>; 233 compatible = "allwinner,sun7i-a20-pll4-clk"; 234 reg = <0x01c20040 0x4>; 235 clocks = <&osc24M>; 236 clock-output-names = "pll8"; 237 }; 238 239 cpu: cpu@01c20054 { 240 #clock-cells = <0>; 241 compatible = "allwinner,sun4i-a10-cpu-clk"; 242 reg = <0x01c20054 0x4>; 243 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 244 clock-output-names = "cpu"; 245 }; 246 247 axi: axi@01c20054 { 248 #clock-cells = <0>; 249 compatible = "allwinner,sun4i-a10-axi-clk"; 250 reg = <0x01c20054 0x4>; 251 clocks = <&cpu>; 252 clock-output-names = "axi"; 253 }; 254 255 ahb: ahb@01c20054 { 256 #clock-cells = <0>; 257 compatible = "allwinner,sun4i-a10-ahb-clk"; 258 reg = <0x01c20054 0x4>; 259 clocks = <&axi>; 260 clock-output-names = "ahb"; 261 }; 262 263 ahb_gates: clk@01c20060 { 264 #clock-cells = <1>; 265 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 266 reg = <0x01c20060 0x8>; 267 clocks = <&ahb>; 268 clock-output-names = "ahb_usb0", "ahb_ehci0", 269 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", 270 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", 271 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", 272 "ahb_nand", "ahb_sdram", "ahb_ace", 273 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", 274 "ahb_spi2", "ahb_spi3", "ahb_sata", 275 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", 276 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", 277 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", 278 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", 279 "ahb_de_fe1", "ahb_gmac", "ahb_mp", 280 "ahb_mali"; 281 }; 282 283 apb0: apb0@01c20054 { 284 #clock-cells = <0>; 285 compatible = "allwinner,sun4i-a10-apb0-clk"; 286 reg = <0x01c20054 0x4>; 287 clocks = <&ahb>; 288 clock-output-names = "apb0"; 289 }; 290 291 apb0_gates: clk@01c20068 { 292 #clock-cells = <1>; 293 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 294 reg = <0x01c20068 0x4>; 295 clocks = <&apb0>; 296 clock-output-names = "apb0_codec", "apb0_spdif", 297 "apb0_ac97", "apb0_iis0", "apb0_iis1", 298 "apb0_pio", "apb0_ir0", "apb0_ir1", 299 "apb0_iis2", "apb0_keypad"; 300 }; 301 302 apb1: clk@01c20058 { 303 #clock-cells = <0>; 304 compatible = "allwinner,sun4i-a10-apb1-clk"; 305 reg = <0x01c20058 0x4>; 306 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 307 clock-output-names = "apb1"; 308 }; 309 310 apb1_gates: clk@01c2006c { 311 #clock-cells = <1>; 312 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 313 reg = <0x01c2006c 0x4>; 314 clocks = <&apb1>; 315 clock-output-names = "apb1_i2c0", "apb1_i2c1", 316 "apb1_i2c2", "apb1_i2c3", "apb1_can", 317 "apb1_scr", "apb1_ps20", "apb1_ps21", 318 "apb1_i2c4", "apb1_uart0", "apb1_uart1", 319 "apb1_uart2", "apb1_uart3", "apb1_uart4", 320 "apb1_uart5", "apb1_uart6", "apb1_uart7"; 321 }; 322 323 nand_clk: clk@01c20080 { 324 #clock-cells = <0>; 325 compatible = "allwinner,sun4i-a10-mod0-clk"; 326 reg = <0x01c20080 0x4>; 327 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 328 clock-output-names = "nand"; 329 }; 330 331 ms_clk: clk@01c20084 { 332 #clock-cells = <0>; 333 compatible = "allwinner,sun4i-a10-mod0-clk"; 334 reg = <0x01c20084 0x4>; 335 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 336 clock-output-names = "ms"; 337 }; 338 339 mmc0_clk: clk@01c20088 { 340 #clock-cells = <1>; 341 compatible = "allwinner,sun4i-a10-mmc-clk"; 342 reg = <0x01c20088 0x4>; 343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 344 clock-output-names = "mmc0", 345 "mmc0_output", 346 "mmc0_sample"; 347 }; 348 349 mmc1_clk: clk@01c2008c { 350 #clock-cells = <1>; 351 compatible = "allwinner,sun4i-a10-mmc-clk"; 352 reg = <0x01c2008c 0x4>; 353 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 354 clock-output-names = "mmc1", 355 "mmc1_output", 356 "mmc1_sample"; 357 }; 358 359 mmc2_clk: clk@01c20090 { 360 #clock-cells = <1>; 361 compatible = "allwinner,sun4i-a10-mmc-clk"; 362 reg = <0x01c20090 0x4>; 363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 364 clock-output-names = "mmc2", 365 "mmc2_output", 366 "mmc2_sample"; 367 }; 368 369 mmc3_clk: clk@01c20094 { 370 #clock-cells = <1>; 371 compatible = "allwinner,sun4i-a10-mmc-clk"; 372 reg = <0x01c20094 0x4>; 373 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 374 clock-output-names = "mmc3", 375 "mmc3_output", 376 "mmc3_sample"; 377 }; 378 379 ts_clk: clk@01c20098 { 380 #clock-cells = <0>; 381 compatible = "allwinner,sun4i-a10-mod0-clk"; 382 reg = <0x01c20098 0x4>; 383 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 384 clock-output-names = "ts"; 385 }; 386 387 ss_clk: clk@01c2009c { 388 #clock-cells = <0>; 389 compatible = "allwinner,sun4i-a10-mod0-clk"; 390 reg = <0x01c2009c 0x4>; 391 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 392 clock-output-names = "ss"; 393 }; 394 395 spi0_clk: clk@01c200a0 { 396 #clock-cells = <0>; 397 compatible = "allwinner,sun4i-a10-mod0-clk"; 398 reg = <0x01c200a0 0x4>; 399 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 400 clock-output-names = "spi0"; 401 }; 402 403 spi1_clk: clk@01c200a4 { 404 #clock-cells = <0>; 405 compatible = "allwinner,sun4i-a10-mod0-clk"; 406 reg = <0x01c200a4 0x4>; 407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 408 clock-output-names = "spi1"; 409 }; 410 411 spi2_clk: clk@01c200a8 { 412 #clock-cells = <0>; 413 compatible = "allwinner,sun4i-a10-mod0-clk"; 414 reg = <0x01c200a8 0x4>; 415 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 416 clock-output-names = "spi2"; 417 }; 418 419 pata_clk: clk@01c200ac { 420 #clock-cells = <0>; 421 compatible = "allwinner,sun4i-a10-mod0-clk"; 422 reg = <0x01c200ac 0x4>; 423 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 424 clock-output-names = "pata"; 425 }; 426 427 ir0_clk: clk@01c200b0 { 428 #clock-cells = <0>; 429 compatible = "allwinner,sun4i-a10-mod0-clk"; 430 reg = <0x01c200b0 0x4>; 431 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 432 clock-output-names = "ir0"; 433 }; 434 435 ir1_clk: clk@01c200b4 { 436 #clock-cells = <0>; 437 compatible = "allwinner,sun4i-a10-mod0-clk"; 438 reg = <0x01c200b4 0x4>; 439 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 440 clock-output-names = "ir1"; 441 }; 442 443 usb_clk: clk@01c200cc { 444 #clock-cells = <1>; 445 #reset-cells = <1>; 446 compatible = "allwinner,sun4i-a10-usb-clk"; 447 reg = <0x01c200cc 0x4>; 448 clocks = <&pll6 1>; 449 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; 450 }; 451 452 spi3_clk: clk@01c200d4 { 453 #clock-cells = <0>; 454 compatible = "allwinner,sun4i-a10-mod0-clk"; 455 reg = <0x01c200d4 0x4>; 456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 457 clock-output-names = "spi3"; 458 }; 459 460 mbus_clk: clk@01c2015c { 461 #clock-cells = <0>; 462 compatible = "allwinner,sun5i-a13-mbus-clk"; 463 reg = <0x01c2015c 0x4>; 464 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 465 clock-output-names = "mbus"; 466 }; 467 468 /* 469 * The following two are dummy clocks, placeholders used in the gmac_tx 470 * clock. The gmac driver will choose one parent depending on the PHY 471 * interface mode, using clk_set_rate auto-reparenting. 472 * The actual TX clock rate is not controlled by the gmac_tx clock. 473 */ 474 mii_phy_tx_clk: clk@2 { 475 #clock-cells = <0>; 476 compatible = "fixed-clock"; 477 clock-frequency = <25000000>; 478 clock-output-names = "mii_phy_tx"; 479 }; 480 481 gmac_int_tx_clk: clk@3 { 482 #clock-cells = <0>; 483 compatible = "fixed-clock"; 484 clock-frequency = <125000000>; 485 clock-output-names = "gmac_int_tx"; 486 }; 487 488 gmac_tx_clk: clk@01c20164 { 489 #clock-cells = <0>; 490 compatible = "allwinner,sun7i-a20-gmac-clk"; 491 reg = <0x01c20164 0x4>; 492 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 493 clock-output-names = "gmac_tx"; 494 }; 495 496 /* 497 * Dummy clock used by output clocks 498 */ 499 osc24M_32k: clk@1 { 500 #clock-cells = <0>; 501 compatible = "fixed-factor-clock"; 502 clock-div = <750>; 503 clock-mult = <1>; 504 clocks = <&osc24M>; 505 clock-output-names = "osc24M_32k"; 506 }; 507 508 clk_out_a: clk@01c201f0 { 509 #clock-cells = <0>; 510 compatible = "allwinner,sun7i-a20-out-clk"; 511 reg = <0x01c201f0 0x4>; 512 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 513 clock-output-names = "clk_out_a"; 514 }; 515 516 clk_out_b: clk@01c201f4 { 517 #clock-cells = <0>; 518 compatible = "allwinner,sun7i-a20-out-clk"; 519 reg = <0x01c201f4 0x4>; 520 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 521 clock-output-names = "clk_out_b"; 522 }; 523 }; 524 525 soc@01c00000 { 526 compatible = "simple-bus"; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges; 530 531 nmi_intc: interrupt-controller@01c00030 { 532 compatible = "allwinner,sun7i-a20-sc-nmi"; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 reg = <0x01c00030 0x0c>; 536 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 dma: dma-controller@01c02000 { 540 compatible = "allwinner,sun4i-a10-dma"; 541 reg = <0x01c02000 0x1000>; 542 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&ahb_gates 6>; 544 #dma-cells = <2>; 545 }; 546 547 spi0: spi@01c05000 { 548 compatible = "allwinner,sun4i-a10-spi"; 549 reg = <0x01c05000 0x1000>; 550 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&ahb_gates 20>, <&spi0_clk>; 552 clock-names = "ahb", "mod"; 553 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 554 <&dma SUN4I_DMA_DEDICATED 26>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 }; 560 561 spi1: spi@01c06000 { 562 compatible = "allwinner,sun4i-a10-spi"; 563 reg = <0x01c06000 0x1000>; 564 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&ahb_gates 21>, <&spi1_clk>; 566 clock-names = "ahb", "mod"; 567 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 568 <&dma SUN4I_DMA_DEDICATED 8>; 569 dma-names = "rx", "tx"; 570 status = "disabled"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 }; 574 575 emac: ethernet@01c0b000 { 576 compatible = "allwinner,sun4i-a10-emac"; 577 reg = <0x01c0b000 0x1000>; 578 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ahb_gates 17>; 580 status = "disabled"; 581 }; 582 583 mdio: mdio@01c0b080 { 584 compatible = "allwinner,sun4i-a10-mdio"; 585 reg = <0x01c0b080 0x14>; 586 status = "disabled"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 }; 590 591 mmc0: mmc@01c0f000 { 592 compatible = "allwinner,sun5i-a13-mmc"; 593 reg = <0x01c0f000 0x1000>; 594 clocks = <&ahb_gates 8>, 595 <&mmc0_clk 0>, 596 <&mmc0_clk 1>, 597 <&mmc0_clk 2>; 598 clock-names = "ahb", 599 "mmc", 600 "output", 601 "sample"; 602 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 603 status = "disabled"; 604 }; 605 606 mmc1: mmc@01c10000 { 607 compatible = "allwinner,sun5i-a13-mmc"; 608 reg = <0x01c10000 0x1000>; 609 clocks = <&ahb_gates 9>, 610 <&mmc1_clk 0>, 611 <&mmc1_clk 1>, 612 <&mmc1_clk 2>; 613 clock-names = "ahb", 614 "mmc", 615 "output", 616 "sample"; 617 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 618 status = "disabled"; 619 }; 620 621 mmc2: mmc@01c11000 { 622 compatible = "allwinner,sun5i-a13-mmc"; 623 reg = <0x01c11000 0x1000>; 624 clocks = <&ahb_gates 10>, 625 <&mmc2_clk 0>, 626 <&mmc2_clk 1>, 627 <&mmc2_clk 2>; 628 clock-names = "ahb", 629 "mmc", 630 "output", 631 "sample"; 632 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 633 status = "disabled"; 634 }; 635 636 mmc3: mmc@01c12000 { 637 compatible = "allwinner,sun5i-a13-mmc"; 638 reg = <0x01c12000 0x1000>; 639 clocks = <&ahb_gates 11>, 640 <&mmc3_clk 0>, 641 <&mmc3_clk 1>, 642 <&mmc3_clk 2>; 643 clock-names = "ahb", 644 "mmc", 645 "output", 646 "sample"; 647 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 648 status = "disabled"; 649 }; 650 651 usbphy: phy@01c13400 { 652 #phy-cells = <1>; 653 compatible = "allwinner,sun7i-a20-usb-phy"; 654 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 655 reg-names = "phy_ctrl", "pmu1", "pmu2"; 656 clocks = <&usb_clk 8>; 657 clock-names = "usb_phy"; 658 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; 659 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 660 status = "disabled"; 661 }; 662 663 ehci0: usb@01c14000 { 664 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 665 reg = <0x01c14000 0x100>; 666 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&ahb_gates 1>; 668 phys = <&usbphy 1>; 669 phy-names = "usb"; 670 status = "disabled"; 671 }; 672 673 ohci0: usb@01c14400 { 674 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 675 reg = <0x01c14400 0x100>; 676 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&usb_clk 6>, <&ahb_gates 2>; 678 phys = <&usbphy 1>; 679 phy-names = "usb"; 680 status = "disabled"; 681 }; 682 683 spi2: spi@01c17000 { 684 compatible = "allwinner,sun4i-a10-spi"; 685 reg = <0x01c17000 0x1000>; 686 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&ahb_gates 22>, <&spi2_clk>; 688 clock-names = "ahb", "mod"; 689 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 690 <&dma SUN4I_DMA_DEDICATED 28>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 }; 696 697 ahci: sata@01c18000 { 698 compatible = "allwinner,sun4i-a10-ahci"; 699 reg = <0x01c18000 0x1000>; 700 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&pll6 0>, <&ahb_gates 25>; 702 status = "disabled"; 703 }; 704 705 ehci1: usb@01c1c000 { 706 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 707 reg = <0x01c1c000 0x100>; 708 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&ahb_gates 3>; 710 phys = <&usbphy 2>; 711 phy-names = "usb"; 712 status = "disabled"; 713 }; 714 715 ohci1: usb@01c1c400 { 716 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 717 reg = <0x01c1c400 0x100>; 718 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&usb_clk 7>, <&ahb_gates 4>; 720 phys = <&usbphy 2>; 721 phy-names = "usb"; 722 status = "disabled"; 723 }; 724 725 spi3: spi@01c1f000 { 726 compatible = "allwinner,sun4i-a10-spi"; 727 reg = <0x01c1f000 0x1000>; 728 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ahb_gates 23>, <&spi3_clk>; 730 clock-names = "ahb", "mod"; 731 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 732 <&dma SUN4I_DMA_DEDICATED 30>; 733 dma-names = "rx", "tx"; 734 status = "disabled"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 }; 738 739 pio: pinctrl@01c20800 { 740 compatible = "allwinner,sun7i-a20-pinctrl"; 741 reg = <0x01c20800 0x400>; 742 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&apb0_gates 5>; 744 gpio-controller; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 #size-cells = <0>; 748 #gpio-cells = <3>; 749 750 pwm0_pins_a: pwm0@0 { 751 allwinner,pins = "PB2"; 752 allwinner,function = "pwm"; 753 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 754 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 755 }; 756 757 pwm1_pins_a: pwm1@0 { 758 allwinner,pins = "PI3"; 759 allwinner,function = "pwm"; 760 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 761 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 762 }; 763 764 uart0_pins_a: uart0@0 { 765 allwinner,pins = "PB22", "PB23"; 766 allwinner,function = "uart0"; 767 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 768 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 769 }; 770 771 uart2_pins_a: uart2@0 { 772 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 773 allwinner,function = "uart2"; 774 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 775 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 776 }; 777 778 uart3_pins_a: uart3@0 { 779 allwinner,pins = "PG6", "PG7", "PG8", "PG9"; 780 allwinner,function = "uart3"; 781 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 782 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 783 }; 784 785 uart3_pins_b: uart3@1 { 786 allwinner,pins = "PH0", "PH1"; 787 allwinner,function = "uart3"; 788 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 789 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 790 }; 791 792 uart4_pins_a: uart4@0 { 793 allwinner,pins = "PG10", "PG11"; 794 allwinner,function = "uart4"; 795 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 796 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 797 }; 798 799 uart5_pins_a: uart5@0 { 800 allwinner,pins = "PI10", "PI11"; 801 allwinner,function = "uart5"; 802 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 803 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 804 }; 805 806 uart6_pins_a: uart6@0 { 807 allwinner,pins = "PI12", "PI13"; 808 allwinner,function = "uart6"; 809 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 810 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 811 }; 812 813 uart7_pins_a: uart7@0 { 814 allwinner,pins = "PI20", "PI21"; 815 allwinner,function = "uart7"; 816 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 817 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 818 }; 819 820 i2c0_pins_a: i2c0@0 { 821 allwinner,pins = "PB0", "PB1"; 822 allwinner,function = "i2c0"; 823 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 825 }; 826 827 i2c1_pins_a: i2c1@0 { 828 allwinner,pins = "PB18", "PB19"; 829 allwinner,function = "i2c1"; 830 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 832 }; 833 834 i2c2_pins_a: i2c2@0 { 835 allwinner,pins = "PB20", "PB21"; 836 allwinner,function = "i2c2"; 837 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 839 }; 840 841 i2c3_pins_a: i2c3@0 { 842 allwinner,pins = "PI0", "PI1"; 843 allwinner,function = "i2c3"; 844 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 845 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 846 }; 847 848 emac_pins_a: emac0@0 { 849 allwinner,pins = "PA0", "PA1", "PA2", 850 "PA3", "PA4", "PA5", "PA6", 851 "PA7", "PA8", "PA9", "PA10", 852 "PA11", "PA12", "PA13", "PA14", 853 "PA15", "PA16"; 854 allwinner,function = "emac"; 855 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 856 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 857 }; 858 859 clk_out_a_pins_a: clk_out_a@0 { 860 allwinner,pins = "PI12"; 861 allwinner,function = "clk_out_a"; 862 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 863 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 864 }; 865 866 clk_out_b_pins_a: clk_out_b@0 { 867 allwinner,pins = "PI13"; 868 allwinner,function = "clk_out_b"; 869 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 870 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 871 }; 872 873 gmac_pins_mii_a: gmac_mii@0 { 874 allwinner,pins = "PA0", "PA1", "PA2", 875 "PA3", "PA4", "PA5", "PA6", 876 "PA7", "PA8", "PA9", "PA10", 877 "PA11", "PA12", "PA13", "PA14", 878 "PA15", "PA16"; 879 allwinner,function = "gmac"; 880 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 881 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 882 }; 883 884 gmac_pins_rgmii_a: gmac_rgmii@0 { 885 allwinner,pins = "PA0", "PA1", "PA2", 886 "PA3", "PA4", "PA5", "PA6", 887 "PA7", "PA8", "PA10", 888 "PA11", "PA12", "PA13", 889 "PA15", "PA16"; 890 allwinner,function = "gmac"; 891 /* 892 * data lines in RGMII mode use DDR mode 893 * and need a higher signal drive strength 894 */ 895 allwinner,drive = <SUN4I_PINCTRL_40_MA>; 896 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 897 }; 898 899 spi0_pins_a: spi0@0 { 900 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; 901 allwinner,function = "spi0"; 902 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 903 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 904 }; 905 906 spi1_pins_a: spi1@0 { 907 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 908 allwinner,function = "spi1"; 909 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 910 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 911 }; 912 913 spi2_pins_a: spi2@0 { 914 allwinner,pins = "PC19", "PC20", "PC21", "PC22"; 915 allwinner,function = "spi2"; 916 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 917 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 918 }; 919 920 spi2_pins_b: spi2@1 { 921 allwinner,pins = "PB14", "PB15", "PB16", "PB17"; 922 allwinner,function = "spi2"; 923 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 924 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 925 }; 926 927 mmc0_pins_a: mmc0@0 { 928 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 929 allwinner,function = "mmc0"; 930 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 931 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 932 }; 933 934 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 935 allwinner,pins = "PH1"; 936 allwinner,function = "gpio_in"; 937 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 938 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 939 }; 940 941 mmc2_pins_a: mmc2@0 { 942 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; 943 allwinner,function = "mmc2"; 944 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 945 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 946 }; 947 948 mmc3_pins_a: mmc3@0 { 949 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 950 allwinner,function = "mmc3"; 951 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 952 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 953 }; 954 955 ir0_pins_a: ir0@0 { 956 allwinner,pins = "PB3","PB4"; 957 allwinner,function = "ir0"; 958 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 959 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 960 }; 961 962 ir1_pins_a: ir1@0 { 963 allwinner,pins = "PB22","PB23"; 964 allwinner,function = "ir1"; 965 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 966 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 967 }; 968 969 ps20_pins_a: ps20@0 { 970 allwinner,pins = "PI20", "PI21"; 971 allwinner,function = "ps2"; 972 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 973 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 974 }; 975 976 ps21_pins_a: ps21@0 { 977 allwinner,pins = "PH12", "PH13"; 978 allwinner,function = "ps2"; 979 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 980 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 981 }; 982 }; 983 984 timer@01c20c00 { 985 compatible = "allwinner,sun4i-a10-timer"; 986 reg = <0x01c20c00 0x90>; 987 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&osc24M>; 994 }; 995 996 wdt: watchdog@01c20c90 { 997 compatible = "allwinner,sun4i-a10-wdt"; 998 reg = <0x01c20c90 0x10>; 999 }; 1000 1001 rtc: rtc@01c20d00 { 1002 compatible = "allwinner,sun7i-a20-rtc"; 1003 reg = <0x01c20d00 0x20>; 1004 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1005 }; 1006 1007 pwm: pwm@01c20e00 { 1008 compatible = "allwinner,sun7i-a20-pwm"; 1009 reg = <0x01c20e00 0xc>; 1010 clocks = <&osc24M>; 1011 #pwm-cells = <3>; 1012 status = "disabled"; 1013 }; 1014 1015 ir0: ir@01c21800 { 1016 compatible = "allwinner,sun4i-a10-ir"; 1017 clocks = <&apb0_gates 6>, <&ir0_clk>; 1018 clock-names = "apb", "ir"; 1019 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1020 reg = <0x01c21800 0x40>; 1021 status = "disabled"; 1022 }; 1023 1024 ir1: ir@01c21c00 { 1025 compatible = "allwinner,sun4i-a10-ir"; 1026 clocks = <&apb0_gates 7>, <&ir1_clk>; 1027 clock-names = "apb", "ir"; 1028 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1029 reg = <0x01c21c00 0x40>; 1030 status = "disabled"; 1031 }; 1032 1033 lradc: lradc@01c22800 { 1034 compatible = "allwinner,sun4i-a10-lradc-keys"; 1035 reg = <0x01c22800 0x100>; 1036 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1037 status = "disabled"; 1038 }; 1039 1040 sid: eeprom@01c23800 { 1041 compatible = "allwinner,sun7i-a20-sid"; 1042 reg = <0x01c23800 0x200>; 1043 }; 1044 1045 rtp: rtp@01c25000 { 1046 compatible = "allwinner,sun4i-a10-ts"; 1047 reg = <0x01c25000 0x100>; 1048 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1049 #thermal-sensor-cells = <0>; 1050 }; 1051 1052 uart0: serial@01c28000 { 1053 compatible = "snps,dw-apb-uart"; 1054 reg = <0x01c28000 0x400>; 1055 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1056 reg-shift = <2>; 1057 reg-io-width = <4>; 1058 clocks = <&apb1_gates 16>; 1059 status = "disabled"; 1060 }; 1061 1062 uart1: serial@01c28400 { 1063 compatible = "snps,dw-apb-uart"; 1064 reg = <0x01c28400 0x400>; 1065 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1066 reg-shift = <2>; 1067 reg-io-width = <4>; 1068 clocks = <&apb1_gates 17>; 1069 status = "disabled"; 1070 }; 1071 1072 uart2: serial@01c28800 { 1073 compatible = "snps,dw-apb-uart"; 1074 reg = <0x01c28800 0x400>; 1075 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1076 reg-shift = <2>; 1077 reg-io-width = <4>; 1078 clocks = <&apb1_gates 18>; 1079 status = "disabled"; 1080 }; 1081 1082 uart3: serial@01c28c00 { 1083 compatible = "snps,dw-apb-uart"; 1084 reg = <0x01c28c00 0x400>; 1085 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1086 reg-shift = <2>; 1087 reg-io-width = <4>; 1088 clocks = <&apb1_gates 19>; 1089 status = "disabled"; 1090 }; 1091 1092 uart4: serial@01c29000 { 1093 compatible = "snps,dw-apb-uart"; 1094 reg = <0x01c29000 0x400>; 1095 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1096 reg-shift = <2>; 1097 reg-io-width = <4>; 1098 clocks = <&apb1_gates 20>; 1099 status = "disabled"; 1100 }; 1101 1102 uart5: serial@01c29400 { 1103 compatible = "snps,dw-apb-uart"; 1104 reg = <0x01c29400 0x400>; 1105 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1106 reg-shift = <2>; 1107 reg-io-width = <4>; 1108 clocks = <&apb1_gates 21>; 1109 status = "disabled"; 1110 }; 1111 1112 uart6: serial@01c29800 { 1113 compatible = "snps,dw-apb-uart"; 1114 reg = <0x01c29800 0x400>; 1115 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1116 reg-shift = <2>; 1117 reg-io-width = <4>; 1118 clocks = <&apb1_gates 22>; 1119 status = "disabled"; 1120 }; 1121 1122 uart7: serial@01c29c00 { 1123 compatible = "snps,dw-apb-uart"; 1124 reg = <0x01c29c00 0x400>; 1125 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1126 reg-shift = <2>; 1127 reg-io-width = <4>; 1128 clocks = <&apb1_gates 23>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c0: i2c@01c2ac00 { 1133 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1134 reg = <0x01c2ac00 0x400>; 1135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&apb1_gates 0>; 1137 status = "disabled"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 }; 1141 1142 i2c1: i2c@01c2b000 { 1143 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1144 reg = <0x01c2b000 0x400>; 1145 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&apb1_gates 1>; 1147 status = "disabled"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 }; 1151 1152 i2c2: i2c@01c2b400 { 1153 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1154 reg = <0x01c2b400 0x400>; 1155 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&apb1_gates 2>; 1157 status = "disabled"; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 }; 1161 1162 i2c3: i2c@01c2b800 { 1163 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1164 reg = <0x01c2b800 0x400>; 1165 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&apb1_gates 3>; 1167 status = "disabled"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 }; 1171 1172 i2c4: i2c@01c2c000 { 1173 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 1174 reg = <0x01c2c000 0x400>; 1175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&apb1_gates 15>; 1177 status = "disabled"; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 }; 1181 1182 gmac: ethernet@01c50000 { 1183 compatible = "allwinner,sun7i-a20-gmac"; 1184 reg = <0x01c50000 0x10000>; 1185 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1186 interrupt-names = "macirq"; 1187 clocks = <&ahb_gates 49>, <&gmac_tx_clk>; 1188 clock-names = "stmmaceth", "allwinner_gmac_tx"; 1189 snps,pbl = <2>; 1190 snps,fixed-burst; 1191 snps,force_sf_dma_mode; 1192 status = "disabled"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 }; 1196 1197 hstimer@01c60000 { 1198 compatible = "allwinner,sun7i-a20-hstimer"; 1199 reg = <0x01c60000 0x1000>; 1200 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&ahb_gates 28>; 1205 }; 1206 1207 gic: interrupt-controller@01c81000 { 1208 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1209 reg = <0x01c81000 0x1000>, 1210 <0x01c82000 0x1000>, 1211 <0x01c84000 0x2000>, 1212 <0x01c86000 0x2000>; 1213 interrupt-controller; 1214 #interrupt-cells = <3>; 1215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1216 }; 1217 1218 ps20: ps2@01c2a000 { 1219 compatible = "allwinner,sun4i-a10-ps2"; 1220 reg = <0x01c2a000 0x400>; 1221 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&apb1_gates 6>; 1223 status = "disabled"; 1224 }; 1225 1226 ps21: ps2@01c2a400 { 1227 compatible = "allwinner,sun4i-a10-ps2"; 1228 reg = <0x01c2a400 0x400>; 1229 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&apb1_gates 7>; 1231 status = "disabled"; 1232 }; 1233 }; 1234}; 1235