if_wb.c revision 113506
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 3341502Swpaul/* 3441502Swpaul * Winbond fast ethernet PCI NIC driver 3541502Swpaul * 3641502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3741502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 3841502Swpaul * Winbond itself and some made by Linksys. 3941502Swpaul * 4041502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4141502Swpaul * Electrical Engineering Department 4241502Swpaul * Columbia University, New York City 4341502Swpaul */ 4441502Swpaul 4541502Swpaul/* 4641502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4741502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 4841502Swpaul * one major difference which is that while the registers do many of 4941502Swpaul * the same things as a tulip adapter, the offsets are different: where 5041502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5141502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5241502Swpaul * programmed differently. 5341502Swpaul * 5441502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5541502Swpaul * a status word, a control word and 32-bit areas that can either be used 5641502Swpaul * to point to two external data blocks, or to point to a single block 5741502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 5841502Swpaul * together in blocks to form fixed length rings or can be chained 5941502Swpaul * together in linked lists. A single packet may be spread out over 6041502Swpaul * several descriptors if necessary. 6141502Swpaul * 6241502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6341502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6441502Swpaul * to hold an entire packet. The link list is looped back to created a 6541502Swpaul * closed ring. 6641502Swpaul * 6741502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 6841502Swpaul * which each contain several individual descriptors linked toghether. 6941502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7041502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7141502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7241502Swpaul * drivers. 7341502Swpaul * 7441502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7541502Swpaul * The sample boards I have all use a Davicom PHY. 7641502Swpaul * 7741502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 7841502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 7941502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8041502Swpaul * I have no idea what he's on about: transmit performance with all 8141502Swpaul * three of my test boards seems fine. 8241502Swpaul */ 8341502Swpaul 84113038Sobrien#include <sys/cdefs.h> 85113038Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 113506 2003-04-15 06:37:30Z mdodd $"); 86113038Sobrien 8748745Swpaul#include "opt_bdg.h" 8841502Swpaul 8941502Swpaul#include <sys/param.h> 9041502Swpaul#include <sys/systm.h> 9141502Swpaul#include <sys/sockio.h> 9241502Swpaul#include <sys/mbuf.h> 9341502Swpaul#include <sys/malloc.h> 9441502Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9650675Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 10141502Swpaul#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 10341502Swpaul 10441502Swpaul#include <net/bpf.h> 10541502Swpaul 10641502Swpaul#include <vm/vm.h> /* for vtophys */ 10741502Swpaul#include <vm/pmap.h> /* for vtophys */ 10841502Swpaul#include <machine/bus_memio.h> 10941502Swpaul#include <machine/bus_pio.h> 11041502Swpaul#include <machine/bus.h> 11149611Swpaul#include <machine/resource.h> 11249611Swpaul#include <sys/bus.h> 11349611Swpaul#include <sys/rman.h> 11441502Swpaul 11541502Swpaul#include <pci/pcireg.h> 11641502Swpaul#include <pci/pcivar.h> 11741502Swpaul 11850675Swpaul#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250675Swpaul#include "miibus_if.h" 12350675Swpaul 12441502Swpaul#define WB_USEIOSPACE 12541502Swpaul 12641502Swpaul#include <pci/if_wbreg.h> 12741502Swpaul 128113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 129113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 13059758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13159758Speter 13241502Swpaul/* 13341502Swpaul * Various supported device vendors/types and their names. 13441502Swpaul */ 13541502Swpaulstatic struct wb_type wb_devs[] = { 13641502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13741502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13841502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13941502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14041502Swpaul { 0, 0, NULL } 14141502Swpaul}; 14241502Swpaul 14392739Salfredstatic int wb_probe (device_t); 14492739Salfredstatic int wb_attach (device_t); 14592739Salfredstatic int wb_detach (device_t); 14641502Swpaul 14798995Salfredstatic void wb_bfree (void *addr, void *args); 14892739Salfredstatic int wb_newbuf (struct wb_softc *, 14948745Swpaul struct wb_chain_onefrag *, 15092739Salfred struct mbuf *); 15192739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15292739Salfred struct mbuf *); 15341502Swpaul 15492739Salfredstatic void wb_rxeof (struct wb_softc *); 15592739Salfredstatic void wb_rxeoc (struct wb_softc *); 15692739Salfredstatic void wb_txeof (struct wb_softc *); 15792739Salfredstatic void wb_txeoc (struct wb_softc *); 15892739Salfredstatic void wb_intr (void *); 15992739Salfredstatic void wb_tick (void *); 16092739Salfredstatic void wb_start (struct ifnet *); 16192739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16292739Salfredstatic void wb_init (void *); 16392739Salfredstatic void wb_stop (struct wb_softc *); 16492739Salfredstatic void wb_watchdog (struct ifnet *); 16592739Salfredstatic void wb_shutdown (device_t); 16692739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16792739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16841502Swpaul 16992739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 17092739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17192739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17292739Salfredstatic void wb_mii_sync (struct wb_softc *); 17392739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17492739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17592739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17641502Swpaul 17792739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 17892739Salfredstatic u_int8_t wb_calchash (caddr_t); 17992739Salfredstatic void wb_setmulti (struct wb_softc *); 18092739Salfredstatic void wb_reset (struct wb_softc *); 18192739Salfredstatic void wb_fixmedia (struct wb_softc *); 18292739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18392739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18441502Swpaul 18592739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18692739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18792739Salfredstatic void wb_miibus_statchg (device_t); 18850675Swpaul 18949611Swpaul#ifdef WB_USEIOSPACE 19049611Swpaul#define WB_RES SYS_RES_IOPORT 19149611Swpaul#define WB_RID WB_PCI_LOIO 19249611Swpaul#else 19349611Swpaul#define WB_RES SYS_RES_MEMORY 19449611Swpaul#define WB_RID WB_PCI_LOMEM 19549611Swpaul#endif 19649611Swpaul 19749611Swpaulstatic device_method_t wb_methods[] = { 19849611Swpaul /* Device interface */ 19949611Swpaul DEVMETHOD(device_probe, wb_probe), 20049611Swpaul DEVMETHOD(device_attach, wb_attach), 20149611Swpaul DEVMETHOD(device_detach, wb_detach), 20249611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20350675Swpaul 20450675Swpaul /* bus interface, for miibus */ 20550675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20650675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20750675Swpaul 20850675Swpaul /* MII interface */ 20950675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21050675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21150675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21249611Swpaul { 0, 0 } 21349611Swpaul}; 21449611Swpaul 21549611Swpaulstatic driver_t wb_driver = { 21651455Swpaul "wb", 21749611Swpaul wb_methods, 21849611Swpaul sizeof(struct wb_softc) 21949611Swpaul}; 22049611Swpaul 22149611Swpaulstatic devclass_t wb_devclass; 22249611Swpaul 223113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22451473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22549611Swpaul 22641502Swpaul#define WB_SETBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) | (x)) 22941502Swpaul 23041502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23141502Swpaul CSR_WRITE_4(sc, reg, \ 232105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23341502Swpaul 23441502Swpaul#define SIO_SET(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23741502Swpaul 23841502Swpaul#define SIO_CLR(x) \ 23941502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 240105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24141502Swpaul 24241502Swpaul/* 24341502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24441502Swpaul */ 245102336Salfredstatic void 246102336Salfredwb_eeprom_putbyte(sc, addr) 24741502Swpaul struct wb_softc *sc; 24842718Swpaul int addr; 24941502Swpaul{ 25041502Swpaul register int d, i; 25141502Swpaul 25241502Swpaul d = addr | WB_EECMD_READ; 25341502Swpaul 25441502Swpaul /* 25541502Swpaul * Feed in each bit and stobe the clock. 25641502Swpaul */ 25741502Swpaul for (i = 0x400; i; i >>= 1) { 25841502Swpaul if (d & i) { 25941502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26041502Swpaul } else { 26141502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26241502Swpaul } 26341502Swpaul DELAY(100); 26441502Swpaul SIO_SET(WB_SIO_EE_CLK); 26541502Swpaul DELAY(150); 26641502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26741502Swpaul DELAY(100); 26841502Swpaul } 26941502Swpaul 27041502Swpaul return; 27141502Swpaul} 27241502Swpaul 27341502Swpaul/* 27441502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27541502Swpaul */ 276102336Salfredstatic void 277102336Salfredwb_eeprom_getword(sc, addr, dest) 27841502Swpaul struct wb_softc *sc; 27942718Swpaul int addr; 28041502Swpaul u_int16_t *dest; 28141502Swpaul{ 28241502Swpaul register int i; 28341502Swpaul u_int16_t word = 0; 28441502Swpaul 28541502Swpaul /* Enter EEPROM access mode. */ 28641502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28741502Swpaul 28841502Swpaul /* 28941502Swpaul * Send address of word we want to read. 29041502Swpaul */ 29141502Swpaul wb_eeprom_putbyte(sc, addr); 29241502Swpaul 29341502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29441502Swpaul 29541502Swpaul /* 29641502Swpaul * Start reading bits from EEPROM. 29741502Swpaul */ 29841502Swpaul for (i = 0x8000; i; i >>= 1) { 29941502Swpaul SIO_SET(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30241502Swpaul word |= i; 30341502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30441502Swpaul DELAY(100); 30541502Swpaul } 30641502Swpaul 30741502Swpaul /* Turn off EEPROM access mode. */ 30841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30941502Swpaul 31041502Swpaul *dest = word; 31141502Swpaul 31241502Swpaul return; 31341502Swpaul} 31441502Swpaul 31541502Swpaul/* 31641502Swpaul * Read a sequence of words from the EEPROM. 31741502Swpaul */ 318102336Salfredstatic void 319102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 32041502Swpaul struct wb_softc *sc; 32141502Swpaul caddr_t dest; 32241502Swpaul int off; 32341502Swpaul int cnt; 32441502Swpaul int swap; 32541502Swpaul{ 32641502Swpaul int i; 32741502Swpaul u_int16_t word = 0, *ptr; 32841502Swpaul 32941502Swpaul for (i = 0; i < cnt; i++) { 33041502Swpaul wb_eeprom_getword(sc, off + i, &word); 33141502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33241502Swpaul if (swap) 33341502Swpaul *ptr = ntohs(word); 33441502Swpaul else 33541502Swpaul *ptr = word; 33641502Swpaul } 33741502Swpaul 33841502Swpaul return; 33941502Swpaul} 34041502Swpaul 34141502Swpaul/* 34241502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34341502Swpaul */ 344102336Salfredstatic void 345102336Salfredwb_mii_sync(sc) 34641502Swpaul struct wb_softc *sc; 34741502Swpaul{ 34841502Swpaul register int i; 34941502Swpaul 35041502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35141502Swpaul 35241502Swpaul for (i = 0; i < 32; i++) { 35341502Swpaul SIO_SET(WB_SIO_MII_CLK); 35441502Swpaul DELAY(1); 35541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul } 35841502Swpaul 35941502Swpaul return; 36041502Swpaul} 36141502Swpaul 36241502Swpaul/* 36341502Swpaul * Clock a series of bits through the MII. 36441502Swpaul */ 365102336Salfredstatic void 366102336Salfredwb_mii_send(sc, bits, cnt) 36741502Swpaul struct wb_softc *sc; 36841502Swpaul u_int32_t bits; 36941502Swpaul int cnt; 37041502Swpaul{ 37141502Swpaul int i; 37241502Swpaul 37341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37441502Swpaul 37541502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37641502Swpaul if (bits & i) { 37741502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37841502Swpaul } else { 37941502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 38041502Swpaul } 38141502Swpaul DELAY(1); 38241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38341502Swpaul DELAY(1); 38441502Swpaul SIO_SET(WB_SIO_MII_CLK); 38541502Swpaul } 38641502Swpaul} 38741502Swpaul 38841502Swpaul/* 38941502Swpaul * Read an PHY register through the MII. 39041502Swpaul */ 391102336Salfredstatic int 392102336Salfredwb_mii_readreg(sc, frame) 39341502Swpaul struct wb_softc *sc; 39441502Swpaul struct wb_mii_frame *frame; 39541502Swpaul 39641502Swpaul{ 39767087Swpaul int i, ack; 39841502Swpaul 39967087Swpaul WB_LOCK(sc); 40041502Swpaul 40141502Swpaul /* 40241502Swpaul * Set up frame for RX. 40341502Swpaul */ 40441502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40541502Swpaul frame->mii_opcode = WB_MII_READOP; 40641502Swpaul frame->mii_turnaround = 0; 40741502Swpaul frame->mii_data = 0; 40841502Swpaul 40941502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 41041502Swpaul 41141502Swpaul /* 41241502Swpaul * Turn on data xmit. 41341502Swpaul */ 41441502Swpaul SIO_SET(WB_SIO_MII_DIR); 41541502Swpaul 41641502Swpaul wb_mii_sync(sc); 41741502Swpaul 41841502Swpaul /* 41941502Swpaul * Send command/address info. 42041502Swpaul */ 42141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42541502Swpaul 42641502Swpaul /* Idle bit */ 42741502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42841502Swpaul DELAY(1); 42941502Swpaul SIO_SET(WB_SIO_MII_CLK); 43041502Swpaul DELAY(1); 43141502Swpaul 43241502Swpaul /* Turn off xmit. */ 43341502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43441502Swpaul /* Check for ack */ 43541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43641502Swpaul DELAY(1); 437109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43841502Swpaul SIO_SET(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44141502Swpaul DELAY(1); 44241502Swpaul SIO_SET(WB_SIO_MII_CLK); 44341502Swpaul DELAY(1); 44441502Swpaul 44541502Swpaul /* 44641502Swpaul * Now try reading data bits. If the ack failed, we still 44741502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44841502Swpaul */ 44941502Swpaul if (ack) { 45041502Swpaul for(i = 0; i < 16; i++) { 45141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45241502Swpaul DELAY(1); 45341502Swpaul SIO_SET(WB_SIO_MII_CLK); 45441502Swpaul DELAY(1); 45541502Swpaul } 45641502Swpaul goto fail; 45741502Swpaul } 45841502Swpaul 45941502Swpaul for (i = 0x8000; i; i >>= 1) { 46041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46141502Swpaul DELAY(1); 46241502Swpaul if (!ack) { 46341502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46441502Swpaul frame->mii_data |= i; 46541502Swpaul DELAY(1); 46641502Swpaul } 46741502Swpaul SIO_SET(WB_SIO_MII_CLK); 46841502Swpaul DELAY(1); 46941502Swpaul } 47041502Swpaul 47141502Swpaulfail: 47241502Swpaul 47341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47441502Swpaul DELAY(1); 47541502Swpaul SIO_SET(WB_SIO_MII_CLK); 47641502Swpaul DELAY(1); 47741502Swpaul 47867087Swpaul WB_UNLOCK(sc); 47941502Swpaul 48041502Swpaul if (ack) 48141502Swpaul return(1); 48241502Swpaul return(0); 48341502Swpaul} 48441502Swpaul 48541502Swpaul/* 48641502Swpaul * Write to a PHY register through the MII. 48741502Swpaul */ 488102336Salfredstatic int 489102336Salfredwb_mii_writereg(sc, frame) 49041502Swpaul struct wb_softc *sc; 49141502Swpaul struct wb_mii_frame *frame; 49241502Swpaul 49341502Swpaul{ 49467087Swpaul WB_LOCK(sc); 49541502Swpaul 49641502Swpaul /* 49741502Swpaul * Set up frame for TX. 49841502Swpaul */ 49941502Swpaul 50041502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50141502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50241502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50341502Swpaul 50441502Swpaul /* 50541502Swpaul * Turn on data output. 50641502Swpaul */ 50741502Swpaul SIO_SET(WB_SIO_MII_DIR); 50841502Swpaul 50941502Swpaul wb_mii_sync(sc); 51041502Swpaul 51141502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51341502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51541502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51641502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51741502Swpaul 51841502Swpaul /* Idle bit. */ 51941502Swpaul SIO_SET(WB_SIO_MII_CLK); 52041502Swpaul DELAY(1); 52141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52241502Swpaul DELAY(1); 52341502Swpaul 52441502Swpaul /* 52541502Swpaul * Turn off xmit. 52641502Swpaul */ 52741502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52841502Swpaul 52967087Swpaul WB_UNLOCK(sc); 53041502Swpaul 53141502Swpaul return(0); 53241502Swpaul} 53341502Swpaul 534102336Salfredstatic int 535102336Salfredwb_miibus_readreg(dev, phy, reg) 53650675Swpaul device_t dev; 53750675Swpaul int phy, reg; 53850675Swpaul{ 53941502Swpaul struct wb_softc *sc; 54041502Swpaul struct wb_mii_frame frame; 54141502Swpaul 54250675Swpaul sc = device_get_softc(dev); 54350675Swpaul 54441502Swpaul bzero((char *)&frame, sizeof(frame)); 54541502Swpaul 54650675Swpaul frame.mii_phyaddr = phy; 54741502Swpaul frame.mii_regaddr = reg; 54841502Swpaul wb_mii_readreg(sc, &frame); 54941502Swpaul 55041502Swpaul return(frame.mii_data); 55141502Swpaul} 55241502Swpaul 553102336Salfredstatic int 554102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55550675Swpaul device_t dev; 55650675Swpaul int phy, reg, data; 55750675Swpaul{ 55841502Swpaul struct wb_softc *sc; 55941502Swpaul struct wb_mii_frame frame; 56041502Swpaul 56150675Swpaul sc = device_get_softc(dev); 56250675Swpaul 56341502Swpaul bzero((char *)&frame, sizeof(frame)); 56441502Swpaul 56550675Swpaul frame.mii_phyaddr = phy; 56641502Swpaul frame.mii_regaddr = reg; 56741502Swpaul frame.mii_data = data; 56841502Swpaul 56941502Swpaul wb_mii_writereg(sc, &frame); 57041502Swpaul 57150675Swpaul return(0); 57250675Swpaul} 57350675Swpaul 574102336Salfredstatic void 575102336Salfredwb_miibus_statchg(dev) 57650675Swpaul device_t dev; 57750675Swpaul{ 57850675Swpaul struct wb_softc *sc; 57950675Swpaul struct mii_data *mii; 58050675Swpaul 58150675Swpaul sc = device_get_softc(dev); 58267087Swpaul WB_LOCK(sc); 58350675Swpaul mii = device_get_softc(sc->wb_miibus); 58450675Swpaul wb_setcfg(sc, mii->mii_media_active); 58567087Swpaul WB_UNLOCK(sc); 58650675Swpaul 58741502Swpaul return; 58841502Swpaul} 58941502Swpaul 59041502Swpaulstatic u_int8_t wb_calchash(addr) 59142718Swpaul caddr_t addr; 59241502Swpaul{ 59341502Swpaul u_int32_t crc, carry; 59441502Swpaul int i, j; 59541502Swpaul u_int8_t c; 59641502Swpaul 59741502Swpaul /* Compute CRC for the address value. */ 59841502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59941502Swpaul 60041502Swpaul for (i = 0; i < 6; i++) { 60141502Swpaul c = *(addr + i); 60241502Swpaul for (j = 0; j < 8; j++) { 60341502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 60441502Swpaul crc <<= 1; 60541502Swpaul c >>= 1; 60641502Swpaul if (carry) 60741502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60841502Swpaul } 60941502Swpaul } 61041502Swpaul 61141502Swpaul /* 61241502Swpaul * return the filter bit position 61341502Swpaul * Note: I arrived at the following nonsense 61441502Swpaul * through experimentation. It's not the usual way to 61541502Swpaul * generate the bit position but it's the only thing 61641502Swpaul * I could come up with that works. 61741502Swpaul */ 61841502Swpaul return(~(crc >> 26) & 0x0000003F); 61941502Swpaul} 62041502Swpaul 62141502Swpaul/* 62241502Swpaul * Program the 64-bit multicast hash filter. 62341502Swpaul */ 624102336Salfredstatic void 625102336Salfredwb_setmulti(sc) 62641502Swpaul struct wb_softc *sc; 62741502Swpaul{ 62841502Swpaul struct ifnet *ifp; 62941502Swpaul int h = 0; 63041502Swpaul u_int32_t hashes[2] = { 0, 0 }; 63141502Swpaul struct ifmultiaddr *ifma; 63241502Swpaul u_int32_t rxfilt; 63341502Swpaul int mcnt = 0; 63441502Swpaul 63541502Swpaul ifp = &sc->arpcom.ac_if; 63641502Swpaul 63741502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63841502Swpaul 63941502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 64041502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 64141502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64241502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64341502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64441502Swpaul return; 64541502Swpaul } 64641502Swpaul 64741502Swpaul /* first, zot all the existing hash bits */ 64841502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64941502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 65041502Swpaul 65141502Swpaul /* now program new ones */ 65272084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65341502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65441502Swpaul continue; 65541502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65641502Swpaul if (h < 32) 65741502Swpaul hashes[0] |= (1 << h); 65841502Swpaul else 65941502Swpaul hashes[1] |= (1 << (h - 32)); 66041502Swpaul mcnt++; 66141502Swpaul } 66241502Swpaul 66341502Swpaul if (mcnt) 66441502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66541502Swpaul else 66641502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66741502Swpaul 66841502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66941502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 67041502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 67141502Swpaul 67241502Swpaul return; 67341502Swpaul} 67441502Swpaul 67541502Swpaul/* 67641502Swpaul * The Winbond manual states that in order to fiddle with the 67741502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67841502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67941502Swpaul */ 680102336Salfredstatic void 681102336Salfredwb_setcfg(sc, media) 68241502Swpaul struct wb_softc *sc; 68350675Swpaul u_int32_t media; 68441502Swpaul{ 68541502Swpaul int i, restart = 0; 68641502Swpaul 68741502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68841502Swpaul restart = 1; 68941502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 69041502Swpaul 69141502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69241502Swpaul DELAY(10); 69341502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69441502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69541502Swpaul break; 69641502Swpaul } 69741502Swpaul 69841502Swpaul if (i == WB_TIMEOUT) 69941502Swpaul printf("wb%d: failed to force tx and " 70041502Swpaul "rx to idle state\n", sc->wb_unit); 70141502Swpaul } 70241502Swpaul 70350675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70450675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70550675Swpaul else 70641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70741502Swpaul 70850675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71041502Swpaul else 71141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71241502Swpaul 71341502Swpaul if (restart) 71441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71541502Swpaul 71641502Swpaul return; 71741502Swpaul} 71841502Swpaul 719102336Salfredstatic void 720102336Salfredwb_reset(sc) 72141502Swpaul struct wb_softc *sc; 72241502Swpaul{ 72341502Swpaul register int i; 72450675Swpaul struct mii_data *mii; 72541502Swpaul 72650675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72850675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72950675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 73050675Swpaul 73141502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73341502Swpaul 73441502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73541502Swpaul DELAY(10); 73641502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73741502Swpaul break; 73841502Swpaul } 73941502Swpaul if (i == WB_TIMEOUT) 74041502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 74141502Swpaul 74241502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74341502Swpaul DELAY(1000); 74441502Swpaul 74550675Swpaul if (sc->wb_miibus == NULL) 74650675Swpaul return; 74741502Swpaul 74850675Swpaul mii = device_get_softc(sc->wb_miibus); 74950675Swpaul if (mii == NULL) 75050675Swpaul return; 75150675Swpaul 75250675Swpaul if (mii->mii_instance) { 75350675Swpaul struct mii_softc *miisc; 75472012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75550675Swpaul mii_phy_reset(miisc); 75650675Swpaul } 75750675Swpaul 75841502Swpaul return; 75941502Swpaul} 76041502Swpaul 761102336Salfredstatic void 762102336Salfredwb_fixmedia(sc) 76350675Swpaul struct wb_softc *sc; 76450675Swpaul{ 76550675Swpaul struct mii_data *mii = NULL; 76650675Swpaul struct ifnet *ifp; 76750675Swpaul u_int32_t media; 76850675Swpaul 76950675Swpaul if (sc->wb_miibus == NULL) 77050675Swpaul return; 77150675Swpaul 77250675Swpaul mii = device_get_softc(sc->wb_miibus); 77350675Swpaul ifp = &sc->arpcom.ac_if; 77450675Swpaul 77550675Swpaul mii_pollstat(mii); 77650675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77750675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77850675Swpaul media |= IFM_100_TX; 77950675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 78050675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 78150675Swpaul media |= IFM_10_T; 78250675Swpaul } else 78350675Swpaul return; 78450675Swpaul 78550675Swpaul ifmedia_set(&mii->mii_media, media); 78650675Swpaul 78750675Swpaul return; 78850675Swpaul} 78950675Swpaul 79041502Swpaul/* 79141502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79241502Swpaul * IDs against our list and return a device name if we find a match. 79341502Swpaul */ 794102336Salfredstatic int 795102336Salfredwb_probe(dev) 79649611Swpaul device_t dev; 79741502Swpaul{ 79841502Swpaul struct wb_type *t; 79941502Swpaul 80041502Swpaul t = wb_devs; 80141502Swpaul 80241502Swpaul while(t->wb_name != NULL) { 80349611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80449611Swpaul (pci_get_device(dev) == t->wb_did)) { 80549611Swpaul device_set_desc(dev, t->wb_name); 80649611Swpaul return(0); 80741502Swpaul } 80841502Swpaul t++; 80941502Swpaul } 81041502Swpaul 81149611Swpaul return(ENXIO); 81241502Swpaul} 81341502Swpaul 81441502Swpaul/* 81541502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81641502Swpaul * setup and ethernet/BPF attach. 81741502Swpaul */ 818102336Salfredstatic int 819102336Salfredwb_attach(dev) 82049611Swpaul device_t dev; 82141502Swpaul{ 82241502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82341502Swpaul u_int32_t command; 82441502Swpaul struct wb_softc *sc; 82541502Swpaul struct ifnet *ifp; 82649611Swpaul int unit, error = 0, rid; 82741502Swpaul 82849611Swpaul sc = device_get_softc(dev); 82949611Swpaul unit = device_get_unit(dev); 83041502Swpaul 83193818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83293818Sjhb MTX_DEF | MTX_RECURSE); 83369583Swpaul 83441502Swpaul /* 83541502Swpaul * Handle power management nonsense. 83641502Swpaul */ 83741502Swpaul 83872813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83972813Swpaul u_int32_t iobase, membase, irq; 84041502Swpaul 84172813Swpaul /* Save important PCI config data. */ 84272813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84372813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84472813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84541502Swpaul 84672813Swpaul /* Reset the power state. */ 84772813Swpaul printf("wb%d: chip is in D%d power mode " 84872813Swpaul "-- setting to D0\n", unit, 84972813Swpaul pci_get_powerstate(dev)); 85072813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 85141502Swpaul 85272813Swpaul /* Restore PCI config data. */ 85372813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85472813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85572813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85641502Swpaul } 85741502Swpaul 85841502Swpaul /* 85941502Swpaul * Map control/status registers. 86041502Swpaul */ 86172813Swpaul pci_enable_busmaster(dev); 86279472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 86379472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 86461041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 86541502Swpaul 86641502Swpaul#ifdef WB_USEIOSPACE 86741502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 86841502Swpaul printf("wb%d: failed to enable I/O ports!\n", unit); 86949611Swpaul error = ENXIO; 87041502Swpaul goto fail; 87141502Swpaul } 87241502Swpaul#else 87341502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 87441502Swpaul printf("wb%d: failed to enable memory mapping!\n", unit); 87549611Swpaul error = ENXIO; 87641502Swpaul goto fail; 87741502Swpaul } 87849611Swpaul#endif 87941502Swpaul 88049611Swpaul rid = WB_RID; 88149611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 88249611Swpaul 0, ~0, 1, RF_ACTIVE); 88349611Swpaul 88449611Swpaul if (sc->wb_res == NULL) { 88549611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 88649611Swpaul error = ENXIO; 88741502Swpaul goto fail; 88841502Swpaul } 88941502Swpaul 89049611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 89149611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 89249611Swpaul 89341502Swpaul /* Allocate interrupt */ 89449611Swpaul rid = 0; 89549611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 89649611Swpaul RF_SHAREABLE | RF_ACTIVE); 89749611Swpaul 89849611Swpaul if (sc->wb_irq == NULL) { 89941502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 90049611Swpaul error = ENXIO; 90141502Swpaul goto fail; 90241502Swpaul } 90341502Swpaul 90450675Swpaul /* Save the cache line size. */ 90550675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 90650675Swpaul 90741502Swpaul /* Reset the adapter. */ 90841502Swpaul wb_reset(sc); 90941502Swpaul 91041502Swpaul /* 91141502Swpaul * Get station address from the EEPROM. 91241502Swpaul */ 91341502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 91441502Swpaul 91541502Swpaul /* 91641502Swpaul * A Winbond chip was detected. Inform the world. 91741502Swpaul */ 91841502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 91941502Swpaul 92041502Swpaul sc->wb_unit = unit; 92141502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 92241502Swpaul 92350675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 92451657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 92550675Swpaul 92650675Swpaul if (sc->wb_ldata == NULL) { 92741502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 92849611Swpaul error = ENXIO; 92949611Swpaul goto fail; 93041502Swpaul } 93141502Swpaul 93241502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 93341502Swpaul 93441502Swpaul ifp = &sc->arpcom.ac_if; 93541502Swpaul ifp->if_softc = sc; 93641502Swpaul ifp->if_unit = unit; 93741502Swpaul ifp->if_name = "wb"; 93841502Swpaul ifp->if_mtu = ETHERMTU; 93941502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 94041502Swpaul ifp->if_ioctl = wb_ioctl; 94141502Swpaul ifp->if_output = ether_output; 94241502Swpaul ifp->if_start = wb_start; 94341502Swpaul ifp->if_watchdog = wb_watchdog; 94441502Swpaul ifp->if_init = wb_init; 94541502Swpaul ifp->if_baudrate = 10000000; 94643515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 94741502Swpaul 94850675Swpaul /* 94950675Swpaul * Do MII setup. 95050675Swpaul */ 95150675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 95250675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 95349611Swpaul error = ENXIO; 95441502Swpaul goto fail; 95541502Swpaul } 95641502Swpaul 95741502Swpaul /* 95863090Sarchie * Call MI attach routine. 95941502Swpaul */ 960106936Ssam ether_ifattach(ifp, eaddr); 96141502Swpaul 962112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 963112872Snjl wb_intr, sc, &sc->wb_intrhand); 964112872Snjl 965112872Snjl if (error) { 966112872Snjl printf("wb%d: couldn't set up irq\n", unit); 967112872Snjl goto fail; 968112872Snjl } 969112872Snjl 97041502Swpaulfail: 97150675Swpaul if (error) 972112872Snjl wb_detach(dev); 97350675Swpaul 97449611Swpaul return(error); 97541502Swpaul} 97641502Swpaul 977102336Salfredstatic int 978102336Salfredwb_detach(dev) 97949611Swpaul device_t dev; 98049611Swpaul{ 98149611Swpaul struct wb_softc *sc; 98249611Swpaul struct ifnet *ifp; 98349611Swpaul 98449611Swpaul sc = device_get_softc(dev); 985112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 98667087Swpaul WB_LOCK(sc); 98749611Swpaul ifp = &sc->arpcom.ac_if; 98849611Swpaul 98950675Swpaul /* Delete any miibus and phy devices attached to this interface */ 990112872Snjl if (device_is_alive(dev)) { 991112872Snjl if (bus_child_present(dev)) 992112872Snjl wb_stop(sc); 993112872Snjl ether_ifdetach(ifp); 994112872Snjl device_delete_child(dev, sc->wb_miibus); 995112872Snjl bus_generic_detach(dev); 996112872Snjl } 99750675Swpaul 998112872Snjl if (sc->wb_intrhand) 999112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1000112872Snjl if (sc->wb_irq) 1001112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1002112872Snjl if (sc->wb_res) 1003112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 100449611Swpaul 1005112872Snjl if (sc->wb_ldata) { 1006112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1007112872Snjl M_DEVBUF); 1008112872Snjl } 100949611Swpaul 101067087Swpaul WB_UNLOCK(sc); 101167087Swpaul mtx_destroy(&sc->wb_mtx); 101249611Swpaul 101349611Swpaul return(0); 101449611Swpaul} 101549611Swpaul 101641502Swpaul/* 101741502Swpaul * Initialize the transmit descriptors. 101841502Swpaul */ 1019102336Salfredstatic int 1020102336Salfredwb_list_tx_init(sc) 102141502Swpaul struct wb_softc *sc; 102241502Swpaul{ 102341502Swpaul struct wb_chain_data *cd; 102441502Swpaul struct wb_list_data *ld; 102541502Swpaul int i; 102641502Swpaul 102741502Swpaul cd = &sc->wb_cdata; 102841502Swpaul ld = sc->wb_ldata; 102941502Swpaul 103041502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 103141502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 103241502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 103341502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103441502Swpaul &cd->wb_tx_chain[0]; 103541502Swpaul } else { 103641502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103741502Swpaul &cd->wb_tx_chain[i + 1]; 103841502Swpaul } 103941502Swpaul } 104041502Swpaul 104141502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 104241502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 104341502Swpaul 104441502Swpaul return(0); 104541502Swpaul} 104641502Swpaul 104741502Swpaul 104841502Swpaul/* 104941502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 105041502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 105141502Swpaul * points back to the first. 105241502Swpaul */ 1053102336Salfredstatic int 1054102336Salfredwb_list_rx_init(sc) 105541502Swpaul struct wb_softc *sc; 105641502Swpaul{ 105741502Swpaul struct wb_chain_data *cd; 105841502Swpaul struct wb_list_data *ld; 105941502Swpaul int i; 106041502Swpaul 106141502Swpaul cd = &sc->wb_cdata; 106241502Swpaul ld = sc->wb_ldata; 106341502Swpaul 106441502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 106541502Swpaul cd->wb_rx_chain[i].wb_ptr = 106641502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 106750675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106848745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106941502Swpaul return(ENOBUFS); 107041502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 107141502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 107241502Swpaul ld->wb_rx_list[i].wb_next = 107341502Swpaul vtophys(&ld->wb_rx_list[0]); 107441502Swpaul } else { 107541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 107641502Swpaul &cd->wb_rx_chain[i + 1]; 107741502Swpaul ld->wb_rx_list[i].wb_next = 107841502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107941502Swpaul } 108041502Swpaul } 108141502Swpaul 108241502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 108341502Swpaul 108441502Swpaul return(0); 108541502Swpaul} 108641502Swpaul 1087102336Salfredstatic void 1088102336Salfredwb_bfree(buf, args) 108998995Salfred void *buf; 109064837Sdwmalone void *args; 109150675Swpaul{ 109250675Swpaul return; 109350675Swpaul} 109450675Swpaul 109541502Swpaul/* 109641502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 109741502Swpaul */ 1098102336Salfredstatic int 1099102336Salfredwb_newbuf(sc, c, m) 110041502Swpaul struct wb_softc *sc; 110141502Swpaul struct wb_chain_onefrag *c; 110248745Swpaul struct mbuf *m; 110341502Swpaul{ 110441502Swpaul struct mbuf *m_new = NULL; 110541502Swpaul 110648745Swpaul if (m == NULL) { 1107111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110887846Sluigi if (m_new == NULL) 110948745Swpaul return(ENOBUFS); 111064837Sdwmalone m_new->m_data = c->wb_buf; 111164837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 111268621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 111368621Sbmilekic EXT_NET_DRV); 111448745Swpaul } else { 111548745Swpaul m_new = m; 111650675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 111748745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111841502Swpaul } 111941502Swpaul 112048745Swpaul m_adj(m_new, sizeof(u_int64_t)); 112148745Swpaul 112241502Swpaul c->wb_mbuf = m_new; 112341502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 112450675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 112541502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 112641502Swpaul 112741502Swpaul return(0); 112841502Swpaul} 112941502Swpaul 113041502Swpaul/* 113141502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 113241502Swpaul * the higher level protocols. 113341502Swpaul */ 1134102336Salfredstatic void 1135102336Salfredwb_rxeof(sc) 113641502Swpaul struct wb_softc *sc; 113741502Swpaul{ 113850675Swpaul struct mbuf *m = NULL; 113941502Swpaul struct ifnet *ifp; 114041502Swpaul struct wb_chain_onefrag *cur_rx; 114141502Swpaul int total_len = 0; 114241502Swpaul u_int32_t rxstat; 114341502Swpaul 114441502Swpaul ifp = &sc->arpcom.ac_if; 114541502Swpaul 114641502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114741502Swpaul WB_RXSTAT_OWN)) { 114848745Swpaul struct mbuf *m0 = NULL; 114948745Swpaul 115041502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 115141502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 115250675Swpaul 115348745Swpaul m = cur_rx->wb_mbuf; 115441502Swpaul 115550675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 115650675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115750675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115850675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115950675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 116041502Swpaul ifp->if_ierrors++; 116150675Swpaul wb_newbuf(sc, cur_rx, m); 116241502Swpaul printf("wb%x: receiver babbling: possible chip " 116341502Swpaul "bug, forcing reset\n", sc->wb_unit); 116450675Swpaul wb_fixmedia(sc); 116550675Swpaul wb_reset(sc); 116650675Swpaul wb_init(sc); 116741502Swpaul return; 116841502Swpaul } 116941502Swpaul 117042718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 117142718Swpaul ifp->if_ierrors++; 117248745Swpaul wb_newbuf(sc, cur_rx, m); 117350675Swpaul break; 117442718Swpaul } 117542718Swpaul 117641502Swpaul /* No errors; receive the packet. */ 117741502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117841502Swpaul 117941502Swpaul /* 118041934Swpaul * XXX The Winbond chip includes the CRC with every 118141934Swpaul * received frame, and there's no way to turn this 118241934Swpaul * behavior off (at least, I can't find anything in 118341934Swpaul * the manual that explains how to do it) so we have 118441934Swpaul * to trim off the CRC manually. 118541934Swpaul */ 118641934Swpaul total_len -= ETHER_CRC_LEN; 118741934Swpaul 118878508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 118978508Sbmilekic NULL); 119048745Swpaul wb_newbuf(sc, cur_rx, m); 119148745Swpaul if (m0 == NULL) { 119248745Swpaul ifp->if_ierrors++; 119350675Swpaul break; 119441502Swpaul } 119548745Swpaul m = m0; 119641502Swpaul 119741502Swpaul ifp->if_ipackets++; 1198106936Ssam (*ifp->if_input)(ifp, m); 119941502Swpaul } 120041502Swpaul} 120141502Swpaul 1202105221Sphkstatic void 1203102336Salfredwb_rxeoc(sc) 120441502Swpaul struct wb_softc *sc; 120541502Swpaul{ 120641502Swpaul wb_rxeof(sc); 120741502Swpaul 120841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120941502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 121041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 121141502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 121241502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 121341502Swpaul 121441502Swpaul return; 121541502Swpaul} 121641502Swpaul 121741502Swpaul/* 121841502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121941502Swpaul * the list buffers. 122041502Swpaul */ 1221102336Salfredstatic void 1222102336Salfredwb_txeof(sc) 122341502Swpaul struct wb_softc *sc; 122441502Swpaul{ 122541502Swpaul struct wb_chain *cur_tx; 122641502Swpaul struct ifnet *ifp; 122741502Swpaul 122841502Swpaul ifp = &sc->arpcom.ac_if; 122941502Swpaul 123041502Swpaul /* Clear the timeout timer. */ 123141502Swpaul ifp->if_timer = 0; 123241502Swpaul 123341502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 123441502Swpaul return; 123541502Swpaul 123641502Swpaul /* 123741502Swpaul * Go through our tx list and free mbufs for those 123841502Swpaul * frames that have been transmitted. 123941502Swpaul */ 124041502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 124141502Swpaul u_int32_t txstat; 124241502Swpaul 124341502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 124441502Swpaul txstat = WB_TXSTATUS(cur_tx); 124541502Swpaul 124641502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124741502Swpaul break; 124841502Swpaul 124941502Swpaul if (txstat & WB_TXSTAT_TXERR) { 125041502Swpaul ifp->if_oerrors++; 125141502Swpaul if (txstat & WB_TXSTAT_ABORT) 125241502Swpaul ifp->if_collisions++; 125341502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 125441502Swpaul ifp->if_collisions++; 125541502Swpaul } 125641502Swpaul 125741502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125841502Swpaul 125941502Swpaul ifp->if_opackets++; 126041502Swpaul m_freem(cur_tx->wb_mbuf); 126141502Swpaul cur_tx->wb_mbuf = NULL; 126241502Swpaul 126341502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 126441502Swpaul sc->wb_cdata.wb_tx_head = NULL; 126541502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126641502Swpaul break; 126741502Swpaul } 126841502Swpaul 126941502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 127041502Swpaul } 127141502Swpaul 127241502Swpaul return; 127341502Swpaul} 127441502Swpaul 127541502Swpaul/* 127641502Swpaul * TX 'end of channel' interrupt handler. 127741502Swpaul */ 1278102336Salfredstatic void 1279102336Salfredwb_txeoc(sc) 128041502Swpaul struct wb_softc *sc; 128141502Swpaul{ 128241502Swpaul struct ifnet *ifp; 128341502Swpaul 128441502Swpaul ifp = &sc->arpcom.ac_if; 128541502Swpaul 128641502Swpaul ifp->if_timer = 0; 128741502Swpaul 128841502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128941502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 129041502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 129141502Swpaul } else { 129241502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 129341502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 129441502Swpaul ifp->if_timer = 5; 129541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129641502Swpaul } 129741502Swpaul } 129841502Swpaul 129941502Swpaul return; 130041502Swpaul} 130141502Swpaul 1302102336Salfredstatic void 1303102336Salfredwb_intr(arg) 130441502Swpaul void *arg; 130541502Swpaul{ 130641502Swpaul struct wb_softc *sc; 130741502Swpaul struct ifnet *ifp; 130841502Swpaul u_int32_t status; 130941502Swpaul 131041502Swpaul sc = arg; 131167087Swpaul WB_LOCK(sc); 131241502Swpaul ifp = &sc->arpcom.ac_if; 131341502Swpaul 131467087Swpaul if (!(ifp->if_flags & IFF_UP)) { 131567087Swpaul WB_UNLOCK(sc); 131641502Swpaul return; 131767087Swpaul } 131841502Swpaul 131941502Swpaul /* Disable interrupts. */ 132041502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 132141502Swpaul 132241502Swpaul for (;;) { 132341502Swpaul 132441502Swpaul status = CSR_READ_4(sc, WB_ISR); 132541502Swpaul if (status) 132641502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 132741502Swpaul 132841502Swpaul if ((status & WB_INTRS) == 0) 132941502Swpaul break; 133041502Swpaul 133141502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 133241502Swpaul ifp->if_ierrors++; 133341502Swpaul wb_reset(sc); 133450675Swpaul if (status & WB_ISR_RX_ERR) 133550675Swpaul wb_fixmedia(sc); 133641502Swpaul wb_init(sc); 133750675Swpaul continue; 133841502Swpaul } 133941502Swpaul 134050675Swpaul if (status & WB_ISR_RX_OK) 134150675Swpaul wb_rxeof(sc); 134250675Swpaul 134350675Swpaul if (status & WB_ISR_RX_IDLE) 134450675Swpaul wb_rxeoc(sc); 134550675Swpaul 134641502Swpaul if (status & WB_ISR_TX_OK) 134741502Swpaul wb_txeof(sc); 134841502Swpaul 134941502Swpaul if (status & WB_ISR_TX_NOBUF) 135041502Swpaul wb_txeoc(sc); 135141502Swpaul 135241502Swpaul if (status & WB_ISR_TX_IDLE) { 135341502Swpaul wb_txeof(sc); 135441502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 135541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135641502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 135741502Swpaul } 135841502Swpaul } 135941502Swpaul 136041502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 136141502Swpaul ifp->if_oerrors++; 136241502Swpaul wb_txeof(sc); 136341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136441502Swpaul /* Jack up TX threshold */ 136541502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 136641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 136741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136941502Swpaul } 137041502Swpaul 137141502Swpaul if (status & WB_ISR_BUS_ERR) { 137241502Swpaul wb_reset(sc); 137341502Swpaul wb_init(sc); 137441502Swpaul } 137541502Swpaul 137641502Swpaul } 137741502Swpaul 137841502Swpaul /* Re-enable interrupts. */ 137941502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 138041502Swpaul 138141502Swpaul if (ifp->if_snd.ifq_head != NULL) { 138241502Swpaul wb_start(ifp); 138341502Swpaul } 138441502Swpaul 138567087Swpaul WB_UNLOCK(sc); 138667087Swpaul 138741502Swpaul return; 138841502Swpaul} 138941502Swpaul 1390102336Salfredstatic void 1391102336Salfredwb_tick(xsc) 139250675Swpaul void *xsc; 139350675Swpaul{ 139450675Swpaul struct wb_softc *sc; 139550675Swpaul struct mii_data *mii; 139650675Swpaul 139750675Swpaul sc = xsc; 139867087Swpaul WB_LOCK(sc); 139950675Swpaul mii = device_get_softc(sc->wb_miibus); 140050675Swpaul 140150675Swpaul mii_tick(mii); 140250675Swpaul 140350675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 140450675Swpaul 140567087Swpaul WB_UNLOCK(sc); 140650685Swpaul 140750675Swpaul return; 140850675Swpaul} 140950675Swpaul 141041502Swpaul/* 141141502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 141241502Swpaul * pointers to the fragment pointers. 141341502Swpaul */ 1414102336Salfredstatic int 1415102336Salfredwb_encap(sc, c, m_head) 141641502Swpaul struct wb_softc *sc; 141741502Swpaul struct wb_chain *c; 141841502Swpaul struct mbuf *m_head; 141941502Swpaul{ 142041502Swpaul int frag = 0; 142141502Swpaul struct wb_desc *f = NULL; 142241502Swpaul int total_len; 142341502Swpaul struct mbuf *m; 142441502Swpaul 142541502Swpaul /* 142641502Swpaul * Start packing the mbufs in this chain into 142741502Swpaul * the fragment pointers. Stop when we run out 142841502Swpaul * of fragments or hit the end of the mbuf chain. 142941502Swpaul */ 143041502Swpaul m = m_head; 143141502Swpaul total_len = 0; 143241502Swpaul 143341502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 143441502Swpaul if (m->m_len != 0) { 143541502Swpaul if (frag == WB_MAXFRAGS) 143641502Swpaul break; 143741502Swpaul total_len += m->m_len; 143841502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143941502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 144041502Swpaul if (frag == 0) { 144141502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 144241502Swpaul f->wb_status = 0; 144341502Swpaul } else 144441502Swpaul f->wb_status = WB_TXSTAT_OWN; 144541502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 144641502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 144741502Swpaul frag++; 144841502Swpaul } 144941502Swpaul } 145041502Swpaul 145141502Swpaul /* 145241502Swpaul * Handle special case: we used up all 16 fragments, 145341502Swpaul * but we have more mbufs left in the chain. Copy the 145441502Swpaul * data into an mbuf cluster. Note that we don't 145541502Swpaul * bother clearing the values in the other fragment 145641502Swpaul * pointers/counters; it wouldn't gain us anything, 145741502Swpaul * and would waste cycles. 145841502Swpaul */ 145941502Swpaul if (m != NULL) { 146041502Swpaul struct mbuf *m_new = NULL; 146141502Swpaul 1462111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 146387846Sluigi if (m_new == NULL) 146441502Swpaul return(1); 146541502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1466111119Simp MCLGET(m_new, M_DONTWAIT); 146741502Swpaul if (!(m_new->m_flags & M_EXT)) { 146841502Swpaul m_freem(m_new); 146941502Swpaul return(1); 147041502Swpaul } 147141502Swpaul } 147241502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 147341502Swpaul mtod(m_new, caddr_t)); 147441502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 147541502Swpaul m_freem(m_head); 147641502Swpaul m_head = m_new; 147741502Swpaul f = &c->wb_ptr->wb_frag[0]; 147841502Swpaul f->wb_status = 0; 147941502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 148041502Swpaul f->wb_ctl = total_len = m_new->m_len; 148141502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 148241502Swpaul frag = 1; 148341502Swpaul } 148441502Swpaul 148541502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148641502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148741502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148841502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 149041502Swpaul f->wb_status = WB_TXSTAT_OWN; 149141502Swpaul frag++; 149241502Swpaul } 149341502Swpaul 149441502Swpaul c->wb_mbuf = m_head; 149541502Swpaul c->wb_lastdesc = frag - 1; 149641502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149741502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149841502Swpaul 149941502Swpaul return(0); 150041502Swpaul} 150141502Swpaul 150241502Swpaul/* 150341502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 150441502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 150541502Swpaul * copy of the pointers since the transmit list fragment pointers are 150641502Swpaul * physical addresses. 150741502Swpaul */ 150841502Swpaul 1509102336Salfredstatic void 1510102336Salfredwb_start(ifp) 151141502Swpaul struct ifnet *ifp; 151241502Swpaul{ 151341502Swpaul struct wb_softc *sc; 151441502Swpaul struct mbuf *m_head = NULL; 151541502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 151641502Swpaul 151741502Swpaul sc = ifp->if_softc; 151867087Swpaul WB_LOCK(sc); 151941502Swpaul 152041502Swpaul /* 152141502Swpaul * Check for an available queue slot. If there are none, 152241502Swpaul * punt. 152341502Swpaul */ 152441502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 152541502Swpaul ifp->if_flags |= IFF_OACTIVE; 152667087Swpaul WB_UNLOCK(sc); 152741502Swpaul return; 152841502Swpaul } 152941502Swpaul 153041502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 153141502Swpaul 153241502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 153341502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 153441502Swpaul if (m_head == NULL) 153541502Swpaul break; 153641502Swpaul 153741502Swpaul /* Pick a descriptor off the free list. */ 153841502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153941502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 154041502Swpaul 154141502Swpaul /* Pack the data into the descriptor. */ 154241502Swpaul wb_encap(sc, cur_tx, m_head); 154341502Swpaul 154441502Swpaul if (cur_tx != start_tx) 154541502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 154641502Swpaul 154741502Swpaul /* 154841502Swpaul * If there's a BPF listener, bounce a copy of this frame 154941502Swpaul * to him. 155041502Swpaul */ 1551106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 155241502Swpaul } 155341502Swpaul 155441502Swpaul /* 155541526Swpaul * If there are no packets queued, bail. 155641526Swpaul */ 155767087Swpaul if (cur_tx == NULL) { 155867087Swpaul WB_UNLOCK(sc); 155941526Swpaul return; 156067087Swpaul } 156141526Swpaul 156241526Swpaul /* 156341502Swpaul * Place the request for the upload interrupt 156441502Swpaul * in the last descriptor in the chain. This way, if 156541502Swpaul * we're chaining several packets at once, we'll only 156641502Swpaul * get an interupt once for the whole chain rather than 156741502Swpaul * once for each packet. 156841502Swpaul */ 156941502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 157042718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 157141502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 157241502Swpaul 157341502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 157441502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 157541502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 157641502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 157741502Swpaul } else { 157841502Swpaul /* 157941502Swpaul * We need to distinguish between the case where 158041502Swpaul * the own bit is clear because the chip cleared it 158141502Swpaul * and where the own bit is clear because we haven't 158241502Swpaul * set it yet. The magic value WB_UNSET is just some 158341502Swpaul * ramdomly chosen number which doesn't have the own 158441502Swpaul * bit set. When we actually transmit the frame, the 158541502Swpaul * status word will have _only_ the own bit set, so 158641502Swpaul * the txeoc handler will be able to tell if it needs 158741502Swpaul * to initiate another transmission to flush out pending 158841502Swpaul * frames. 158941502Swpaul */ 159041502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 159141502Swpaul } 159241502Swpaul 159341502Swpaul /* 159441502Swpaul * Set a timeout in case the chip goes out to lunch. 159541502Swpaul */ 159641502Swpaul ifp->if_timer = 5; 159767087Swpaul WB_UNLOCK(sc); 159841502Swpaul 159941502Swpaul return; 160041502Swpaul} 160141502Swpaul 1602102336Salfredstatic void 1603102336Salfredwb_init(xsc) 160441502Swpaul void *xsc; 160541502Swpaul{ 160641502Swpaul struct wb_softc *sc = xsc; 160741502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160867087Swpaul int i; 160950675Swpaul struct mii_data *mii; 161041502Swpaul 161167087Swpaul WB_LOCK(sc); 161250675Swpaul mii = device_get_softc(sc->wb_miibus); 161341502Swpaul 161441502Swpaul /* 161541502Swpaul * Cancel pending I/O and free all RX/TX buffers. 161641502Swpaul */ 161741502Swpaul wb_stop(sc); 161841502Swpaul wb_reset(sc); 161941502Swpaul 162041502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 162141502Swpaul 162241502Swpaul /* 162341502Swpaul * Set cache alignment and burst length. 162441502Swpaul */ 162550675Swpaul#ifdef foo 162641502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 162741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162950675Swpaul#endif 163041502Swpaul 163150675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 163250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 163350675Swpaul switch(sc->wb_cachesize) { 163450675Swpaul case 32: 163550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 163650675Swpaul break; 163750675Swpaul case 16: 163850675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163950675Swpaul break; 164050675Swpaul case 8: 164150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 164250675Swpaul break; 164350675Swpaul case 0: 164450675Swpaul default: 164550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 164650675Swpaul break; 164750675Swpaul } 164850675Swpaul 164941502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 165041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 165141502Swpaul 165241502Swpaul /* Init our MAC address */ 165341502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 165441502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 165541502Swpaul } 165641502Swpaul 165741502Swpaul /* Init circular RX list. */ 165841502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165941502Swpaul printf("wb%d: initialization failed: no " 166041502Swpaul "memory for rx buffers\n", sc->wb_unit); 166141502Swpaul wb_stop(sc); 166267087Swpaul WB_UNLOCK(sc); 166341502Swpaul return; 166441502Swpaul } 166541502Swpaul 166641502Swpaul /* Init TX descriptors. */ 166741502Swpaul wb_list_tx_init(sc); 166841502Swpaul 166941502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 167041502Swpaul if (ifp->if_flags & IFF_PROMISC) { 167141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 167241502Swpaul } else { 167341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 167441502Swpaul } 167541502Swpaul 167641502Swpaul /* 167741502Swpaul * Set capture broadcast bit to capture broadcast frames. 167841502Swpaul */ 167941502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 168041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 168141502Swpaul } else { 168241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 168341502Swpaul } 168441502Swpaul 168541502Swpaul /* 168641502Swpaul * Program the multicast filter, if necessary. 168741502Swpaul */ 168841502Swpaul wb_setmulti(sc); 168941502Swpaul 169041502Swpaul /* 169141502Swpaul * Load the address of the RX list. 169241502Swpaul */ 169341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169441502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 169541502Swpaul 169641502Swpaul /* 169741502Swpaul * Enable interrupts. 169841502Swpaul */ 169941502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 170041502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 170141502Swpaul 170241502Swpaul /* Enable receiver and transmitter. */ 170341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 170441502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 170541502Swpaul 170641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170741502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170941502Swpaul 171050675Swpaul mii_mediachg(mii); 171141502Swpaul 171241502Swpaul ifp->if_flags |= IFF_RUNNING; 171341502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 171441502Swpaul 171550675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 171667087Swpaul WB_UNLOCK(sc); 171750675Swpaul 171841502Swpaul return; 171941502Swpaul} 172041502Swpaul 172141502Swpaul/* 172241502Swpaul * Set media options. 172341502Swpaul */ 1724102336Salfredstatic int 1725102336Salfredwb_ifmedia_upd(ifp) 172641502Swpaul struct ifnet *ifp; 172741502Swpaul{ 172841502Swpaul struct wb_softc *sc; 172941502Swpaul 173041502Swpaul sc = ifp->if_softc; 173141502Swpaul 173250675Swpaul if (ifp->if_flags & IFF_UP) 173350675Swpaul wb_init(sc); 173441502Swpaul 173541502Swpaul return(0); 173641502Swpaul} 173741502Swpaul 173841502Swpaul/* 173941502Swpaul * Report current media status. 174041502Swpaul */ 1741102336Salfredstatic void 1742102336Salfredwb_ifmedia_sts(ifp, ifmr) 174341502Swpaul struct ifnet *ifp; 174441502Swpaul struct ifmediareq *ifmr; 174541502Swpaul{ 174641502Swpaul struct wb_softc *sc; 174750675Swpaul struct mii_data *mii; 174841502Swpaul 174941502Swpaul sc = ifp->if_softc; 175041502Swpaul 175150675Swpaul mii = device_get_softc(sc->wb_miibus); 175241502Swpaul 175350675Swpaul mii_pollstat(mii); 175450675Swpaul ifmr->ifm_active = mii->mii_media_active; 175550675Swpaul ifmr->ifm_status = mii->mii_media_status; 175641502Swpaul 175741502Swpaul return; 175841502Swpaul} 175941502Swpaul 1760102336Salfredstatic int 1761102336Salfredwb_ioctl(ifp, command, data) 176241502Swpaul struct ifnet *ifp; 176341502Swpaul u_long command; 176441502Swpaul caddr_t data; 176541502Swpaul{ 176641502Swpaul struct wb_softc *sc = ifp->if_softc; 176750675Swpaul struct mii_data *mii; 176841502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176967087Swpaul int error = 0; 177041502Swpaul 177167087Swpaul WB_LOCK(sc); 177241502Swpaul 177341502Swpaul switch(command) { 177441502Swpaul case SIOCSIFFLAGS: 177541502Swpaul if (ifp->if_flags & IFF_UP) { 177641502Swpaul wb_init(sc); 177741502Swpaul } else { 177841502Swpaul if (ifp->if_flags & IFF_RUNNING) 177941502Swpaul wb_stop(sc); 178041502Swpaul } 178141502Swpaul error = 0; 178241502Swpaul break; 178341502Swpaul case SIOCADDMULTI: 178441502Swpaul case SIOCDELMULTI: 178541502Swpaul wb_setmulti(sc); 178641502Swpaul error = 0; 178741502Swpaul break; 178841502Swpaul case SIOCGIFMEDIA: 178941502Swpaul case SIOCSIFMEDIA: 179050675Swpaul mii = device_get_softc(sc->wb_miibus); 179150675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 179241502Swpaul break; 179341502Swpaul default: 1794106936Ssam error = ether_ioctl(ifp, command, data); 179541502Swpaul break; 179641502Swpaul } 179741502Swpaul 179867087Swpaul WB_UNLOCK(sc); 179941502Swpaul 180041502Swpaul return(error); 180141502Swpaul} 180241502Swpaul 1803102336Salfredstatic void 1804102336Salfredwb_watchdog(ifp) 180541502Swpaul struct ifnet *ifp; 180641502Swpaul{ 180741502Swpaul struct wb_softc *sc; 180841502Swpaul 180941502Swpaul sc = ifp->if_softc; 181041502Swpaul 181167087Swpaul WB_LOCK(sc); 181241502Swpaul ifp->if_oerrors++; 181341502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 181450675Swpaul#ifdef foo 181541502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 181641502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 181741502Swpaul sc->wb_unit); 181850675Swpaul#endif 181941502Swpaul wb_stop(sc); 182041502Swpaul wb_reset(sc); 182141502Swpaul wb_init(sc); 182241502Swpaul 182341502Swpaul if (ifp->if_snd.ifq_head != NULL) 182441502Swpaul wb_start(ifp); 182567087Swpaul WB_UNLOCK(sc); 182641502Swpaul 182741502Swpaul return; 182841502Swpaul} 182941502Swpaul 183041502Swpaul/* 183141502Swpaul * Stop the adapter and free any mbufs allocated to the 183241502Swpaul * RX and TX lists. 183341502Swpaul */ 1834102336Salfredstatic void 1835102336Salfredwb_stop(sc) 183641502Swpaul struct wb_softc *sc; 183741502Swpaul{ 183841502Swpaul register int i; 183941502Swpaul struct ifnet *ifp; 184041502Swpaul 184167087Swpaul WB_LOCK(sc); 184241502Swpaul ifp = &sc->arpcom.ac_if; 184341502Swpaul ifp->if_timer = 0; 184441502Swpaul 184550675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 184650675Swpaul 184741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184841502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184941502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 185041502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 185141502Swpaul 185241502Swpaul /* 185341502Swpaul * Free data in the RX lists. 185441502Swpaul */ 185541502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 185641502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 185741502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185841502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185941502Swpaul } 186041502Swpaul } 186141502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 186241502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 186341502Swpaul 186441502Swpaul /* 186541502Swpaul * Free the TX list buffers. 186641502Swpaul */ 186741502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186841502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186941502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 187041502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 187141502Swpaul } 187241502Swpaul } 187341502Swpaul 187441502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 187541502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 187641502Swpaul 187741502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187867087Swpaul WB_UNLOCK(sc); 187941502Swpaul 188041502Swpaul return; 188141502Swpaul} 188241502Swpaul 188341502Swpaul/* 188441502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 188541502Swpaul * get confused by errant DMAs when rebooting. 188641502Swpaul */ 1887102336Salfredstatic void 1888102336Salfredwb_shutdown(dev) 188949611Swpaul device_t dev; 189041502Swpaul{ 189149611Swpaul struct wb_softc *sc; 189241502Swpaul 189349611Swpaul sc = device_get_softc(dev); 189441502Swpaul wb_stop(sc); 189541502Swpaul 189641502Swpaul return; 189741502Swpaul} 1898