if_wb.c revision 113506
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Winbond fast ethernet PCI NIC driver 35 * 36 * Supports various cheap network adapters based on the Winbond W89C840F 37 * fast ethernet controller chip. This includes adapters manufactured by 38 * Winbond itself and some made by Linksys. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Winbond W89C840F chip is a bus master; in some ways it resembles 47 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48 * one major difference which is that while the registers do many of 49 * the same things as a tulip adapter, the offsets are different: where 50 * tulip registers are typically spaced 8 bytes apart, the Winbond 51 * registers are spaced 4 bytes apart. The receiver filter is also 52 * programmed differently. 53 * 54 * Like the tulip, the Winbond chip uses small descriptors containing 55 * a status word, a control word and 32-bit areas that can either be used 56 * to point to two external data blocks, or to point to a single block 57 * and another descriptor in a linked list. Descriptors can be grouped 58 * together in blocks to form fixed length rings or can be chained 59 * together in linked lists. A single packet may be spread out over 60 * several descriptors if necessary. 61 * 62 * For the receive ring, this driver uses a linked list of descriptors, 63 * each pointing to a single mbuf cluster buffer, which us large enough 64 * to hold an entire packet. The link list is looped back to created a 65 * closed ring. 66 * 67 * For transmission, the driver creates a linked list of 'super descriptors' 68 * which each contain several individual descriptors linked toghether. 69 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70 * abuse as fragment pointers. This allows us to use a buffer managment 71 * scheme very similar to that used in the ThunderLAN and Etherlink XL 72 * drivers. 73 * 74 * Autonegotiation is performed using the external PHY via the MII bus. 75 * The sample boards I have all use a Davicom PHY. 76 * 77 * Note: the author of the Linux driver for the Winbond chip alludes 78 * to some sort of flaw in the chip's design that seems to mandate some 79 * drastic workaround which signigicantly impairs transmit performance. 80 * I have no idea what he's on about: transmit performance with all 81 * three of my test boards seems fine. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 113506 2003-04-15 06:37:30Z mdodd $"); 86 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <pci/pcireg.h> 116#include <pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, pci, 1, 1, 1); 129MODULE_DEPEND(wb, ether, 1, 1, 1); 130MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132/* 133 * Various supported device vendors/types and their names. 134 */ 135static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141}; 142 143static int wb_probe (device_t); 144static int wb_attach (device_t); 145static int wb_detach (device_t); 146 147static void wb_bfree (void *addr, void *args); 148static int wb_newbuf (struct wb_softc *, 149 struct wb_chain_onefrag *, 150 struct mbuf *); 151static int wb_encap (struct wb_softc *, struct wb_chain *, 152 struct mbuf *); 153 154static void wb_rxeof (struct wb_softc *); 155static void wb_rxeoc (struct wb_softc *); 156static void wb_txeof (struct wb_softc *); 157static void wb_txeoc (struct wb_softc *); 158static void wb_intr (void *); 159static void wb_tick (void *); 160static void wb_start (struct ifnet *); 161static int wb_ioctl (struct ifnet *, u_long, caddr_t); 162static void wb_init (void *); 163static void wb_stop (struct wb_softc *); 164static void wb_watchdog (struct ifnet *); 165static void wb_shutdown (device_t); 166static int wb_ifmedia_upd (struct ifnet *); 167static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168 169static void wb_eeprom_putbyte (struct wb_softc *, int); 170static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172static void wb_mii_sync (struct wb_softc *); 173static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177static void wb_setcfg (struct wb_softc *, u_int32_t); 178static u_int8_t wb_calchash (caddr_t); 179static void wb_setmulti (struct wb_softc *); 180static void wb_reset (struct wb_softc *); 181static void wb_fixmedia (struct wb_softc *); 182static int wb_list_rx_init (struct wb_softc *); 183static int wb_list_tx_init (struct wb_softc *); 184 185static int wb_miibus_readreg (device_t, int, int); 186static int wb_miibus_writereg (device_t, int, int, int); 187static void wb_miibus_statchg (device_t); 188 189#ifdef WB_USEIOSPACE 190#define WB_RES SYS_RES_IOPORT 191#define WB_RID WB_PCI_LOIO 192#else 193#define WB_RES SYS_RES_MEMORY 194#define WB_RID WB_PCI_LOMEM 195#endif 196 197static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213}; 214 215static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219}; 220 221static devclass_t wb_devclass; 222 223DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 224DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 225 226#define WB_SETBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define WB_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_4(sc, WB_SIO, \ 240 CSR_READ_4(sc, WB_SIO) & ~(x)) 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void 246wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249{ 250 register int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271} 272 273/* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276static void 277wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281{ 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313} 314 315/* 316 * Read a sequence of words from the EEPROM. 317 */ 318static void 319wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void 345wb_mii_sync(sc) 346 struct wb_softc *sc; 347{ 348 register int i; 349 350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(WB_SIO_MII_CLK); 354 DELAY(1); 355 SIO_CLR(WB_SIO_MII_CLK); 356 DELAY(1); 357 } 358 359 return; 360} 361 362/* 363 * Clock a series of bits through the MII. 364 */ 365static void 366wb_mii_send(sc, bits, cnt) 367 struct wb_softc *sc; 368 u_int32_t bits; 369 int cnt; 370{ 371 int i; 372 373 SIO_CLR(WB_SIO_MII_CLK); 374 375 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 376 if (bits & i) { 377 SIO_SET(WB_SIO_MII_DATAIN); 378 } else { 379 SIO_CLR(WB_SIO_MII_DATAIN); 380 } 381 DELAY(1); 382 SIO_CLR(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 } 386} 387 388/* 389 * Read an PHY register through the MII. 390 */ 391static int 392wb_mii_readreg(sc, frame) 393 struct wb_softc *sc; 394 struct wb_mii_frame *frame; 395 396{ 397 int i, ack; 398 399 WB_LOCK(sc); 400 401 /* 402 * Set up frame for RX. 403 */ 404 frame->mii_stdelim = WB_MII_STARTDELIM; 405 frame->mii_opcode = WB_MII_READOP; 406 frame->mii_turnaround = 0; 407 frame->mii_data = 0; 408 409 CSR_WRITE_4(sc, WB_SIO, 0); 410 411 /* 412 * Turn on data xmit. 413 */ 414 SIO_SET(WB_SIO_MII_DIR); 415 416 wb_mii_sync(sc); 417 418 /* 419 * Send command/address info. 420 */ 421 wb_mii_send(sc, frame->mii_stdelim, 2); 422 wb_mii_send(sc, frame->mii_opcode, 2); 423 wb_mii_send(sc, frame->mii_phyaddr, 5); 424 wb_mii_send(sc, frame->mii_regaddr, 5); 425 426 /* Idle bit */ 427 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 /* Turn off xmit. */ 433 SIO_CLR(WB_SIO_MII_DIR); 434 /* Check for ack */ 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 SIO_CLR(WB_SIO_MII_CLK); 452 DELAY(1); 453 SIO_SET(WB_SIO_MII_CLK); 454 DELAY(1); 455 } 456 goto fail; 457 } 458 459 for (i = 0x8000; i; i >>= 1) { 460 SIO_CLR(WB_SIO_MII_CLK); 461 DELAY(1); 462 if (!ack) { 463 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464 frame->mii_data |= i; 465 DELAY(1); 466 } 467 SIO_SET(WB_SIO_MII_CLK); 468 DELAY(1); 469 } 470 471fail: 472 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 SIO_SET(WB_SIO_MII_CLK); 476 DELAY(1); 477 478 WB_UNLOCK(sc); 479 480 if (ack) 481 return(1); 482 return(0); 483} 484 485/* 486 * Write to a PHY register through the MII. 487 */ 488static int 489wb_mii_writereg(sc, frame) 490 struct wb_softc *sc; 491 struct wb_mii_frame *frame; 492 493{ 494 WB_LOCK(sc); 495 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = WB_MII_STARTDELIM; 501 frame->mii_opcode = WB_MII_WRITEOP; 502 frame->mii_turnaround = WB_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(WB_SIO_MII_DIR); 508 509 wb_mii_sync(sc); 510 511 wb_mii_send(sc, frame->mii_stdelim, 2); 512 wb_mii_send(sc, frame->mii_opcode, 2); 513 wb_mii_send(sc, frame->mii_phyaddr, 5); 514 wb_mii_send(sc, frame->mii_regaddr, 5); 515 wb_mii_send(sc, frame->mii_turnaround, 2); 516 wb_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(WB_SIO_MII_CLK); 520 DELAY(1); 521 SIO_CLR(WB_SIO_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(WB_SIO_MII_DIR); 528 529 WB_UNLOCK(sc); 530 531 return(0); 532} 533 534static int 535wb_miibus_readreg(dev, phy, reg) 536 device_t dev; 537 int phy, reg; 538{ 539 struct wb_softc *sc; 540 struct wb_mii_frame frame; 541 542 sc = device_get_softc(dev); 543 544 bzero((char *)&frame, sizeof(frame)); 545 546 frame.mii_phyaddr = phy; 547 frame.mii_regaddr = reg; 548 wb_mii_readreg(sc, &frame); 549 550 return(frame.mii_data); 551} 552 553static int 554wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557{ 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572} 573 574static void 575wb_miibus_statchg(dev) 576 device_t dev; 577{ 578 struct wb_softc *sc; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 WB_LOCK(sc); 583 mii = device_get_softc(sc->wb_miibus); 584 wb_setcfg(sc, mii->mii_media_active); 585 WB_UNLOCK(sc); 586 587 return; 588} 589 590static u_int8_t wb_calchash(addr) 591 caddr_t addr; 592{ 593 u_int32_t crc, carry; 594 int i, j; 595 u_int8_t c; 596 597 /* Compute CRC for the address value. */ 598 crc = 0xFFFFFFFF; /* initial value */ 599 600 for (i = 0; i < 6; i++) { 601 c = *(addr + i); 602 for (j = 0; j < 8; j++) { 603 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 604 crc <<= 1; 605 c >>= 1; 606 if (carry) 607 crc = (crc ^ 0x04c11db6) | carry; 608 } 609 } 610 611 /* 612 * return the filter bit position 613 * Note: I arrived at the following nonsense 614 * through experimentation. It's not the usual way to 615 * generate the bit position but it's the only thing 616 * I could come up with that works. 617 */ 618 return(~(crc >> 26) & 0x0000003F); 619} 620 621/* 622 * Program the 64-bit multicast hash filter. 623 */ 624static void 625wb_setmulti(sc) 626 struct wb_softc *sc; 627{ 628 struct ifnet *ifp; 629 int h = 0; 630 u_int32_t hashes[2] = { 0, 0 }; 631 struct ifmultiaddr *ifma; 632 u_int32_t rxfilt; 633 int mcnt = 0; 634 635 ifp = &sc->arpcom.ac_if; 636 637 rxfilt = CSR_READ_4(sc, WB_NETCFG); 638 639 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 640 rxfilt |= WB_NETCFG_RX_MULTI; 641 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 642 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 643 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 644 return; 645 } 646 647 /* first, zot all the existing hash bits */ 648 CSR_WRITE_4(sc, WB_MAR0, 0); 649 CSR_WRITE_4(sc, WB_MAR1, 0); 650 651 /* now program new ones */ 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 663 if (mcnt) 664 rxfilt |= WB_NETCFG_RX_MULTI; 665 else 666 rxfilt &= ~WB_NETCFG_RX_MULTI; 667 668 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 670 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 671 672 return; 673} 674 675/* 676 * The Winbond manual states that in order to fiddle with the 677 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 678 * first have to put the transmit and/or receive logic in the idle state. 679 */ 680static void 681wb_setcfg(sc, media) 682 struct wb_softc *sc; 683 u_int32_t media; 684{ 685 int i, restart = 0; 686 687 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 688 restart = 1; 689 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 690 691 for (i = 0; i < WB_TIMEOUT; i++) { 692 DELAY(10); 693 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 694 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 695 break; 696 } 697 698 if (i == WB_TIMEOUT) 699 printf("wb%d: failed to force tx and " 700 "rx to idle state\n", sc->wb_unit); 701 } 702 703 if (IFM_SUBTYPE(media) == IFM_10_T) 704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 else 706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707 708 if ((media & IFM_GMASK) == IFM_FDX) 709 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 else 711 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712 713 if (restart) 714 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 715 716 return; 717} 718 719static void 720wb_reset(sc) 721 struct wb_softc *sc; 722{ 723 register int i; 724 struct mii_data *mii; 725 726 CSR_WRITE_4(sc, WB_NETCFG, 0); 727 CSR_WRITE_4(sc, WB_BUSCTL, 0); 728 CSR_WRITE_4(sc, WB_TXADDR, 0); 729 CSR_WRITE_4(sc, WB_RXADDR, 0); 730 731 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 732 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 733 734 for (i = 0; i < WB_TIMEOUT; i++) { 735 DELAY(10); 736 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 737 break; 738 } 739 if (i == WB_TIMEOUT) 740 printf("wb%d: reset never completed!\n", sc->wb_unit); 741 742 /* Wait a little while for the chip to get its brains in order. */ 743 DELAY(1000); 744 745 if (sc->wb_miibus == NULL) 746 return; 747 748 mii = device_get_softc(sc->wb_miibus); 749 if (mii == NULL) 750 return; 751 752 if (mii->mii_instance) { 753 struct mii_softc *miisc; 754 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 755 mii_phy_reset(miisc); 756 } 757 758 return; 759} 760 761static void 762wb_fixmedia(sc) 763 struct wb_softc *sc; 764{ 765 struct mii_data *mii = NULL; 766 struct ifnet *ifp; 767 u_int32_t media; 768 769 if (sc->wb_miibus == NULL) 770 return; 771 772 mii = device_get_softc(sc->wb_miibus); 773 ifp = &sc->arpcom.ac_if; 774 775 mii_pollstat(mii); 776 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 777 media = mii->mii_media_active & ~IFM_10_T; 778 media |= IFM_100_TX; 779 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 780 media = mii->mii_media_active & ~IFM_100_TX; 781 media |= IFM_10_T; 782 } else 783 return; 784 785 ifmedia_set(&mii->mii_media, media); 786 787 return; 788} 789 790/* 791 * Probe for a Winbond chip. Check the PCI vendor and device 792 * IDs against our list and return a device name if we find a match. 793 */ 794static int 795wb_probe(dev) 796 device_t dev; 797{ 798 struct wb_type *t; 799 800 t = wb_devs; 801 802 while(t->wb_name != NULL) { 803 if ((pci_get_vendor(dev) == t->wb_vid) && 804 (pci_get_device(dev) == t->wb_did)) { 805 device_set_desc(dev, t->wb_name); 806 return(0); 807 } 808 t++; 809 } 810 811 return(ENXIO); 812} 813 814/* 815 * Attach the interface. Allocate softc structures, do ifmedia 816 * setup and ethernet/BPF attach. 817 */ 818static int 819wb_attach(dev) 820 device_t dev; 821{ 822 u_char eaddr[ETHER_ADDR_LEN]; 823 u_int32_t command; 824 struct wb_softc *sc; 825 struct ifnet *ifp; 826 int unit, error = 0, rid; 827 828 sc = device_get_softc(dev); 829 unit = device_get_unit(dev); 830 831 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 832 MTX_DEF | MTX_RECURSE); 833 834 /* 835 * Handle power management nonsense. 836 */ 837 838 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 839 u_int32_t iobase, membase, irq; 840 841 /* Save important PCI config data. */ 842 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 843 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 844 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 845 846 /* Reset the power state. */ 847 printf("wb%d: chip is in D%d power mode " 848 "-- setting to D0\n", unit, 849 pci_get_powerstate(dev)); 850 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 851 852 /* Restore PCI config data. */ 853 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 854 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 855 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 856 } 857 858 /* 859 * Map control/status registers. 860 */ 861 pci_enable_busmaster(dev); 862 pci_enable_io(dev, SYS_RES_IOPORT); 863 pci_enable_io(dev, SYS_RES_MEMORY); 864 command = pci_read_config(dev, PCIR_COMMAND, 4); 865 866#ifdef WB_USEIOSPACE 867 if (!(command & PCIM_CMD_PORTEN)) { 868 printf("wb%d: failed to enable I/O ports!\n", unit); 869 error = ENXIO; 870 goto fail; 871 } 872#else 873 if (!(command & PCIM_CMD_MEMEN)) { 874 printf("wb%d: failed to enable memory mapping!\n", unit); 875 error = ENXIO; 876 goto fail; 877 } 878#endif 879 880 rid = WB_RID; 881 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 882 0, ~0, 1, RF_ACTIVE); 883 884 if (sc->wb_res == NULL) { 885 printf("wb%d: couldn't map ports/memory\n", unit); 886 error = ENXIO; 887 goto fail; 888 } 889 890 sc->wb_btag = rman_get_bustag(sc->wb_res); 891 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 892 893 /* Allocate interrupt */ 894 rid = 0; 895 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 896 RF_SHAREABLE | RF_ACTIVE); 897 898 if (sc->wb_irq == NULL) { 899 printf("wb%d: couldn't map interrupt\n", unit); 900 error = ENXIO; 901 goto fail; 902 } 903 904 /* Save the cache line size. */ 905 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 906 907 /* Reset the adapter. */ 908 wb_reset(sc); 909 910 /* 911 * Get station address from the EEPROM. 912 */ 913 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 914 915 /* 916 * A Winbond chip was detected. Inform the world. 917 */ 918 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 919 920 sc->wb_unit = unit; 921 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 922 923 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 924 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 925 926 if (sc->wb_ldata == NULL) { 927 printf("wb%d: no memory for list buffers!\n", unit); 928 error = ENXIO; 929 goto fail; 930 } 931 932 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 933 934 ifp = &sc->arpcom.ac_if; 935 ifp->if_softc = sc; 936 ifp->if_unit = unit; 937 ifp->if_name = "wb"; 938 ifp->if_mtu = ETHERMTU; 939 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 940 ifp->if_ioctl = wb_ioctl; 941 ifp->if_output = ether_output; 942 ifp->if_start = wb_start; 943 ifp->if_watchdog = wb_watchdog; 944 ifp->if_init = wb_init; 945 ifp->if_baudrate = 10000000; 946 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 947 948 /* 949 * Do MII setup. 950 */ 951 if (mii_phy_probe(dev, &sc->wb_miibus, 952 wb_ifmedia_upd, wb_ifmedia_sts)) { 953 error = ENXIO; 954 goto fail; 955 } 956 957 /* 958 * Call MI attach routine. 959 */ 960 ether_ifattach(ifp, eaddr); 961 962 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 963 wb_intr, sc, &sc->wb_intrhand); 964 965 if (error) { 966 printf("wb%d: couldn't set up irq\n", unit); 967 goto fail; 968 } 969 970fail: 971 if (error) 972 wb_detach(dev); 973 974 return(error); 975} 976 977static int 978wb_detach(dev) 979 device_t dev; 980{ 981 struct wb_softc *sc; 982 struct ifnet *ifp; 983 984 sc = device_get_softc(dev); 985 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 986 WB_LOCK(sc); 987 ifp = &sc->arpcom.ac_if; 988 989 /* Delete any miibus and phy devices attached to this interface */ 990 if (device_is_alive(dev)) { 991 if (bus_child_present(dev)) 992 wb_stop(sc); 993 ether_ifdetach(ifp); 994 device_delete_child(dev, sc->wb_miibus); 995 bus_generic_detach(dev); 996 } 997 998 if (sc->wb_intrhand) 999 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1000 if (sc->wb_irq) 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1002 if (sc->wb_res) 1003 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1004 1005 if (sc->wb_ldata) { 1006 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1007 M_DEVBUF); 1008 } 1009 1010 WB_UNLOCK(sc); 1011 mtx_destroy(&sc->wb_mtx); 1012 1013 return(0); 1014} 1015 1016/* 1017 * Initialize the transmit descriptors. 1018 */ 1019static int 1020wb_list_tx_init(sc) 1021 struct wb_softc *sc; 1022{ 1023 struct wb_chain_data *cd; 1024 struct wb_list_data *ld; 1025 int i; 1026 1027 cd = &sc->wb_cdata; 1028 ld = sc->wb_ldata; 1029 1030 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1031 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1032 if (i == (WB_TX_LIST_CNT - 1)) { 1033 cd->wb_tx_chain[i].wb_nextdesc = 1034 &cd->wb_tx_chain[0]; 1035 } else { 1036 cd->wb_tx_chain[i].wb_nextdesc = 1037 &cd->wb_tx_chain[i + 1]; 1038 } 1039 } 1040 1041 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1042 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1043 1044 return(0); 1045} 1046 1047 1048/* 1049 * Initialize the RX descriptors and allocate mbufs for them. Note that 1050 * we arrange the descriptors in a closed ring, so that the last descriptor 1051 * points back to the first. 1052 */ 1053static int 1054wb_list_rx_init(sc) 1055 struct wb_softc *sc; 1056{ 1057 struct wb_chain_data *cd; 1058 struct wb_list_data *ld; 1059 int i; 1060 1061 cd = &sc->wb_cdata; 1062 ld = sc->wb_ldata; 1063 1064 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1065 cd->wb_rx_chain[i].wb_ptr = 1066 (struct wb_desc *)&ld->wb_rx_list[i]; 1067 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1068 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1069 return(ENOBUFS); 1070 if (i == (WB_RX_LIST_CNT - 1)) { 1071 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1072 ld->wb_rx_list[i].wb_next = 1073 vtophys(&ld->wb_rx_list[0]); 1074 } else { 1075 cd->wb_rx_chain[i].wb_nextdesc = 1076 &cd->wb_rx_chain[i + 1]; 1077 ld->wb_rx_list[i].wb_next = 1078 vtophys(&ld->wb_rx_list[i + 1]); 1079 } 1080 } 1081 1082 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1083 1084 return(0); 1085} 1086 1087static void 1088wb_bfree(buf, args) 1089 void *buf; 1090 void *args; 1091{ 1092 return; 1093} 1094 1095/* 1096 * Initialize an RX descriptor and attach an MBUF cluster. 1097 */ 1098static int 1099wb_newbuf(sc, c, m) 1100 struct wb_softc *sc; 1101 struct wb_chain_onefrag *c; 1102 struct mbuf *m; 1103{ 1104 struct mbuf *m_new = NULL; 1105 1106 if (m == NULL) { 1107 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1108 if (m_new == NULL) 1109 return(ENOBUFS); 1110 m_new->m_data = c->wb_buf; 1111 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1112 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1113 EXT_NET_DRV); 1114 } else { 1115 m_new = m; 1116 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1117 m_new->m_data = m_new->m_ext.ext_buf; 1118 } 1119 1120 m_adj(m_new, sizeof(u_int64_t)); 1121 1122 c->wb_mbuf = m_new; 1123 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1124 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1125 c->wb_ptr->wb_status = WB_RXSTAT; 1126 1127 return(0); 1128} 1129 1130/* 1131 * A frame has been uploaded: pass the resulting mbuf chain up to 1132 * the higher level protocols. 1133 */ 1134static void 1135wb_rxeof(sc) 1136 struct wb_softc *sc; 1137{ 1138 struct mbuf *m = NULL; 1139 struct ifnet *ifp; 1140 struct wb_chain_onefrag *cur_rx; 1141 int total_len = 0; 1142 u_int32_t rxstat; 1143 1144 ifp = &sc->arpcom.ac_if; 1145 1146 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1147 WB_RXSTAT_OWN)) { 1148 struct mbuf *m0 = NULL; 1149 1150 cur_rx = sc->wb_cdata.wb_rx_head; 1151 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1152 1153 m = cur_rx->wb_mbuf; 1154 1155 if ((rxstat & WB_RXSTAT_MIIERR) || 1156 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1157 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1158 !(rxstat & WB_RXSTAT_LASTFRAG) || 1159 !(rxstat & WB_RXSTAT_RXCMP)) { 1160 ifp->if_ierrors++; 1161 wb_newbuf(sc, cur_rx, m); 1162 printf("wb%x: receiver babbling: possible chip " 1163 "bug, forcing reset\n", sc->wb_unit); 1164 wb_fixmedia(sc); 1165 wb_reset(sc); 1166 wb_init(sc); 1167 return; 1168 } 1169 1170 if (rxstat & WB_RXSTAT_RXERR) { 1171 ifp->if_ierrors++; 1172 wb_newbuf(sc, cur_rx, m); 1173 break; 1174 } 1175 1176 /* No errors; receive the packet. */ 1177 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1178 1179 /* 1180 * XXX The Winbond chip includes the CRC with every 1181 * received frame, and there's no way to turn this 1182 * behavior off (at least, I can't find anything in 1183 * the manual that explains how to do it) so we have 1184 * to trim off the CRC manually. 1185 */ 1186 total_len -= ETHER_CRC_LEN; 1187 1188 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1189 NULL); 1190 wb_newbuf(sc, cur_rx, m); 1191 if (m0 == NULL) { 1192 ifp->if_ierrors++; 1193 break; 1194 } 1195 m = m0; 1196 1197 ifp->if_ipackets++; 1198 (*ifp->if_input)(ifp, m); 1199 } 1200} 1201 1202static void 1203wb_rxeoc(sc) 1204 struct wb_softc *sc; 1205{ 1206 wb_rxeof(sc); 1207 1208 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1209 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1210 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1211 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1212 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1213 1214 return; 1215} 1216 1217/* 1218 * A frame was downloaded to the chip. It's safe for us to clean up 1219 * the list buffers. 1220 */ 1221static void 1222wb_txeof(sc) 1223 struct wb_softc *sc; 1224{ 1225 struct wb_chain *cur_tx; 1226 struct ifnet *ifp; 1227 1228 ifp = &sc->arpcom.ac_if; 1229 1230 /* Clear the timeout timer. */ 1231 ifp->if_timer = 0; 1232 1233 if (sc->wb_cdata.wb_tx_head == NULL) 1234 return; 1235 1236 /* 1237 * Go through our tx list and free mbufs for those 1238 * frames that have been transmitted. 1239 */ 1240 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1241 u_int32_t txstat; 1242 1243 cur_tx = sc->wb_cdata.wb_tx_head; 1244 txstat = WB_TXSTATUS(cur_tx); 1245 1246 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1247 break; 1248 1249 if (txstat & WB_TXSTAT_TXERR) { 1250 ifp->if_oerrors++; 1251 if (txstat & WB_TXSTAT_ABORT) 1252 ifp->if_collisions++; 1253 if (txstat & WB_TXSTAT_LATECOLL) 1254 ifp->if_collisions++; 1255 } 1256 1257 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1258 1259 ifp->if_opackets++; 1260 m_freem(cur_tx->wb_mbuf); 1261 cur_tx->wb_mbuf = NULL; 1262 1263 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1264 sc->wb_cdata.wb_tx_head = NULL; 1265 sc->wb_cdata.wb_tx_tail = NULL; 1266 break; 1267 } 1268 1269 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1270 } 1271 1272 return; 1273} 1274 1275/* 1276 * TX 'end of channel' interrupt handler. 1277 */ 1278static void 1279wb_txeoc(sc) 1280 struct wb_softc *sc; 1281{ 1282 struct ifnet *ifp; 1283 1284 ifp = &sc->arpcom.ac_if; 1285 1286 ifp->if_timer = 0; 1287 1288 if (sc->wb_cdata.wb_tx_head == NULL) { 1289 ifp->if_flags &= ~IFF_OACTIVE; 1290 sc->wb_cdata.wb_tx_tail = NULL; 1291 } else { 1292 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1293 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1294 ifp->if_timer = 5; 1295 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1296 } 1297 } 1298 1299 return; 1300} 1301 1302static void 1303wb_intr(arg) 1304 void *arg; 1305{ 1306 struct wb_softc *sc; 1307 struct ifnet *ifp; 1308 u_int32_t status; 1309 1310 sc = arg; 1311 WB_LOCK(sc); 1312 ifp = &sc->arpcom.ac_if; 1313 1314 if (!(ifp->if_flags & IFF_UP)) { 1315 WB_UNLOCK(sc); 1316 return; 1317 } 1318 1319 /* Disable interrupts. */ 1320 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1321 1322 for (;;) { 1323 1324 status = CSR_READ_4(sc, WB_ISR); 1325 if (status) 1326 CSR_WRITE_4(sc, WB_ISR, status); 1327 1328 if ((status & WB_INTRS) == 0) 1329 break; 1330 1331 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1332 ifp->if_ierrors++; 1333 wb_reset(sc); 1334 if (status & WB_ISR_RX_ERR) 1335 wb_fixmedia(sc); 1336 wb_init(sc); 1337 continue; 1338 } 1339 1340 if (status & WB_ISR_RX_OK) 1341 wb_rxeof(sc); 1342 1343 if (status & WB_ISR_RX_IDLE) 1344 wb_rxeoc(sc); 1345 1346 if (status & WB_ISR_TX_OK) 1347 wb_txeof(sc); 1348 1349 if (status & WB_ISR_TX_NOBUF) 1350 wb_txeoc(sc); 1351 1352 if (status & WB_ISR_TX_IDLE) { 1353 wb_txeof(sc); 1354 if (sc->wb_cdata.wb_tx_head != NULL) { 1355 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1356 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1357 } 1358 } 1359 1360 if (status & WB_ISR_TX_UNDERRUN) { 1361 ifp->if_oerrors++; 1362 wb_txeof(sc); 1363 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1364 /* Jack up TX threshold */ 1365 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1366 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1367 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1368 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1369 } 1370 1371 if (status & WB_ISR_BUS_ERR) { 1372 wb_reset(sc); 1373 wb_init(sc); 1374 } 1375 1376 } 1377 1378 /* Re-enable interrupts. */ 1379 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1380 1381 if (ifp->if_snd.ifq_head != NULL) { 1382 wb_start(ifp); 1383 } 1384 1385 WB_UNLOCK(sc); 1386 1387 return; 1388} 1389 1390static void 1391wb_tick(xsc) 1392 void *xsc; 1393{ 1394 struct wb_softc *sc; 1395 struct mii_data *mii; 1396 1397 sc = xsc; 1398 WB_LOCK(sc); 1399 mii = device_get_softc(sc->wb_miibus); 1400 1401 mii_tick(mii); 1402 1403 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1404 1405 WB_UNLOCK(sc); 1406 1407 return; 1408} 1409 1410/* 1411 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1412 * pointers to the fragment pointers. 1413 */ 1414static int 1415wb_encap(sc, c, m_head) 1416 struct wb_softc *sc; 1417 struct wb_chain *c; 1418 struct mbuf *m_head; 1419{ 1420 int frag = 0; 1421 struct wb_desc *f = NULL; 1422 int total_len; 1423 struct mbuf *m; 1424 1425 /* 1426 * Start packing the mbufs in this chain into 1427 * the fragment pointers. Stop when we run out 1428 * of fragments or hit the end of the mbuf chain. 1429 */ 1430 m = m_head; 1431 total_len = 0; 1432 1433 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1434 if (m->m_len != 0) { 1435 if (frag == WB_MAXFRAGS) 1436 break; 1437 total_len += m->m_len; 1438 f = &c->wb_ptr->wb_frag[frag]; 1439 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1440 if (frag == 0) { 1441 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1442 f->wb_status = 0; 1443 } else 1444 f->wb_status = WB_TXSTAT_OWN; 1445 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1446 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1447 frag++; 1448 } 1449 } 1450 1451 /* 1452 * Handle special case: we used up all 16 fragments, 1453 * but we have more mbufs left in the chain. Copy the 1454 * data into an mbuf cluster. Note that we don't 1455 * bother clearing the values in the other fragment 1456 * pointers/counters; it wouldn't gain us anything, 1457 * and would waste cycles. 1458 */ 1459 if (m != NULL) { 1460 struct mbuf *m_new = NULL; 1461 1462 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1463 if (m_new == NULL) 1464 return(1); 1465 if (m_head->m_pkthdr.len > MHLEN) { 1466 MCLGET(m_new, M_DONTWAIT); 1467 if (!(m_new->m_flags & M_EXT)) { 1468 m_freem(m_new); 1469 return(1); 1470 } 1471 } 1472 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1473 mtod(m_new, caddr_t)); 1474 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1475 m_freem(m_head); 1476 m_head = m_new; 1477 f = &c->wb_ptr->wb_frag[0]; 1478 f->wb_status = 0; 1479 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1480 f->wb_ctl = total_len = m_new->m_len; 1481 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1482 frag = 1; 1483 } 1484 1485 if (total_len < WB_MIN_FRAMELEN) { 1486 f = &c->wb_ptr->wb_frag[frag]; 1487 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1488 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1489 f->wb_ctl |= WB_TXCTL_TLINK; 1490 f->wb_status = WB_TXSTAT_OWN; 1491 frag++; 1492 } 1493 1494 c->wb_mbuf = m_head; 1495 c->wb_lastdesc = frag - 1; 1496 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1497 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1498 1499 return(0); 1500} 1501 1502/* 1503 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1504 * to the mbuf data regions directly in the transmit lists. We also save a 1505 * copy of the pointers since the transmit list fragment pointers are 1506 * physical addresses. 1507 */ 1508 1509static void 1510wb_start(ifp) 1511 struct ifnet *ifp; 1512{ 1513 struct wb_softc *sc; 1514 struct mbuf *m_head = NULL; 1515 struct wb_chain *cur_tx = NULL, *start_tx; 1516 1517 sc = ifp->if_softc; 1518 WB_LOCK(sc); 1519 1520 /* 1521 * Check for an available queue slot. If there are none, 1522 * punt. 1523 */ 1524 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1525 ifp->if_flags |= IFF_OACTIVE; 1526 WB_UNLOCK(sc); 1527 return; 1528 } 1529 1530 start_tx = sc->wb_cdata.wb_tx_free; 1531 1532 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1533 IF_DEQUEUE(&ifp->if_snd, m_head); 1534 if (m_head == NULL) 1535 break; 1536 1537 /* Pick a descriptor off the free list. */ 1538 cur_tx = sc->wb_cdata.wb_tx_free; 1539 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1540 1541 /* Pack the data into the descriptor. */ 1542 wb_encap(sc, cur_tx, m_head); 1543 1544 if (cur_tx != start_tx) 1545 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1546 1547 /* 1548 * If there's a BPF listener, bounce a copy of this frame 1549 * to him. 1550 */ 1551 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1552 } 1553 1554 /* 1555 * If there are no packets queued, bail. 1556 */ 1557 if (cur_tx == NULL) { 1558 WB_UNLOCK(sc); 1559 return; 1560 } 1561 1562 /* 1563 * Place the request for the upload interrupt 1564 * in the last descriptor in the chain. This way, if 1565 * we're chaining several packets at once, we'll only 1566 * get an interupt once for the whole chain rather than 1567 * once for each packet. 1568 */ 1569 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1570 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1571 sc->wb_cdata.wb_tx_tail = cur_tx; 1572 1573 if (sc->wb_cdata.wb_tx_head == NULL) { 1574 sc->wb_cdata.wb_tx_head = start_tx; 1575 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1576 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1577 } else { 1578 /* 1579 * We need to distinguish between the case where 1580 * the own bit is clear because the chip cleared it 1581 * and where the own bit is clear because we haven't 1582 * set it yet. The magic value WB_UNSET is just some 1583 * ramdomly chosen number which doesn't have the own 1584 * bit set. When we actually transmit the frame, the 1585 * status word will have _only_ the own bit set, so 1586 * the txeoc handler will be able to tell if it needs 1587 * to initiate another transmission to flush out pending 1588 * frames. 1589 */ 1590 WB_TXOWN(start_tx) = WB_UNSENT; 1591 } 1592 1593 /* 1594 * Set a timeout in case the chip goes out to lunch. 1595 */ 1596 ifp->if_timer = 5; 1597 WB_UNLOCK(sc); 1598 1599 return; 1600} 1601 1602static void 1603wb_init(xsc) 1604 void *xsc; 1605{ 1606 struct wb_softc *sc = xsc; 1607 struct ifnet *ifp = &sc->arpcom.ac_if; 1608 int i; 1609 struct mii_data *mii; 1610 1611 WB_LOCK(sc); 1612 mii = device_get_softc(sc->wb_miibus); 1613 1614 /* 1615 * Cancel pending I/O and free all RX/TX buffers. 1616 */ 1617 wb_stop(sc); 1618 wb_reset(sc); 1619 1620 sc->wb_txthresh = WB_TXTHRESH_INIT; 1621 1622 /* 1623 * Set cache alignment and burst length. 1624 */ 1625#ifdef foo 1626 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1627 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1628 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1629#endif 1630 1631 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1632 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1633 switch(sc->wb_cachesize) { 1634 case 32: 1635 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1636 break; 1637 case 16: 1638 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1639 break; 1640 case 8: 1641 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1642 break; 1643 case 0: 1644 default: 1645 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1646 break; 1647 } 1648 1649 /* This doesn't tend to work too well at 100Mbps. */ 1650 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1651 1652 /* Init our MAC address */ 1653 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1654 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1655 } 1656 1657 /* Init circular RX list. */ 1658 if (wb_list_rx_init(sc) == ENOBUFS) { 1659 printf("wb%d: initialization failed: no " 1660 "memory for rx buffers\n", sc->wb_unit); 1661 wb_stop(sc); 1662 WB_UNLOCK(sc); 1663 return; 1664 } 1665 1666 /* Init TX descriptors. */ 1667 wb_list_tx_init(sc); 1668 1669 /* If we want promiscuous mode, set the allframes bit. */ 1670 if (ifp->if_flags & IFF_PROMISC) { 1671 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1672 } else { 1673 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1674 } 1675 1676 /* 1677 * Set capture broadcast bit to capture broadcast frames. 1678 */ 1679 if (ifp->if_flags & IFF_BROADCAST) { 1680 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1681 } else { 1682 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1683 } 1684 1685 /* 1686 * Program the multicast filter, if necessary. 1687 */ 1688 wb_setmulti(sc); 1689 1690 /* 1691 * Load the address of the RX list. 1692 */ 1693 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1694 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1695 1696 /* 1697 * Enable interrupts. 1698 */ 1699 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1700 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1701 1702 /* Enable receiver and transmitter. */ 1703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1704 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1705 1706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1707 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1709 1710 mii_mediachg(mii); 1711 1712 ifp->if_flags |= IFF_RUNNING; 1713 ifp->if_flags &= ~IFF_OACTIVE; 1714 1715 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1716 WB_UNLOCK(sc); 1717 1718 return; 1719} 1720 1721/* 1722 * Set media options. 1723 */ 1724static int 1725wb_ifmedia_upd(ifp) 1726 struct ifnet *ifp; 1727{ 1728 struct wb_softc *sc; 1729 1730 sc = ifp->if_softc; 1731 1732 if (ifp->if_flags & IFF_UP) 1733 wb_init(sc); 1734 1735 return(0); 1736} 1737 1738/* 1739 * Report current media status. 1740 */ 1741static void 1742wb_ifmedia_sts(ifp, ifmr) 1743 struct ifnet *ifp; 1744 struct ifmediareq *ifmr; 1745{ 1746 struct wb_softc *sc; 1747 struct mii_data *mii; 1748 1749 sc = ifp->if_softc; 1750 1751 mii = device_get_softc(sc->wb_miibus); 1752 1753 mii_pollstat(mii); 1754 ifmr->ifm_active = mii->mii_media_active; 1755 ifmr->ifm_status = mii->mii_media_status; 1756 1757 return; 1758} 1759 1760static int 1761wb_ioctl(ifp, command, data) 1762 struct ifnet *ifp; 1763 u_long command; 1764 caddr_t data; 1765{ 1766 struct wb_softc *sc = ifp->if_softc; 1767 struct mii_data *mii; 1768 struct ifreq *ifr = (struct ifreq *) data; 1769 int error = 0; 1770 1771 WB_LOCK(sc); 1772 1773 switch(command) { 1774 case SIOCSIFFLAGS: 1775 if (ifp->if_flags & IFF_UP) { 1776 wb_init(sc); 1777 } else { 1778 if (ifp->if_flags & IFF_RUNNING) 1779 wb_stop(sc); 1780 } 1781 error = 0; 1782 break; 1783 case SIOCADDMULTI: 1784 case SIOCDELMULTI: 1785 wb_setmulti(sc); 1786 error = 0; 1787 break; 1788 case SIOCGIFMEDIA: 1789 case SIOCSIFMEDIA: 1790 mii = device_get_softc(sc->wb_miibus); 1791 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1792 break; 1793 default: 1794 error = ether_ioctl(ifp, command, data); 1795 break; 1796 } 1797 1798 WB_UNLOCK(sc); 1799 1800 return(error); 1801} 1802 1803static void 1804wb_watchdog(ifp) 1805 struct ifnet *ifp; 1806{ 1807 struct wb_softc *sc; 1808 1809 sc = ifp->if_softc; 1810 1811 WB_LOCK(sc); 1812 ifp->if_oerrors++; 1813 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1814#ifdef foo 1815 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1816 printf("wb%d: no carrier - transceiver cable problem?\n", 1817 sc->wb_unit); 1818#endif 1819 wb_stop(sc); 1820 wb_reset(sc); 1821 wb_init(sc); 1822 1823 if (ifp->if_snd.ifq_head != NULL) 1824 wb_start(ifp); 1825 WB_UNLOCK(sc); 1826 1827 return; 1828} 1829 1830/* 1831 * Stop the adapter and free any mbufs allocated to the 1832 * RX and TX lists. 1833 */ 1834static void 1835wb_stop(sc) 1836 struct wb_softc *sc; 1837{ 1838 register int i; 1839 struct ifnet *ifp; 1840 1841 WB_LOCK(sc); 1842 ifp = &sc->arpcom.ac_if; 1843 ifp->if_timer = 0; 1844 1845 untimeout(wb_tick, sc, sc->wb_stat_ch); 1846 1847 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1848 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1849 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1850 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1851 1852 /* 1853 * Free data in the RX lists. 1854 */ 1855 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1856 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1857 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1858 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1859 } 1860 } 1861 bzero((char *)&sc->wb_ldata->wb_rx_list, 1862 sizeof(sc->wb_ldata->wb_rx_list)); 1863 1864 /* 1865 * Free the TX list buffers. 1866 */ 1867 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1868 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1869 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1870 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1871 } 1872 } 1873 1874 bzero((char *)&sc->wb_ldata->wb_tx_list, 1875 sizeof(sc->wb_ldata->wb_tx_list)); 1876 1877 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1878 WB_UNLOCK(sc); 1879 1880 return; 1881} 1882 1883/* 1884 * Stop all chip I/O so that the kernel's probe routines don't 1885 * get confused by errant DMAs when rebooting. 1886 */ 1887static void 1888wb_shutdown(dev) 1889 device_t dev; 1890{ 1891 struct wb_softc *sc; 1892 1893 sc = device_get_softc(dev); 1894 wb_stop(sc); 1895 1896 return; 1897} 1898