if_wb.c revision 113038
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 3341502Swpaul/* 3441502Swpaul * Winbond fast ethernet PCI NIC driver 3541502Swpaul * 3641502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3741502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 3841502Swpaul * Winbond itself and some made by Linksys. 3941502Swpaul * 4041502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4141502Swpaul * Electrical Engineering Department 4241502Swpaul * Columbia University, New York City 4341502Swpaul */ 4441502Swpaul 4541502Swpaul/* 4641502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4741502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 4841502Swpaul * one major difference which is that while the registers do many of 4941502Swpaul * the same things as a tulip adapter, the offsets are different: where 5041502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5141502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5241502Swpaul * programmed differently. 5341502Swpaul * 5441502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5541502Swpaul * a status word, a control word and 32-bit areas that can either be used 5641502Swpaul * to point to two external data blocks, or to point to a single block 5741502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 5841502Swpaul * together in blocks to form fixed length rings or can be chained 5941502Swpaul * together in linked lists. A single packet may be spread out over 6041502Swpaul * several descriptors if necessary. 6141502Swpaul * 6241502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6341502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6441502Swpaul * to hold an entire packet. The link list is looped back to created a 6541502Swpaul * closed ring. 6641502Swpaul * 6741502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 6841502Swpaul * which each contain several individual descriptors linked toghether. 6941502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7041502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7141502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7241502Swpaul * drivers. 7341502Swpaul * 7441502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7541502Swpaul * The sample boards I have all use a Davicom PHY. 7641502Swpaul * 7741502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 7841502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 7941502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8041502Swpaul * I have no idea what he's on about: transmit performance with all 8141502Swpaul * three of my test boards seems fine. 8241502Swpaul */ 8341502Swpaul 84113038Sobrien#include <sys/cdefs.h> 85113038Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 113038 2003-04-03 21:36:33Z obrien $"); 86113038Sobrien 8748745Swpaul#include "opt_bdg.h" 8841502Swpaul 8941502Swpaul#include <sys/param.h> 9041502Swpaul#include <sys/systm.h> 9141502Swpaul#include <sys/sockio.h> 9241502Swpaul#include <sys/mbuf.h> 9341502Swpaul#include <sys/malloc.h> 9441502Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9650675Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 10141502Swpaul#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 10341502Swpaul 10441502Swpaul#include <net/bpf.h> 10541502Swpaul 10641502Swpaul#include <vm/vm.h> /* for vtophys */ 10741502Swpaul#include <vm/pmap.h> /* for vtophys */ 10841502Swpaul#include <machine/bus_memio.h> 10941502Swpaul#include <machine/bus_pio.h> 11041502Swpaul#include <machine/bus.h> 11149611Swpaul#include <machine/resource.h> 11249611Swpaul#include <sys/bus.h> 11349611Swpaul#include <sys/rman.h> 11441502Swpaul 11541502Swpaul#include <pci/pcireg.h> 11641502Swpaul#include <pci/pcivar.h> 11741502Swpaul 11850675Swpaul#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250675Swpaul#include "miibus_if.h" 12350675Swpaul 12441502Swpaul#define WB_USEIOSPACE 12541502Swpaul 12641502Swpaul#include <pci/if_wbreg.h> 12741502Swpaul 12859758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12959758Speter 13041502Swpaul/* 13141502Swpaul * Various supported device vendors/types and their names. 13241502Swpaul */ 13341502Swpaulstatic struct wb_type wb_devs[] = { 13441502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13541502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13641502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13741502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13841502Swpaul { 0, 0, NULL } 13941502Swpaul}; 14041502Swpaul 14192739Salfredstatic int wb_probe (device_t); 14292739Salfredstatic int wb_attach (device_t); 14392739Salfredstatic int wb_detach (device_t); 14441502Swpaul 14598995Salfredstatic void wb_bfree (void *addr, void *args); 14692739Salfredstatic int wb_newbuf (struct wb_softc *, 14748745Swpaul struct wb_chain_onefrag *, 14892739Salfred struct mbuf *); 14992739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15092739Salfred struct mbuf *); 15141502Swpaul 15292739Salfredstatic void wb_rxeof (struct wb_softc *); 15392739Salfredstatic void wb_rxeoc (struct wb_softc *); 15492739Salfredstatic void wb_txeof (struct wb_softc *); 15592739Salfredstatic void wb_txeoc (struct wb_softc *); 15692739Salfredstatic void wb_intr (void *); 15792739Salfredstatic void wb_tick (void *); 15892739Salfredstatic void wb_start (struct ifnet *); 15992739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16092739Salfredstatic void wb_init (void *); 16192739Salfredstatic void wb_stop (struct wb_softc *); 16292739Salfredstatic void wb_watchdog (struct ifnet *); 16392739Salfredstatic void wb_shutdown (device_t); 16492739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16592739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16641502Swpaul 16792739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 16892739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 16992739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17092739Salfredstatic void wb_mii_sync (struct wb_softc *); 17192739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17292739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17392739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17441502Swpaul 17592739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 17692739Salfredstatic u_int8_t wb_calchash (caddr_t); 17792739Salfredstatic void wb_setmulti (struct wb_softc *); 17892739Salfredstatic void wb_reset (struct wb_softc *); 17992739Salfredstatic void wb_fixmedia (struct wb_softc *); 18092739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18192739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18241502Swpaul 18392739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18492739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18592739Salfredstatic void wb_miibus_statchg (device_t); 18650675Swpaul 18749611Swpaul#ifdef WB_USEIOSPACE 18849611Swpaul#define WB_RES SYS_RES_IOPORT 18949611Swpaul#define WB_RID WB_PCI_LOIO 19049611Swpaul#else 19149611Swpaul#define WB_RES SYS_RES_MEMORY 19249611Swpaul#define WB_RID WB_PCI_LOMEM 19349611Swpaul#endif 19449611Swpaul 19549611Swpaulstatic device_method_t wb_methods[] = { 19649611Swpaul /* Device interface */ 19749611Swpaul DEVMETHOD(device_probe, wb_probe), 19849611Swpaul DEVMETHOD(device_attach, wb_attach), 19949611Swpaul DEVMETHOD(device_detach, wb_detach), 20049611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20150675Swpaul 20250675Swpaul /* bus interface, for miibus */ 20350675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20450675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20550675Swpaul 20650675Swpaul /* MII interface */ 20750675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20850675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 20950675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21049611Swpaul { 0, 0 } 21149611Swpaul}; 21249611Swpaul 21349611Swpaulstatic driver_t wb_driver = { 21451455Swpaul "wb", 21549611Swpaul wb_methods, 21649611Swpaul sizeof(struct wb_softc) 21749611Swpaul}; 21849611Swpaul 21949611Swpaulstatic devclass_t wb_devclass; 22049611Swpaul 22151533SwpaulDRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 22251473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22349611Swpaul 22441502Swpaul#define WB_SETBIT(sc, reg, x) \ 22541502Swpaul CSR_WRITE_4(sc, reg, \ 226105221Sphk CSR_READ_4(sc, reg) | (x)) 22741502Swpaul 22841502Swpaul#define WB_CLRBIT(sc, reg, x) \ 22941502Swpaul CSR_WRITE_4(sc, reg, \ 230105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23141502Swpaul 23241502Swpaul#define SIO_SET(x) \ 23341502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 234105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23541502Swpaul 23641502Swpaul#define SIO_CLR(x) \ 23741502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 238105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 23941502Swpaul 24041502Swpaul/* 24141502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24241502Swpaul */ 243102336Salfredstatic void 244102336Salfredwb_eeprom_putbyte(sc, addr) 24541502Swpaul struct wb_softc *sc; 24642718Swpaul int addr; 24741502Swpaul{ 24841502Swpaul register int d, i; 24941502Swpaul 25041502Swpaul d = addr | WB_EECMD_READ; 25141502Swpaul 25241502Swpaul /* 25341502Swpaul * Feed in each bit and stobe the clock. 25441502Swpaul */ 25541502Swpaul for (i = 0x400; i; i >>= 1) { 25641502Swpaul if (d & i) { 25741502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25841502Swpaul } else { 25941502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26041502Swpaul } 26141502Swpaul DELAY(100); 26241502Swpaul SIO_SET(WB_SIO_EE_CLK); 26341502Swpaul DELAY(150); 26441502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26541502Swpaul DELAY(100); 26641502Swpaul } 26741502Swpaul 26841502Swpaul return; 26941502Swpaul} 27041502Swpaul 27141502Swpaul/* 27241502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27341502Swpaul */ 274102336Salfredstatic void 275102336Salfredwb_eeprom_getword(sc, addr, dest) 27641502Swpaul struct wb_softc *sc; 27742718Swpaul int addr; 27841502Swpaul u_int16_t *dest; 27941502Swpaul{ 28041502Swpaul register int i; 28141502Swpaul u_int16_t word = 0; 28241502Swpaul 28341502Swpaul /* Enter EEPROM access mode. */ 28441502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28541502Swpaul 28641502Swpaul /* 28741502Swpaul * Send address of word we want to read. 28841502Swpaul */ 28941502Swpaul wb_eeprom_putbyte(sc, addr); 29041502Swpaul 29141502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29241502Swpaul 29341502Swpaul /* 29441502Swpaul * Start reading bits from EEPROM. 29541502Swpaul */ 29641502Swpaul for (i = 0x8000; i; i >>= 1) { 29741502Swpaul SIO_SET(WB_SIO_EE_CLK); 29841502Swpaul DELAY(100); 29941502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30041502Swpaul word |= i; 30141502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30241502Swpaul DELAY(100); 30341502Swpaul } 30441502Swpaul 30541502Swpaul /* Turn off EEPROM access mode. */ 30641502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30741502Swpaul 30841502Swpaul *dest = word; 30941502Swpaul 31041502Swpaul return; 31141502Swpaul} 31241502Swpaul 31341502Swpaul/* 31441502Swpaul * Read a sequence of words from the EEPROM. 31541502Swpaul */ 316102336Salfredstatic void 317102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31841502Swpaul struct wb_softc *sc; 31941502Swpaul caddr_t dest; 32041502Swpaul int off; 32141502Swpaul int cnt; 32241502Swpaul int swap; 32341502Swpaul{ 32441502Swpaul int i; 32541502Swpaul u_int16_t word = 0, *ptr; 32641502Swpaul 32741502Swpaul for (i = 0; i < cnt; i++) { 32841502Swpaul wb_eeprom_getword(sc, off + i, &word); 32941502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33041502Swpaul if (swap) 33141502Swpaul *ptr = ntohs(word); 33241502Swpaul else 33341502Swpaul *ptr = word; 33441502Swpaul } 33541502Swpaul 33641502Swpaul return; 33741502Swpaul} 33841502Swpaul 33941502Swpaul/* 34041502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34141502Swpaul */ 342102336Salfredstatic void 343102336Salfredwb_mii_sync(sc) 34441502Swpaul struct wb_softc *sc; 34541502Swpaul{ 34641502Swpaul register int i; 34741502Swpaul 34841502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 34941502Swpaul 35041502Swpaul for (i = 0; i < 32; i++) { 35141502Swpaul SIO_SET(WB_SIO_MII_CLK); 35241502Swpaul DELAY(1); 35341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35441502Swpaul DELAY(1); 35541502Swpaul } 35641502Swpaul 35741502Swpaul return; 35841502Swpaul} 35941502Swpaul 36041502Swpaul/* 36141502Swpaul * Clock a series of bits through the MII. 36241502Swpaul */ 363102336Salfredstatic void 364102336Salfredwb_mii_send(sc, bits, cnt) 36541502Swpaul struct wb_softc *sc; 36641502Swpaul u_int32_t bits; 36741502Swpaul int cnt; 36841502Swpaul{ 36941502Swpaul int i; 37041502Swpaul 37141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37241502Swpaul 37341502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37441502Swpaul if (bits & i) { 37541502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37641502Swpaul } else { 37741502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37841502Swpaul } 37941502Swpaul DELAY(1); 38041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38141502Swpaul DELAY(1); 38241502Swpaul SIO_SET(WB_SIO_MII_CLK); 38341502Swpaul } 38441502Swpaul} 38541502Swpaul 38641502Swpaul/* 38741502Swpaul * Read an PHY register through the MII. 38841502Swpaul */ 389102336Salfredstatic int 390102336Salfredwb_mii_readreg(sc, frame) 39141502Swpaul struct wb_softc *sc; 39241502Swpaul struct wb_mii_frame *frame; 39341502Swpaul 39441502Swpaul{ 39567087Swpaul int i, ack; 39641502Swpaul 39767087Swpaul WB_LOCK(sc); 39841502Swpaul 39941502Swpaul /* 40041502Swpaul * Set up frame for RX. 40141502Swpaul */ 40241502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40341502Swpaul frame->mii_opcode = WB_MII_READOP; 40441502Swpaul frame->mii_turnaround = 0; 40541502Swpaul frame->mii_data = 0; 40641502Swpaul 40741502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40841502Swpaul 40941502Swpaul /* 41041502Swpaul * Turn on data xmit. 41141502Swpaul */ 41241502Swpaul SIO_SET(WB_SIO_MII_DIR); 41341502Swpaul 41441502Swpaul wb_mii_sync(sc); 41541502Swpaul 41641502Swpaul /* 41741502Swpaul * Send command/address info. 41841502Swpaul */ 41941502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42041502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42141502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42241502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42341502Swpaul 42441502Swpaul /* Idle bit */ 42541502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42641502Swpaul DELAY(1); 42741502Swpaul SIO_SET(WB_SIO_MII_CLK); 42841502Swpaul DELAY(1); 42941502Swpaul 43041502Swpaul /* Turn off xmit. */ 43141502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43241502Swpaul /* Check for ack */ 43341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43441502Swpaul DELAY(1); 435109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43641502Swpaul SIO_SET(WB_SIO_MII_CLK); 43741502Swpaul DELAY(1); 43841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul SIO_SET(WB_SIO_MII_CLK); 44141502Swpaul DELAY(1); 44241502Swpaul 44341502Swpaul /* 44441502Swpaul * Now try reading data bits. If the ack failed, we still 44541502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44641502Swpaul */ 44741502Swpaul if (ack) { 44841502Swpaul for(i = 0; i < 16; i++) { 44941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45041502Swpaul DELAY(1); 45141502Swpaul SIO_SET(WB_SIO_MII_CLK); 45241502Swpaul DELAY(1); 45341502Swpaul } 45441502Swpaul goto fail; 45541502Swpaul } 45641502Swpaul 45741502Swpaul for (i = 0x8000; i; i >>= 1) { 45841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45941502Swpaul DELAY(1); 46041502Swpaul if (!ack) { 46141502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46241502Swpaul frame->mii_data |= i; 46341502Swpaul DELAY(1); 46441502Swpaul } 46541502Swpaul SIO_SET(WB_SIO_MII_CLK); 46641502Swpaul DELAY(1); 46741502Swpaul } 46841502Swpaul 46941502Swpaulfail: 47041502Swpaul 47141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47241502Swpaul DELAY(1); 47341502Swpaul SIO_SET(WB_SIO_MII_CLK); 47441502Swpaul DELAY(1); 47541502Swpaul 47667087Swpaul WB_UNLOCK(sc); 47741502Swpaul 47841502Swpaul if (ack) 47941502Swpaul return(1); 48041502Swpaul return(0); 48141502Swpaul} 48241502Swpaul 48341502Swpaul/* 48441502Swpaul * Write to a PHY register through the MII. 48541502Swpaul */ 486102336Salfredstatic int 487102336Salfredwb_mii_writereg(sc, frame) 48841502Swpaul struct wb_softc *sc; 48941502Swpaul struct wb_mii_frame *frame; 49041502Swpaul 49141502Swpaul{ 49267087Swpaul WB_LOCK(sc); 49341502Swpaul 49441502Swpaul /* 49541502Swpaul * Set up frame for TX. 49641502Swpaul */ 49741502Swpaul 49841502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49941502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50041502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50141502Swpaul 50241502Swpaul /* 50341502Swpaul * Turn on data output. 50441502Swpaul */ 50541502Swpaul SIO_SET(WB_SIO_MII_DIR); 50641502Swpaul 50741502Swpaul wb_mii_sync(sc); 50841502Swpaul 50941502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51041502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51141502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51241502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51341502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51441502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51541502Swpaul 51641502Swpaul /* Idle bit. */ 51741502Swpaul SIO_SET(WB_SIO_MII_CLK); 51841502Swpaul DELAY(1); 51941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52041502Swpaul DELAY(1); 52141502Swpaul 52241502Swpaul /* 52341502Swpaul * Turn off xmit. 52441502Swpaul */ 52541502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52641502Swpaul 52767087Swpaul WB_UNLOCK(sc); 52841502Swpaul 52941502Swpaul return(0); 53041502Swpaul} 53141502Swpaul 532102336Salfredstatic int 533102336Salfredwb_miibus_readreg(dev, phy, reg) 53450675Swpaul device_t dev; 53550675Swpaul int phy, reg; 53650675Swpaul{ 53741502Swpaul struct wb_softc *sc; 53841502Swpaul struct wb_mii_frame frame; 53941502Swpaul 54050675Swpaul sc = device_get_softc(dev); 54150675Swpaul 54241502Swpaul bzero((char *)&frame, sizeof(frame)); 54341502Swpaul 54450675Swpaul frame.mii_phyaddr = phy; 54541502Swpaul frame.mii_regaddr = reg; 54641502Swpaul wb_mii_readreg(sc, &frame); 54741502Swpaul 54841502Swpaul return(frame.mii_data); 54941502Swpaul} 55041502Swpaul 551102336Salfredstatic int 552102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55350675Swpaul device_t dev; 55450675Swpaul int phy, reg, data; 55550675Swpaul{ 55641502Swpaul struct wb_softc *sc; 55741502Swpaul struct wb_mii_frame frame; 55841502Swpaul 55950675Swpaul sc = device_get_softc(dev); 56050675Swpaul 56141502Swpaul bzero((char *)&frame, sizeof(frame)); 56241502Swpaul 56350675Swpaul frame.mii_phyaddr = phy; 56441502Swpaul frame.mii_regaddr = reg; 56541502Swpaul frame.mii_data = data; 56641502Swpaul 56741502Swpaul wb_mii_writereg(sc, &frame); 56841502Swpaul 56950675Swpaul return(0); 57050675Swpaul} 57150675Swpaul 572102336Salfredstatic void 573102336Salfredwb_miibus_statchg(dev) 57450675Swpaul device_t dev; 57550675Swpaul{ 57650675Swpaul struct wb_softc *sc; 57750675Swpaul struct mii_data *mii; 57850675Swpaul 57950675Swpaul sc = device_get_softc(dev); 58067087Swpaul WB_LOCK(sc); 58150675Swpaul mii = device_get_softc(sc->wb_miibus); 58250675Swpaul wb_setcfg(sc, mii->mii_media_active); 58367087Swpaul WB_UNLOCK(sc); 58450675Swpaul 58541502Swpaul return; 58641502Swpaul} 58741502Swpaul 58841502Swpaulstatic u_int8_t wb_calchash(addr) 58942718Swpaul caddr_t addr; 59041502Swpaul{ 59141502Swpaul u_int32_t crc, carry; 59241502Swpaul int i, j; 59341502Swpaul u_int8_t c; 59441502Swpaul 59541502Swpaul /* Compute CRC for the address value. */ 59641502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59741502Swpaul 59841502Swpaul for (i = 0; i < 6; i++) { 59941502Swpaul c = *(addr + i); 60041502Swpaul for (j = 0; j < 8; j++) { 60141502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 60241502Swpaul crc <<= 1; 60341502Swpaul c >>= 1; 60441502Swpaul if (carry) 60541502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60641502Swpaul } 60741502Swpaul } 60841502Swpaul 60941502Swpaul /* 61041502Swpaul * return the filter bit position 61141502Swpaul * Note: I arrived at the following nonsense 61241502Swpaul * through experimentation. It's not the usual way to 61341502Swpaul * generate the bit position but it's the only thing 61441502Swpaul * I could come up with that works. 61541502Swpaul */ 61641502Swpaul return(~(crc >> 26) & 0x0000003F); 61741502Swpaul} 61841502Swpaul 61941502Swpaul/* 62041502Swpaul * Program the 64-bit multicast hash filter. 62141502Swpaul */ 622102336Salfredstatic void 623102336Salfredwb_setmulti(sc) 62441502Swpaul struct wb_softc *sc; 62541502Swpaul{ 62641502Swpaul struct ifnet *ifp; 62741502Swpaul int h = 0; 62841502Swpaul u_int32_t hashes[2] = { 0, 0 }; 62941502Swpaul struct ifmultiaddr *ifma; 63041502Swpaul u_int32_t rxfilt; 63141502Swpaul int mcnt = 0; 63241502Swpaul 63341502Swpaul ifp = &sc->arpcom.ac_if; 63441502Swpaul 63541502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63641502Swpaul 63741502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63841502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64241502Swpaul return; 64341502Swpaul } 64441502Swpaul 64541502Swpaul /* first, zot all the existing hash bits */ 64641502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64741502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64841502Swpaul 64941502Swpaul /* now program new ones */ 65072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65141502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65241502Swpaul continue; 65341502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65441502Swpaul if (h < 32) 65541502Swpaul hashes[0] |= (1 << h); 65641502Swpaul else 65741502Swpaul hashes[1] |= (1 << (h - 32)); 65841502Swpaul mcnt++; 65941502Swpaul } 66041502Swpaul 66141502Swpaul if (mcnt) 66241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66341502Swpaul else 66441502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66541502Swpaul 66641502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66741502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66841502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 66941502Swpaul 67041502Swpaul return; 67141502Swpaul} 67241502Swpaul 67341502Swpaul/* 67441502Swpaul * The Winbond manual states that in order to fiddle with the 67541502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67641502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67741502Swpaul */ 678102336Salfredstatic void 679102336Salfredwb_setcfg(sc, media) 68041502Swpaul struct wb_softc *sc; 68150675Swpaul u_int32_t media; 68241502Swpaul{ 68341502Swpaul int i, restart = 0; 68441502Swpaul 68541502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68641502Swpaul restart = 1; 68741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68841502Swpaul 68941502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69041502Swpaul DELAY(10); 69141502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69241502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69341502Swpaul break; 69441502Swpaul } 69541502Swpaul 69641502Swpaul if (i == WB_TIMEOUT) 69741502Swpaul printf("wb%d: failed to force tx and " 69841502Swpaul "rx to idle state\n", sc->wb_unit); 69941502Swpaul } 70041502Swpaul 70150675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70250675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70350675Swpaul else 70441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70541502Swpaul 70650675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70841502Swpaul else 70941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71041502Swpaul 71141502Swpaul if (restart) 71241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71341502Swpaul 71441502Swpaul return; 71541502Swpaul} 71641502Swpaul 717102336Salfredstatic void 718102336Salfredwb_reset(sc) 71941502Swpaul struct wb_softc *sc; 72041502Swpaul{ 72141502Swpaul register int i; 72250675Swpaul struct mii_data *mii; 72341502Swpaul 72450675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72650675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72850675Swpaul 72941502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73141502Swpaul 73241502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73341502Swpaul DELAY(10); 73441502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73541502Swpaul break; 73641502Swpaul } 73741502Swpaul if (i == WB_TIMEOUT) 73841502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 73941502Swpaul 74041502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74141502Swpaul DELAY(1000); 74241502Swpaul 74350675Swpaul if (sc->wb_miibus == NULL) 74450675Swpaul return; 74541502Swpaul 74650675Swpaul mii = device_get_softc(sc->wb_miibus); 74750675Swpaul if (mii == NULL) 74850675Swpaul return; 74950675Swpaul 75050675Swpaul if (mii->mii_instance) { 75150675Swpaul struct mii_softc *miisc; 75272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75350675Swpaul mii_phy_reset(miisc); 75450675Swpaul } 75550675Swpaul 75641502Swpaul return; 75741502Swpaul} 75841502Swpaul 759102336Salfredstatic void 760102336Salfredwb_fixmedia(sc) 76150675Swpaul struct wb_softc *sc; 76250675Swpaul{ 76350675Swpaul struct mii_data *mii = NULL; 76450675Swpaul struct ifnet *ifp; 76550675Swpaul u_int32_t media; 76650675Swpaul 76750675Swpaul if (sc->wb_miibus == NULL) 76850675Swpaul return; 76950675Swpaul 77050675Swpaul mii = device_get_softc(sc->wb_miibus); 77150675Swpaul ifp = &sc->arpcom.ac_if; 77250675Swpaul 77350675Swpaul mii_pollstat(mii); 77450675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77550675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77650675Swpaul media |= IFM_100_TX; 77750675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 77850675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 77950675Swpaul media |= IFM_10_T; 78050675Swpaul } else 78150675Swpaul return; 78250675Swpaul 78350675Swpaul ifmedia_set(&mii->mii_media, media); 78450675Swpaul 78550675Swpaul return; 78650675Swpaul} 78750675Swpaul 78841502Swpaul/* 78941502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79041502Swpaul * IDs against our list and return a device name if we find a match. 79141502Swpaul */ 792102336Salfredstatic int 793102336Salfredwb_probe(dev) 79449611Swpaul device_t dev; 79541502Swpaul{ 79641502Swpaul struct wb_type *t; 79741502Swpaul 79841502Swpaul t = wb_devs; 79941502Swpaul 80041502Swpaul while(t->wb_name != NULL) { 80149611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80249611Swpaul (pci_get_device(dev) == t->wb_did)) { 80349611Swpaul device_set_desc(dev, t->wb_name); 80449611Swpaul return(0); 80541502Swpaul } 80641502Swpaul t++; 80741502Swpaul } 80841502Swpaul 80949611Swpaul return(ENXIO); 81041502Swpaul} 81141502Swpaul 81241502Swpaul/* 81341502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81441502Swpaul * setup and ethernet/BPF attach. 81541502Swpaul */ 816102336Salfredstatic int 817102336Salfredwb_attach(dev) 81849611Swpaul device_t dev; 81941502Swpaul{ 82041502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82141502Swpaul u_int32_t command; 82241502Swpaul struct wb_softc *sc; 82341502Swpaul struct ifnet *ifp; 82449611Swpaul int unit, error = 0, rid; 82541502Swpaul 82649611Swpaul sc = device_get_softc(dev); 82749611Swpaul unit = device_get_unit(dev); 82841502Swpaul 82993818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83093818Sjhb MTX_DEF | MTX_RECURSE); 83169583Swpaul 83241502Swpaul /* 83341502Swpaul * Handle power management nonsense. 83441502Swpaul */ 83541502Swpaul 83672813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83772813Swpaul u_int32_t iobase, membase, irq; 83841502Swpaul 83972813Swpaul /* Save important PCI config data. */ 84072813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84172813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84272813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84341502Swpaul 84472813Swpaul /* Reset the power state. */ 84572813Swpaul printf("wb%d: chip is in D%d power mode " 84672813Swpaul "-- setting to D0\n", unit, 84772813Swpaul pci_get_powerstate(dev)); 84872813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 84941502Swpaul 85072813Swpaul /* Restore PCI config data. */ 85172813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85272813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85372813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85441502Swpaul } 85541502Swpaul 85641502Swpaul /* 85741502Swpaul * Map control/status registers. 85841502Swpaul */ 85972813Swpaul pci_enable_busmaster(dev); 86079472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 86179472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 86261041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 86341502Swpaul 86441502Swpaul#ifdef WB_USEIOSPACE 86541502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 86641502Swpaul printf("wb%d: failed to enable I/O ports!\n", unit); 86749611Swpaul error = ENXIO; 86841502Swpaul goto fail; 86941502Swpaul } 87041502Swpaul#else 87141502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 87241502Swpaul printf("wb%d: failed to enable memory mapping!\n", unit); 87349611Swpaul error = ENXIO; 87441502Swpaul goto fail; 87541502Swpaul } 87649611Swpaul#endif 87741502Swpaul 87849611Swpaul rid = WB_RID; 87949611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 88049611Swpaul 0, ~0, 1, RF_ACTIVE); 88149611Swpaul 88249611Swpaul if (sc->wb_res == NULL) { 88349611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 88449611Swpaul error = ENXIO; 88541502Swpaul goto fail; 88641502Swpaul } 88741502Swpaul 88849611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 88949611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 89049611Swpaul 89141502Swpaul /* Allocate interrupt */ 89249611Swpaul rid = 0; 89349611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 89449611Swpaul RF_SHAREABLE | RF_ACTIVE); 89549611Swpaul 89649611Swpaul if (sc->wb_irq == NULL) { 89741502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 89849611Swpaul error = ENXIO; 89941502Swpaul goto fail; 90041502Swpaul } 90141502Swpaul 90250675Swpaul /* Save the cache line size. */ 90350675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 90450675Swpaul 90541502Swpaul /* Reset the adapter. */ 90641502Swpaul wb_reset(sc); 90741502Swpaul 90841502Swpaul /* 90941502Swpaul * Get station address from the EEPROM. 91041502Swpaul */ 91141502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 91241502Swpaul 91341502Swpaul /* 91441502Swpaul * A Winbond chip was detected. Inform the world. 91541502Swpaul */ 91641502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 91741502Swpaul 91841502Swpaul sc->wb_unit = unit; 91941502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 92041502Swpaul 92150675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 92251657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 92350675Swpaul 92450675Swpaul if (sc->wb_ldata == NULL) { 92541502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 92649611Swpaul error = ENXIO; 92749611Swpaul goto fail; 92841502Swpaul } 92941502Swpaul 93041502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 93141502Swpaul 93241502Swpaul ifp = &sc->arpcom.ac_if; 93341502Swpaul ifp->if_softc = sc; 93441502Swpaul ifp->if_unit = unit; 93541502Swpaul ifp->if_name = "wb"; 93641502Swpaul ifp->if_mtu = ETHERMTU; 93741502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 93841502Swpaul ifp->if_ioctl = wb_ioctl; 93941502Swpaul ifp->if_output = ether_output; 94041502Swpaul ifp->if_start = wb_start; 94141502Swpaul ifp->if_watchdog = wb_watchdog; 94241502Swpaul ifp->if_init = wb_init; 94341502Swpaul ifp->if_baudrate = 10000000; 94443515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 94541502Swpaul 94650675Swpaul /* 94750675Swpaul * Do MII setup. 94850675Swpaul */ 94950675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 95050675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 95149611Swpaul error = ENXIO; 95241502Swpaul goto fail; 95341502Swpaul } 95441502Swpaul 95541502Swpaul /* 95663090Sarchie * Call MI attach routine. 95741502Swpaul */ 958106936Ssam ether_ifattach(ifp, eaddr); 95941502Swpaul 960112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 961112872Snjl wb_intr, sc, &sc->wb_intrhand); 962112872Snjl 963112872Snjl if (error) { 964112872Snjl printf("wb%d: couldn't set up irq\n", unit); 965112872Snjl goto fail; 966112872Snjl } 967112872Snjl 96841502Swpaulfail: 96950675Swpaul if (error) 970112872Snjl wb_detach(dev); 97150675Swpaul 97249611Swpaul return(error); 97341502Swpaul} 97441502Swpaul 975102336Salfredstatic int 976102336Salfredwb_detach(dev) 97749611Swpaul device_t dev; 97849611Swpaul{ 97949611Swpaul struct wb_softc *sc; 98049611Swpaul struct ifnet *ifp; 98149611Swpaul 98249611Swpaul sc = device_get_softc(dev); 983112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 98467087Swpaul WB_LOCK(sc); 98549611Swpaul ifp = &sc->arpcom.ac_if; 98649611Swpaul 98750675Swpaul /* Delete any miibus and phy devices attached to this interface */ 988112872Snjl if (device_is_alive(dev)) { 989112872Snjl if (bus_child_present(dev)) 990112872Snjl wb_stop(sc); 991112872Snjl ether_ifdetach(ifp); 992112872Snjl device_delete_child(dev, sc->wb_miibus); 993112872Snjl bus_generic_detach(dev); 994112872Snjl } 99550675Swpaul 996112872Snjl if (sc->wb_intrhand) 997112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 998112872Snjl if (sc->wb_irq) 999112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1000112872Snjl if (sc->wb_res) 1001112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 100249611Swpaul 1003112872Snjl if (sc->wb_ldata) { 1004112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1005112872Snjl M_DEVBUF); 1006112872Snjl } 100749611Swpaul 100867087Swpaul WB_UNLOCK(sc); 100967087Swpaul mtx_destroy(&sc->wb_mtx); 101049611Swpaul 101149611Swpaul return(0); 101249611Swpaul} 101349611Swpaul 101441502Swpaul/* 101541502Swpaul * Initialize the transmit descriptors. 101641502Swpaul */ 1017102336Salfredstatic int 1018102336Salfredwb_list_tx_init(sc) 101941502Swpaul struct wb_softc *sc; 102041502Swpaul{ 102141502Swpaul struct wb_chain_data *cd; 102241502Swpaul struct wb_list_data *ld; 102341502Swpaul int i; 102441502Swpaul 102541502Swpaul cd = &sc->wb_cdata; 102641502Swpaul ld = sc->wb_ldata; 102741502Swpaul 102841502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102941502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 103041502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 103141502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103241502Swpaul &cd->wb_tx_chain[0]; 103341502Swpaul } else { 103441502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103541502Swpaul &cd->wb_tx_chain[i + 1]; 103641502Swpaul } 103741502Swpaul } 103841502Swpaul 103941502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 104041502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 104141502Swpaul 104241502Swpaul return(0); 104341502Swpaul} 104441502Swpaul 104541502Swpaul 104641502Swpaul/* 104741502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104841502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104941502Swpaul * points back to the first. 105041502Swpaul */ 1051102336Salfredstatic int 1052102336Salfredwb_list_rx_init(sc) 105341502Swpaul struct wb_softc *sc; 105441502Swpaul{ 105541502Swpaul struct wb_chain_data *cd; 105641502Swpaul struct wb_list_data *ld; 105741502Swpaul int i; 105841502Swpaul 105941502Swpaul cd = &sc->wb_cdata; 106041502Swpaul ld = sc->wb_ldata; 106141502Swpaul 106241502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 106341502Swpaul cd->wb_rx_chain[i].wb_ptr = 106441502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 106550675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106648745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106741502Swpaul return(ENOBUFS); 106841502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 107041502Swpaul ld->wb_rx_list[i].wb_next = 107141502Swpaul vtophys(&ld->wb_rx_list[0]); 107241502Swpaul } else { 107341502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 107441502Swpaul &cd->wb_rx_chain[i + 1]; 107541502Swpaul ld->wb_rx_list[i].wb_next = 107641502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107741502Swpaul } 107841502Swpaul } 107941502Swpaul 108041502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 108141502Swpaul 108241502Swpaul return(0); 108341502Swpaul} 108441502Swpaul 1085102336Salfredstatic void 1086102336Salfredwb_bfree(buf, args) 108798995Salfred void *buf; 108864837Sdwmalone void *args; 108950675Swpaul{ 109050675Swpaul return; 109150675Swpaul} 109250675Swpaul 109341502Swpaul/* 109441502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 109541502Swpaul */ 1096102336Salfredstatic int 1097102336Salfredwb_newbuf(sc, c, m) 109841502Swpaul struct wb_softc *sc; 109941502Swpaul struct wb_chain_onefrag *c; 110048745Swpaul struct mbuf *m; 110141502Swpaul{ 110241502Swpaul struct mbuf *m_new = NULL; 110341502Swpaul 110448745Swpaul if (m == NULL) { 1105111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110687846Sluigi if (m_new == NULL) 110748745Swpaul return(ENOBUFS); 110864837Sdwmalone m_new->m_data = c->wb_buf; 110964837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 111068621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 111168621Sbmilekic EXT_NET_DRV); 111248745Swpaul } else { 111348745Swpaul m_new = m; 111450675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 111548745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111641502Swpaul } 111741502Swpaul 111848745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111948745Swpaul 112041502Swpaul c->wb_mbuf = m_new; 112141502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 112250675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 112341502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 112441502Swpaul 112541502Swpaul return(0); 112641502Swpaul} 112741502Swpaul 112841502Swpaul/* 112941502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 113041502Swpaul * the higher level protocols. 113141502Swpaul */ 1132102336Salfredstatic void 1133102336Salfredwb_rxeof(sc) 113441502Swpaul struct wb_softc *sc; 113541502Swpaul{ 113650675Swpaul struct mbuf *m = NULL; 113741502Swpaul struct ifnet *ifp; 113841502Swpaul struct wb_chain_onefrag *cur_rx; 113941502Swpaul int total_len = 0; 114041502Swpaul u_int32_t rxstat; 114141502Swpaul 114241502Swpaul ifp = &sc->arpcom.ac_if; 114341502Swpaul 114441502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114541502Swpaul WB_RXSTAT_OWN)) { 114648745Swpaul struct mbuf *m0 = NULL; 114748745Swpaul 114841502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114941502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 115050675Swpaul 115148745Swpaul m = cur_rx->wb_mbuf; 115241502Swpaul 115350675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 115450675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115550675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115650675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115750675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115841502Swpaul ifp->if_ierrors++; 115950675Swpaul wb_newbuf(sc, cur_rx, m); 116041502Swpaul printf("wb%x: receiver babbling: possible chip " 116141502Swpaul "bug, forcing reset\n", sc->wb_unit); 116250675Swpaul wb_fixmedia(sc); 116350675Swpaul wb_reset(sc); 116450675Swpaul wb_init(sc); 116541502Swpaul return; 116641502Swpaul } 116741502Swpaul 116842718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116942718Swpaul ifp->if_ierrors++; 117048745Swpaul wb_newbuf(sc, cur_rx, m); 117150675Swpaul break; 117242718Swpaul } 117342718Swpaul 117441502Swpaul /* No errors; receive the packet. */ 117541502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117641502Swpaul 117741502Swpaul /* 117841934Swpaul * XXX The Winbond chip includes the CRC with every 117941934Swpaul * received frame, and there's no way to turn this 118041934Swpaul * behavior off (at least, I can't find anything in 118141934Swpaul * the manual that explains how to do it) so we have 118241934Swpaul * to trim off the CRC manually. 118341934Swpaul */ 118441934Swpaul total_len -= ETHER_CRC_LEN; 118541934Swpaul 118678508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 118778508Sbmilekic NULL); 118848745Swpaul wb_newbuf(sc, cur_rx, m); 118948745Swpaul if (m0 == NULL) { 119048745Swpaul ifp->if_ierrors++; 119150675Swpaul break; 119241502Swpaul } 119348745Swpaul m = m0; 119441502Swpaul 119541502Swpaul ifp->if_ipackets++; 1196106936Ssam (*ifp->if_input)(ifp, m); 119741502Swpaul } 119841502Swpaul} 119941502Swpaul 1200105221Sphkstatic void 1201102336Salfredwb_rxeoc(sc) 120241502Swpaul struct wb_softc *sc; 120341502Swpaul{ 120441502Swpaul wb_rxeof(sc); 120541502Swpaul 120641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120941502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 121041502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 121141502Swpaul 121241502Swpaul return; 121341502Swpaul} 121441502Swpaul 121541502Swpaul/* 121641502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121741502Swpaul * the list buffers. 121841502Swpaul */ 1219102336Salfredstatic void 1220102336Salfredwb_txeof(sc) 122141502Swpaul struct wb_softc *sc; 122241502Swpaul{ 122341502Swpaul struct wb_chain *cur_tx; 122441502Swpaul struct ifnet *ifp; 122541502Swpaul 122641502Swpaul ifp = &sc->arpcom.ac_if; 122741502Swpaul 122841502Swpaul /* Clear the timeout timer. */ 122941502Swpaul ifp->if_timer = 0; 123041502Swpaul 123141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 123241502Swpaul return; 123341502Swpaul 123441502Swpaul /* 123541502Swpaul * Go through our tx list and free mbufs for those 123641502Swpaul * frames that have been transmitted. 123741502Swpaul */ 123841502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123941502Swpaul u_int32_t txstat; 124041502Swpaul 124141502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 124241502Swpaul txstat = WB_TXSTATUS(cur_tx); 124341502Swpaul 124441502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124541502Swpaul break; 124641502Swpaul 124741502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124841502Swpaul ifp->if_oerrors++; 124941502Swpaul if (txstat & WB_TXSTAT_ABORT) 125041502Swpaul ifp->if_collisions++; 125141502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 125241502Swpaul ifp->if_collisions++; 125341502Swpaul } 125441502Swpaul 125541502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125641502Swpaul 125741502Swpaul ifp->if_opackets++; 125841502Swpaul m_freem(cur_tx->wb_mbuf); 125941502Swpaul cur_tx->wb_mbuf = NULL; 126041502Swpaul 126141502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 126241502Swpaul sc->wb_cdata.wb_tx_head = NULL; 126341502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126441502Swpaul break; 126541502Swpaul } 126641502Swpaul 126741502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126841502Swpaul } 126941502Swpaul 127041502Swpaul return; 127141502Swpaul} 127241502Swpaul 127341502Swpaul/* 127441502Swpaul * TX 'end of channel' interrupt handler. 127541502Swpaul */ 1276102336Salfredstatic void 1277102336Salfredwb_txeoc(sc) 127841502Swpaul struct wb_softc *sc; 127941502Swpaul{ 128041502Swpaul struct ifnet *ifp; 128141502Swpaul 128241502Swpaul ifp = &sc->arpcom.ac_if; 128341502Swpaul 128441502Swpaul ifp->if_timer = 0; 128541502Swpaul 128641502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128741502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128841502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128941502Swpaul } else { 129041502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 129141502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 129241502Swpaul ifp->if_timer = 5; 129341502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129441502Swpaul } 129541502Swpaul } 129641502Swpaul 129741502Swpaul return; 129841502Swpaul} 129941502Swpaul 1300102336Salfredstatic void 1301102336Salfredwb_intr(arg) 130241502Swpaul void *arg; 130341502Swpaul{ 130441502Swpaul struct wb_softc *sc; 130541502Swpaul struct ifnet *ifp; 130641502Swpaul u_int32_t status; 130741502Swpaul 130841502Swpaul sc = arg; 130967087Swpaul WB_LOCK(sc); 131041502Swpaul ifp = &sc->arpcom.ac_if; 131141502Swpaul 131267087Swpaul if (!(ifp->if_flags & IFF_UP)) { 131367087Swpaul WB_UNLOCK(sc); 131441502Swpaul return; 131567087Swpaul } 131641502Swpaul 131741502Swpaul /* Disable interrupts. */ 131841502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131941502Swpaul 132041502Swpaul for (;;) { 132141502Swpaul 132241502Swpaul status = CSR_READ_4(sc, WB_ISR); 132341502Swpaul if (status) 132441502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 132541502Swpaul 132641502Swpaul if ((status & WB_INTRS) == 0) 132741502Swpaul break; 132841502Swpaul 132941502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 133041502Swpaul ifp->if_ierrors++; 133141502Swpaul wb_reset(sc); 133250675Swpaul if (status & WB_ISR_RX_ERR) 133350675Swpaul wb_fixmedia(sc); 133441502Swpaul wb_init(sc); 133550675Swpaul continue; 133641502Swpaul } 133741502Swpaul 133850675Swpaul if (status & WB_ISR_RX_OK) 133950675Swpaul wb_rxeof(sc); 134050675Swpaul 134150675Swpaul if (status & WB_ISR_RX_IDLE) 134250675Swpaul wb_rxeoc(sc); 134350675Swpaul 134441502Swpaul if (status & WB_ISR_TX_OK) 134541502Swpaul wb_txeof(sc); 134641502Swpaul 134741502Swpaul if (status & WB_ISR_TX_NOBUF) 134841502Swpaul wb_txeoc(sc); 134941502Swpaul 135041502Swpaul if (status & WB_ISR_TX_IDLE) { 135141502Swpaul wb_txeof(sc); 135241502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 135341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 135541502Swpaul } 135641502Swpaul } 135741502Swpaul 135841502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135941502Swpaul ifp->if_oerrors++; 136041502Swpaul wb_txeof(sc); 136141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136241502Swpaul /* Jack up TX threshold */ 136341502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 136441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 136541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136741502Swpaul } 136841502Swpaul 136941502Swpaul if (status & WB_ISR_BUS_ERR) { 137041502Swpaul wb_reset(sc); 137141502Swpaul wb_init(sc); 137241502Swpaul } 137341502Swpaul 137441502Swpaul } 137541502Swpaul 137641502Swpaul /* Re-enable interrupts. */ 137741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137841502Swpaul 137941502Swpaul if (ifp->if_snd.ifq_head != NULL) { 138041502Swpaul wb_start(ifp); 138141502Swpaul } 138241502Swpaul 138367087Swpaul WB_UNLOCK(sc); 138467087Swpaul 138541502Swpaul return; 138641502Swpaul} 138741502Swpaul 1388102336Salfredstatic void 1389102336Salfredwb_tick(xsc) 139050675Swpaul void *xsc; 139150675Swpaul{ 139250675Swpaul struct wb_softc *sc; 139350675Swpaul struct mii_data *mii; 139450675Swpaul 139550675Swpaul sc = xsc; 139667087Swpaul WB_LOCK(sc); 139750675Swpaul mii = device_get_softc(sc->wb_miibus); 139850675Swpaul 139950675Swpaul mii_tick(mii); 140050675Swpaul 140150675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 140250675Swpaul 140367087Swpaul WB_UNLOCK(sc); 140450685Swpaul 140550675Swpaul return; 140650675Swpaul} 140750675Swpaul 140841502Swpaul/* 140941502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 141041502Swpaul * pointers to the fragment pointers. 141141502Swpaul */ 1412102336Salfredstatic int 1413102336Salfredwb_encap(sc, c, m_head) 141441502Swpaul struct wb_softc *sc; 141541502Swpaul struct wb_chain *c; 141641502Swpaul struct mbuf *m_head; 141741502Swpaul{ 141841502Swpaul int frag = 0; 141941502Swpaul struct wb_desc *f = NULL; 142041502Swpaul int total_len; 142141502Swpaul struct mbuf *m; 142241502Swpaul 142341502Swpaul /* 142441502Swpaul * Start packing the mbufs in this chain into 142541502Swpaul * the fragment pointers. Stop when we run out 142641502Swpaul * of fragments or hit the end of the mbuf chain. 142741502Swpaul */ 142841502Swpaul m = m_head; 142941502Swpaul total_len = 0; 143041502Swpaul 143141502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 143241502Swpaul if (m->m_len != 0) { 143341502Swpaul if (frag == WB_MAXFRAGS) 143441502Swpaul break; 143541502Swpaul total_len += m->m_len; 143641502Swpaul f = &c->wb_ptr->wb_frag[frag]; 143741502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143841502Swpaul if (frag == 0) { 143941502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 144041502Swpaul f->wb_status = 0; 144141502Swpaul } else 144241502Swpaul f->wb_status = WB_TXSTAT_OWN; 144341502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 144441502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 144541502Swpaul frag++; 144641502Swpaul } 144741502Swpaul } 144841502Swpaul 144941502Swpaul /* 145041502Swpaul * Handle special case: we used up all 16 fragments, 145141502Swpaul * but we have more mbufs left in the chain. Copy the 145241502Swpaul * data into an mbuf cluster. Note that we don't 145341502Swpaul * bother clearing the values in the other fragment 145441502Swpaul * pointers/counters; it wouldn't gain us anything, 145541502Swpaul * and would waste cycles. 145641502Swpaul */ 145741502Swpaul if (m != NULL) { 145841502Swpaul struct mbuf *m_new = NULL; 145941502Swpaul 1460111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 146187846Sluigi if (m_new == NULL) 146241502Swpaul return(1); 146341502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1464111119Simp MCLGET(m_new, M_DONTWAIT); 146541502Swpaul if (!(m_new->m_flags & M_EXT)) { 146641502Swpaul m_freem(m_new); 146741502Swpaul return(1); 146841502Swpaul } 146941502Swpaul } 147041502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 147141502Swpaul mtod(m_new, caddr_t)); 147241502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 147341502Swpaul m_freem(m_head); 147441502Swpaul m_head = m_new; 147541502Swpaul f = &c->wb_ptr->wb_frag[0]; 147641502Swpaul f->wb_status = 0; 147741502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147841502Swpaul f->wb_ctl = total_len = m_new->m_len; 147941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 148041502Swpaul frag = 1; 148141502Swpaul } 148241502Swpaul 148341502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148441502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148541502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148641502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148741502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148841502Swpaul f->wb_status = WB_TXSTAT_OWN; 148941502Swpaul frag++; 149041502Swpaul } 149141502Swpaul 149241502Swpaul c->wb_mbuf = m_head; 149341502Swpaul c->wb_lastdesc = frag - 1; 149441502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149541502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149641502Swpaul 149741502Swpaul return(0); 149841502Swpaul} 149941502Swpaul 150041502Swpaul/* 150141502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 150241502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 150341502Swpaul * copy of the pointers since the transmit list fragment pointers are 150441502Swpaul * physical addresses. 150541502Swpaul */ 150641502Swpaul 1507102336Salfredstatic void 1508102336Salfredwb_start(ifp) 150941502Swpaul struct ifnet *ifp; 151041502Swpaul{ 151141502Swpaul struct wb_softc *sc; 151241502Swpaul struct mbuf *m_head = NULL; 151341502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 151441502Swpaul 151541502Swpaul sc = ifp->if_softc; 151667087Swpaul WB_LOCK(sc); 151741502Swpaul 151841502Swpaul /* 151941502Swpaul * Check for an available queue slot. If there are none, 152041502Swpaul * punt. 152141502Swpaul */ 152241502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 152341502Swpaul ifp->if_flags |= IFF_OACTIVE; 152467087Swpaul WB_UNLOCK(sc); 152541502Swpaul return; 152641502Swpaul } 152741502Swpaul 152841502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152941502Swpaul 153041502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 153141502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 153241502Swpaul if (m_head == NULL) 153341502Swpaul break; 153441502Swpaul 153541502Swpaul /* Pick a descriptor off the free list. */ 153641502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153741502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153841502Swpaul 153941502Swpaul /* Pack the data into the descriptor. */ 154041502Swpaul wb_encap(sc, cur_tx, m_head); 154141502Swpaul 154241502Swpaul if (cur_tx != start_tx) 154341502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 154441502Swpaul 154541502Swpaul /* 154641502Swpaul * If there's a BPF listener, bounce a copy of this frame 154741502Swpaul * to him. 154841502Swpaul */ 1549106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 155041502Swpaul } 155141502Swpaul 155241502Swpaul /* 155341526Swpaul * If there are no packets queued, bail. 155441526Swpaul */ 155567087Swpaul if (cur_tx == NULL) { 155667087Swpaul WB_UNLOCK(sc); 155741526Swpaul return; 155867087Swpaul } 155941526Swpaul 156041526Swpaul /* 156141502Swpaul * Place the request for the upload interrupt 156241502Swpaul * in the last descriptor in the chain. This way, if 156341502Swpaul * we're chaining several packets at once, we'll only 156441502Swpaul * get an interupt once for the whole chain rather than 156541502Swpaul * once for each packet. 156641502Swpaul */ 156741502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156842718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156941502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 157041502Swpaul 157141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 157241502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 157341502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 157441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 157541502Swpaul } else { 157641502Swpaul /* 157741502Swpaul * We need to distinguish between the case where 157841502Swpaul * the own bit is clear because the chip cleared it 157941502Swpaul * and where the own bit is clear because we haven't 158041502Swpaul * set it yet. The magic value WB_UNSET is just some 158141502Swpaul * ramdomly chosen number which doesn't have the own 158241502Swpaul * bit set. When we actually transmit the frame, the 158341502Swpaul * status word will have _only_ the own bit set, so 158441502Swpaul * the txeoc handler will be able to tell if it needs 158541502Swpaul * to initiate another transmission to flush out pending 158641502Swpaul * frames. 158741502Swpaul */ 158841502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158941502Swpaul } 159041502Swpaul 159141502Swpaul /* 159241502Swpaul * Set a timeout in case the chip goes out to lunch. 159341502Swpaul */ 159441502Swpaul ifp->if_timer = 5; 159567087Swpaul WB_UNLOCK(sc); 159641502Swpaul 159741502Swpaul return; 159841502Swpaul} 159941502Swpaul 1600102336Salfredstatic void 1601102336Salfredwb_init(xsc) 160241502Swpaul void *xsc; 160341502Swpaul{ 160441502Swpaul struct wb_softc *sc = xsc; 160541502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160667087Swpaul int i; 160750675Swpaul struct mii_data *mii; 160841502Swpaul 160967087Swpaul WB_LOCK(sc); 161050675Swpaul mii = device_get_softc(sc->wb_miibus); 161141502Swpaul 161241502Swpaul /* 161341502Swpaul * Cancel pending I/O and free all RX/TX buffers. 161441502Swpaul */ 161541502Swpaul wb_stop(sc); 161641502Swpaul wb_reset(sc); 161741502Swpaul 161841502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161941502Swpaul 162041502Swpaul /* 162141502Swpaul * Set cache alignment and burst length. 162241502Swpaul */ 162350675Swpaul#ifdef foo 162441502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 162541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 162641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 162750675Swpaul#endif 162841502Swpaul 162950675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 163050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 163150675Swpaul switch(sc->wb_cachesize) { 163250675Swpaul case 32: 163350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 163450675Swpaul break; 163550675Swpaul case 16: 163650675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 163750675Swpaul break; 163850675Swpaul case 8: 163950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 164050675Swpaul break; 164150675Swpaul case 0: 164250675Swpaul default: 164350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 164450675Swpaul break; 164550675Swpaul } 164650675Swpaul 164741502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 164841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164941502Swpaul 165041502Swpaul /* Init our MAC address */ 165141502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 165241502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 165341502Swpaul } 165441502Swpaul 165541502Swpaul /* Init circular RX list. */ 165641502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 165741502Swpaul printf("wb%d: initialization failed: no " 165841502Swpaul "memory for rx buffers\n", sc->wb_unit); 165941502Swpaul wb_stop(sc); 166067087Swpaul WB_UNLOCK(sc); 166141502Swpaul return; 166241502Swpaul } 166341502Swpaul 166441502Swpaul /* Init TX descriptors. */ 166541502Swpaul wb_list_tx_init(sc); 166641502Swpaul 166741502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 166841502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 167041502Swpaul } else { 167141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 167241502Swpaul } 167341502Swpaul 167441502Swpaul /* 167541502Swpaul * Set capture broadcast bit to capture broadcast frames. 167641502Swpaul */ 167741502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 167841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167941502Swpaul } else { 168041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 168141502Swpaul } 168241502Swpaul 168341502Swpaul /* 168441502Swpaul * Program the multicast filter, if necessary. 168541502Swpaul */ 168641502Swpaul wb_setmulti(sc); 168741502Swpaul 168841502Swpaul /* 168941502Swpaul * Load the address of the RX list. 169041502Swpaul */ 169141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169241502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 169341502Swpaul 169441502Swpaul /* 169541502Swpaul * Enable interrupts. 169641502Swpaul */ 169741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 169841502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169941502Swpaul 170041502Swpaul /* Enable receiver and transmitter. */ 170141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 170241502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 170341502Swpaul 170441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170541502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 170641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 170741502Swpaul 170850675Swpaul mii_mediachg(mii); 170941502Swpaul 171041502Swpaul ifp->if_flags |= IFF_RUNNING; 171141502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 171241502Swpaul 171350675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 171467087Swpaul WB_UNLOCK(sc); 171550675Swpaul 171641502Swpaul return; 171741502Swpaul} 171841502Swpaul 171941502Swpaul/* 172041502Swpaul * Set media options. 172141502Swpaul */ 1722102336Salfredstatic int 1723102336Salfredwb_ifmedia_upd(ifp) 172441502Swpaul struct ifnet *ifp; 172541502Swpaul{ 172641502Swpaul struct wb_softc *sc; 172741502Swpaul 172841502Swpaul sc = ifp->if_softc; 172941502Swpaul 173050675Swpaul if (ifp->if_flags & IFF_UP) 173150675Swpaul wb_init(sc); 173241502Swpaul 173341502Swpaul return(0); 173441502Swpaul} 173541502Swpaul 173641502Swpaul/* 173741502Swpaul * Report current media status. 173841502Swpaul */ 1739102336Salfredstatic void 1740102336Salfredwb_ifmedia_sts(ifp, ifmr) 174141502Swpaul struct ifnet *ifp; 174241502Swpaul struct ifmediareq *ifmr; 174341502Swpaul{ 174441502Swpaul struct wb_softc *sc; 174550675Swpaul struct mii_data *mii; 174641502Swpaul 174741502Swpaul sc = ifp->if_softc; 174841502Swpaul 174950675Swpaul mii = device_get_softc(sc->wb_miibus); 175041502Swpaul 175150675Swpaul mii_pollstat(mii); 175250675Swpaul ifmr->ifm_active = mii->mii_media_active; 175350675Swpaul ifmr->ifm_status = mii->mii_media_status; 175441502Swpaul 175541502Swpaul return; 175641502Swpaul} 175741502Swpaul 1758102336Salfredstatic int 1759102336Salfredwb_ioctl(ifp, command, data) 176041502Swpaul struct ifnet *ifp; 176141502Swpaul u_long command; 176241502Swpaul caddr_t data; 176341502Swpaul{ 176441502Swpaul struct wb_softc *sc = ifp->if_softc; 176550675Swpaul struct mii_data *mii; 176641502Swpaul struct ifreq *ifr = (struct ifreq *) data; 176767087Swpaul int error = 0; 176841502Swpaul 176967087Swpaul WB_LOCK(sc); 177041502Swpaul 177141502Swpaul switch(command) { 177241502Swpaul case SIOCSIFFLAGS: 177341502Swpaul if (ifp->if_flags & IFF_UP) { 177441502Swpaul wb_init(sc); 177541502Swpaul } else { 177641502Swpaul if (ifp->if_flags & IFF_RUNNING) 177741502Swpaul wb_stop(sc); 177841502Swpaul } 177941502Swpaul error = 0; 178041502Swpaul break; 178141502Swpaul case SIOCADDMULTI: 178241502Swpaul case SIOCDELMULTI: 178341502Swpaul wb_setmulti(sc); 178441502Swpaul error = 0; 178541502Swpaul break; 178641502Swpaul case SIOCGIFMEDIA: 178741502Swpaul case SIOCSIFMEDIA: 178850675Swpaul mii = device_get_softc(sc->wb_miibus); 178950675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 179041502Swpaul break; 179141502Swpaul default: 1792106936Ssam error = ether_ioctl(ifp, command, data); 179341502Swpaul break; 179441502Swpaul } 179541502Swpaul 179667087Swpaul WB_UNLOCK(sc); 179741502Swpaul 179841502Swpaul return(error); 179941502Swpaul} 180041502Swpaul 1801102336Salfredstatic void 1802102336Salfredwb_watchdog(ifp) 180341502Swpaul struct ifnet *ifp; 180441502Swpaul{ 180541502Swpaul struct wb_softc *sc; 180641502Swpaul 180741502Swpaul sc = ifp->if_softc; 180841502Swpaul 180967087Swpaul WB_LOCK(sc); 181041502Swpaul ifp->if_oerrors++; 181141502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 181250675Swpaul#ifdef foo 181341502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 181441502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 181541502Swpaul sc->wb_unit); 181650675Swpaul#endif 181741502Swpaul wb_stop(sc); 181841502Swpaul wb_reset(sc); 181941502Swpaul wb_init(sc); 182041502Swpaul 182141502Swpaul if (ifp->if_snd.ifq_head != NULL) 182241502Swpaul wb_start(ifp); 182367087Swpaul WB_UNLOCK(sc); 182441502Swpaul 182541502Swpaul return; 182641502Swpaul} 182741502Swpaul 182841502Swpaul/* 182941502Swpaul * Stop the adapter and free any mbufs allocated to the 183041502Swpaul * RX and TX lists. 183141502Swpaul */ 1832102336Salfredstatic void 1833102336Salfredwb_stop(sc) 183441502Swpaul struct wb_softc *sc; 183541502Swpaul{ 183641502Swpaul register int i; 183741502Swpaul struct ifnet *ifp; 183841502Swpaul 183967087Swpaul WB_LOCK(sc); 184041502Swpaul ifp = &sc->arpcom.ac_if; 184141502Swpaul ifp->if_timer = 0; 184241502Swpaul 184350675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 184450675Swpaul 184541502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 184641502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 184741502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 184841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 184941502Swpaul 185041502Swpaul /* 185141502Swpaul * Free data in the RX lists. 185241502Swpaul */ 185341502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 185441502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 185541502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 185641502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 185741502Swpaul } 185841502Swpaul } 185941502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 186041502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 186141502Swpaul 186241502Swpaul /* 186341502Swpaul * Free the TX list buffers. 186441502Swpaul */ 186541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 186641502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 186741502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 186841502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 186941502Swpaul } 187041502Swpaul } 187141502Swpaul 187241502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 187341502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 187441502Swpaul 187541502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 187667087Swpaul WB_UNLOCK(sc); 187741502Swpaul 187841502Swpaul return; 187941502Swpaul} 188041502Swpaul 188141502Swpaul/* 188241502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 188341502Swpaul * get confused by errant DMAs when rebooting. 188441502Swpaul */ 1885102336Salfredstatic void 1886102336Salfredwb_shutdown(dev) 188749611Swpaul device_t dev; 188841502Swpaul{ 188949611Swpaul struct wb_softc *sc; 189041502Swpaul 189149611Swpaul sc = device_get_softc(dev); 189241502Swpaul wb_stop(sc); 189341502Swpaul 189441502Swpaul return; 189541502Swpaul} 1896