if_wb.c revision 113038
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Winbond fast ethernet PCI NIC driver 35 * 36 * Supports various cheap network adapters based on the Winbond W89C840F 37 * fast ethernet controller chip. This includes adapters manufactured by 38 * Winbond itself and some made by Linksys. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Winbond W89C840F chip is a bus master; in some ways it resembles 47 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48 * one major difference which is that while the registers do many of 49 * the same things as a tulip adapter, the offsets are different: where 50 * tulip registers are typically spaced 8 bytes apart, the Winbond 51 * registers are spaced 4 bytes apart. The receiver filter is also 52 * programmed differently. 53 * 54 * Like the tulip, the Winbond chip uses small descriptors containing 55 * a status word, a control word and 32-bit areas that can either be used 56 * to point to two external data blocks, or to point to a single block 57 * and another descriptor in a linked list. Descriptors can be grouped 58 * together in blocks to form fixed length rings or can be chained 59 * together in linked lists. A single packet may be spread out over 60 * several descriptors if necessary. 61 * 62 * For the receive ring, this driver uses a linked list of descriptors, 63 * each pointing to a single mbuf cluster buffer, which us large enough 64 * to hold an entire packet. The link list is looped back to created a 65 * closed ring. 66 * 67 * For transmission, the driver creates a linked list of 'super descriptors' 68 * which each contain several individual descriptors linked toghether. 69 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70 * abuse as fragment pointers. This allows us to use a buffer managment 71 * scheme very similar to that used in the ThunderLAN and Etherlink XL 72 * drivers. 73 * 74 * Autonegotiation is performed using the external PHY via the MII bus. 75 * The sample boards I have all use a Davicom PHY. 76 * 77 * Note: the author of the Linux driver for the Winbond chip alludes 78 * to some sort of flaw in the chip's design that seems to mandate some 79 * drastic workaround which signigicantly impairs transmit performance. 80 * I have no idea what he's on about: transmit performance with all 81 * three of my test boards seems fine. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 113038 2003-04-03 21:36:33Z obrien $"); 86 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <pci/pcireg.h> 116#include <pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, miibus, 1, 1, 1); 129 130/* 131 * Various supported device vendors/types and their names. 132 */ 133static struct wb_type wb_devs[] = { 134 { WB_VENDORID, WB_DEVICEID_840F, 135 "Winbond W89C840F 10/100BaseTX" }, 136 { CP_VENDORID, CP_DEVICEID_RL100, 137 "Compex RL100-ATX 10/100baseTX" }, 138 { 0, 0, NULL } 139}; 140 141static int wb_probe (device_t); 142static int wb_attach (device_t); 143static int wb_detach (device_t); 144 145static void wb_bfree (void *addr, void *args); 146static int wb_newbuf (struct wb_softc *, 147 struct wb_chain_onefrag *, 148 struct mbuf *); 149static int wb_encap (struct wb_softc *, struct wb_chain *, 150 struct mbuf *); 151 152static void wb_rxeof (struct wb_softc *); 153static void wb_rxeoc (struct wb_softc *); 154static void wb_txeof (struct wb_softc *); 155static void wb_txeoc (struct wb_softc *); 156static void wb_intr (void *); 157static void wb_tick (void *); 158static void wb_start (struct ifnet *); 159static int wb_ioctl (struct ifnet *, u_long, caddr_t); 160static void wb_init (void *); 161static void wb_stop (struct wb_softc *); 162static void wb_watchdog (struct ifnet *); 163static void wb_shutdown (device_t); 164static int wb_ifmedia_upd (struct ifnet *); 165static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 166 167static void wb_eeprom_putbyte (struct wb_softc *, int); 168static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 169static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 170static void wb_mii_sync (struct wb_softc *); 171static void wb_mii_send (struct wb_softc *, u_int32_t, int); 172static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 173static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 174 175static void wb_setcfg (struct wb_softc *, u_int32_t); 176static u_int8_t wb_calchash (caddr_t); 177static void wb_setmulti (struct wb_softc *); 178static void wb_reset (struct wb_softc *); 179static void wb_fixmedia (struct wb_softc *); 180static int wb_list_rx_init (struct wb_softc *); 181static int wb_list_tx_init (struct wb_softc *); 182 183static int wb_miibus_readreg (device_t, int, int); 184static int wb_miibus_writereg (device_t, int, int, int); 185static void wb_miibus_statchg (device_t); 186 187#ifdef WB_USEIOSPACE 188#define WB_RES SYS_RES_IOPORT 189#define WB_RID WB_PCI_LOIO 190#else 191#define WB_RES SYS_RES_MEMORY 192#define WB_RID WB_PCI_LOMEM 193#endif 194 195static device_method_t wb_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, wb_probe), 198 DEVMETHOD(device_attach, wb_attach), 199 DEVMETHOD(device_detach, wb_detach), 200 DEVMETHOD(device_shutdown, wb_shutdown), 201 202 /* bus interface, for miibus */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 208 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 209 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 210 { 0, 0 } 211}; 212 213static driver_t wb_driver = { 214 "wb", 215 wb_methods, 216 sizeof(struct wb_softc) 217}; 218 219static devclass_t wb_devclass; 220 221DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 222DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 223 224#define WB_SETBIT(sc, reg, x) \ 225 CSR_WRITE_4(sc, reg, \ 226 CSR_READ_4(sc, reg) | (x)) 227 228#define WB_CLRBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, \ 230 CSR_READ_4(sc, reg) & ~(x)) 231 232#define SIO_SET(x) \ 233 CSR_WRITE_4(sc, WB_SIO, \ 234 CSR_READ_4(sc, WB_SIO) | (x)) 235 236#define SIO_CLR(x) \ 237 CSR_WRITE_4(sc, WB_SIO, \ 238 CSR_READ_4(sc, WB_SIO) & ~(x)) 239 240/* 241 * Send a read command and address to the EEPROM, check for ACK. 242 */ 243static void 244wb_eeprom_putbyte(sc, addr) 245 struct wb_softc *sc; 246 int addr; 247{ 248 register int d, i; 249 250 d = addr | WB_EECMD_READ; 251 252 /* 253 * Feed in each bit and stobe the clock. 254 */ 255 for (i = 0x400; i; i >>= 1) { 256 if (d & i) { 257 SIO_SET(WB_SIO_EE_DATAIN); 258 } else { 259 SIO_CLR(WB_SIO_EE_DATAIN); 260 } 261 DELAY(100); 262 SIO_SET(WB_SIO_EE_CLK); 263 DELAY(150); 264 SIO_CLR(WB_SIO_EE_CLK); 265 DELAY(100); 266 } 267 268 return; 269} 270 271/* 272 * Read a word of data stored in the EEPROM at address 'addr.' 273 */ 274static void 275wb_eeprom_getword(sc, addr, dest) 276 struct wb_softc *sc; 277 int addr; 278 u_int16_t *dest; 279{ 280 register int i; 281 u_int16_t word = 0; 282 283 /* Enter EEPROM access mode. */ 284 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 285 286 /* 287 * Send address of word we want to read. 288 */ 289 wb_eeprom_putbyte(sc, addr); 290 291 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 292 293 /* 294 * Start reading bits from EEPROM. 295 */ 296 for (i = 0x8000; i; i >>= 1) { 297 SIO_SET(WB_SIO_EE_CLK); 298 DELAY(100); 299 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 300 word |= i; 301 SIO_CLR(WB_SIO_EE_CLK); 302 DELAY(100); 303 } 304 305 /* Turn off EEPROM access mode. */ 306 CSR_WRITE_4(sc, WB_SIO, 0); 307 308 *dest = word; 309 310 return; 311} 312 313/* 314 * Read a sequence of words from the EEPROM. 315 */ 316static void 317wb_read_eeprom(sc, dest, off, cnt, swap) 318 struct wb_softc *sc; 319 caddr_t dest; 320 int off; 321 int cnt; 322 int swap; 323{ 324 int i; 325 u_int16_t word = 0, *ptr; 326 327 for (i = 0; i < cnt; i++) { 328 wb_eeprom_getword(sc, off + i, &word); 329 ptr = (u_int16_t *)(dest + (i * 2)); 330 if (swap) 331 *ptr = ntohs(word); 332 else 333 *ptr = word; 334 } 335 336 return; 337} 338 339/* 340 * Sync the PHYs by setting data bit and strobing the clock 32 times. 341 */ 342static void 343wb_mii_sync(sc) 344 struct wb_softc *sc; 345{ 346 register int i; 347 348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 349 350 for (i = 0; i < 32; i++) { 351 SIO_SET(WB_SIO_MII_CLK); 352 DELAY(1); 353 SIO_CLR(WB_SIO_MII_CLK); 354 DELAY(1); 355 } 356 357 return; 358} 359 360/* 361 * Clock a series of bits through the MII. 362 */ 363static void 364wb_mii_send(sc, bits, cnt) 365 struct wb_softc *sc; 366 u_int32_t bits; 367 int cnt; 368{ 369 int i; 370 371 SIO_CLR(WB_SIO_MII_CLK); 372 373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 374 if (bits & i) { 375 SIO_SET(WB_SIO_MII_DATAIN); 376 } else { 377 SIO_CLR(WB_SIO_MII_DATAIN); 378 } 379 DELAY(1); 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 } 384} 385 386/* 387 * Read an PHY register through the MII. 388 */ 389static int 390wb_mii_readreg(sc, frame) 391 struct wb_softc *sc; 392 struct wb_mii_frame *frame; 393 394{ 395 int i, ack; 396 397 WB_LOCK(sc); 398 399 /* 400 * Set up frame for RX. 401 */ 402 frame->mii_stdelim = WB_MII_STARTDELIM; 403 frame->mii_opcode = WB_MII_READOP; 404 frame->mii_turnaround = 0; 405 frame->mii_data = 0; 406 407 CSR_WRITE_4(sc, WB_SIO, 0); 408 409 /* 410 * Turn on data xmit. 411 */ 412 SIO_SET(WB_SIO_MII_DIR); 413 414 wb_mii_sync(sc); 415 416 /* 417 * Send command/address info. 418 */ 419 wb_mii_send(sc, frame->mii_stdelim, 2); 420 wb_mii_send(sc, frame->mii_opcode, 2); 421 wb_mii_send(sc, frame->mii_phyaddr, 5); 422 wb_mii_send(sc, frame->mii_regaddr, 5); 423 424 /* Idle bit */ 425 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 426 DELAY(1); 427 SIO_SET(WB_SIO_MII_CLK); 428 DELAY(1); 429 430 /* Turn off xmit. */ 431 SIO_CLR(WB_SIO_MII_DIR); 432 /* Check for ack */ 433 SIO_CLR(WB_SIO_MII_CLK); 434 DELAY(1); 435 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 436 SIO_SET(WB_SIO_MII_CLK); 437 DELAY(1); 438 SIO_CLR(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_SET(WB_SIO_MII_CLK); 441 DELAY(1); 442 443 /* 444 * Now try reading data bits. If the ack failed, we still 445 * need to clock through 16 cycles to keep the PHY(s) in sync. 446 */ 447 if (ack) { 448 for(i = 0; i < 16; i++) { 449 SIO_CLR(WB_SIO_MII_CLK); 450 DELAY(1); 451 SIO_SET(WB_SIO_MII_CLK); 452 DELAY(1); 453 } 454 goto fail; 455 } 456 457 for (i = 0x8000; i; i >>= 1) { 458 SIO_CLR(WB_SIO_MII_CLK); 459 DELAY(1); 460 if (!ack) { 461 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 462 frame->mii_data |= i; 463 DELAY(1); 464 } 465 SIO_SET(WB_SIO_MII_CLK); 466 DELAY(1); 467 } 468 469fail: 470 471 SIO_CLR(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_SET(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 WB_UNLOCK(sc); 477 478 if (ack) 479 return(1); 480 return(0); 481} 482 483/* 484 * Write to a PHY register through the MII. 485 */ 486static int 487wb_mii_writereg(sc, frame) 488 struct wb_softc *sc; 489 struct wb_mii_frame *frame; 490 491{ 492 WB_LOCK(sc); 493 494 /* 495 * Set up frame for TX. 496 */ 497 498 frame->mii_stdelim = WB_MII_STARTDELIM; 499 frame->mii_opcode = WB_MII_WRITEOP; 500 frame->mii_turnaround = WB_MII_TURNAROUND; 501 502 /* 503 * Turn on data output. 504 */ 505 SIO_SET(WB_SIO_MII_DIR); 506 507 wb_mii_sync(sc); 508 509 wb_mii_send(sc, frame->mii_stdelim, 2); 510 wb_mii_send(sc, frame->mii_opcode, 2); 511 wb_mii_send(sc, frame->mii_phyaddr, 5); 512 wb_mii_send(sc, frame->mii_regaddr, 5); 513 wb_mii_send(sc, frame->mii_turnaround, 2); 514 wb_mii_send(sc, frame->mii_data, 16); 515 516 /* Idle bit. */ 517 SIO_SET(WB_SIO_MII_CLK); 518 DELAY(1); 519 SIO_CLR(WB_SIO_MII_CLK); 520 DELAY(1); 521 522 /* 523 * Turn off xmit. 524 */ 525 SIO_CLR(WB_SIO_MII_DIR); 526 527 WB_UNLOCK(sc); 528 529 return(0); 530} 531 532static int 533wb_miibus_readreg(dev, phy, reg) 534 device_t dev; 535 int phy, reg; 536{ 537 struct wb_softc *sc; 538 struct wb_mii_frame frame; 539 540 sc = device_get_softc(dev); 541 542 bzero((char *)&frame, sizeof(frame)); 543 544 frame.mii_phyaddr = phy; 545 frame.mii_regaddr = reg; 546 wb_mii_readreg(sc, &frame); 547 548 return(frame.mii_data); 549} 550 551static int 552wb_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555{ 556 struct wb_softc *sc; 557 struct wb_mii_frame frame; 558 559 sc = device_get_softc(dev); 560 561 bzero((char *)&frame, sizeof(frame)); 562 563 frame.mii_phyaddr = phy; 564 frame.mii_regaddr = reg; 565 frame.mii_data = data; 566 567 wb_mii_writereg(sc, &frame); 568 569 return(0); 570} 571 572static void 573wb_miibus_statchg(dev) 574 device_t dev; 575{ 576 struct wb_softc *sc; 577 struct mii_data *mii; 578 579 sc = device_get_softc(dev); 580 WB_LOCK(sc); 581 mii = device_get_softc(sc->wb_miibus); 582 wb_setcfg(sc, mii->mii_media_active); 583 WB_UNLOCK(sc); 584 585 return; 586} 587 588static u_int8_t wb_calchash(addr) 589 caddr_t addr; 590{ 591 u_int32_t crc, carry; 592 int i, j; 593 u_int8_t c; 594 595 /* Compute CRC for the address value. */ 596 crc = 0xFFFFFFFF; /* initial value */ 597 598 for (i = 0; i < 6; i++) { 599 c = *(addr + i); 600 for (j = 0; j < 8; j++) { 601 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 602 crc <<= 1; 603 c >>= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617} 618 619/* 620 * Program the 64-bit multicast hash filter. 621 */ 622static void 623wb_setmulti(sc) 624 struct wb_softc *sc; 625{ 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, WB_NETCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= WB_NETCFG_RX_MULTI; 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, WB_MAR0, 0); 647 CSR_WRITE_4(sc, WB_MAR1, 0); 648 649 /* now program new ones */ 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671} 672 673/* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678static void 679wb_setcfg(sc, media) 680 struct wb_softc *sc; 681 u_int32_t media; 682{ 683 int i, restart = 0; 684 685 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 686 restart = 1; 687 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 688 689 for (i = 0; i < WB_TIMEOUT; i++) { 690 DELAY(10); 691 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 692 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 693 break; 694 } 695 696 if (i == WB_TIMEOUT) 697 printf("wb%d: failed to force tx and " 698 "rx to idle state\n", sc->wb_unit); 699 } 700 701 if (IFM_SUBTYPE(media) == IFM_10_T) 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 703 else 704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705 706 if ((media & IFM_GMASK) == IFM_FDX) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 708 else 709 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710 711 if (restart) 712 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 713 714 return; 715} 716 717static void 718wb_reset(sc) 719 struct wb_softc *sc; 720{ 721 register int i; 722 struct mii_data *mii; 723 724 CSR_WRITE_4(sc, WB_NETCFG, 0); 725 CSR_WRITE_4(sc, WB_BUSCTL, 0); 726 CSR_WRITE_4(sc, WB_TXADDR, 0); 727 CSR_WRITE_4(sc, WB_RXADDR, 0); 728 729 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 732 for (i = 0; i < WB_TIMEOUT; i++) { 733 DELAY(10); 734 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 735 break; 736 } 737 if (i == WB_TIMEOUT) 738 printf("wb%d: reset never completed!\n", sc->wb_unit); 739 740 /* Wait a little while for the chip to get its brains in order. */ 741 DELAY(1000); 742 743 if (sc->wb_miibus == NULL) 744 return; 745 746 mii = device_get_softc(sc->wb_miibus); 747 if (mii == NULL) 748 return; 749 750 if (mii->mii_instance) { 751 struct mii_softc *miisc; 752 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 753 mii_phy_reset(miisc); 754 } 755 756 return; 757} 758 759static void 760wb_fixmedia(sc) 761 struct wb_softc *sc; 762{ 763 struct mii_data *mii = NULL; 764 struct ifnet *ifp; 765 u_int32_t media; 766 767 if (sc->wb_miibus == NULL) 768 return; 769 770 mii = device_get_softc(sc->wb_miibus); 771 ifp = &sc->arpcom.ac_if; 772 773 mii_pollstat(mii); 774 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 775 media = mii->mii_media_active & ~IFM_10_T; 776 media |= IFM_100_TX; 777 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 778 media = mii->mii_media_active & ~IFM_100_TX; 779 media |= IFM_10_T; 780 } else 781 return; 782 783 ifmedia_set(&mii->mii_media, media); 784 785 return; 786} 787 788/* 789 * Probe for a Winbond chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792static int 793wb_probe(dev) 794 device_t dev; 795{ 796 struct wb_type *t; 797 798 t = wb_devs; 799 800 while(t->wb_name != NULL) { 801 if ((pci_get_vendor(dev) == t->wb_vid) && 802 (pci_get_device(dev) == t->wb_did)) { 803 device_set_desc(dev, t->wb_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810} 811 812/* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816static int 817wb_attach(dev) 818 device_t dev; 819{ 820 u_char eaddr[ETHER_ADDR_LEN]; 821 u_int32_t command; 822 struct wb_softc *sc; 823 struct ifnet *ifp; 824 int unit, error = 0, rid; 825 826 sc = device_get_softc(dev); 827 unit = device_get_unit(dev); 828 829 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 830 MTX_DEF | MTX_RECURSE); 831 832 /* 833 * Handle power management nonsense. 834 */ 835 836 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 837 u_int32_t iobase, membase, irq; 838 839 /* Save important PCI config data. */ 840 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 841 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 842 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 843 844 /* Reset the power state. */ 845 printf("wb%d: chip is in D%d power mode " 846 "-- setting to D0\n", unit, 847 pci_get_powerstate(dev)); 848 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 849 850 /* Restore PCI config data. */ 851 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 852 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 853 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 854 } 855 856 /* 857 * Map control/status registers. 858 */ 859 pci_enable_busmaster(dev); 860 pci_enable_io(dev, SYS_RES_IOPORT); 861 pci_enable_io(dev, SYS_RES_MEMORY); 862 command = pci_read_config(dev, PCIR_COMMAND, 4); 863 864#ifdef WB_USEIOSPACE 865 if (!(command & PCIM_CMD_PORTEN)) { 866 printf("wb%d: failed to enable I/O ports!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870#else 871 if (!(command & PCIM_CMD_MEMEN)) { 872 printf("wb%d: failed to enable memory mapping!\n", unit); 873 error = ENXIO; 874 goto fail; 875 } 876#endif 877 878 rid = WB_RID; 879 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 880 0, ~0, 1, RF_ACTIVE); 881 882 if (sc->wb_res == NULL) { 883 printf("wb%d: couldn't map ports/memory\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887 888 sc->wb_btag = rman_get_bustag(sc->wb_res); 889 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 890 891 /* Allocate interrupt */ 892 rid = 0; 893 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 894 RF_SHAREABLE | RF_ACTIVE); 895 896 if (sc->wb_irq == NULL) { 897 printf("wb%d: couldn't map interrupt\n", unit); 898 error = ENXIO; 899 goto fail; 900 } 901 902 /* Save the cache line size. */ 903 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 904 905 /* Reset the adapter. */ 906 wb_reset(sc); 907 908 /* 909 * Get station address from the EEPROM. 910 */ 911 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 912 913 /* 914 * A Winbond chip was detected. Inform the world. 915 */ 916 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 917 918 sc->wb_unit = unit; 919 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 920 921 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 922 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 923 924 if (sc->wb_ldata == NULL) { 925 printf("wb%d: no memory for list buffers!\n", unit); 926 error = ENXIO; 927 goto fail; 928 } 929 930 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 931 932 ifp = &sc->arpcom.ac_if; 933 ifp->if_softc = sc; 934 ifp->if_unit = unit; 935 ifp->if_name = "wb"; 936 ifp->if_mtu = ETHERMTU; 937 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 938 ifp->if_ioctl = wb_ioctl; 939 ifp->if_output = ether_output; 940 ifp->if_start = wb_start; 941 ifp->if_watchdog = wb_watchdog; 942 ifp->if_init = wb_init; 943 ifp->if_baudrate = 10000000; 944 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 945 946 /* 947 * Do MII setup. 948 */ 949 if (mii_phy_probe(dev, &sc->wb_miibus, 950 wb_ifmedia_upd, wb_ifmedia_sts)) { 951 error = ENXIO; 952 goto fail; 953 } 954 955 /* 956 * Call MI attach routine. 957 */ 958 ether_ifattach(ifp, eaddr); 959 960 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 961 wb_intr, sc, &sc->wb_intrhand); 962 963 if (error) { 964 printf("wb%d: couldn't set up irq\n", unit); 965 goto fail; 966 } 967 968fail: 969 if (error) 970 wb_detach(dev); 971 972 return(error); 973} 974 975static int 976wb_detach(dev) 977 device_t dev; 978{ 979 struct wb_softc *sc; 980 struct ifnet *ifp; 981 982 sc = device_get_softc(dev); 983 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 984 WB_LOCK(sc); 985 ifp = &sc->arpcom.ac_if; 986 987 /* Delete any miibus and phy devices attached to this interface */ 988 if (device_is_alive(dev)) { 989 if (bus_child_present(dev)) 990 wb_stop(sc); 991 ether_ifdetach(ifp); 992 device_delete_child(dev, sc->wb_miibus); 993 bus_generic_detach(dev); 994 } 995 996 if (sc->wb_intrhand) 997 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 998 if (sc->wb_irq) 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1000 if (sc->wb_res) 1001 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1002 1003 if (sc->wb_ldata) { 1004 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1005 M_DEVBUF); 1006 } 1007 1008 WB_UNLOCK(sc); 1009 mtx_destroy(&sc->wb_mtx); 1010 1011 return(0); 1012} 1013 1014/* 1015 * Initialize the transmit descriptors. 1016 */ 1017static int 1018wb_list_tx_init(sc) 1019 struct wb_softc *sc; 1020{ 1021 struct wb_chain_data *cd; 1022 struct wb_list_data *ld; 1023 int i; 1024 1025 cd = &sc->wb_cdata; 1026 ld = sc->wb_ldata; 1027 1028 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1029 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1030 if (i == (WB_TX_LIST_CNT - 1)) { 1031 cd->wb_tx_chain[i].wb_nextdesc = 1032 &cd->wb_tx_chain[0]; 1033 } else { 1034 cd->wb_tx_chain[i].wb_nextdesc = 1035 &cd->wb_tx_chain[i + 1]; 1036 } 1037 } 1038 1039 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1040 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1041 1042 return(0); 1043} 1044 1045 1046/* 1047 * Initialize the RX descriptors and allocate mbufs for them. Note that 1048 * we arrange the descriptors in a closed ring, so that the last descriptor 1049 * points back to the first. 1050 */ 1051static int 1052wb_list_rx_init(sc) 1053 struct wb_softc *sc; 1054{ 1055 struct wb_chain_data *cd; 1056 struct wb_list_data *ld; 1057 int i; 1058 1059 cd = &sc->wb_cdata; 1060 ld = sc->wb_ldata; 1061 1062 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1063 cd->wb_rx_chain[i].wb_ptr = 1064 (struct wb_desc *)&ld->wb_rx_list[i]; 1065 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1066 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1067 return(ENOBUFS); 1068 if (i == (WB_RX_LIST_CNT - 1)) { 1069 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1070 ld->wb_rx_list[i].wb_next = 1071 vtophys(&ld->wb_rx_list[0]); 1072 } else { 1073 cd->wb_rx_chain[i].wb_nextdesc = 1074 &cd->wb_rx_chain[i + 1]; 1075 ld->wb_rx_list[i].wb_next = 1076 vtophys(&ld->wb_rx_list[i + 1]); 1077 } 1078 } 1079 1080 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1081 1082 return(0); 1083} 1084 1085static void 1086wb_bfree(buf, args) 1087 void *buf; 1088 void *args; 1089{ 1090 return; 1091} 1092 1093/* 1094 * Initialize an RX descriptor and attach an MBUF cluster. 1095 */ 1096static int 1097wb_newbuf(sc, c, m) 1098 struct wb_softc *sc; 1099 struct wb_chain_onefrag *c; 1100 struct mbuf *m; 1101{ 1102 struct mbuf *m_new = NULL; 1103 1104 if (m == NULL) { 1105 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1106 if (m_new == NULL) 1107 return(ENOBUFS); 1108 m_new->m_data = c->wb_buf; 1109 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1110 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1111 EXT_NET_DRV); 1112 } else { 1113 m_new = m; 1114 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1115 m_new->m_data = m_new->m_ext.ext_buf; 1116 } 1117 1118 m_adj(m_new, sizeof(u_int64_t)); 1119 1120 c->wb_mbuf = m_new; 1121 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1122 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1123 c->wb_ptr->wb_status = WB_RXSTAT; 1124 1125 return(0); 1126} 1127 1128/* 1129 * A frame has been uploaded: pass the resulting mbuf chain up to 1130 * the higher level protocols. 1131 */ 1132static void 1133wb_rxeof(sc) 1134 struct wb_softc *sc; 1135{ 1136 struct mbuf *m = NULL; 1137 struct ifnet *ifp; 1138 struct wb_chain_onefrag *cur_rx; 1139 int total_len = 0; 1140 u_int32_t rxstat; 1141 1142 ifp = &sc->arpcom.ac_if; 1143 1144 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1145 WB_RXSTAT_OWN)) { 1146 struct mbuf *m0 = NULL; 1147 1148 cur_rx = sc->wb_cdata.wb_rx_head; 1149 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1150 1151 m = cur_rx->wb_mbuf; 1152 1153 if ((rxstat & WB_RXSTAT_MIIERR) || 1154 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1155 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1156 !(rxstat & WB_RXSTAT_LASTFRAG) || 1157 !(rxstat & WB_RXSTAT_RXCMP)) { 1158 ifp->if_ierrors++; 1159 wb_newbuf(sc, cur_rx, m); 1160 printf("wb%x: receiver babbling: possible chip " 1161 "bug, forcing reset\n", sc->wb_unit); 1162 wb_fixmedia(sc); 1163 wb_reset(sc); 1164 wb_init(sc); 1165 return; 1166 } 1167 1168 if (rxstat & WB_RXSTAT_RXERR) { 1169 ifp->if_ierrors++; 1170 wb_newbuf(sc, cur_rx, m); 1171 break; 1172 } 1173 1174 /* No errors; receive the packet. */ 1175 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1176 1177 /* 1178 * XXX The Winbond chip includes the CRC with every 1179 * received frame, and there's no way to turn this 1180 * behavior off (at least, I can't find anything in 1181 * the manual that explains how to do it) so we have 1182 * to trim off the CRC manually. 1183 */ 1184 total_len -= ETHER_CRC_LEN; 1185 1186 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1187 NULL); 1188 wb_newbuf(sc, cur_rx, m); 1189 if (m0 == NULL) { 1190 ifp->if_ierrors++; 1191 break; 1192 } 1193 m = m0; 1194 1195 ifp->if_ipackets++; 1196 (*ifp->if_input)(ifp, m); 1197 } 1198} 1199 1200static void 1201wb_rxeoc(sc) 1202 struct wb_softc *sc; 1203{ 1204 wb_rxeof(sc); 1205 1206 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1207 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1208 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1209 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1210 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1211 1212 return; 1213} 1214 1215/* 1216 * A frame was downloaded to the chip. It's safe for us to clean up 1217 * the list buffers. 1218 */ 1219static void 1220wb_txeof(sc) 1221 struct wb_softc *sc; 1222{ 1223 struct wb_chain *cur_tx; 1224 struct ifnet *ifp; 1225 1226 ifp = &sc->arpcom.ac_if; 1227 1228 /* Clear the timeout timer. */ 1229 ifp->if_timer = 0; 1230 1231 if (sc->wb_cdata.wb_tx_head == NULL) 1232 return; 1233 1234 /* 1235 * Go through our tx list and free mbufs for those 1236 * frames that have been transmitted. 1237 */ 1238 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1239 u_int32_t txstat; 1240 1241 cur_tx = sc->wb_cdata.wb_tx_head; 1242 txstat = WB_TXSTATUS(cur_tx); 1243 1244 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1245 break; 1246 1247 if (txstat & WB_TXSTAT_TXERR) { 1248 ifp->if_oerrors++; 1249 if (txstat & WB_TXSTAT_ABORT) 1250 ifp->if_collisions++; 1251 if (txstat & WB_TXSTAT_LATECOLL) 1252 ifp->if_collisions++; 1253 } 1254 1255 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1256 1257 ifp->if_opackets++; 1258 m_freem(cur_tx->wb_mbuf); 1259 cur_tx->wb_mbuf = NULL; 1260 1261 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1262 sc->wb_cdata.wb_tx_head = NULL; 1263 sc->wb_cdata.wb_tx_tail = NULL; 1264 break; 1265 } 1266 1267 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1268 } 1269 1270 return; 1271} 1272 1273/* 1274 * TX 'end of channel' interrupt handler. 1275 */ 1276static void 1277wb_txeoc(sc) 1278 struct wb_softc *sc; 1279{ 1280 struct ifnet *ifp; 1281 1282 ifp = &sc->arpcom.ac_if; 1283 1284 ifp->if_timer = 0; 1285 1286 if (sc->wb_cdata.wb_tx_head == NULL) { 1287 ifp->if_flags &= ~IFF_OACTIVE; 1288 sc->wb_cdata.wb_tx_tail = NULL; 1289 } else { 1290 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1291 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1292 ifp->if_timer = 5; 1293 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1294 } 1295 } 1296 1297 return; 1298} 1299 1300static void 1301wb_intr(arg) 1302 void *arg; 1303{ 1304 struct wb_softc *sc; 1305 struct ifnet *ifp; 1306 u_int32_t status; 1307 1308 sc = arg; 1309 WB_LOCK(sc); 1310 ifp = &sc->arpcom.ac_if; 1311 1312 if (!(ifp->if_flags & IFF_UP)) { 1313 WB_UNLOCK(sc); 1314 return; 1315 } 1316 1317 /* Disable interrupts. */ 1318 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1319 1320 for (;;) { 1321 1322 status = CSR_READ_4(sc, WB_ISR); 1323 if (status) 1324 CSR_WRITE_4(sc, WB_ISR, status); 1325 1326 if ((status & WB_INTRS) == 0) 1327 break; 1328 1329 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1330 ifp->if_ierrors++; 1331 wb_reset(sc); 1332 if (status & WB_ISR_RX_ERR) 1333 wb_fixmedia(sc); 1334 wb_init(sc); 1335 continue; 1336 } 1337 1338 if (status & WB_ISR_RX_OK) 1339 wb_rxeof(sc); 1340 1341 if (status & WB_ISR_RX_IDLE) 1342 wb_rxeoc(sc); 1343 1344 if (status & WB_ISR_TX_OK) 1345 wb_txeof(sc); 1346 1347 if (status & WB_ISR_TX_NOBUF) 1348 wb_txeoc(sc); 1349 1350 if (status & WB_ISR_TX_IDLE) { 1351 wb_txeof(sc); 1352 if (sc->wb_cdata.wb_tx_head != NULL) { 1353 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1354 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1355 } 1356 } 1357 1358 if (status & WB_ISR_TX_UNDERRUN) { 1359 ifp->if_oerrors++; 1360 wb_txeof(sc); 1361 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1362 /* Jack up TX threshold */ 1363 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1364 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1365 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1366 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1367 } 1368 1369 if (status & WB_ISR_BUS_ERR) { 1370 wb_reset(sc); 1371 wb_init(sc); 1372 } 1373 1374 } 1375 1376 /* Re-enable interrupts. */ 1377 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1378 1379 if (ifp->if_snd.ifq_head != NULL) { 1380 wb_start(ifp); 1381 } 1382 1383 WB_UNLOCK(sc); 1384 1385 return; 1386} 1387 1388static void 1389wb_tick(xsc) 1390 void *xsc; 1391{ 1392 struct wb_softc *sc; 1393 struct mii_data *mii; 1394 1395 sc = xsc; 1396 WB_LOCK(sc); 1397 mii = device_get_softc(sc->wb_miibus); 1398 1399 mii_tick(mii); 1400 1401 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1402 1403 WB_UNLOCK(sc); 1404 1405 return; 1406} 1407 1408/* 1409 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1410 * pointers to the fragment pointers. 1411 */ 1412static int 1413wb_encap(sc, c, m_head) 1414 struct wb_softc *sc; 1415 struct wb_chain *c; 1416 struct mbuf *m_head; 1417{ 1418 int frag = 0; 1419 struct wb_desc *f = NULL; 1420 int total_len; 1421 struct mbuf *m; 1422 1423 /* 1424 * Start packing the mbufs in this chain into 1425 * the fragment pointers. Stop when we run out 1426 * of fragments or hit the end of the mbuf chain. 1427 */ 1428 m = m_head; 1429 total_len = 0; 1430 1431 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1432 if (m->m_len != 0) { 1433 if (frag == WB_MAXFRAGS) 1434 break; 1435 total_len += m->m_len; 1436 f = &c->wb_ptr->wb_frag[frag]; 1437 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1438 if (frag == 0) { 1439 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1440 f->wb_status = 0; 1441 } else 1442 f->wb_status = WB_TXSTAT_OWN; 1443 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1444 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1445 frag++; 1446 } 1447 } 1448 1449 /* 1450 * Handle special case: we used up all 16 fragments, 1451 * but we have more mbufs left in the chain. Copy the 1452 * data into an mbuf cluster. Note that we don't 1453 * bother clearing the values in the other fragment 1454 * pointers/counters; it wouldn't gain us anything, 1455 * and would waste cycles. 1456 */ 1457 if (m != NULL) { 1458 struct mbuf *m_new = NULL; 1459 1460 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1461 if (m_new == NULL) 1462 return(1); 1463 if (m_head->m_pkthdr.len > MHLEN) { 1464 MCLGET(m_new, M_DONTWAIT); 1465 if (!(m_new->m_flags & M_EXT)) { 1466 m_freem(m_new); 1467 return(1); 1468 } 1469 } 1470 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1471 mtod(m_new, caddr_t)); 1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1473 m_freem(m_head); 1474 m_head = m_new; 1475 f = &c->wb_ptr->wb_frag[0]; 1476 f->wb_status = 0; 1477 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1478 f->wb_ctl = total_len = m_new->m_len; 1479 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1480 frag = 1; 1481 } 1482 1483 if (total_len < WB_MIN_FRAMELEN) { 1484 f = &c->wb_ptr->wb_frag[frag]; 1485 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1486 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1487 f->wb_ctl |= WB_TXCTL_TLINK; 1488 f->wb_status = WB_TXSTAT_OWN; 1489 frag++; 1490 } 1491 1492 c->wb_mbuf = m_head; 1493 c->wb_lastdesc = frag - 1; 1494 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1495 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1496 1497 return(0); 1498} 1499 1500/* 1501 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1502 * to the mbuf data regions directly in the transmit lists. We also save a 1503 * copy of the pointers since the transmit list fragment pointers are 1504 * physical addresses. 1505 */ 1506 1507static void 1508wb_start(ifp) 1509 struct ifnet *ifp; 1510{ 1511 struct wb_softc *sc; 1512 struct mbuf *m_head = NULL; 1513 struct wb_chain *cur_tx = NULL, *start_tx; 1514 1515 sc = ifp->if_softc; 1516 WB_LOCK(sc); 1517 1518 /* 1519 * Check for an available queue slot. If there are none, 1520 * punt. 1521 */ 1522 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1523 ifp->if_flags |= IFF_OACTIVE; 1524 WB_UNLOCK(sc); 1525 return; 1526 } 1527 1528 start_tx = sc->wb_cdata.wb_tx_free; 1529 1530 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1531 IF_DEQUEUE(&ifp->if_snd, m_head); 1532 if (m_head == NULL) 1533 break; 1534 1535 /* Pick a descriptor off the free list. */ 1536 cur_tx = sc->wb_cdata.wb_tx_free; 1537 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1538 1539 /* Pack the data into the descriptor. */ 1540 wb_encap(sc, cur_tx, m_head); 1541 1542 if (cur_tx != start_tx) 1543 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1544 1545 /* 1546 * If there's a BPF listener, bounce a copy of this frame 1547 * to him. 1548 */ 1549 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1550 } 1551 1552 /* 1553 * If there are no packets queued, bail. 1554 */ 1555 if (cur_tx == NULL) { 1556 WB_UNLOCK(sc); 1557 return; 1558 } 1559 1560 /* 1561 * Place the request for the upload interrupt 1562 * in the last descriptor in the chain. This way, if 1563 * we're chaining several packets at once, we'll only 1564 * get an interupt once for the whole chain rather than 1565 * once for each packet. 1566 */ 1567 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1568 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1569 sc->wb_cdata.wb_tx_tail = cur_tx; 1570 1571 if (sc->wb_cdata.wb_tx_head == NULL) { 1572 sc->wb_cdata.wb_tx_head = start_tx; 1573 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1574 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1575 } else { 1576 /* 1577 * We need to distinguish between the case where 1578 * the own bit is clear because the chip cleared it 1579 * and where the own bit is clear because we haven't 1580 * set it yet. The magic value WB_UNSET is just some 1581 * ramdomly chosen number which doesn't have the own 1582 * bit set. When we actually transmit the frame, the 1583 * status word will have _only_ the own bit set, so 1584 * the txeoc handler will be able to tell if it needs 1585 * to initiate another transmission to flush out pending 1586 * frames. 1587 */ 1588 WB_TXOWN(start_tx) = WB_UNSENT; 1589 } 1590 1591 /* 1592 * Set a timeout in case the chip goes out to lunch. 1593 */ 1594 ifp->if_timer = 5; 1595 WB_UNLOCK(sc); 1596 1597 return; 1598} 1599 1600static void 1601wb_init(xsc) 1602 void *xsc; 1603{ 1604 struct wb_softc *sc = xsc; 1605 struct ifnet *ifp = &sc->arpcom.ac_if; 1606 int i; 1607 struct mii_data *mii; 1608 1609 WB_LOCK(sc); 1610 mii = device_get_softc(sc->wb_miibus); 1611 1612 /* 1613 * Cancel pending I/O and free all RX/TX buffers. 1614 */ 1615 wb_stop(sc); 1616 wb_reset(sc); 1617 1618 sc->wb_txthresh = WB_TXTHRESH_INIT; 1619 1620 /* 1621 * Set cache alignment and burst length. 1622 */ 1623#ifdef foo 1624 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1625 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1626 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1627#endif 1628 1629 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1630 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1631 switch(sc->wb_cachesize) { 1632 case 32: 1633 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1634 break; 1635 case 16: 1636 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1637 break; 1638 case 8: 1639 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1640 break; 1641 case 0: 1642 default: 1643 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1644 break; 1645 } 1646 1647 /* This doesn't tend to work too well at 100Mbps. */ 1648 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1649 1650 /* Init our MAC address */ 1651 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1652 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1653 } 1654 1655 /* Init circular RX list. */ 1656 if (wb_list_rx_init(sc) == ENOBUFS) { 1657 printf("wb%d: initialization failed: no " 1658 "memory for rx buffers\n", sc->wb_unit); 1659 wb_stop(sc); 1660 WB_UNLOCK(sc); 1661 return; 1662 } 1663 1664 /* Init TX descriptors. */ 1665 wb_list_tx_init(sc); 1666 1667 /* If we want promiscuous mode, set the allframes bit. */ 1668 if (ifp->if_flags & IFF_PROMISC) { 1669 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1670 } else { 1671 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1672 } 1673 1674 /* 1675 * Set capture broadcast bit to capture broadcast frames. 1676 */ 1677 if (ifp->if_flags & IFF_BROADCAST) { 1678 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1679 } else { 1680 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1681 } 1682 1683 /* 1684 * Program the multicast filter, if necessary. 1685 */ 1686 wb_setmulti(sc); 1687 1688 /* 1689 * Load the address of the RX list. 1690 */ 1691 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1692 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1693 1694 /* 1695 * Enable interrupts. 1696 */ 1697 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1698 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1699 1700 /* Enable receiver and transmitter. */ 1701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1702 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1703 1704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1705 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1707 1708 mii_mediachg(mii); 1709 1710 ifp->if_flags |= IFF_RUNNING; 1711 ifp->if_flags &= ~IFF_OACTIVE; 1712 1713 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1714 WB_UNLOCK(sc); 1715 1716 return; 1717} 1718 1719/* 1720 * Set media options. 1721 */ 1722static int 1723wb_ifmedia_upd(ifp) 1724 struct ifnet *ifp; 1725{ 1726 struct wb_softc *sc; 1727 1728 sc = ifp->if_softc; 1729 1730 if (ifp->if_flags & IFF_UP) 1731 wb_init(sc); 1732 1733 return(0); 1734} 1735 1736/* 1737 * Report current media status. 1738 */ 1739static void 1740wb_ifmedia_sts(ifp, ifmr) 1741 struct ifnet *ifp; 1742 struct ifmediareq *ifmr; 1743{ 1744 struct wb_softc *sc; 1745 struct mii_data *mii; 1746 1747 sc = ifp->if_softc; 1748 1749 mii = device_get_softc(sc->wb_miibus); 1750 1751 mii_pollstat(mii); 1752 ifmr->ifm_active = mii->mii_media_active; 1753 ifmr->ifm_status = mii->mii_media_status; 1754 1755 return; 1756} 1757 1758static int 1759wb_ioctl(ifp, command, data) 1760 struct ifnet *ifp; 1761 u_long command; 1762 caddr_t data; 1763{ 1764 struct wb_softc *sc = ifp->if_softc; 1765 struct mii_data *mii; 1766 struct ifreq *ifr = (struct ifreq *) data; 1767 int error = 0; 1768 1769 WB_LOCK(sc); 1770 1771 switch(command) { 1772 case SIOCSIFFLAGS: 1773 if (ifp->if_flags & IFF_UP) { 1774 wb_init(sc); 1775 } else { 1776 if (ifp->if_flags & IFF_RUNNING) 1777 wb_stop(sc); 1778 } 1779 error = 0; 1780 break; 1781 case SIOCADDMULTI: 1782 case SIOCDELMULTI: 1783 wb_setmulti(sc); 1784 error = 0; 1785 break; 1786 case SIOCGIFMEDIA: 1787 case SIOCSIFMEDIA: 1788 mii = device_get_softc(sc->wb_miibus); 1789 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1790 break; 1791 default: 1792 error = ether_ioctl(ifp, command, data); 1793 break; 1794 } 1795 1796 WB_UNLOCK(sc); 1797 1798 return(error); 1799} 1800 1801static void 1802wb_watchdog(ifp) 1803 struct ifnet *ifp; 1804{ 1805 struct wb_softc *sc; 1806 1807 sc = ifp->if_softc; 1808 1809 WB_LOCK(sc); 1810 ifp->if_oerrors++; 1811 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1812#ifdef foo 1813 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1814 printf("wb%d: no carrier - transceiver cable problem?\n", 1815 sc->wb_unit); 1816#endif 1817 wb_stop(sc); 1818 wb_reset(sc); 1819 wb_init(sc); 1820 1821 if (ifp->if_snd.ifq_head != NULL) 1822 wb_start(ifp); 1823 WB_UNLOCK(sc); 1824 1825 return; 1826} 1827 1828/* 1829 * Stop the adapter and free any mbufs allocated to the 1830 * RX and TX lists. 1831 */ 1832static void 1833wb_stop(sc) 1834 struct wb_softc *sc; 1835{ 1836 register int i; 1837 struct ifnet *ifp; 1838 1839 WB_LOCK(sc); 1840 ifp = &sc->arpcom.ac_if; 1841 ifp->if_timer = 0; 1842 1843 untimeout(wb_tick, sc, sc->wb_stat_ch); 1844 1845 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1846 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1847 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1848 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1849 1850 /* 1851 * Free data in the RX lists. 1852 */ 1853 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1854 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1855 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1856 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1857 } 1858 } 1859 bzero((char *)&sc->wb_ldata->wb_rx_list, 1860 sizeof(sc->wb_ldata->wb_rx_list)); 1861 1862 /* 1863 * Free the TX list buffers. 1864 */ 1865 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1866 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1867 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1868 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1869 } 1870 } 1871 1872 bzero((char *)&sc->wb_ldata->wb_tx_list, 1873 sizeof(sc->wb_ldata->wb_tx_list)); 1874 1875 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1876 WB_UNLOCK(sc); 1877 1878 return; 1879} 1880 1881/* 1882 * Stop all chip I/O so that the kernel's probe routines don't 1883 * get confused by errant DMAs when rebooting. 1884 */ 1885static void 1886wb_shutdown(dev) 1887 device_t dev; 1888{ 1889 struct wb_softc *sc; 1890 1891 sc = device_get_softc(dev); 1892 wb_stop(sc); 1893 1894 return; 1895} 1896