1/* $FreeBSD: releng/10.2/sys/dev/usb/controller/musb_otg.c 279279 2015-02-25 12:24:24Z hselasky $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#ifdef USB_GLOBAL_INCLUDE_FILE 40#include USB_GLOBAL_INCLUDE_FILE 41#else 42#include <sys/stdint.h> 43#include <sys/stddef.h> 44#include <sys/param.h> 45#include <sys/queue.h> 46#include <sys/types.h> 47#include <sys/systm.h> 48#include <sys/kernel.h> 49#include <sys/bus.h> 50#include <sys/module.h> 51#include <sys/lock.h> 52#include <sys/mutex.h> 53#include <sys/condvar.h> 54#include <sys/sysctl.h> 55#include <sys/sx.h> 56#include <sys/unistd.h> 57#include <sys/callout.h> 58#include <sys/malloc.h> 59#include <sys/priv.h> 60 61#include <dev/usb/usb.h> 62#include <dev/usb/usbdi.h> 63 64#define USB_DEBUG_VAR musbotgdebug 65 66#include <dev/usb/usb_core.h> 67#include <dev/usb/usb_debug.h> 68#include <dev/usb/usb_busdma.h> 69#include <dev/usb/usb_process.h> 70#include <dev/usb/usb_transfer.h> 71#include <dev/usb/usb_device.h> 72#include <dev/usb/usb_hub.h> 73#include <dev/usb/usb_util.h> 74 75#include <dev/usb/usb_controller.h> 76#include <dev/usb/usb_bus.h> 77#endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79#include <dev/usb/controller/musb_otg.h> 80 81#define MUSBOTG_INTR_ENDPT 1 82 83#define MUSBOTG_BUS2SC(bus) \ 84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 86 87#define MUSBOTG_PC2SC(pc) \ 88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 89 90#ifdef USB_DEBUG 91static int musbotgdebug = 0; 92 93static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 94SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 95 &musbotgdebug, 0, "Debug level"); 96#endif 97 98#define MAX_NAK_TO 16 99 100/* prototypes */ 101 102struct usb_bus_methods musbotg_bus_methods; 103struct usb_pipe_methods musbotg_device_bulk_methods; 104struct usb_pipe_methods musbotg_device_ctrl_methods; 105struct usb_pipe_methods musbotg_device_intr_methods; 106struct usb_pipe_methods musbotg_device_isoc_methods; 107 108/* Control transfers: Device mode */ 109static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 110static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 111static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 112static musbotg_cmd_t musbotg_dev_ctrl_status; 113 114/* Control transfers: Host mode */ 115static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 116static musbotg_cmd_t musbotg_host_ctrl_data_rx; 117static musbotg_cmd_t musbotg_host_ctrl_data_tx; 118static musbotg_cmd_t musbotg_host_ctrl_status_rx; 119static musbotg_cmd_t musbotg_host_ctrl_status_tx; 120 121/* Bulk, Interrupt, Isochronous: Device mode */ 122static musbotg_cmd_t musbotg_dev_data_rx; 123static musbotg_cmd_t musbotg_dev_data_tx; 124 125/* Bulk, Interrupt, Isochronous: Host mode */ 126static musbotg_cmd_t musbotg_host_data_rx; 127static musbotg_cmd_t musbotg_host_data_tx; 128 129static void musbotg_device_done(struct usb_xfer *, usb_error_t); 130static void musbotg_do_poll(struct usb_bus *); 131static void musbotg_standard_done(struct usb_xfer *); 132static void musbotg_interrupt_poll(struct musbotg_softc *); 133static void musbotg_root_intr(struct musbotg_softc *); 134static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td); 135static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 136static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 137 138/* 139 * Here is a configuration that the chip supports. 140 */ 141static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 142 143 [0] = { 144 .max_in_frame_size = 64,/* fixed */ 145 .max_out_frame_size = 64, /* fixed */ 146 .is_simplex = 1, 147 .support_control = 1, 148 } 149}; 150 151static int 152musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td) 153{ 154 int ch; 155 int ep; 156 157 ep = td->ep_no; 158 159 /* In device mode each EP got its own channel */ 160 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 161 musbotg_ep_int_set(sc, ep, 1); 162 return (ep); 163 } 164 165 /* 166 * All control transactions go through EP0 167 */ 168 if (ep == 0) { 169 if (sc->sc_channel_mask & (1 << 0)) 170 return (-1); 171 sc->sc_channel_mask |= (1 << 0); 172 musbotg_ep_int_set(sc, ep, 1); 173 return (0); 174 } 175 176 for (ch = 1; ch < MUSB2_EP_MAX; ch++) { 177 if (!(sc->sc_channel_mask & (1 << ch))) { 178 sc->sc_channel_mask |= (1 << ch); 179 musbotg_ep_int_set(sc, ch, 1); 180 return (ch); 181 } 182 } 183 184 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 185 186 return (-1); 187} 188 189static void 190musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 191{ 192 193 DPRINTFN(1, "ep_no=%d\n", td->channel); 194 195 if (sc->sc_mode == MUSB2_DEVICE_MODE) 196 return; 197 198 if (td == NULL) 199 return; 200 if (td->channel == -1) 201 return; 202 203 musbotg_ep_int_set(sc, td->channel, 0); 204 sc->sc_channel_mask &= ~(1 << td->channel); 205 206 td->channel = -1; 207} 208 209static void 210musbotg_get_hw_ep_profile(struct usb_device *udev, 211 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 212{ 213 struct musbotg_softc *sc; 214 215 sc = MUSBOTG_BUS2SC(udev->bus); 216 217 if (ep_addr == 0) { 218 /* control endpoint */ 219 *ppf = musbotg_ep_profile; 220 } else if (ep_addr <= sc->sc_ep_max) { 221 /* other endpoints */ 222 *ppf = sc->sc_hw_ep_profile + ep_addr; 223 } else { 224 *ppf = NULL; 225 } 226} 227 228static void 229musbotg_clocks_on(struct musbotg_softc *sc) 230{ 231 if (sc->sc_flags.clocks_off && 232 sc->sc_flags.port_powered) { 233 234 DPRINTFN(4, "\n"); 235 236 if (sc->sc_clocks_on) { 237 (sc->sc_clocks_on) (sc->sc_clocks_arg); 238 } 239 sc->sc_flags.clocks_off = 0; 240 241 /* XXX enable Transceiver */ 242 } 243} 244 245static void 246musbotg_clocks_off(struct musbotg_softc *sc) 247{ 248 if (!sc->sc_flags.clocks_off) { 249 250 DPRINTFN(4, "\n"); 251 252 /* XXX disable Transceiver */ 253 254 if (sc->sc_clocks_off) { 255 (sc->sc_clocks_off) (sc->sc_clocks_arg); 256 } 257 sc->sc_flags.clocks_off = 1; 258 } 259} 260 261static void 262musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 263{ 264 uint8_t temp; 265 266 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 267 if (on) 268 temp |= MUSB2_MASK_SOFTC; 269 else 270 temp &= ~MUSB2_MASK_SOFTC; 271 272 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 273} 274 275static void 276musbotg_pull_up(struct musbotg_softc *sc) 277{ 278 /* pullup D+, if possible */ 279 280 if (!sc->sc_flags.d_pulled_up && 281 sc->sc_flags.port_powered) { 282 sc->sc_flags.d_pulled_up = 1; 283 musbotg_pull_common(sc, 1); 284 } 285} 286 287static void 288musbotg_pull_down(struct musbotg_softc *sc) 289{ 290 /* pulldown D+, if possible */ 291 292 if (sc->sc_flags.d_pulled_up) { 293 sc->sc_flags.d_pulled_up = 0; 294 musbotg_pull_common(sc, 0); 295 } 296} 297 298static void 299musbotg_suspend_host(struct musbotg_softc *sc) 300{ 301 uint8_t temp; 302 303 if (sc->sc_flags.status_suspend) { 304 return; 305 } 306 307 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 308 temp |= MUSB2_MASK_SUSPMODE; 309 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 310 sc->sc_flags.status_suspend = 1; 311} 312 313static void 314musbotg_wakeup_host(struct musbotg_softc *sc) 315{ 316 uint8_t temp; 317 318 if (!(sc->sc_flags.status_suspend)) { 319 return; 320 } 321 322 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 323 temp &= ~MUSB2_MASK_SUSPMODE; 324 temp |= MUSB2_MASK_RESUME; 325 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 326 327 /* wait 20 milliseconds */ 328 /* Wait for reset to complete. */ 329 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 330 331 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 332 temp &= ~MUSB2_MASK_RESUME; 333 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 334 335 sc->sc_flags.status_suspend = 0; 336} 337 338static void 339musbotg_wakeup_peer(struct musbotg_softc *sc) 340{ 341 uint8_t temp; 342 343 if (!(sc->sc_flags.status_suspend)) { 344 return; 345 } 346 347 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 348 temp |= MUSB2_MASK_RESUME; 349 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 350 351 /* wait 8 milliseconds */ 352 /* Wait for reset to complete. */ 353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 354 355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 356 temp &= ~MUSB2_MASK_RESUME; 357 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 358} 359 360static void 361musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 362{ 363 DPRINTFN(4, "addr=%d\n", addr); 364 addr &= 0x7F; 365 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 366} 367 368static uint8_t 369musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 370{ 371 struct musbotg_softc *sc; 372 struct usb_device_request req; 373 uint16_t count; 374 uint8_t csr; 375 376 /* get pointer to softc */ 377 sc = MUSBOTG_PC2SC(td->pc); 378 379 if (td->channel == -1) 380 td->channel = musbotg_channel_alloc(sc, td); 381 382 /* EP0 is busy, wait */ 383 if (td->channel == -1) 384 return (1); 385 386 DPRINTFN(1, "ep_no=%d\n", td->channel); 387 388 /* select endpoint 0 */ 389 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 390 391 /* read out FIFO status */ 392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 393 394 DPRINTFN(4, "csr=0x%02x\n", csr); 395 396 /* 397 * NOTE: If DATAEND is set we should not call the 398 * callback, hence the status stage is not complete. 399 */ 400 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 401 /* do not stall at this point */ 402 td->did_stall = 1; 403 /* wait for interrupt */ 404 DPRINTFN(1, "CSR0 DATAEND\n"); 405 goto not_complete; 406 } 407 408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 409 /* clear SENTSTALL */ 410 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 411 /* get latest status */ 412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 413 /* update EP0 state */ 414 sc->sc_ep0_busy = 0; 415 } 416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 417 /* clear SETUPEND */ 418 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 419 MUSB2_MASK_CSR0L_SETUPEND_CLR); 420 /* get latest status */ 421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 422 /* update EP0 state */ 423 sc->sc_ep0_busy = 0; 424 } 425 if (sc->sc_ep0_busy) { 426 DPRINTFN(1, "EP0 BUSY\n"); 427 goto not_complete; 428 } 429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 430 goto not_complete; 431 } 432 /* get the packet byte count */ 433 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 434 435 /* verify data length */ 436 if (count != td->remainder) { 437 DPRINTFN(1, "Invalid SETUP packet " 438 "length, %d bytes\n", count); 439 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 440 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 441 /* don't clear stall */ 442 td->did_stall = 1; 443 goto not_complete; 444 } 445 if (count != sizeof(req)) { 446 DPRINTFN(1, "Unsupported SETUP packet " 447 "length, %d bytes\n", count); 448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 449 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 450 /* don't clear stall */ 451 td->did_stall = 1; 452 goto not_complete; 453 } 454 /* clear did stall flag */ 455 td->did_stall = 0; 456 457 /* receive data */ 458 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 459 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 460 461 /* copy data into real buffer */ 462 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 463 464 td->offset = sizeof(req); 465 td->remainder = 0; 466 467 /* set pending command */ 468 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 469 470 /* we need set stall or dataend after this */ 471 sc->sc_ep0_busy = 1; 472 473 /* sneak peek the set address */ 474 if ((req.bmRequestType == UT_WRITE_DEVICE) && 475 (req.bRequest == UR_SET_ADDRESS)) { 476 sc->sc_dv_addr = req.wValue[0] & 0x7F; 477 } else { 478 sc->sc_dv_addr = 0xFF; 479 } 480 481 musbotg_channel_free(sc, td); 482 return (0); /* complete */ 483 484not_complete: 485 /* abort any ongoing transfer */ 486 if (!td->did_stall) { 487 DPRINTFN(4, "stalling\n"); 488 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 489 MUSB2_MASK_CSR0L_SENDSTALL); 490 td->did_stall = 1; 491 } 492 return (1); /* not complete */ 493} 494 495static uint8_t 496musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 497{ 498 struct musbotg_softc *sc; 499 struct usb_device_request req; 500 uint8_t csr, csrh; 501 502 /* get pointer to softc */ 503 sc = MUSBOTG_PC2SC(td->pc); 504 505 if (td->channel == -1) 506 td->channel = musbotg_channel_alloc(sc, td); 507 508 /* EP0 is busy, wait */ 509 if (td->channel == -1) 510 return (1); 511 512 DPRINTFN(1, "ep_no=%d\n", td->channel); 513 514 /* select endpoint 0 */ 515 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 516 517 /* read out FIFO status */ 518 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 519 DPRINTFN(4, "csr=0x%02x\n", csr); 520 521 /* Not ready yet yet */ 522 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 523 return (1); 524 525 /* Failed */ 526 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 527 MUSB2_MASK_CSR0L_ERROR)) 528 { 529 /* Clear status bit */ 530 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 531 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 532 td->error = 1; 533 } 534 535 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 536 DPRINTFN(1, "NAK timeout\n"); 537 538 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 539 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 540 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 543 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 544 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 545 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 546 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 547 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 548 } 549 } 550 551 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 552 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 553 554 td->error = 1; 555 } 556 557 if (td->error) { 558 musbotg_channel_free(sc, td); 559 return (0); 560 } 561 562 /* Fifo is not empty and there is no NAK timeout */ 563 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 564 return (1); 565 566 /* check if we are complete */ 567 if (td->remainder == 0) { 568 /* we are complete */ 569 musbotg_channel_free(sc, td); 570 return (0); 571 } 572 573 /* copy data into real buffer */ 574 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 575 576 /* send data */ 577 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 578 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 579 580 /* update offset and remainder */ 581 td->offset += sizeof(req); 582 td->remainder -= sizeof(req); 583 584 585 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 586 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 587 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 588 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 589 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 590 591 /* write command */ 592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 593 MUSB2_MASK_CSR0L_TXPKTRDY | 594 MUSB2_MASK_CSR0L_SETUPPKT); 595 596 /* Just to be consistent, not used above */ 597 td->transaction_started = 1; 598 599 return (1); /* in progress */ 600} 601 602/* Control endpoint only data handling functions (RX/TX/SYNC) */ 603 604static uint8_t 605musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 606{ 607 struct usb_page_search buf_res; 608 struct musbotg_softc *sc; 609 uint16_t count; 610 uint8_t csr; 611 uint8_t got_short; 612 613 /* get pointer to softc */ 614 sc = MUSBOTG_PC2SC(td->pc); 615 616 /* select endpoint 0 */ 617 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 618 619 /* check if a command is pending */ 620 if (sc->sc_ep0_cmd) { 621 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 622 sc->sc_ep0_cmd = 0; 623 } 624 /* read out FIFO status */ 625 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 626 627 DPRINTFN(4, "csr=0x%02x\n", csr); 628 629 got_short = 0; 630 631 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 632 MUSB2_MASK_CSR0L_SENTSTALL)) { 633 if (td->remainder == 0) { 634 /* 635 * We are actually complete and have 636 * received the next SETUP 637 */ 638 DPRINTFN(4, "faking complete\n"); 639 return (0); /* complete */ 640 } 641 /* 642 * USB Host Aborted the transfer. 643 */ 644 td->error = 1; 645 return (0); /* complete */ 646 } 647 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 648 return (1); /* not complete */ 649 } 650 /* get the packet byte count */ 651 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 652 653 /* verify the packet byte count */ 654 if (count != td->max_frame_size) { 655 if (count < td->max_frame_size) { 656 /* we have a short packet */ 657 td->short_pkt = 1; 658 got_short = 1; 659 } else { 660 /* invalid USB packet */ 661 td->error = 1; 662 return (0); /* we are complete */ 663 } 664 } 665 /* verify the packet byte count */ 666 if (count > td->remainder) { 667 /* invalid USB packet */ 668 td->error = 1; 669 return (0); /* we are complete */ 670 } 671 while (count > 0) { 672 uint32_t temp; 673 674 usbd_get_page(td->pc, td->offset, &buf_res); 675 676 /* get correct length */ 677 if (buf_res.length > count) { 678 buf_res.length = count; 679 } 680 /* check for unaligned memory address */ 681 if (USB_P2U(buf_res.buffer) & 3) { 682 683 temp = count & ~3; 684 685 if (temp) { 686 /* receive data 4 bytes at a time */ 687 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 688 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 689 temp / 4); 690 } 691 temp = count & 3; 692 if (temp) { 693 /* receive data 1 byte at a time */ 694 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 695 MUSB2_REG_EPFIFO(0), 696 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 697 } 698 usbd_copy_in(td->pc, td->offset, 699 sc->sc_bounce_buf, count); 700 701 /* update offset and remainder */ 702 td->offset += count; 703 td->remainder -= count; 704 break; 705 } 706 /* check if we can optimise */ 707 if (buf_res.length >= 4) { 708 709 /* receive data 4 bytes at a time */ 710 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 711 MUSB2_REG_EPFIFO(0), buf_res.buffer, 712 buf_res.length / 4); 713 714 temp = buf_res.length & ~3; 715 716 /* update counters */ 717 count -= temp; 718 td->offset += temp; 719 td->remainder -= temp; 720 continue; 721 } 722 /* receive data */ 723 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 724 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 725 726 /* update counters */ 727 count -= buf_res.length; 728 td->offset += buf_res.length; 729 td->remainder -= buf_res.length; 730 } 731 732 /* check if we are complete */ 733 if ((td->remainder == 0) || got_short) { 734 if (td->short_pkt) { 735 /* we are complete */ 736 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 737 return (0); 738 } 739 /* else need to receive a zero length packet */ 740 } 741 /* write command - need more data */ 742 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 743 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 744 return (1); /* not complete */ 745} 746 747static uint8_t 748musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 749{ 750 struct usb_page_search buf_res; 751 struct musbotg_softc *sc; 752 uint16_t count; 753 uint8_t csr; 754 755 /* get pointer to softc */ 756 sc = MUSBOTG_PC2SC(td->pc); 757 758 /* select endpoint 0 */ 759 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 760 761 /* check if a command is pending */ 762 if (sc->sc_ep0_cmd) { 763 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 764 sc->sc_ep0_cmd = 0; 765 } 766 /* read out FIFO status */ 767 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 768 769 DPRINTFN(4, "csr=0x%02x\n", csr); 770 771 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 772 MUSB2_MASK_CSR0L_SENTSTALL)) { 773 /* 774 * The current transfer was aborted 775 * by the USB Host 776 */ 777 td->error = 1; 778 return (0); /* complete */ 779 } 780 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 781 return (1); /* not complete */ 782 } 783 count = td->max_frame_size; 784 if (td->remainder < count) { 785 /* we have a short packet */ 786 td->short_pkt = 1; 787 count = td->remainder; 788 } 789 while (count > 0) { 790 uint32_t temp; 791 792 usbd_get_page(td->pc, td->offset, &buf_res); 793 794 /* get correct length */ 795 if (buf_res.length > count) { 796 buf_res.length = count; 797 } 798 /* check for unaligned memory address */ 799 if (USB_P2U(buf_res.buffer) & 3) { 800 801 usbd_copy_out(td->pc, td->offset, 802 sc->sc_bounce_buf, count); 803 804 temp = count & ~3; 805 806 if (temp) { 807 /* transmit data 4 bytes at a time */ 808 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 809 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 810 temp / 4); 811 } 812 temp = count & 3; 813 if (temp) { 814 /* receive data 1 byte at a time */ 815 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 816 MUSB2_REG_EPFIFO(0), 817 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 818 } 819 /* update offset and remainder */ 820 td->offset += count; 821 td->remainder -= count; 822 break; 823 } 824 /* check if we can optimise */ 825 if (buf_res.length >= 4) { 826 827 /* transmit data 4 bytes at a time */ 828 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 829 MUSB2_REG_EPFIFO(0), buf_res.buffer, 830 buf_res.length / 4); 831 832 temp = buf_res.length & ~3; 833 834 /* update counters */ 835 count -= temp; 836 td->offset += temp; 837 td->remainder -= temp; 838 continue; 839 } 840 /* transmit data */ 841 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 842 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 843 844 /* update counters */ 845 count -= buf_res.length; 846 td->offset += buf_res.length; 847 td->remainder -= buf_res.length; 848 } 849 850 /* check remainder */ 851 if (td->remainder == 0) { 852 if (td->short_pkt) { 853 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 854 return (0); /* complete */ 855 } 856 /* else we need to transmit a short packet */ 857 } 858 /* write command */ 859 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 860 MUSB2_MASK_CSR0L_TXPKTRDY); 861 862 return (1); /* not complete */ 863} 864 865static uint8_t 866musbotg_host_ctrl_data_rx(struct musbotg_td *td) 867{ 868 struct usb_page_search buf_res; 869 struct musbotg_softc *sc; 870 uint16_t count; 871 uint8_t csr; 872 uint8_t got_short; 873 874 /* get pointer to softc */ 875 sc = MUSBOTG_PC2SC(td->pc); 876 877 if (td->channel == -1) 878 td->channel = musbotg_channel_alloc(sc, td); 879 880 /* EP0 is busy, wait */ 881 if (td->channel == -1) 882 return (1); 883 884 DPRINTFN(1, "ep_no=%d\n", td->channel); 885 886 /* select endpoint 0 */ 887 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 888 889 /* read out FIFO status */ 890 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 891 892 DPRINTFN(4, "csr=0x%02x\n", csr); 893 894 got_short = 0; 895 if (!td->transaction_started) { 896 td->transaction_started = 1; 897 898 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 899 900 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 901 td->dev_addr); 902 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 903 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 904 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 905 906 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 907 MUSB2_MASK_CSR0L_REQPKT); 908 909 return (1); 910 } 911 912 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 913 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 914 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 915 916 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 918 919 td->error = 1; 920 } 921 922 /* Failed */ 923 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 924 MUSB2_MASK_CSR0L_ERROR)) 925 { 926 /* Clear status bit */ 927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 928 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 929 td->error = 1; 930 } 931 932 if (td->error) { 933 musbotg_channel_free(sc, td); 934 return (0); /* we are complete */ 935 } 936 937 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 938 return (1); /* not yet */ 939 940 /* get the packet byte count */ 941 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 942 943 /* verify the packet byte count */ 944 if (count != td->max_frame_size) { 945 if (count < td->max_frame_size) { 946 /* we have a short packet */ 947 td->short_pkt = 1; 948 got_short = 1; 949 } else { 950 /* invalid USB packet */ 951 td->error = 1; 952 musbotg_channel_free(sc, td); 953 return (0); /* we are complete */ 954 } 955 } 956 /* verify the packet byte count */ 957 if (count > td->remainder) { 958 /* invalid USB packet */ 959 td->error = 1; 960 musbotg_channel_free(sc, td); 961 return (0); /* we are complete */ 962 } 963 while (count > 0) { 964 uint32_t temp; 965 966 usbd_get_page(td->pc, td->offset, &buf_res); 967 968 /* get correct length */ 969 if (buf_res.length > count) { 970 buf_res.length = count; 971 } 972 /* check for unaligned memory address */ 973 if (USB_P2U(buf_res.buffer) & 3) { 974 975 temp = count & ~3; 976 977 if (temp) { 978 /* receive data 4 bytes at a time */ 979 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 980 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 981 temp / 4); 982 } 983 temp = count & 3; 984 if (temp) { 985 /* receive data 1 byte at a time */ 986 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 987 MUSB2_REG_EPFIFO(0), 988 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 989 } 990 usbd_copy_in(td->pc, td->offset, 991 sc->sc_bounce_buf, count); 992 993 /* update offset and remainder */ 994 td->offset += count; 995 td->remainder -= count; 996 break; 997 } 998 /* check if we can optimise */ 999 if (buf_res.length >= 4) { 1000 1001 /* receive data 4 bytes at a time */ 1002 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1003 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1004 buf_res.length / 4); 1005 1006 temp = buf_res.length & ~3; 1007 1008 /* update counters */ 1009 count -= temp; 1010 td->offset += temp; 1011 td->remainder -= temp; 1012 continue; 1013 } 1014 /* receive data */ 1015 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1016 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1017 1018 /* update counters */ 1019 count -= buf_res.length; 1020 td->offset += buf_res.length; 1021 td->remainder -= buf_res.length; 1022 } 1023 1024 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1025 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1026 1027 /* check if we are complete */ 1028 if ((td->remainder == 0) || got_short) { 1029 if (td->short_pkt) { 1030 /* we are complete */ 1031 1032 musbotg_channel_free(sc, td); 1033 return (0); 1034 } 1035 /* else need to receive a zero length packet */ 1036 } 1037 1038 td->transaction_started = 1; 1039 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1040 MUSB2_MASK_CSR0L_REQPKT); 1041 1042 return (1); /* not complete */ 1043} 1044 1045static uint8_t 1046musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1047{ 1048 struct usb_page_search buf_res; 1049 struct musbotg_softc *sc; 1050 uint16_t count; 1051 uint8_t csr, csrh; 1052 1053 /* get pointer to softc */ 1054 sc = MUSBOTG_PC2SC(td->pc); 1055 1056 if (td->channel == -1) 1057 td->channel = musbotg_channel_alloc(sc, td); 1058 1059 /* No free EPs */ 1060 if (td->channel == -1) 1061 return (1); 1062 1063 DPRINTFN(1, "ep_no=%d\n", td->channel); 1064 1065 /* select endpoint */ 1066 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1067 1068 /* read out FIFO status */ 1069 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1070 DPRINTFN(4, "csr=0x%02x\n", csr); 1071 1072 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1073 MUSB2_MASK_CSR0L_ERROR)) { 1074 /* clear status bits */ 1075 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1076 td->error = 1; 1077 } 1078 1079 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1080 1081 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1083 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1084 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1085 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1086 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1087 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1088 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1089 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1090 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1091 } 1092 } 1093 1094 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1095 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1096 1097 td->error = 1; 1098 } 1099 1100 1101 if (td->error) { 1102 musbotg_channel_free(sc, td); 1103 return (0); /* complete */ 1104 } 1105 1106 /* 1107 * Wait while FIFO is empty. 1108 * Do not flush it because it will cause transactions 1109 * with size more then packet size. It might upset 1110 * some devices 1111 */ 1112 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1113 return (1); 1114 1115 /* Packet still being processed */ 1116 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1117 return (1); 1118 1119 if (td->transaction_started) { 1120 /* check remainder */ 1121 if (td->remainder == 0) { 1122 if (td->short_pkt) { 1123 musbotg_channel_free(sc, td); 1124 return (0); /* complete */ 1125 } 1126 /* else we need to transmit a short packet */ 1127 } 1128 1129 /* We're not complete - more transactions required */ 1130 td->transaction_started = 0; 1131 } 1132 1133 /* check for short packet */ 1134 count = td->max_frame_size; 1135 if (td->remainder < count) { 1136 /* we have a short packet */ 1137 td->short_pkt = 1; 1138 count = td->remainder; 1139 } 1140 1141 while (count > 0) { 1142 uint32_t temp; 1143 1144 usbd_get_page(td->pc, td->offset, &buf_res); 1145 1146 /* get correct length */ 1147 if (buf_res.length > count) { 1148 buf_res.length = count; 1149 } 1150 /* check for unaligned memory address */ 1151 if (USB_P2U(buf_res.buffer) & 3) { 1152 1153 usbd_copy_out(td->pc, td->offset, 1154 sc->sc_bounce_buf, count); 1155 1156 temp = count & ~3; 1157 1158 if (temp) { 1159 /* transmit data 4 bytes at a time */ 1160 bus_space_write_multi_4(sc->sc_io_tag, 1161 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1162 sc->sc_bounce_buf, temp / 4); 1163 } 1164 temp = count & 3; 1165 if (temp) { 1166 /* receive data 1 byte at a time */ 1167 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1168 MUSB2_REG_EPFIFO(0), 1169 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1170 } 1171 /* update offset and remainder */ 1172 td->offset += count; 1173 td->remainder -= count; 1174 break; 1175 } 1176 /* check if we can optimise */ 1177 if (buf_res.length >= 4) { 1178 1179 /* transmit data 4 bytes at a time */ 1180 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1181 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1182 buf_res.length / 4); 1183 1184 temp = buf_res.length & ~3; 1185 1186 /* update counters */ 1187 count -= temp; 1188 td->offset += temp; 1189 td->remainder -= temp; 1190 continue; 1191 } 1192 /* transmit data */ 1193 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1194 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1195 buf_res.length); 1196 1197 /* update counters */ 1198 count -= buf_res.length; 1199 td->offset += buf_res.length; 1200 td->remainder -= buf_res.length; 1201 } 1202 1203 /* Function address */ 1204 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1205 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1206 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1207 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1208 1209 /* TX NAK timeout */ 1210 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1211 1212 /* write command */ 1213 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1214 MUSB2_MASK_CSR0L_TXPKTRDY); 1215 1216 td->transaction_started = 1; 1217 1218 return (1); /* not complete */ 1219} 1220 1221static uint8_t 1222musbotg_dev_ctrl_status(struct musbotg_td *td) 1223{ 1224 struct musbotg_softc *sc; 1225 uint8_t csr; 1226 1227 /* get pointer to softc */ 1228 sc = MUSBOTG_PC2SC(td->pc); 1229 1230 /* select endpoint 0 */ 1231 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1232 1233 if (sc->sc_ep0_busy) { 1234 sc->sc_ep0_busy = 0; 1235 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1236 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1237 sc->sc_ep0_cmd = 0; 1238 } 1239 /* read out FIFO status */ 1240 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1241 1242 DPRINTFN(4, "csr=0x%02x\n", csr); 1243 1244 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1245 /* wait for interrupt */ 1246 return (1); /* not complete */ 1247 } 1248 if (sc->sc_dv_addr != 0xFF) { 1249 /* write function address */ 1250 musbotg_set_address(sc, sc->sc_dv_addr); 1251 } 1252 1253 musbotg_channel_free(sc, td); 1254 return (0); /* complete */ 1255} 1256 1257static uint8_t 1258musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1259{ 1260 struct musbotg_softc *sc; 1261 uint8_t csr, csrh; 1262 1263 /* get pointer to softc */ 1264 sc = MUSBOTG_PC2SC(td->pc); 1265 1266 if (td->channel == -1) 1267 td->channel = musbotg_channel_alloc(sc, td); 1268 1269 /* EP0 is busy, wait */ 1270 if (td->channel == -1) 1271 return (1); 1272 1273 DPRINTFN(1, "ep_no=%d\n", td->channel); 1274 1275 /* select endpoint 0 */ 1276 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1277 1278 if (!td->transaction_started) { 1279 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1280 td->dev_addr); 1281 1282 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1283 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1284 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1285 1286 /* RX NAK timeout */ 1287 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1288 1289 td->transaction_started = 1; 1290 1291 /* Disable PING */ 1292 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1293 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1294 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1295 1296 /* write command */ 1297 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1298 MUSB2_MASK_CSR0L_STATUSPKT | 1299 MUSB2_MASK_CSR0L_REQPKT); 1300 1301 return (1); /* Just started */ 1302 1303 } 1304 1305 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1306 1307 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1308 1309 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1310 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1311 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1312 musbotg_channel_free(sc, td); 1313 return (0); /* complete */ 1314 } 1315 1316 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1317 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1318 MUSB2_MASK_CSR0L_REQPKT); 1319 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1320 1321 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1322 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1323 td->error = 1; 1324 } 1325 1326 /* Failed */ 1327 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1328 MUSB2_MASK_CSR0L_ERROR)) 1329 { 1330 /* Clear status bit */ 1331 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1332 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1333 td->error = 1; 1334 } 1335 1336 if (td->error) { 1337 musbotg_channel_free(sc, td); 1338 return (0); 1339 } 1340 1341 return (1); /* Not ready yet */ 1342} 1343 1344static uint8_t 1345musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1346{ 1347 struct musbotg_softc *sc; 1348 uint8_t csr; 1349 1350 /* get pointer to softc */ 1351 sc = MUSBOTG_PC2SC(td->pc); 1352 1353 if (td->channel == -1) 1354 td->channel = musbotg_channel_alloc(sc, td); 1355 1356 /* EP0 is busy, wait */ 1357 if (td->channel == -1) 1358 return (1); 1359 1360 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1361 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1362 1363 /* select endpoint 0 */ 1364 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1365 1366 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1367 DPRINTFN(4, "csr=0x%02x\n", csr); 1368 1369 /* Not yet */ 1370 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1371 return (1); 1372 1373 /* Failed */ 1374 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1375 MUSB2_MASK_CSR0L_ERROR)) 1376 { 1377 /* Clear status bit */ 1378 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1379 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1380 td->error = 1; 1381 musbotg_channel_free(sc, td); 1382 return (0); /* complete */ 1383 } 1384 1385 if (td->transaction_started) { 1386 musbotg_channel_free(sc, td); 1387 return (0); /* complete */ 1388 } 1389 1390 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1391 1392 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1394 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1395 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1396 1397 /* TX NAK timeout */ 1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1399 1400 td->transaction_started = 1; 1401 1402 /* write command */ 1403 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1404 MUSB2_MASK_CSR0L_STATUSPKT | 1405 MUSB2_MASK_CSR0L_TXPKTRDY); 1406 1407 return (1); /* wait for interrupt */ 1408} 1409 1410static uint8_t 1411musbotg_dev_data_rx(struct musbotg_td *td) 1412{ 1413 struct usb_page_search buf_res; 1414 struct musbotg_softc *sc; 1415 uint16_t count; 1416 uint8_t csr; 1417 uint8_t to; 1418 uint8_t got_short; 1419 1420 to = 8; /* don't loop forever! */ 1421 got_short = 0; 1422 1423 /* get pointer to softc */ 1424 sc = MUSBOTG_PC2SC(td->pc); 1425 1426 if (td->channel == -1) 1427 td->channel = musbotg_channel_alloc(sc, td); 1428 1429 /* EP0 is busy, wait */ 1430 if (td->channel == -1) 1431 return (1); 1432 1433 /* select endpoint */ 1434 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1435 1436repeat: 1437 /* read out FIFO status */ 1438 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1439 1440 DPRINTFN(4, "csr=0x%02x\n", csr); 1441 1442 /* clear overrun */ 1443 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1444 /* make sure we don't clear "RXPKTRDY" */ 1445 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1446 MUSB2_MASK_CSRL_RXPKTRDY); 1447 } 1448 1449 /* check status */ 1450 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1451 return (1); /* not complete */ 1452 1453 /* get the packet byte count */ 1454 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1455 1456 DPRINTFN(4, "count=0x%04x\n", count); 1457 1458 /* 1459 * Check for short or invalid packet: 1460 */ 1461 if (count != td->max_frame_size) { 1462 if (count < td->max_frame_size) { 1463 /* we have a short packet */ 1464 td->short_pkt = 1; 1465 got_short = 1; 1466 } else { 1467 /* invalid USB packet */ 1468 td->error = 1; 1469 musbotg_channel_free(sc, td); 1470 return (0); /* we are complete */ 1471 } 1472 } 1473 /* verify the packet byte count */ 1474 if (count > td->remainder) { 1475 /* invalid USB packet */ 1476 td->error = 1; 1477 musbotg_channel_free(sc, td); 1478 return (0); /* we are complete */ 1479 } 1480 while (count > 0) { 1481 uint32_t temp; 1482 1483 usbd_get_page(td->pc, td->offset, &buf_res); 1484 1485 /* get correct length */ 1486 if (buf_res.length > count) { 1487 buf_res.length = count; 1488 } 1489 /* check for unaligned memory address */ 1490 if (USB_P2U(buf_res.buffer) & 3) { 1491 1492 temp = count & ~3; 1493 1494 if (temp) { 1495 /* receive data 4 bytes at a time */ 1496 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1497 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1498 temp / 4); 1499 } 1500 temp = count & 3; 1501 if (temp) { 1502 /* receive data 1 byte at a time */ 1503 bus_space_read_multi_1(sc->sc_io_tag, 1504 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1505 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1506 } 1507 usbd_copy_in(td->pc, td->offset, 1508 sc->sc_bounce_buf, count); 1509 1510 /* update offset and remainder */ 1511 td->offset += count; 1512 td->remainder -= count; 1513 break; 1514 } 1515 /* check if we can optimise */ 1516 if (buf_res.length >= 4) { 1517 1518 /* receive data 4 bytes at a time */ 1519 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1520 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1521 buf_res.length / 4); 1522 1523 temp = buf_res.length & ~3; 1524 1525 /* update counters */ 1526 count -= temp; 1527 td->offset += temp; 1528 td->remainder -= temp; 1529 continue; 1530 } 1531 /* receive data */ 1532 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1533 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1534 buf_res.length); 1535 1536 /* update counters */ 1537 count -= buf_res.length; 1538 td->offset += buf_res.length; 1539 td->remainder -= buf_res.length; 1540 } 1541 1542 /* clear status bits */ 1543 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1544 1545 /* check if we are complete */ 1546 if ((td->remainder == 0) || got_short) { 1547 if (td->short_pkt) { 1548 /* we are complete */ 1549 musbotg_channel_free(sc, td); 1550 return (0); 1551 } 1552 /* else need to receive a zero length packet */ 1553 } 1554 if (--to) { 1555 goto repeat; 1556 } 1557 return (1); /* not complete */ 1558} 1559 1560static uint8_t 1561musbotg_dev_data_tx(struct musbotg_td *td) 1562{ 1563 struct usb_page_search buf_res; 1564 struct musbotg_softc *sc; 1565 uint16_t count; 1566 uint8_t csr; 1567 uint8_t to; 1568 1569 to = 8; /* don't loop forever! */ 1570 1571 /* get pointer to softc */ 1572 sc = MUSBOTG_PC2SC(td->pc); 1573 1574 if (td->channel == -1) 1575 td->channel = musbotg_channel_alloc(sc, td); 1576 1577 /* EP0 is busy, wait */ 1578 if (td->channel == -1) 1579 return (1); 1580 1581 /* select endpoint */ 1582 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1583 1584repeat: 1585 1586 /* read out FIFO status */ 1587 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1588 1589 DPRINTFN(4, "csr=0x%02x\n", csr); 1590 1591 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1592 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1593 /* clear status bits */ 1594 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1595 } 1596 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1597 return (1); /* not complete */ 1598 } 1599 /* check for short packet */ 1600 count = td->max_frame_size; 1601 if (td->remainder < count) { 1602 /* we have a short packet */ 1603 td->short_pkt = 1; 1604 count = td->remainder; 1605 } 1606 while (count > 0) { 1607 uint32_t temp; 1608 1609 usbd_get_page(td->pc, td->offset, &buf_res); 1610 1611 /* get correct length */ 1612 if (buf_res.length > count) { 1613 buf_res.length = count; 1614 } 1615 /* check for unaligned memory address */ 1616 if (USB_P2U(buf_res.buffer) & 3) { 1617 1618 usbd_copy_out(td->pc, td->offset, 1619 sc->sc_bounce_buf, count); 1620 1621 temp = count & ~3; 1622 1623 if (temp) { 1624 /* transmit data 4 bytes at a time */ 1625 bus_space_write_multi_4(sc->sc_io_tag, 1626 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1627 sc->sc_bounce_buf, temp / 4); 1628 } 1629 temp = count & 3; 1630 if (temp) { 1631 /* receive data 1 byte at a time */ 1632 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1633 MUSB2_REG_EPFIFO(td->channel), 1634 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1635 } 1636 /* update offset and remainder */ 1637 td->offset += count; 1638 td->remainder -= count; 1639 break; 1640 } 1641 /* check if we can optimise */ 1642 if (buf_res.length >= 4) { 1643 1644 /* transmit data 4 bytes at a time */ 1645 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1646 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1647 buf_res.length / 4); 1648 1649 temp = buf_res.length & ~3; 1650 1651 /* update counters */ 1652 count -= temp; 1653 td->offset += temp; 1654 td->remainder -= temp; 1655 continue; 1656 } 1657 /* transmit data */ 1658 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1659 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1660 buf_res.length); 1661 1662 /* update counters */ 1663 count -= buf_res.length; 1664 td->offset += buf_res.length; 1665 td->remainder -= buf_res.length; 1666 } 1667 1668 /* Max packet size */ 1669 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1670 1671 /* write command */ 1672 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1673 MUSB2_MASK_CSRL_TXPKTRDY); 1674 1675 /* check remainder */ 1676 if (td->remainder == 0) { 1677 if (td->short_pkt) { 1678 musbotg_channel_free(sc, td); 1679 return (0); /* complete */ 1680 } 1681 /* else we need to transmit a short packet */ 1682 } 1683 if (--to) { 1684 goto repeat; 1685 } 1686 return (1); /* not complete */ 1687} 1688 1689static uint8_t 1690musbotg_host_data_rx(struct musbotg_td *td) 1691{ 1692 struct usb_page_search buf_res; 1693 struct musbotg_softc *sc; 1694 uint16_t count; 1695 uint8_t csr, csrh; 1696 uint8_t to; 1697 uint8_t got_short; 1698 1699 /* get pointer to softc */ 1700 sc = MUSBOTG_PC2SC(td->pc); 1701 1702 if (td->channel == -1) 1703 td->channel = musbotg_channel_alloc(sc, td); 1704 1705 /* No free EPs */ 1706 if (td->channel == -1) 1707 return (1); 1708 1709 DPRINTFN(1, "ep_no=%d\n", td->channel); 1710 1711 to = 8; /* don't loop forever! */ 1712 got_short = 0; 1713 1714 /* select endpoint */ 1715 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1716 1717repeat: 1718 /* read out FIFO status */ 1719 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1720 DPRINTFN(4, "csr=0x%02x\n", csr); 1721 1722 if (!td->transaction_started) { 1723 /* Function address */ 1724 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1725 td->dev_addr); 1726 1727 /* SPLIT transaction */ 1728 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1729 td->haddr); 1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1731 td->hport); 1732 1733 /* RX NAK timeout */ 1734 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1736 else 1737 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1738 1739 /* Protocol, speed, device endpoint */ 1740 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1741 1742 /* Max packet size */ 1743 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1744 1745 /* Data Toggle */ 1746 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1747 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1748 1749 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1750 if (td->toggle) 1751 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1752 else 1753 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1754 1755 /* Set data toggle */ 1756 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1757 1758 /* write command */ 1759 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1760 MUSB2_MASK_CSRL_RXREQPKT); 1761 1762 td->transaction_started = 1; 1763 return (1); 1764 } 1765 1766 /* clear NAK timeout */ 1767 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1768 DPRINTFN(4, "NAK Timeout\n"); 1769 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1770 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1771 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1772 1773 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1774 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1775 } 1776 1777 td->error = 1; 1778 } 1779 1780 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1781 DPRINTFN(4, "RXERROR\n"); 1782 td->error = 1; 1783 } 1784 1785 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1786 DPRINTFN(4, "RXSTALL\n"); 1787 td->error = 1; 1788 } 1789 1790 if (td->error) { 1791 musbotg_channel_free(sc, td); 1792 return (0); /* we are complete */ 1793 } 1794 1795 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1796 /* No data available yet */ 1797 return (1); 1798 } 1799 1800 td->toggle ^= 1; 1801 /* get the packet byte count */ 1802 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1803 DPRINTFN(4, "count=0x%04x\n", count); 1804 1805 /* 1806 * Check for short or invalid packet: 1807 */ 1808 if (count != td->max_frame_size) { 1809 if (count < td->max_frame_size) { 1810 /* we have a short packet */ 1811 td->short_pkt = 1; 1812 got_short = 1; 1813 } else { 1814 /* invalid USB packet */ 1815 td->error = 1; 1816 musbotg_channel_free(sc, td); 1817 return (0); /* we are complete */ 1818 } 1819 } 1820 1821 /* verify the packet byte count */ 1822 if (count > td->remainder) { 1823 /* invalid USB packet */ 1824 td->error = 1; 1825 musbotg_channel_free(sc, td); 1826 return (0); /* we are complete */ 1827 } 1828 1829 while (count > 0) { 1830 uint32_t temp; 1831 1832 usbd_get_page(td->pc, td->offset, &buf_res); 1833 1834 /* get correct length */ 1835 if (buf_res.length > count) { 1836 buf_res.length = count; 1837 } 1838 /* check for unaligned memory address */ 1839 if (USB_P2U(buf_res.buffer) & 3) { 1840 1841 temp = count & ~3; 1842 1843 if (temp) { 1844 /* receive data 4 bytes at a time */ 1845 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1846 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1847 temp / 4); 1848 } 1849 temp = count & 3; 1850 if (temp) { 1851 /* receive data 1 byte at a time */ 1852 bus_space_read_multi_1(sc->sc_io_tag, 1853 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1854 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1855 } 1856 usbd_copy_in(td->pc, td->offset, 1857 sc->sc_bounce_buf, count); 1858 1859 /* update offset and remainder */ 1860 td->offset += count; 1861 td->remainder -= count; 1862 break; 1863 } 1864 /* check if we can optimise */ 1865 if (buf_res.length >= 4) { 1866 1867 /* receive data 4 bytes at a time */ 1868 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1869 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1870 buf_res.length / 4); 1871 1872 temp = buf_res.length & ~3; 1873 1874 /* update counters */ 1875 count -= temp; 1876 td->offset += temp; 1877 td->remainder -= temp; 1878 continue; 1879 } 1880 /* receive data */ 1881 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1882 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1883 buf_res.length); 1884 1885 /* update counters */ 1886 count -= buf_res.length; 1887 td->offset += buf_res.length; 1888 td->remainder -= buf_res.length; 1889 } 1890 1891 /* clear status bits */ 1892 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1893 1894 /* check if we are complete */ 1895 if ((td->remainder == 0) || got_short) { 1896 if (td->short_pkt) { 1897 /* we are complete */ 1898 musbotg_channel_free(sc, td); 1899 return (0); 1900 } 1901 /* else need to receive a zero length packet */ 1902 } 1903 1904 /* Reset transaction state and restart */ 1905 td->transaction_started = 0; 1906 1907 if (--to) 1908 goto repeat; 1909 1910 return (1); /* not complete */ 1911} 1912 1913static uint8_t 1914musbotg_host_data_tx(struct musbotg_td *td) 1915{ 1916 struct usb_page_search buf_res; 1917 struct musbotg_softc *sc; 1918 uint16_t count; 1919 uint8_t csr, csrh; 1920 1921 /* get pointer to softc */ 1922 sc = MUSBOTG_PC2SC(td->pc); 1923 1924 if (td->channel == -1) 1925 td->channel = musbotg_channel_alloc(sc, td); 1926 1927 /* No free EPs */ 1928 if (td->channel == -1) 1929 return (1); 1930 1931 DPRINTFN(1, "ep_no=%d\n", td->channel); 1932 1933 /* select endpoint */ 1934 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1935 1936 /* read out FIFO status */ 1937 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1938 DPRINTFN(4, "csr=0x%02x\n", csr); 1939 1940 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1941 MUSB2_MASK_CSRL_TXERROR)) { 1942 /* clear status bits */ 1943 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1944 td->error = 1; 1945 musbotg_channel_free(sc, td); 1946 return (0); /* complete */ 1947 } 1948 1949 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1950 /* 1951 * Flush TX FIFO before clearing NAK TO 1952 */ 1953 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1954 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1956 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1957 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1958 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1959 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1960 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1961 } 1962 } 1963 1964 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1965 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1966 1967 td->error = 1; 1968 musbotg_channel_free(sc, td); 1969 return (0); /* complete */ 1970 } 1971 1972 /* 1973 * Wait while FIFO is empty. 1974 * Do not flush it because it will cause transactions 1975 * with size more then packet size. It might upset 1976 * some devices 1977 */ 1978 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1979 return (1); 1980 1981 /* Packet still being processed */ 1982 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1983 return (1); 1984 1985 if (td->transaction_started) { 1986 /* check remainder */ 1987 if (td->remainder == 0) { 1988 if (td->short_pkt) { 1989 musbotg_channel_free(sc, td); 1990 return (0); /* complete */ 1991 } 1992 /* else we need to transmit a short packet */ 1993 } 1994 1995 /* We're not complete - more transactions required */ 1996 td->transaction_started = 0; 1997 } 1998 1999 /* check for short packet */ 2000 count = td->max_frame_size; 2001 if (td->remainder < count) { 2002 /* we have a short packet */ 2003 td->short_pkt = 1; 2004 count = td->remainder; 2005 } 2006 2007 while (count > 0) { 2008 uint32_t temp; 2009 2010 usbd_get_page(td->pc, td->offset, &buf_res); 2011 2012 /* get correct length */ 2013 if (buf_res.length > count) { 2014 buf_res.length = count; 2015 } 2016 /* check for unaligned memory address */ 2017 if (USB_P2U(buf_res.buffer) & 3) { 2018 2019 usbd_copy_out(td->pc, td->offset, 2020 sc->sc_bounce_buf, count); 2021 2022 temp = count & ~3; 2023 2024 if (temp) { 2025 /* transmit data 4 bytes at a time */ 2026 bus_space_write_multi_4(sc->sc_io_tag, 2027 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2028 sc->sc_bounce_buf, temp / 4); 2029 } 2030 temp = count & 3; 2031 if (temp) { 2032 /* receive data 1 byte at a time */ 2033 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2034 MUSB2_REG_EPFIFO(td->channel), 2035 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2036 } 2037 /* update offset and remainder */ 2038 td->offset += count; 2039 td->remainder -= count; 2040 break; 2041 } 2042 /* check if we can optimise */ 2043 if (buf_res.length >= 4) { 2044 2045 /* transmit data 4 bytes at a time */ 2046 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2047 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2048 buf_res.length / 4); 2049 2050 temp = buf_res.length & ~3; 2051 2052 /* update counters */ 2053 count -= temp; 2054 td->offset += temp; 2055 td->remainder -= temp; 2056 continue; 2057 } 2058 /* transmit data */ 2059 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2060 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2061 buf_res.length); 2062 2063 /* update counters */ 2064 count -= buf_res.length; 2065 td->offset += buf_res.length; 2066 td->remainder -= buf_res.length; 2067 } 2068 2069 /* Function address */ 2070 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2071 td->dev_addr); 2072 2073 /* SPLIT transaction */ 2074 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2075 td->haddr); 2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2077 td->hport); 2078 2079 /* TX NAK timeout */ 2080 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2082 else 2083 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2084 2085 /* Protocol, speed, device endpoint */ 2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2087 2088 /* Max packet size */ 2089 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2090 2091 if (!td->transaction_started) { 2092 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2093 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2094 2095 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2096 if (td->toggle) 2097 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2098 else 2099 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2100 2101 /* Set data toggle */ 2102 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2103 } 2104 2105 /* write command */ 2106 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2107 MUSB2_MASK_CSRL_TXPKTRDY); 2108 2109 /* Update Data Toggle */ 2110 td->toggle ^= 1; 2111 td->transaction_started = 1; 2112 2113 return (1); /* not complete */ 2114} 2115 2116static uint8_t 2117musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2118{ 2119 struct musbotg_softc *sc; 2120 struct musbotg_td *td; 2121 2122 DPRINTFN(8, "\n"); 2123 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2124 2125 td = xfer->td_transfer_cache; 2126 while (1) { 2127 2128 if ((td->func) (td)) { 2129 /* operation in progress */ 2130 break; 2131 } 2132 2133 if (((void *)td) == xfer->td_transfer_last) { 2134 goto done; 2135 } 2136 if (td->error) { 2137 goto done; 2138 } else if (td->remainder > 0) { 2139 /* 2140 * We had a short transfer. If there is no alternate 2141 * next, stop processing ! 2142 */ 2143 if (!td->alt_next) { 2144 goto done; 2145 } 2146 } 2147 /* 2148 * Fetch the next transfer descriptor and transfer 2149 * some flags to the next transfer descriptor 2150 */ 2151 td = td->obj_next; 2152 xfer->td_transfer_cache = td; 2153 } 2154 2155 return (1); /* not complete */ 2156done: 2157 /* compute all actual lengths */ 2158 musbotg_standard_done(xfer); 2159 2160 return (0); /* complete */ 2161} 2162 2163static void 2164musbotg_interrupt_poll(struct musbotg_softc *sc) 2165{ 2166 struct usb_xfer *xfer; 2167 2168repeat: 2169 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2170 if (!musbotg_xfer_do_fifo(xfer)) { 2171 /* queue has been modified */ 2172 goto repeat; 2173 } 2174 } 2175} 2176 2177void 2178musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2179{ 2180 DPRINTFN(4, "vbus = %u\n", is_on); 2181 2182 USB_BUS_LOCK(&sc->sc_bus); 2183 if (is_on) { 2184 if (!sc->sc_flags.status_vbus) { 2185 sc->sc_flags.status_vbus = 1; 2186 2187 /* complete root HUB interrupt endpoint */ 2188 musbotg_root_intr(sc); 2189 } 2190 } else { 2191 if (sc->sc_flags.status_vbus) { 2192 sc->sc_flags.status_vbus = 0; 2193 sc->sc_flags.status_bus_reset = 0; 2194 sc->sc_flags.status_suspend = 0; 2195 sc->sc_flags.change_suspend = 0; 2196 sc->sc_flags.change_connect = 1; 2197 2198 /* complete root HUB interrupt endpoint */ 2199 musbotg_root_intr(sc); 2200 } 2201 } 2202 2203 USB_BUS_UNLOCK(&sc->sc_bus); 2204} 2205 2206void 2207musbotg_connect_interrupt(struct musbotg_softc *sc) 2208{ 2209 USB_BUS_LOCK(&sc->sc_bus); 2210 sc->sc_flags.change_connect = 1; 2211 2212 /* complete root HUB interrupt endpoint */ 2213 musbotg_root_intr(sc); 2214 USB_BUS_UNLOCK(&sc->sc_bus); 2215} 2216 2217void 2218musbotg_interrupt(struct musbotg_softc *sc, 2219 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2220{ 2221 uint16_t rx_status; 2222 uint16_t tx_status; 2223 uint8_t usb_status; 2224 uint8_t temp; 2225 uint8_t to = 2; 2226 2227 USB_BUS_LOCK(&sc->sc_bus); 2228 2229repeat: 2230 2231 /* read all interrupt registers */ 2232 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2233 2234 /* read all FIFO interrupts */ 2235 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2236 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2237 rx_status |= rxstat; 2238 tx_status |= txstat; 2239 usb_status |= stat; 2240 2241 /* Clear platform flags after first time */ 2242 rxstat = 0; 2243 txstat = 0; 2244 stat = 0; 2245 2246 /* check for any bus state change interrupts */ 2247 2248 if (usb_status & (MUSB2_MASK_IRESET | 2249 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2250 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC | 2251 MUSB2_MASK_IVBUSERR)) { 2252 2253 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2254 2255 if (usb_status & MUSB2_MASK_IRESET) { 2256 2257 /* set correct state */ 2258 sc->sc_flags.status_bus_reset = 1; 2259 sc->sc_flags.status_suspend = 0; 2260 sc->sc_flags.change_suspend = 0; 2261 sc->sc_flags.change_connect = 1; 2262 2263 /* determine line speed */ 2264 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2265 if (temp & MUSB2_MASK_HSMODE) 2266 sc->sc_flags.status_high_speed = 1; 2267 else 2268 sc->sc_flags.status_high_speed = 0; 2269 2270 /* 2271 * After reset all interrupts are on and we need to 2272 * turn them off! 2273 */ 2274 temp = MUSB2_MASK_IRESET; 2275 /* disable resume interrupt */ 2276 temp &= ~MUSB2_MASK_IRESUME; 2277 /* enable suspend interrupt */ 2278 temp |= MUSB2_MASK_ISUSP; 2279 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2280 /* disable TX and RX interrupts */ 2281 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2282 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2283 } 2284 /* 2285 * If RXRSM and RXSUSP is set at the same time we interpret 2286 * that like RESUME. Resume is set when there is at least 3 2287 * milliseconds of inactivity on the USB BUS. 2288 */ 2289 if (usb_status & MUSB2_MASK_IRESUME) { 2290 if (sc->sc_flags.status_suspend) { 2291 sc->sc_flags.status_suspend = 0; 2292 sc->sc_flags.change_suspend = 1; 2293 2294 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2295 /* disable resume interrupt */ 2296 temp &= ~MUSB2_MASK_IRESUME; 2297 /* enable suspend interrupt */ 2298 temp |= MUSB2_MASK_ISUSP; 2299 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2300 } 2301 } else if (usb_status & MUSB2_MASK_ISUSP) { 2302 if (!sc->sc_flags.status_suspend) { 2303 sc->sc_flags.status_suspend = 1; 2304 sc->sc_flags.change_suspend = 1; 2305 2306 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2307 /* disable suspend interrupt */ 2308 temp &= ~MUSB2_MASK_ISUSP; 2309 /* enable resume interrupt */ 2310 temp |= MUSB2_MASK_IRESUME; 2311 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2312 } 2313 } 2314 if (usb_status & 2315 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2316 sc->sc_flags.change_connect = 1; 2317 2318 /* 2319 * Host Mode: There is no IRESET so assume bus is 2320 * always in reset state once device is connected. 2321 */ 2322 if (sc->sc_mode == MUSB2_HOST_MODE) { 2323 /* check for VBUS error in USB host mode */ 2324 if (usb_status & MUSB2_MASK_IVBUSERR) { 2325 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 2326 temp |= MUSB2_MASK_SESS; 2327 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 2328 } 2329 if (usb_status & MUSB2_MASK_ICONN) 2330 sc->sc_flags.status_bus_reset = 1; 2331 if (usb_status & MUSB2_MASK_IDISC) 2332 sc->sc_flags.status_bus_reset = 0; 2333 } 2334 2335 /* complete root HUB interrupt endpoint */ 2336 musbotg_root_intr(sc); 2337 } 2338 /* check for any endpoint interrupts */ 2339 2340 if (rx_status || tx_status) { 2341 DPRINTFN(4, "real endpoint interrupt " 2342 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2343 } 2344 /* poll one time regardless of FIFO status */ 2345 2346 musbotg_interrupt_poll(sc); 2347 2348 if (--to) 2349 goto repeat; 2350 2351 USB_BUS_UNLOCK(&sc->sc_bus); 2352} 2353 2354static void 2355musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2356{ 2357 struct musbotg_td *td; 2358 2359 /* get current Transfer Descriptor */ 2360 td = temp->td_next; 2361 temp->td = td; 2362 2363 /* prepare for next TD */ 2364 temp->td_next = td->obj_next; 2365 2366 /* fill out the Transfer Descriptor */ 2367 td->func = temp->func; 2368 td->pc = temp->pc; 2369 td->offset = temp->offset; 2370 td->remainder = temp->len; 2371 td->error = 0; 2372 td->transaction_started = 0; 2373 td->did_stall = temp->did_stall; 2374 td->short_pkt = temp->short_pkt; 2375 td->alt_next = temp->setup_alt_next; 2376 td->channel = temp->channel; 2377 td->dev_addr = temp->dev_addr; 2378 td->haddr = temp->haddr; 2379 td->hport = temp->hport; 2380 td->transfer_type = temp->transfer_type; 2381} 2382 2383static void 2384musbotg_setup_standard_chain(struct usb_xfer *xfer) 2385{ 2386 struct musbotg_std_temp temp; 2387 struct musbotg_softc *sc; 2388 struct musbotg_td *td; 2389 uint32_t x; 2390 uint8_t ep_no; 2391 uint8_t xfer_type; 2392 enum usb_dev_speed speed; 2393 int tx; 2394 int dev_addr; 2395 2396 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2397 xfer->address, UE_GET_ADDR(xfer->endpointno), 2398 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2399 2400 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2401 ep_no = (xfer->endpointno & UE_ADDR); 2402 2403 temp.max_frame_size = xfer->max_frame_size; 2404 2405 td = xfer->td_start[0]; 2406 xfer->td_transfer_first = td; 2407 xfer->td_transfer_cache = td; 2408 2409 /* setup temp */ 2410 dev_addr = xfer->address; 2411 2412 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2413 2414 temp.pc = NULL; 2415 temp.td = NULL; 2416 temp.td_next = xfer->td_start[0]; 2417 temp.offset = 0; 2418 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2419 temp.did_stall = !xfer->flags_int.control_stall; 2420 temp.channel = -1; 2421 temp.dev_addr = dev_addr; 2422 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2423 temp.hport = xfer->xroot->udev->hs_port_no; 2424 2425 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2426 speed = usbd_get_speed(xfer->xroot->udev); 2427 2428 switch (speed) { 2429 case USB_SPEED_LOW: 2430 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2431 break; 2432 case USB_SPEED_FULL: 2433 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2434 break; 2435 case USB_SPEED_HIGH: 2436 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2437 break; 2438 default: 2439 temp.transfer_type = 0; 2440 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2441 break; 2442 } 2443 2444 switch (xfer_type) { 2445 case UE_CONTROL: 2446 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2447 break; 2448 case UE_ISOCHRONOUS: 2449 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2450 break; 2451 case UE_BULK: 2452 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2453 break; 2454 case UE_INTERRUPT: 2455 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2456 break; 2457 default: 2458 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2459 xfer_type); 2460 break; 2461 } 2462 2463 temp.transfer_type |= ep_no; 2464 td->toggle = xfer->endpoint->toggle_next; 2465 } 2466 2467 /* check if we should prepend a setup message */ 2468 2469 if (xfer->flags_int.control_xfr) { 2470 if (xfer->flags_int.control_hdr) { 2471 2472 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2473 temp.func = &musbotg_dev_ctrl_setup_rx; 2474 else 2475 temp.func = &musbotg_host_ctrl_setup_tx; 2476 2477 temp.len = xfer->frlengths[0]; 2478 temp.pc = xfer->frbuffers + 0; 2479 temp.short_pkt = temp.len ? 1 : 0; 2480 2481 musbotg_setup_standard_chain_sub(&temp); 2482 } 2483 x = 1; 2484 } else { 2485 x = 0; 2486 } 2487 2488 tx = 0; 2489 2490 if (x != xfer->nframes) { 2491 if (xfer->endpointno & UE_DIR_IN) 2492 tx = 1; 2493 2494 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2495 tx = !tx; 2496 2497 if (tx) { 2498 if (xfer->flags_int.control_xfr) 2499 temp.func = &musbotg_host_ctrl_data_tx; 2500 else 2501 temp.func = &musbotg_host_data_tx; 2502 } else { 2503 if (xfer->flags_int.control_xfr) 2504 temp.func = &musbotg_host_ctrl_data_rx; 2505 else 2506 temp.func = &musbotg_host_data_rx; 2507 } 2508 2509 } else { 2510 if (tx) { 2511 if (xfer->flags_int.control_xfr) 2512 temp.func = &musbotg_dev_ctrl_data_tx; 2513 else 2514 temp.func = &musbotg_dev_data_tx; 2515 } else { 2516 if (xfer->flags_int.control_xfr) 2517 temp.func = &musbotg_dev_ctrl_data_rx; 2518 else 2519 temp.func = &musbotg_dev_data_rx; 2520 } 2521 } 2522 2523 /* setup "pc" pointer */ 2524 temp.pc = xfer->frbuffers + x; 2525 } 2526 while (x != xfer->nframes) { 2527 2528 /* DATA0 / DATA1 message */ 2529 2530 temp.len = xfer->frlengths[x]; 2531 2532 x++; 2533 2534 if (x == xfer->nframes) { 2535 if (xfer->flags_int.control_xfr) { 2536 if (xfer->flags_int.control_act) { 2537 temp.setup_alt_next = 0; 2538 } 2539 } else { 2540 temp.setup_alt_next = 0; 2541 } 2542 } 2543 if (temp.len == 0) { 2544 2545 /* make sure that we send an USB packet */ 2546 2547 temp.short_pkt = 0; 2548 2549 } else { 2550 2551 if (xfer->flags_int.isochronous_xfr) { 2552 /* isochronous data transfer */ 2553 /* don't force short */ 2554 temp.short_pkt = 1; 2555 } else { 2556 /* regular data transfer */ 2557 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2558 } 2559 } 2560 2561 musbotg_setup_standard_chain_sub(&temp); 2562 2563 if (xfer->flags_int.isochronous_xfr) { 2564 temp.offset += temp.len; 2565 } else { 2566 /* get next Page Cache pointer */ 2567 temp.pc = xfer->frbuffers + x; 2568 } 2569 } 2570 2571 /* check for control transfer */ 2572 if (xfer->flags_int.control_xfr) { 2573 2574 /* always setup a valid "pc" pointer for status and sync */ 2575 temp.pc = xfer->frbuffers + 0; 2576 temp.len = 0; 2577 temp.short_pkt = 0; 2578 temp.setup_alt_next = 0; 2579 2580 /* check if we should append a status stage */ 2581 if (!xfer->flags_int.control_act) { 2582 /* 2583 * Send a DATA1 message and invert the current 2584 * endpoint direction. 2585 */ 2586 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2587 temp.func = &musbotg_dev_ctrl_status; 2588 else { 2589 if (xfer->endpointno & UE_DIR_IN) 2590 temp.func = musbotg_host_ctrl_status_tx; 2591 else 2592 temp.func = musbotg_host_ctrl_status_rx; 2593 } 2594 musbotg_setup_standard_chain_sub(&temp); 2595 } 2596 } 2597 /* must have at least one frame! */ 2598 td = temp.td; 2599 xfer->td_transfer_last = td; 2600} 2601 2602static void 2603musbotg_timeout(void *arg) 2604{ 2605 struct usb_xfer *xfer = arg; 2606 2607 DPRINTFN(1, "xfer=%p\n", xfer); 2608 2609 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2610 2611 /* transfer is transferred */ 2612 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2613} 2614 2615static void 2616musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2617{ 2618 uint16_t temp; 2619 2620 /* 2621 * Only enable the endpoint interrupt when we are 2622 * actually waiting for data, hence we are dealing 2623 * with level triggered interrupts ! 2624 */ 2625 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2626 2627 if (channel == -1) 2628 return; 2629 2630 if (channel == 0) { 2631 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2632 if (on) 2633 temp |= MUSB2_MASK_EPINT(0); 2634 else 2635 temp &= ~MUSB2_MASK_EPINT(0); 2636 2637 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2638 } else { 2639 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2640 if (on) 2641 temp |= MUSB2_MASK_EPINT(channel); 2642 else 2643 temp &= ~MUSB2_MASK_EPINT(channel); 2644 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2645 2646 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2647 if (on) 2648 temp |= MUSB2_MASK_EPINT(channel); 2649 else 2650 temp &= ~MUSB2_MASK_EPINT(channel); 2651 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2652 } 2653 2654 if (sc->sc_ep_int_set) 2655 sc->sc_ep_int_set(sc, channel, on); 2656} 2657 2658static void 2659musbotg_start_standard_chain(struct usb_xfer *xfer) 2660{ 2661 DPRINTFN(8, "\n"); 2662 2663 /* poll one time */ 2664 if (musbotg_xfer_do_fifo(xfer)) { 2665 2666 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2667 2668 /* put transfer on interrupt queue */ 2669 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2670 2671 /* start timeout, if any */ 2672 if (xfer->timeout != 0) { 2673 usbd_transfer_timeout_ms(xfer, 2674 &musbotg_timeout, xfer->timeout); 2675 } 2676 } 2677} 2678 2679static void 2680musbotg_root_intr(struct musbotg_softc *sc) 2681{ 2682 DPRINTFN(8, "\n"); 2683 2684 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2685 2686 /* set port bit */ 2687 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2688 2689 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2690 sizeof(sc->sc_hub_idata)); 2691} 2692 2693static usb_error_t 2694musbotg_standard_done_sub(struct usb_xfer *xfer) 2695{ 2696 struct musbotg_td *td; 2697 uint32_t len; 2698 uint8_t error; 2699 2700 DPRINTFN(8, "\n"); 2701 2702 td = xfer->td_transfer_cache; 2703 2704 do { 2705 len = td->remainder; 2706 2707 xfer->endpoint->toggle_next = td->toggle; 2708 2709 if (xfer->aframes != xfer->nframes) { 2710 /* 2711 * Verify the length and subtract 2712 * the remainder from "frlengths[]": 2713 */ 2714 if (len > xfer->frlengths[xfer->aframes]) { 2715 td->error = 1; 2716 } else { 2717 xfer->frlengths[xfer->aframes] -= len; 2718 } 2719 } 2720 /* Check for transfer error */ 2721 if (td->error) { 2722 /* the transfer is finished */ 2723 error = 1; 2724 td = NULL; 2725 break; 2726 } 2727 /* Check for short transfer */ 2728 if (len > 0) { 2729 if (xfer->flags_int.short_frames_ok) { 2730 /* follow alt next */ 2731 if (td->alt_next) { 2732 td = td->obj_next; 2733 } else { 2734 td = NULL; 2735 } 2736 } else { 2737 /* the transfer is finished */ 2738 td = NULL; 2739 } 2740 error = 0; 2741 break; 2742 } 2743 td = td->obj_next; 2744 2745 /* this USB frame is complete */ 2746 error = 0; 2747 break; 2748 2749 } while (0); 2750 2751 /* update transfer cache */ 2752 2753 xfer->td_transfer_cache = td; 2754 2755 return (error ? 2756 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2757} 2758 2759static void 2760musbotg_standard_done(struct usb_xfer *xfer) 2761{ 2762 usb_error_t err = 0; 2763 2764 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2765 xfer, xfer->endpoint); 2766 2767 /* reset scanner */ 2768 2769 xfer->td_transfer_cache = xfer->td_transfer_first; 2770 2771 if (xfer->flags_int.control_xfr) { 2772 2773 if (xfer->flags_int.control_hdr) { 2774 2775 err = musbotg_standard_done_sub(xfer); 2776 } 2777 xfer->aframes = 1; 2778 2779 if (xfer->td_transfer_cache == NULL) { 2780 goto done; 2781 } 2782 } 2783 while (xfer->aframes != xfer->nframes) { 2784 2785 err = musbotg_standard_done_sub(xfer); 2786 xfer->aframes++; 2787 2788 if (xfer->td_transfer_cache == NULL) { 2789 goto done; 2790 } 2791 } 2792 2793 if (xfer->flags_int.control_xfr && 2794 !xfer->flags_int.control_act) { 2795 2796 err = musbotg_standard_done_sub(xfer); 2797 } 2798done: 2799 musbotg_device_done(xfer, err); 2800} 2801 2802/*------------------------------------------------------------------------* 2803 * musbotg_device_done 2804 * 2805 * NOTE: this function can be called more than one time on the 2806 * same USB transfer! 2807 *------------------------------------------------------------------------*/ 2808static void 2809musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2810{ 2811 struct musbotg_td *td; 2812 struct musbotg_softc *sc; 2813 2814 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2815 2816 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2817 xfer, xfer->endpoint, error); 2818 2819 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2820 2821 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2822 td = xfer->td_transfer_cache; 2823 2824 if (td && (td->channel != -1)) 2825 musbotg_channel_free(sc, td); 2826 2827 /* dequeue transfer and start next transfer */ 2828 usbd_transfer_done(xfer, error); 2829} 2830 2831static void 2832musbotg_xfer_stall(struct usb_xfer *xfer) 2833{ 2834 musbotg_device_done(xfer, USB_ERR_STALLED); 2835} 2836 2837static void 2838musbotg_set_stall(struct usb_device *udev, 2839 struct usb_endpoint *ep, uint8_t *did_stall) 2840{ 2841 struct musbotg_softc *sc; 2842 uint8_t ep_no; 2843 2844 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2845 2846 DPRINTFN(4, "endpoint=%p\n", ep); 2847 2848 /* set FORCESTALL */ 2849 sc = MUSBOTG_BUS2SC(udev->bus); 2850 2851 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2852 2853 /* select endpoint */ 2854 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2855 2856 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2857 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2858 MUSB2_MASK_CSRL_TXSENDSTALL); 2859 } else { 2860 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2861 MUSB2_MASK_CSRL_RXSENDSTALL); 2862 } 2863} 2864 2865static void 2866musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2867 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2868{ 2869 uint16_t mps; 2870 uint16_t temp; 2871 uint8_t csr; 2872 2873 if (ep_type == UE_CONTROL) { 2874 /* clearing stall is not needed */ 2875 return; 2876 } 2877 /* select endpoint */ 2878 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2879 2880 /* compute max frame size */ 2881 mps = wMaxPacket & 0x7FF; 2882 switch ((wMaxPacket >> 11) & 3) { 2883 case 1: 2884 mps *= 2; 2885 break; 2886 case 2: 2887 mps *= 3; 2888 break; 2889 default: 2890 break; 2891 } 2892 2893 if (ep_dir == UE_DIR_IN) { 2894 2895 temp = 0; 2896 2897 /* Configure endpoint */ 2898 switch (ep_type) { 2899 case UE_INTERRUPT: 2900 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2902 MUSB2_MASK_CSRH_TXMODE | temp); 2903 break; 2904 case UE_ISOCHRONOUS: 2905 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2906 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2907 MUSB2_MASK_CSRH_TXMODE | 2908 MUSB2_MASK_CSRH_TXISO | temp); 2909 break; 2910 case UE_BULK: 2911 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2913 MUSB2_MASK_CSRH_TXMODE | temp); 2914 break; 2915 default: 2916 break; 2917 } 2918 2919 /* Need to flush twice in case of double bufring */ 2920 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2921 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2923 MUSB2_MASK_CSRL_TXFFLUSH); 2924 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2925 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2926 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2927 MUSB2_MASK_CSRL_TXFFLUSH); 2928 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2929 } 2930 } 2931 /* reset data toggle */ 2932 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2933 MUSB2_MASK_CSRL_TXDT_CLR); 2934 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2935 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2936 2937 /* set double/single buffering */ 2938 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2939 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2940 max_in_frame_size / 2)) { 2941 /* double buffer */ 2942 temp &= ~(1 << ep_no); 2943 } else { 2944 /* single buffer */ 2945 temp |= (1 << ep_no); 2946 } 2947 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2948 2949 /* clear sent stall */ 2950 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2951 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2952 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2953 } 2954 } else { 2955 2956 temp = 0; 2957 2958 /* Configure endpoint */ 2959 switch (ep_type) { 2960 case UE_INTERRUPT: 2961 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2962 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2963 MUSB2_MASK_CSRH_RXNYET | temp); 2964 break; 2965 case UE_ISOCHRONOUS: 2966 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2967 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2968 MUSB2_MASK_CSRH_RXNYET | 2969 MUSB2_MASK_CSRH_RXISO | temp); 2970 break; 2971 case UE_BULK: 2972 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2973 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2974 break; 2975 default: 2976 break; 2977 } 2978 2979 /* Need to flush twice in case of double bufring */ 2980 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2981 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2982 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2983 MUSB2_MASK_CSRL_RXFFLUSH); 2984 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2985 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2986 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2987 MUSB2_MASK_CSRL_RXFFLUSH); 2988 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2989 } 2990 } 2991 /* reset data toggle */ 2992 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2993 MUSB2_MASK_CSRL_RXDT_CLR); 2994 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2995 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2996 2997 /* set double/single buffering */ 2998 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2999 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 3000 max_out_frame_size / 2)) { 3001 /* double buffer */ 3002 temp &= ~(1 << ep_no); 3003 } else { 3004 /* single buffer */ 3005 temp |= (1 << ep_no); 3006 } 3007 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 3008 3009 /* clear sent stall */ 3010 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3011 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3012 } 3013 } 3014} 3015 3016static void 3017musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3018{ 3019 struct musbotg_softc *sc; 3020 struct usb_endpoint_descriptor *ed; 3021 3022 DPRINTFN(4, "endpoint=%p\n", ep); 3023 3024 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3025 3026 /* check mode */ 3027 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3028 /* not supported */ 3029 return; 3030 } 3031 /* get softc */ 3032 sc = MUSBOTG_BUS2SC(udev->bus); 3033 3034 /* get endpoint descriptor */ 3035 ed = ep->edesc; 3036 3037 /* reset endpoint */ 3038 musbotg_clear_stall_sub(sc, 3039 UGETW(ed->wMaxPacketSize), 3040 (ed->bEndpointAddress & UE_ADDR), 3041 (ed->bmAttributes & UE_XFERTYPE), 3042 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3043} 3044 3045usb_error_t 3046musbotg_init(struct musbotg_softc *sc) 3047{ 3048 struct usb_hw_ep_profile *pf; 3049 uint16_t offset; 3050 uint8_t nrx; 3051 uint8_t ntx; 3052 uint8_t temp; 3053 uint8_t fsize; 3054 uint8_t frx; 3055 uint8_t ftx; 3056 uint8_t dynfifo; 3057 3058 DPRINTFN(1, "start\n"); 3059 3060 /* set up the bus structure */ 3061 sc->sc_bus.usbrev = USB_REV_2_0; 3062 sc->sc_bus.methods = &musbotg_bus_methods; 3063 3064 USB_BUS_LOCK(&sc->sc_bus); 3065 3066 /* turn on clocks */ 3067 3068 if (sc->sc_clocks_on) { 3069 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3070 } 3071 3072 /* wait a little for things to stabilise */ 3073 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3074 3075 /* disable all interrupts */ 3076 3077 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3078 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3079 3080 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3081 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3082 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3083 3084 /* disable pullup */ 3085 3086 musbotg_pull_common(sc, 0); 3087 3088 /* wait a little bit (10ms) */ 3089 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3090 3091 3092 /* disable double packet buffering */ 3093 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3094 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3095 3096 /* enable HighSpeed and ISO Update flags */ 3097 3098 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3099 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3100 3101 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3102 /* clear Session bit, if set */ 3103 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3104 temp &= ~MUSB2_MASK_SESS; 3105 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3106 } else { 3107 /* Enter session for Host mode */ 3108 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3109 temp |= MUSB2_MASK_SESS; 3110 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3111 } 3112 3113 /* wait a little for things to stabilise */ 3114 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3115 3116 DPRINTF("DEVCTL=0x%02x\n", temp); 3117 3118 /* disable testmode */ 3119 3120 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3121 3122 /* set default value */ 3123 3124 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3125 3126 /* select endpoint index 0 */ 3127 3128 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3129 3130 /* read out number of endpoints */ 3131 3132 nrx = 3133 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3134 3135 ntx = 3136 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3137 3138 /* these numbers exclude the control endpoint */ 3139 3140 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3141 3142 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3143 if (sc->sc_ep_max == 0) { 3144 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3145 } 3146 /* read out configuration data */ 3147 3148 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3149 3150 DPRINTFN(2, "Config Data: 0x%02x\n", 3151 sc->sc_conf_data); 3152 3153 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3154 3155 if (dynfifo) { 3156 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3157 "assuming 16Kbytes of FIFO RAM\n"); 3158 } 3159 3160 DPRINTFN(2, "HW version: 0x%04x\n", 3161 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3162 3163 /* initialise endpoint profiles */ 3164 3165 offset = 0; 3166 3167 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3168 pf = sc->sc_hw_ep_profile + temp; 3169 3170 /* select endpoint */ 3171 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3172 3173 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3174 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3175 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3176 3177 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3178 temp, ftx, frx, dynfifo); 3179 3180 if (dynfifo) { 3181 if (frx && (temp <= nrx)) { 3182 if (temp == 1) { 3183 frx = 12; /* 4K */ 3184 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3185 MUSB2_VAL_FIFOSZ_4096 | 3186 MUSB2_MASK_FIFODB); 3187 } else if (temp < 8) { 3188 frx = 10; /* 1K */ 3189 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3190 MUSB2_VAL_FIFOSZ_512 | 3191 MUSB2_MASK_FIFODB); 3192 } else { 3193 frx = 7; /* 128 bytes */ 3194 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3195 MUSB2_VAL_FIFOSZ_128); 3196 } 3197 3198 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3199 offset >> 3); 3200 3201 offset += (1 << frx); 3202 } 3203 if (ftx && (temp <= ntx)) { 3204 if (temp == 1) { 3205 ftx = 12; /* 4K */ 3206 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3207 MUSB2_VAL_FIFOSZ_4096 | 3208 MUSB2_MASK_FIFODB); 3209 } else if (temp < 8) { 3210 ftx = 10; /* 1K */ 3211 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3212 MUSB2_VAL_FIFOSZ_512 | 3213 MUSB2_MASK_FIFODB); 3214 } else { 3215 ftx = 7; /* 128 bytes */ 3216 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3217 MUSB2_VAL_FIFOSZ_128); 3218 } 3219 3220 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3221 offset >> 3); 3222 3223 offset += (1 << ftx); 3224 } 3225 } 3226 3227 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3228 pf->max_in_frame_size = 1 << ftx; 3229 pf->max_out_frame_size = 1 << frx; 3230 pf->is_simplex = 0; /* duplex */ 3231 pf->support_multi_buffer = 1; 3232 pf->support_bulk = 1; 3233 pf->support_interrupt = 1; 3234 pf->support_isochronous = 1; 3235 pf->support_in = 1; 3236 pf->support_out = 1; 3237 } else if (frx && (temp <= nrx)) { 3238 pf->max_out_frame_size = 1 << frx; 3239 pf->is_simplex = 1; /* simplex */ 3240 pf->support_multi_buffer = 1; 3241 pf->support_bulk = 1; 3242 pf->support_interrupt = 1; 3243 pf->support_isochronous = 1; 3244 pf->support_out = 1; 3245 } else if (ftx && (temp <= ntx)) { 3246 pf->max_in_frame_size = 1 << ftx; 3247 pf->is_simplex = 1; /* simplex */ 3248 pf->support_multi_buffer = 1; 3249 pf->support_bulk = 1; 3250 pf->support_interrupt = 1; 3251 pf->support_isochronous = 1; 3252 pf->support_in = 1; 3253 } 3254 } 3255 3256 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3257 3258 /* turn on default interrupts */ 3259 3260 if (sc->sc_mode == MUSB2_HOST_MODE) 3261 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3262 else 3263 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3264 MUSB2_MASK_IRESET); 3265 3266 musbotg_clocks_off(sc); 3267 3268 USB_BUS_UNLOCK(&sc->sc_bus); 3269 3270 /* catch any lost interrupts */ 3271 3272 musbotg_do_poll(&sc->sc_bus); 3273 3274 return (0); /* success */ 3275} 3276 3277void 3278musbotg_uninit(struct musbotg_softc *sc) 3279{ 3280 USB_BUS_LOCK(&sc->sc_bus); 3281 3282 /* disable all interrupts */ 3283 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3284 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3285 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3286 3287 sc->sc_flags.port_powered = 0; 3288 sc->sc_flags.status_vbus = 0; 3289 sc->sc_flags.status_bus_reset = 0; 3290 sc->sc_flags.status_suspend = 0; 3291 sc->sc_flags.change_suspend = 0; 3292 sc->sc_flags.change_connect = 1; 3293 3294 musbotg_pull_down(sc); 3295 musbotg_clocks_off(sc); 3296 USB_BUS_UNLOCK(&sc->sc_bus); 3297} 3298 3299static void 3300musbotg_suspend(struct musbotg_softc *sc) 3301{ 3302 /* TODO */ 3303} 3304 3305static void 3306musbotg_resume(struct musbotg_softc *sc) 3307{ 3308 /* TODO */ 3309} 3310 3311static void 3312musbotg_do_poll(struct usb_bus *bus) 3313{ 3314 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3315 3316 USB_BUS_LOCK(&sc->sc_bus); 3317 musbotg_interrupt_poll(sc); 3318 USB_BUS_UNLOCK(&sc->sc_bus); 3319} 3320 3321/*------------------------------------------------------------------------* 3322 * musbotg bulk support 3323 *------------------------------------------------------------------------*/ 3324static void 3325musbotg_device_bulk_open(struct usb_xfer *xfer) 3326{ 3327 return; 3328} 3329 3330static void 3331musbotg_device_bulk_close(struct usb_xfer *xfer) 3332{ 3333 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3334} 3335 3336static void 3337musbotg_device_bulk_enter(struct usb_xfer *xfer) 3338{ 3339 return; 3340} 3341 3342static void 3343musbotg_device_bulk_start(struct usb_xfer *xfer) 3344{ 3345 /* setup TDs */ 3346 musbotg_setup_standard_chain(xfer); 3347 musbotg_start_standard_chain(xfer); 3348} 3349 3350struct usb_pipe_methods musbotg_device_bulk_methods = 3351{ 3352 .open = musbotg_device_bulk_open, 3353 .close = musbotg_device_bulk_close, 3354 .enter = musbotg_device_bulk_enter, 3355 .start = musbotg_device_bulk_start, 3356}; 3357 3358/*------------------------------------------------------------------------* 3359 * musbotg control support 3360 *------------------------------------------------------------------------*/ 3361static void 3362musbotg_device_ctrl_open(struct usb_xfer *xfer) 3363{ 3364 return; 3365} 3366 3367static void 3368musbotg_device_ctrl_close(struct usb_xfer *xfer) 3369{ 3370 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3371} 3372 3373static void 3374musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3375{ 3376 return; 3377} 3378 3379static void 3380musbotg_device_ctrl_start(struct usb_xfer *xfer) 3381{ 3382 /* setup TDs */ 3383 musbotg_setup_standard_chain(xfer); 3384 musbotg_start_standard_chain(xfer); 3385} 3386 3387struct usb_pipe_methods musbotg_device_ctrl_methods = 3388{ 3389 .open = musbotg_device_ctrl_open, 3390 .close = musbotg_device_ctrl_close, 3391 .enter = musbotg_device_ctrl_enter, 3392 .start = musbotg_device_ctrl_start, 3393}; 3394 3395/*------------------------------------------------------------------------* 3396 * musbotg interrupt support 3397 *------------------------------------------------------------------------*/ 3398static void 3399musbotg_device_intr_open(struct usb_xfer *xfer) 3400{ 3401 return; 3402} 3403 3404static void 3405musbotg_device_intr_close(struct usb_xfer *xfer) 3406{ 3407 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3408} 3409 3410static void 3411musbotg_device_intr_enter(struct usb_xfer *xfer) 3412{ 3413 return; 3414} 3415 3416static void 3417musbotg_device_intr_start(struct usb_xfer *xfer) 3418{ 3419 /* setup TDs */ 3420 musbotg_setup_standard_chain(xfer); 3421 musbotg_start_standard_chain(xfer); 3422} 3423 3424struct usb_pipe_methods musbotg_device_intr_methods = 3425{ 3426 .open = musbotg_device_intr_open, 3427 .close = musbotg_device_intr_close, 3428 .enter = musbotg_device_intr_enter, 3429 .start = musbotg_device_intr_start, 3430}; 3431 3432/*------------------------------------------------------------------------* 3433 * musbotg full speed isochronous support 3434 *------------------------------------------------------------------------*/ 3435static void 3436musbotg_device_isoc_open(struct usb_xfer *xfer) 3437{ 3438 return; 3439} 3440 3441static void 3442musbotg_device_isoc_close(struct usb_xfer *xfer) 3443{ 3444 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3445} 3446 3447static void 3448musbotg_device_isoc_enter(struct usb_xfer *xfer) 3449{ 3450 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3451 uint32_t temp; 3452 uint32_t nframes; 3453 uint32_t fs_frames; 3454 3455 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3456 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3457 3458 /* get the current frame index */ 3459 3460 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3461 3462 /* 3463 * check if the frame index is within the window where the frames 3464 * will be inserted 3465 */ 3466 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3467 3468 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3469 fs_frames = (xfer->nframes + 7) / 8; 3470 } else { 3471 fs_frames = xfer->nframes; 3472 } 3473 3474 if ((xfer->endpoint->is_synced == 0) || 3475 (temp < fs_frames)) { 3476 /* 3477 * If there is data underflow or the pipe queue is 3478 * empty we schedule the transfer a few frames ahead 3479 * of the current frame position. Else two isochronous 3480 * transfers might overlap. 3481 */ 3482 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3483 xfer->endpoint->is_synced = 1; 3484 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3485 } 3486 /* 3487 * compute how many milliseconds the insertion is ahead of the 3488 * current frame position: 3489 */ 3490 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3491 3492 /* 3493 * pre-compute when the isochronous transfer will be finished: 3494 */ 3495 xfer->isoc_time_complete = 3496 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3497 fs_frames; 3498 3499 /* compute frame number for next insertion */ 3500 xfer->endpoint->isoc_next += fs_frames; 3501 3502 /* setup TDs */ 3503 musbotg_setup_standard_chain(xfer); 3504} 3505 3506static void 3507musbotg_device_isoc_start(struct usb_xfer *xfer) 3508{ 3509 /* start TD chain */ 3510 musbotg_start_standard_chain(xfer); 3511} 3512 3513struct usb_pipe_methods musbotg_device_isoc_methods = 3514{ 3515 .open = musbotg_device_isoc_open, 3516 .close = musbotg_device_isoc_close, 3517 .enter = musbotg_device_isoc_enter, 3518 .start = musbotg_device_isoc_start, 3519}; 3520 3521/*------------------------------------------------------------------------* 3522 * musbotg root control support 3523 *------------------------------------------------------------------------* 3524 * Simulate a hardware HUB by handling all the necessary requests. 3525 *------------------------------------------------------------------------*/ 3526 3527static const struct usb_device_descriptor musbotg_devd = { 3528 .bLength = sizeof(struct usb_device_descriptor), 3529 .bDescriptorType = UDESC_DEVICE, 3530 .bcdUSB = {0x00, 0x02}, 3531 .bDeviceClass = UDCLASS_HUB, 3532 .bDeviceSubClass = UDSUBCLASS_HUB, 3533 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3534 .bMaxPacketSize = 64, 3535 .bcdDevice = {0x00, 0x01}, 3536 .iManufacturer = 1, 3537 .iProduct = 2, 3538 .bNumConfigurations = 1, 3539}; 3540 3541static const struct usb_device_qualifier musbotg_odevd = { 3542 .bLength = sizeof(struct usb_device_qualifier), 3543 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3544 .bcdUSB = {0x00, 0x02}, 3545 .bDeviceClass = UDCLASS_HUB, 3546 .bDeviceSubClass = UDSUBCLASS_HUB, 3547 .bDeviceProtocol = UDPROTO_FSHUB, 3548 .bMaxPacketSize0 = 0, 3549 .bNumConfigurations = 0, 3550}; 3551 3552static const struct musbotg_config_desc musbotg_confd = { 3553 .confd = { 3554 .bLength = sizeof(struct usb_config_descriptor), 3555 .bDescriptorType = UDESC_CONFIG, 3556 .wTotalLength[0] = sizeof(musbotg_confd), 3557 .bNumInterface = 1, 3558 .bConfigurationValue = 1, 3559 .iConfiguration = 0, 3560 .bmAttributes = UC_SELF_POWERED, 3561 .bMaxPower = 0, 3562 }, 3563 .ifcd = { 3564 .bLength = sizeof(struct usb_interface_descriptor), 3565 .bDescriptorType = UDESC_INTERFACE, 3566 .bNumEndpoints = 1, 3567 .bInterfaceClass = UICLASS_HUB, 3568 .bInterfaceSubClass = UISUBCLASS_HUB, 3569 .bInterfaceProtocol = 0, 3570 }, 3571 .endpd = { 3572 .bLength = sizeof(struct usb_endpoint_descriptor), 3573 .bDescriptorType = UDESC_ENDPOINT, 3574 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3575 .bmAttributes = UE_INTERRUPT, 3576 .wMaxPacketSize[0] = 8, 3577 .bInterval = 255, 3578 }, 3579}; 3580 3581#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3582 3583static const struct usb_hub_descriptor_min musbotg_hubd = { 3584 .bDescLength = sizeof(musbotg_hubd), 3585 .bDescriptorType = UDESC_HUB, 3586 .bNbrPorts = 1, 3587 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3588 .bPwrOn2PwrGood = 50, 3589 .bHubContrCurrent = 0, 3590 .DeviceRemovable = {0}, /* port is removable */ 3591}; 3592 3593#define STRING_VENDOR \ 3594 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3595 3596#define STRING_PRODUCT \ 3597 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3598 3599USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3600USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3601 3602static usb_error_t 3603musbotg_roothub_exec(struct usb_device *udev, 3604 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3605{ 3606 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3607 const void *ptr; 3608 uint16_t len; 3609 uint16_t value; 3610 uint16_t index; 3611 uint8_t reg; 3612 usb_error_t err; 3613 3614 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3615 3616 /* buffer reset */ 3617 ptr = (const void *)&sc->sc_hub_temp; 3618 len = 0; 3619 err = 0; 3620 3621 value = UGETW(req->wValue); 3622 index = UGETW(req->wIndex); 3623 3624 /* demultiplex the control request */ 3625 3626 switch (req->bmRequestType) { 3627 case UT_READ_DEVICE: 3628 switch (req->bRequest) { 3629 case UR_GET_DESCRIPTOR: 3630 goto tr_handle_get_descriptor; 3631 case UR_GET_CONFIG: 3632 goto tr_handle_get_config; 3633 case UR_GET_STATUS: 3634 goto tr_handle_get_status; 3635 default: 3636 goto tr_stalled; 3637 } 3638 break; 3639 3640 case UT_WRITE_DEVICE: 3641 switch (req->bRequest) { 3642 case UR_SET_ADDRESS: 3643 goto tr_handle_set_address; 3644 case UR_SET_CONFIG: 3645 goto tr_handle_set_config; 3646 case UR_CLEAR_FEATURE: 3647 goto tr_valid; /* nop */ 3648 case UR_SET_DESCRIPTOR: 3649 goto tr_valid; /* nop */ 3650 case UR_SET_FEATURE: 3651 default: 3652 goto tr_stalled; 3653 } 3654 break; 3655 3656 case UT_WRITE_ENDPOINT: 3657 switch (req->bRequest) { 3658 case UR_CLEAR_FEATURE: 3659 switch (UGETW(req->wValue)) { 3660 case UF_ENDPOINT_HALT: 3661 goto tr_handle_clear_halt; 3662 case UF_DEVICE_REMOTE_WAKEUP: 3663 goto tr_handle_clear_wakeup; 3664 default: 3665 goto tr_stalled; 3666 } 3667 break; 3668 case UR_SET_FEATURE: 3669 switch (UGETW(req->wValue)) { 3670 case UF_ENDPOINT_HALT: 3671 goto tr_handle_set_halt; 3672 case UF_DEVICE_REMOTE_WAKEUP: 3673 goto tr_handle_set_wakeup; 3674 default: 3675 goto tr_stalled; 3676 } 3677 break; 3678 case UR_SYNCH_FRAME: 3679 goto tr_valid; /* nop */ 3680 default: 3681 goto tr_stalled; 3682 } 3683 break; 3684 3685 case UT_READ_ENDPOINT: 3686 switch (req->bRequest) { 3687 case UR_GET_STATUS: 3688 goto tr_handle_get_ep_status; 3689 default: 3690 goto tr_stalled; 3691 } 3692 break; 3693 3694 case UT_WRITE_INTERFACE: 3695 switch (req->bRequest) { 3696 case UR_SET_INTERFACE: 3697 goto tr_handle_set_interface; 3698 case UR_CLEAR_FEATURE: 3699 goto tr_valid; /* nop */ 3700 case UR_SET_FEATURE: 3701 default: 3702 goto tr_stalled; 3703 } 3704 break; 3705 3706 case UT_READ_INTERFACE: 3707 switch (req->bRequest) { 3708 case UR_GET_INTERFACE: 3709 goto tr_handle_get_interface; 3710 case UR_GET_STATUS: 3711 goto tr_handle_get_iface_status; 3712 default: 3713 goto tr_stalled; 3714 } 3715 break; 3716 3717 case UT_WRITE_CLASS_INTERFACE: 3718 case UT_WRITE_VENDOR_INTERFACE: 3719 /* XXX forward */ 3720 break; 3721 3722 case UT_READ_CLASS_INTERFACE: 3723 case UT_READ_VENDOR_INTERFACE: 3724 /* XXX forward */ 3725 break; 3726 3727 case UT_WRITE_CLASS_DEVICE: 3728 switch (req->bRequest) { 3729 case UR_CLEAR_FEATURE: 3730 goto tr_valid; 3731 case UR_SET_DESCRIPTOR: 3732 case UR_SET_FEATURE: 3733 break; 3734 default: 3735 goto tr_stalled; 3736 } 3737 break; 3738 3739 case UT_WRITE_CLASS_OTHER: 3740 switch (req->bRequest) { 3741 case UR_CLEAR_FEATURE: 3742 goto tr_handle_clear_port_feature; 3743 case UR_SET_FEATURE: 3744 goto tr_handle_set_port_feature; 3745 case UR_CLEAR_TT_BUFFER: 3746 case UR_RESET_TT: 3747 case UR_STOP_TT: 3748 goto tr_valid; 3749 3750 default: 3751 goto tr_stalled; 3752 } 3753 break; 3754 3755 case UT_READ_CLASS_OTHER: 3756 switch (req->bRequest) { 3757 case UR_GET_TT_STATE: 3758 goto tr_handle_get_tt_state; 3759 case UR_GET_STATUS: 3760 goto tr_handle_get_port_status; 3761 default: 3762 goto tr_stalled; 3763 } 3764 break; 3765 3766 case UT_READ_CLASS_DEVICE: 3767 switch (req->bRequest) { 3768 case UR_GET_DESCRIPTOR: 3769 goto tr_handle_get_class_descriptor; 3770 case UR_GET_STATUS: 3771 goto tr_handle_get_class_status; 3772 3773 default: 3774 goto tr_stalled; 3775 } 3776 break; 3777 default: 3778 goto tr_stalled; 3779 } 3780 goto tr_valid; 3781 3782tr_handle_get_descriptor: 3783 switch (value >> 8) { 3784 case UDESC_DEVICE: 3785 if (value & 0xff) { 3786 goto tr_stalled; 3787 } 3788 len = sizeof(musbotg_devd); 3789 ptr = (const void *)&musbotg_devd; 3790 goto tr_valid; 3791 case UDESC_DEVICE_QUALIFIER: 3792 if (value & 0xff) { 3793 goto tr_stalled; 3794 } 3795 len = sizeof(musbotg_odevd); 3796 ptr = (const void *)&musbotg_odevd; 3797 goto tr_valid; 3798 case UDESC_CONFIG: 3799 if (value & 0xff) { 3800 goto tr_stalled; 3801 } 3802 len = sizeof(musbotg_confd); 3803 ptr = (const void *)&musbotg_confd; 3804 goto tr_valid; 3805 case UDESC_STRING: 3806 switch (value & 0xff) { 3807 case 0: /* Language table */ 3808 len = sizeof(usb_string_lang_en); 3809 ptr = (const void *)&usb_string_lang_en; 3810 goto tr_valid; 3811 3812 case 1: /* Vendor */ 3813 len = sizeof(musbotg_vendor); 3814 ptr = (const void *)&musbotg_vendor; 3815 goto tr_valid; 3816 3817 case 2: /* Product */ 3818 len = sizeof(musbotg_product); 3819 ptr = (const void *)&musbotg_product; 3820 goto tr_valid; 3821 default: 3822 break; 3823 } 3824 break; 3825 default: 3826 goto tr_stalled; 3827 } 3828 goto tr_stalled; 3829 3830tr_handle_get_config: 3831 len = 1; 3832 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3833 goto tr_valid; 3834 3835tr_handle_get_status: 3836 len = 2; 3837 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3838 goto tr_valid; 3839 3840tr_handle_set_address: 3841 if (value & 0xFF00) { 3842 goto tr_stalled; 3843 } 3844 sc->sc_rt_addr = value; 3845 goto tr_valid; 3846 3847tr_handle_set_config: 3848 if (value >= 2) { 3849 goto tr_stalled; 3850 } 3851 sc->sc_conf = value; 3852 goto tr_valid; 3853 3854tr_handle_get_interface: 3855 len = 1; 3856 sc->sc_hub_temp.wValue[0] = 0; 3857 goto tr_valid; 3858 3859tr_handle_get_tt_state: 3860tr_handle_get_class_status: 3861tr_handle_get_iface_status: 3862tr_handle_get_ep_status: 3863 len = 2; 3864 USETW(sc->sc_hub_temp.wValue, 0); 3865 goto tr_valid; 3866 3867tr_handle_set_halt: 3868tr_handle_set_interface: 3869tr_handle_set_wakeup: 3870tr_handle_clear_wakeup: 3871tr_handle_clear_halt: 3872 goto tr_valid; 3873 3874tr_handle_clear_port_feature: 3875 if (index != 1) { 3876 goto tr_stalled; 3877 } 3878 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3879 3880 switch (value) { 3881 case UHF_PORT_SUSPEND: 3882 if (sc->sc_mode == MUSB2_HOST_MODE) 3883 musbotg_wakeup_host(sc); 3884 else 3885 musbotg_wakeup_peer(sc); 3886 break; 3887 3888 case UHF_PORT_ENABLE: 3889 sc->sc_flags.port_enabled = 0; 3890 break; 3891 3892 case UHF_C_PORT_ENABLE: 3893 sc->sc_flags.change_enabled = 0; 3894 break; 3895 3896 case UHF_C_PORT_OVER_CURRENT: 3897 sc->sc_flags.change_over_current = 0; 3898 break; 3899 3900 case UHF_C_PORT_RESET: 3901 sc->sc_flags.change_reset = 0; 3902 break; 3903 3904 case UHF_PORT_TEST: 3905 case UHF_PORT_INDICATOR: 3906 /* nops */ 3907 break; 3908 3909 case UHF_PORT_POWER: 3910 sc->sc_flags.port_powered = 0; 3911 musbotg_pull_down(sc); 3912 musbotg_clocks_off(sc); 3913 break; 3914 case UHF_C_PORT_CONNECTION: 3915 sc->sc_flags.change_connect = 0; 3916 break; 3917 case UHF_C_PORT_SUSPEND: 3918 sc->sc_flags.change_suspend = 0; 3919 break; 3920 default: 3921 err = USB_ERR_IOERROR; 3922 goto done; 3923 } 3924 goto tr_valid; 3925 3926tr_handle_set_port_feature: 3927 if (index != 1) { 3928 goto tr_stalled; 3929 } 3930 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3931 3932 switch (value) { 3933 case UHF_PORT_ENABLE: 3934 sc->sc_flags.port_enabled = 1; 3935 break; 3936 case UHF_PORT_SUSPEND: 3937 if (sc->sc_mode == MUSB2_HOST_MODE) 3938 musbotg_suspend_host(sc); 3939 break; 3940 3941 case UHF_PORT_RESET: 3942 if (sc->sc_mode == MUSB2_HOST_MODE) { 3943 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3944 reg |= MUSB2_MASK_RESET; 3945 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3946 3947 /* Wait for 20 msec */ 3948 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3949 3950 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3951 reg &= ~MUSB2_MASK_RESET; 3952 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3953 3954 /* determine line speed */ 3955 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3956 if (reg & MUSB2_MASK_HSMODE) 3957 sc->sc_flags.status_high_speed = 1; 3958 else 3959 sc->sc_flags.status_high_speed = 0; 3960 3961 sc->sc_flags.change_reset = 1; 3962 } else 3963 err = USB_ERR_IOERROR; 3964 break; 3965 3966 case UHF_PORT_TEST: 3967 case UHF_PORT_INDICATOR: 3968 /* nops */ 3969 break; 3970 case UHF_PORT_POWER: 3971 sc->sc_flags.port_powered = 1; 3972 break; 3973 default: 3974 err = USB_ERR_IOERROR; 3975 goto done; 3976 } 3977 goto tr_valid; 3978 3979tr_handle_get_port_status: 3980 3981 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3982 3983 if (index != 1) { 3984 goto tr_stalled; 3985 } 3986 if (sc->sc_flags.status_vbus) { 3987 musbotg_clocks_on(sc); 3988 musbotg_pull_up(sc); 3989 } else { 3990 musbotg_pull_down(sc); 3991 musbotg_clocks_off(sc); 3992 } 3993 3994 /* Select Device Side Mode */ 3995 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3996 value = UPS_PORT_MODE_DEVICE; 3997 else 3998 value = 0; 3999 4000 if (sc->sc_flags.status_high_speed) { 4001 value |= UPS_HIGH_SPEED; 4002 } 4003 if (sc->sc_flags.port_powered) { 4004 value |= UPS_PORT_POWER; 4005 } 4006 if (sc->sc_flags.port_enabled) { 4007 value |= UPS_PORT_ENABLED; 4008 } 4009 4010 if (sc->sc_flags.port_over_current) 4011 value |= UPS_OVERCURRENT_INDICATOR; 4012 4013 if (sc->sc_flags.status_vbus && 4014 sc->sc_flags.status_bus_reset) { 4015 value |= UPS_CURRENT_CONNECT_STATUS; 4016 } 4017 if (sc->sc_flags.status_suspend) { 4018 value |= UPS_SUSPEND; 4019 } 4020 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4021 4022 value = 0; 4023 4024 if (sc->sc_flags.change_connect) { 4025 value |= UPS_C_CONNECT_STATUS; 4026 4027 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 4028 if (sc->sc_flags.status_vbus && 4029 sc->sc_flags.status_bus_reset) { 4030 /* reset EP0 state */ 4031 sc->sc_ep0_busy = 0; 4032 sc->sc_ep0_cmd = 0; 4033 } 4034 } 4035 } 4036 if (sc->sc_flags.change_suspend) 4037 value |= UPS_C_SUSPEND; 4038 if (sc->sc_flags.change_reset) 4039 value |= UPS_C_PORT_RESET; 4040 if (sc->sc_flags.change_over_current) 4041 value |= UPS_C_OVERCURRENT_INDICATOR; 4042 4043 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4044 len = sizeof(sc->sc_hub_temp.ps); 4045 goto tr_valid; 4046 4047tr_handle_get_class_descriptor: 4048 if (value & 0xFF) { 4049 goto tr_stalled; 4050 } 4051 ptr = (const void *)&musbotg_hubd; 4052 len = sizeof(musbotg_hubd); 4053 goto tr_valid; 4054 4055tr_stalled: 4056 err = USB_ERR_STALLED; 4057tr_valid: 4058done: 4059 *plength = len; 4060 *pptr = ptr; 4061 return (err); 4062} 4063 4064static void 4065musbotg_xfer_setup(struct usb_setup_params *parm) 4066{ 4067 struct musbotg_softc *sc; 4068 struct usb_xfer *xfer; 4069 void *last_obj; 4070 uint32_t ntd; 4071 uint32_t n; 4072 uint8_t ep_no; 4073 4074 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4075 xfer = parm->curr_xfer; 4076 4077 /* 4078 * NOTE: This driver does not use any of the parameters that 4079 * are computed from the following values. Just set some 4080 * reasonable dummies: 4081 */ 4082 parm->hc_max_packet_size = 0x400; 4083 parm->hc_max_frame_size = 0xc00; 4084 4085 if ((parm->methods == &musbotg_device_isoc_methods) || 4086 (parm->methods == &musbotg_device_intr_methods)) 4087 parm->hc_max_packet_count = 3; 4088 else 4089 parm->hc_max_packet_count = 1; 4090 4091 usbd_transfer_setup_sub(parm); 4092 4093 /* 4094 * compute maximum number of TDs 4095 */ 4096 if (parm->methods == &musbotg_device_ctrl_methods) { 4097 4098 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4099 4100 } else if (parm->methods == &musbotg_device_bulk_methods) { 4101 4102 ntd = xfer->nframes + 1 /* SYNC */ ; 4103 4104 } else if (parm->methods == &musbotg_device_intr_methods) { 4105 4106 ntd = xfer->nframes + 1 /* SYNC */ ; 4107 4108 } else if (parm->methods == &musbotg_device_isoc_methods) { 4109 4110 ntd = xfer->nframes + 1 /* SYNC */ ; 4111 4112 } else { 4113 4114 ntd = 0; 4115 } 4116 4117 /* 4118 * check if "usbd_transfer_setup_sub" set an error 4119 */ 4120 if (parm->err) { 4121 return; 4122 } 4123 /* 4124 * allocate transfer descriptors 4125 */ 4126 last_obj = NULL; 4127 4128 ep_no = xfer->endpointno & UE_ADDR; 4129 4130 /* 4131 * Check for a valid endpoint profile in USB device mode: 4132 */ 4133 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4134 const struct usb_hw_ep_profile *pf; 4135 4136 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4137 4138 if (pf == NULL) { 4139 /* should not happen */ 4140 parm->err = USB_ERR_INVAL; 4141 return; 4142 } 4143 } 4144 4145 /* align data */ 4146 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4147 4148 for (n = 0; n != ntd; n++) { 4149 4150 struct musbotg_td *td; 4151 4152 if (parm->buf) { 4153 4154 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4155 4156 /* init TD */ 4157 td->max_frame_size = xfer->max_frame_size; 4158 td->reg_max_packet = xfer->max_packet_size | 4159 ((xfer->max_packet_count - 1) << 11); 4160 td->ep_no = ep_no; 4161 td->obj_next = last_obj; 4162 4163 last_obj = td; 4164 } 4165 parm->size[0] += sizeof(*td); 4166 } 4167 4168 xfer->td_start[0] = last_obj; 4169} 4170 4171static void 4172musbotg_xfer_unsetup(struct usb_xfer *xfer) 4173{ 4174 return; 4175} 4176 4177static void 4178musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4179{ 4180 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4181 4182 if (sc->sc_mode == MUSB2_HOST_MODE) 4183 *pus = 2000; /* microseconds */ 4184 else 4185 *pus = 0; 4186} 4187 4188static void 4189musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4190 struct usb_endpoint *ep) 4191{ 4192 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4193 4194 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4195 ep, udev->address, 4196 edesc->bEndpointAddress, udev->flags.usb_mode, 4197 sc->sc_rt_addr); 4198 4199 if (udev->device_index != sc->sc_rt_addr) { 4200 switch (edesc->bmAttributes & UE_XFERTYPE) { 4201 case UE_CONTROL: 4202 ep->methods = &musbotg_device_ctrl_methods; 4203 break; 4204 case UE_INTERRUPT: 4205 ep->methods = &musbotg_device_intr_methods; 4206 break; 4207 case UE_ISOCHRONOUS: 4208 ep->methods = &musbotg_device_isoc_methods; 4209 break; 4210 case UE_BULK: 4211 ep->methods = &musbotg_device_bulk_methods; 4212 break; 4213 default: 4214 /* do nothing */ 4215 break; 4216 } 4217 } 4218} 4219 4220static void 4221musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4222{ 4223 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4224 4225 switch (state) { 4226 case USB_HW_POWER_SUSPEND: 4227 musbotg_suspend(sc); 4228 break; 4229 case USB_HW_POWER_SHUTDOWN: 4230 musbotg_uninit(sc); 4231 break; 4232 case USB_HW_POWER_RESUME: 4233 musbotg_resume(sc); 4234 break; 4235 default: 4236 break; 4237 } 4238} 4239 4240struct usb_bus_methods musbotg_bus_methods = 4241{ 4242 .endpoint_init = &musbotg_ep_init, 4243 .get_dma_delay = &musbotg_get_dma_delay, 4244 .xfer_setup = &musbotg_xfer_setup, 4245 .xfer_unsetup = &musbotg_xfer_unsetup, 4246 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4247 .xfer_stall = &musbotg_xfer_stall, 4248 .set_stall = &musbotg_set_stall, 4249 .clear_stall = &musbotg_clear_stall, 4250 .roothub_exec = &musbotg_roothub_exec, 4251 .xfer_poll = &musbotg_do_poll, 4252 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4253}; 4254