ichwd.h revision 221015
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 221015 2011-04-25 14:10:33Z attilio $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t device; 36129124Sdes char *desc; 37171820Sdes unsigned int version; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42171820Sdes device_t ich; 43175012Sdes int ich_version; 44129124Sdes 45129124Sdes int active; 46129124Sdes unsigned int timeout; 47129124Sdes 48221015Sattilio int smi_enabled; 49129124Sdes int smi_rid; 50129124Sdes struct resource *smi_res; 51129124Sdes bus_space_tag_t smi_bst; 52129124Sdes bus_space_handle_t smi_bsh; 53129124Sdes 54129124Sdes int tco_rid; 55129124Sdes struct resource *tco_res; 56129124Sdes bus_space_tag_t tco_bst; 57129124Sdes bus_space_handle_t tco_bsh; 58129124Sdes 59171820Sdes int gcs_rid; 60171820Sdes struct resource *gcs_res; 61171820Sdes bus_space_tag_t gcs_bst; 62171820Sdes bus_space_handle_t gcs_bsh; 63171820Sdes 64129124Sdes eventhandler_tag ev_tag; 65129124Sdes}; 66129124Sdes 67129124Sdes#define VENDORID_INTEL 0x8086 68211908Sjfv#define DEVICEID_CPT0 0x1c40 69211908Sjfv#define DEVICEID_CPT1 0x1c41 70211908Sjfv#define DEVICEID_CPT2 0x1c42 71211908Sjfv#define DEVICEID_CPT3 0x1c43 72211908Sjfv#define DEVICEID_CPT4 0x1c44 73211908Sjfv#define DEVICEID_CPT5 0x1c45 74211908Sjfv#define DEVICEID_CPT6 0x1c46 75211908Sjfv#define DEVICEID_CPT7 0x1c47 76211908Sjfv#define DEVICEID_CPT8 0x1c48 77211908Sjfv#define DEVICEID_CPT9 0x1c49 78211908Sjfv#define DEVICEID_CPT10 0x1c4a 79211908Sjfv#define DEVICEID_CPT11 0x1c4b 80211908Sjfv#define DEVICEID_CPT12 0x1c4c 81211908Sjfv#define DEVICEID_CPT13 0x1c4d 82211908Sjfv#define DEVICEID_CPT14 0x1c4e 83211908Sjfv#define DEVICEID_CPT15 0x1c4f 84211908Sjfv#define DEVICEID_CPT16 0x1c50 85211908Sjfv#define DEVICEID_CPT17 0x1c51 86211908Sjfv#define DEVICEID_CPT18 0x1c52 87211908Sjfv#define DEVICEID_CPT19 0x1c53 88211908Sjfv#define DEVICEID_CPT20 0x1c54 89211908Sjfv#define DEVICEID_CPT21 0x1c55 90211908Sjfv#define DEVICEID_CPT22 0x1c56 91211908Sjfv#define DEVICEID_CPT23 0x1c57 92211908Sjfv#define DEVICEID_CPT24 0x1c58 93211908Sjfv#define DEVICEID_CPT25 0x1c59 94211908Sjfv#define DEVICEID_CPT26 0x1c5a 95211908Sjfv#define DEVICEID_CPT27 0x1c5b 96211908Sjfv#define DEVICEID_CPT28 0x1c5c 97211908Sjfv#define DEVICEID_CPT29 0x1c5d 98211908Sjfv#define DEVICEID_CPT30 0x1c5e 99211908Sjfv#define DEVICEID_CPT31 0x1c5f 100218149Sjfv#define DEVICEID_PATSBURG_LPC1 0x1d40 101218149Sjfv#define DEVICEID_PATSBURG_LPC2 0x1d41 102218140Sjfv#define DEVICEID_DH89XXCC_LPC 0x2310 103129124Sdes#define DEVICEID_82801AA 0x2410 104129124Sdes#define DEVICEID_82801AB 0x2420 105129124Sdes#define DEVICEID_82801BA 0x2440 106129124Sdes#define DEVICEID_82801BAM 0x244c 107129124Sdes#define DEVICEID_82801CA 0x2480 108129124Sdes#define DEVICEID_82801CAM 0x248c 109129124Sdes#define DEVICEID_82801DB 0x24c0 110129124Sdes#define DEVICEID_82801DBM 0x24cc 111129124Sdes#define DEVICEID_82801E 0x2450 112182161Sjhb#define DEVICEID_82801EB 0x24dc 113129124Sdes#define DEVICEID_82801EBR 0x24d0 114155785Sambrisko#define DEVICEID_6300ESB 0x25a1 115155785Sambrisko#define DEVICEID_82801FBR 0x2640 116171820Sdes#define DEVICEID_ICH6M 0x2641 117171820Sdes#define DEVICEID_ICH6W 0x2642 118173661Sjfv#define DEVICEID_63XXESB 0x2670 119171820Sdes#define DEVICEID_ICH7 0x27b8 120182161Sjhb#define DEVICEID_ICH7DH 0x27b0 121171820Sdes#define DEVICEID_ICH7M 0x27b9 122202917Sremko#define DEVICEID_NM10 0x27bc 123171820Sdes#define DEVICEID_ICH7MDH 0x27bd 124171820Sdes#define DEVICEID_ICH8 0x2810 125171820Sdes#define DEVICEID_ICH8DH 0x2812 126171820Sdes#define DEVICEID_ICH8DO 0x2814 127175128Sdes#define DEVICEID_ICH8M 0x2815 128182161Sjhb#define DEVICEID_ICH8ME 0x2811 129175013Sdes#define DEVICEID_ICH9 0x2918 130175013Sdes#define DEVICEID_ICH9DH 0x2912 131175013Sdes#define DEVICEID_ICH9DO 0x2914 132182161Sjhb#define DEVICEID_ICH9M 0x2919 133182161Sjhb#define DEVICEID_ICH9ME 0x2917 134182161Sjhb#define DEVICEID_ICH9R 0x2916 135182161Sjhb#define DEVICEID_ICH10 0x3a18 136182161Sjhb#define DEVICEID_ICH10D 0x3a1a 137182161Sjhb#define DEVICEID_ICH10DO 0x3a14 138182161Sjhb#define DEVICEID_ICH10R 0x3a16 139211908Sjfv#define DEVICEID_PCH 0x3b00 140211908Sjfv#define DEVICEID_PCHM 0x3b01 141211908Sjfv#define DEVICEID_P55 0x3b02 142211908Sjfv#define DEVICEID_PM55 0x3b03 143202812Semaste#define DEVICEID_H55 0x3b06 144211908Sjfv#define DEVICEID_QM57 0x3b07 145211908Sjfv#define DEVICEID_H57 0x3b08 146211908Sjfv#define DEVICEID_HM55 0x3b09 147211908Sjfv#define DEVICEID_Q57 0x3b0a 148211908Sjfv#define DEVICEID_HM57 0x3b0b 149211908Sjfv#define DEVICEID_PCHMSFF 0x3b0d 150211908Sjfv#define DEVICEID_QS57 0x3b0f 151211908Sjfv#define DEVICEID_3400 0x3b12 152211908Sjfv#define DEVICEID_3420 0x3b14 153211908Sjfv#define DEVICEID_3450 0x3b16 154129124Sdes 155171820Sdes/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 156129124Sdes#define ICH_GEN_STA 0xd4 157129124Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 158129124Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 159129124Sdes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 160129124Sdes 161171820Sdes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 162171820Sdes#define ICH_RCBA 0xf0 163171820Sdes#define ICH_GCS_OFFSET 0x3410 164171820Sdes#define ICH_GCS_SIZE 0x4 165171820Sdes#define ICH_GCS_NO_REBOOT 0x20 166171820Sdes 167129124Sdes/* register names and locations (relative to PMBASE) */ 168129124Sdes#define SMI_BASE 0x30 /* base address for SMI registers */ 169129124Sdes#define SMI_LEN 0x08 170129124Sdes#define SMI_EN 0x00 /* SMI Control and Enable Register */ 171129124Sdes#define SMI_STS 0x04 /* SMI Status Register */ 172129124Sdes#define TCO_BASE 0x60 /* base address for TCO registers */ 173171820Sdes#define TCO_LEN 0x20 174129124Sdes#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 175171820Sdes#define TCO_TMR1 0x01 /* TCO Timer Initial Value 176171820Sdes (ICH5 and older, 8 bits) */ 177171820Sdes#define TCO_TMR2 0x12 /* TCO Timer Initial Value 178171820Sdes (ICH6 and newer, 16 bits) */ 179129124Sdes#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 180129124Sdes#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 181129124Sdes#define TCO1_STS 0x04 /* TCO Status 1 */ 182129124Sdes#define TCO2_STS 0x06 /* TCO Status 2 */ 183129124Sdes#define TCO1_CNT 0x08 /* TCO Control 1 */ 184171820Sdes#define TCO2_CNT 0x08 /* TCO Control 2 */ 185220925Sattilio#define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 186220925Sattilio#define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 187129124Sdes 188129124Sdes/* bit definitions for SMI_EN and SMI_STS */ 189129124Sdes#define SMI_TCO_EN 0x2000 190129124Sdes#define SMI_TCO_STS 0x2000 191220925Sattilio#define SMI_GBL_EN 0x0001 192129124Sdes 193129124Sdes/* timer value mask for TCO_RLD and TCO_TMR */ 194129124Sdes#define TCO_TIMER_MASK 0x1f 195129124Sdes 196129124Sdes/* status bits for TCO1_STS */ 197220925Sattilio#define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */ 198129124Sdes#define TCO_TIMEOUT 0x08 /* timed out */ 199129124Sdes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 200129124Sdes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 201129124Sdes 202129124Sdes/* status bits for TCO2_STS */ 203129124Sdes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 204129124Sdes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 205129124Sdes 206129124Sdes/* control bits for TCO1_CNT */ 207220925Sattilio#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 208220925Sattilio#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 209220925Sattilio#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 210220925Sattilio#define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 211129124Sdes 212216298Sattilio/* 213216298Sattilio * Masks for the TCO timer value field in TCO_RLD. 214216298Sattilio * If the datasheets are to be believed, the minimum value actually varies 215216298Sattilio * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 216216298Sattilio * I suspect this is a bug in the ICH5 datasheet and that the minimum is 217216298Sattilio * uniformly 2, but I'd rather err on the side of caution. 218216298Sattilio */ 219216298Sattilio#define TCO_RLD_TMR_MIN 0x0004 220216298Sattilio#define TCO_RLD1_TMR_MAX 0x003f 221216298Sattilio#define TCO_RLD2_TMR_MAX 0x03ff 222216298Sattilio 223171820Sdes/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 224171820Sdes#define ICHWD_TICK 600000000 225129124Sdes 226129124Sdes#endif 227