ichwd.h revision 221015 
1/*-
2 * Copyright (c) 2004 Texas A&M University
3 * All rights reserved.
4 *
5 * Developer: Wm. Daryl Hawkins
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ichwd/ichwd.h 221015 2011-04-25 14:10:33Z attilio $
29 */
30
31#ifndef _ICHWD_H_
32#define _ICHWD_H_
33
34struct ichwd_device {
35	uint16_t		 device;
36	char			*desc;
37	unsigned int		 version;
38};
39
40struct ichwd_softc {
41	device_t		 device;
42	device_t		 ich;
43	int			 ich_version;
44
45	int			 active;
46	unsigned int		 timeout;
47
48	int			 smi_enabled;
49	int			 smi_rid;
50	struct resource		*smi_res;
51	bus_space_tag_t		 smi_bst;
52	bus_space_handle_t	 smi_bsh;
53
54	int			 tco_rid;
55	struct resource		*tco_res;
56	bus_space_tag_t		 tco_bst;
57	bus_space_handle_t	 tco_bsh;
58
59	int			 gcs_rid;
60	struct resource		*gcs_res;
61	bus_space_tag_t		 gcs_bst;
62	bus_space_handle_t	 gcs_bsh;
63
64	eventhandler_tag	 ev_tag;
65};
66
67#define VENDORID_INTEL		0x8086
68#define DEVICEID_CPT0		0x1c40
69#define DEVICEID_CPT1		0x1c41
70#define DEVICEID_CPT2		0x1c42
71#define DEVICEID_CPT3		0x1c43
72#define DEVICEID_CPT4		0x1c44
73#define DEVICEID_CPT5		0x1c45
74#define DEVICEID_CPT6		0x1c46
75#define DEVICEID_CPT7		0x1c47
76#define DEVICEID_CPT8		0x1c48
77#define DEVICEID_CPT9		0x1c49
78#define DEVICEID_CPT10		0x1c4a
79#define DEVICEID_CPT11		0x1c4b
80#define DEVICEID_CPT12		0x1c4c
81#define DEVICEID_CPT13		0x1c4d
82#define DEVICEID_CPT14		0x1c4e
83#define DEVICEID_CPT15		0x1c4f
84#define DEVICEID_CPT16		0x1c50
85#define DEVICEID_CPT17		0x1c51
86#define DEVICEID_CPT18		0x1c52
87#define DEVICEID_CPT19		0x1c53
88#define DEVICEID_CPT20		0x1c54
89#define DEVICEID_CPT21		0x1c55
90#define DEVICEID_CPT22		0x1c56
91#define DEVICEID_CPT23		0x1c57
92#define DEVICEID_CPT24		0x1c58
93#define DEVICEID_CPT25		0x1c59
94#define DEVICEID_CPT26		0x1c5a
95#define DEVICEID_CPT27		0x1c5b
96#define DEVICEID_CPT28		0x1c5c
97#define DEVICEID_CPT29		0x1c5d
98#define DEVICEID_CPT30		0x1c5e
99#define DEVICEID_CPT31		0x1c5f
100#define DEVICEID_PATSBURG_LPC1	0x1d40
101#define DEVICEID_PATSBURG_LPC2	0x1d41
102#define DEVICEID_DH89XXCC_LPC	0x2310
103#define DEVICEID_82801AA	0x2410
104#define DEVICEID_82801AB	0x2420
105#define DEVICEID_82801BA	0x2440
106#define DEVICEID_82801BAM	0x244c
107#define DEVICEID_82801CA	0x2480
108#define DEVICEID_82801CAM	0x248c
109#define DEVICEID_82801DB	0x24c0
110#define DEVICEID_82801DBM	0x24cc
111#define DEVICEID_82801E		0x2450
112#define DEVICEID_82801EB	0x24dc
113#define DEVICEID_82801EBR	0x24d0
114#define DEVICEID_6300ESB	0x25a1
115#define DEVICEID_82801FBR	0x2640
116#define DEVICEID_ICH6M		0x2641
117#define DEVICEID_ICH6W		0x2642
118#define DEVICEID_63XXESB	0x2670
119#define DEVICEID_ICH7		0x27b8
120#define DEVICEID_ICH7DH		0x27b0
121#define DEVICEID_ICH7M		0x27b9
122#define DEVICEID_NM10		0x27bc
123#define DEVICEID_ICH7MDH	0x27bd
124#define DEVICEID_ICH8		0x2810
125#define DEVICEID_ICH8DH		0x2812
126#define DEVICEID_ICH8DO		0x2814
127#define DEVICEID_ICH8M		0x2815
128#define DEVICEID_ICH8ME		0x2811
129#define DEVICEID_ICH9		0x2918
130#define DEVICEID_ICH9DH		0x2912
131#define DEVICEID_ICH9DO		0x2914
132#define DEVICEID_ICH9M		0x2919
133#define DEVICEID_ICH9ME		0x2917
134#define DEVICEID_ICH9R		0x2916
135#define DEVICEID_ICH10		0x3a18
136#define DEVICEID_ICH10D		0x3a1a
137#define DEVICEID_ICH10DO	0x3a14
138#define DEVICEID_ICH10R		0x3a16
139#define DEVICEID_PCH		0x3b00
140#define DEVICEID_PCHM		0x3b01
141#define DEVICEID_P55		0x3b02
142#define DEVICEID_PM55		0x3b03
143#define DEVICEID_H55		0x3b06
144#define DEVICEID_QM57		0x3b07
145#define DEVICEID_H57		0x3b08
146#define DEVICEID_HM55		0x3b09
147#define DEVICEID_Q57		0x3b0a
148#define DEVICEID_HM57		0x3b0b
149#define DEVICEID_PCHMSFF	0x3b0d
150#define DEVICEID_QS57		0x3b0f
151#define DEVICEID_3400		0x3b12
152#define DEVICEID_3420		0x3b14
153#define DEVICEID_3450		0x3b16
154
155/* ICH LPC Interface Bridge Registers (ICH5 and older) */
156#define ICH_GEN_STA		0xd4
157#define ICH_GEN_STA_NO_REBOOT	0x02
158#define ICH_PMBASE		0x40 /* ACPI base address register */
159#define ICH_PMBASE_MASK		0x7f80 /* bits 7-15 */
160
161/* ICH Chipset Configuration Registers (ICH6 and newer) */
162#define ICH_RCBA		0xf0
163#define ICH_GCS_OFFSET		0x3410
164#define ICH_GCS_SIZE		0x4
165#define ICH_GCS_NO_REBOOT	0x20
166
167/* register names and locations (relative to PMBASE) */
168#define SMI_BASE		0x30 /* base address for SMI registers */
169#define SMI_LEN			0x08
170#define SMI_EN			0x00 /* SMI Control and Enable Register */
171#define SMI_STS			0x04 /* SMI Status Register */
172#define TCO_BASE		0x60 /* base address for TCO registers */
173#define TCO_LEN			0x20
174#define TCO_RLD			0x00 /* TCO Reload and Current Value */
175#define TCO_TMR1		0x01 /* TCO Timer Initial Value
176					(ICH5 and older, 8 bits) */
177#define TCO_TMR2		0x12 /* TCO Timer Initial Value
178					(ICH6 and newer, 16 bits) */
179#define TCO_DAT_IN		0x02 /* TCO Data In (DO NOT USE) */
180#define TCO_DAT_OUT		0x03 /* TCO Data Out (DO NOT USE) */
181#define TCO1_STS		0x04 /* TCO Status 1 */
182#define TCO2_STS		0x06 /* TCO Status 2 */
183#define TCO1_CNT		0x08 /* TCO Control 1 */
184#define TCO2_CNT		0x08 /* TCO Control 2 */
185#define TCO_MESSAGE1		0x0c /* TCO Message 1 */
186#define TCO_MESSAGE2		0x0d /* TCO Message 2 */
187
188/* bit definitions for SMI_EN and SMI_STS */
189#define SMI_TCO_EN		0x2000
190#define SMI_TCO_STS		0x2000
191#define SMI_GBL_EN		0x0001
192
193/* timer value mask for TCO_RLD and TCO_TMR */
194#define TCO_TIMER_MASK		0x1f
195
196/* status bits for TCO1_STS */
197#define TCO_NEWCENTURY		0x80 /* set for RTC year roll over (99 to 00) */
198#define TCO_TIMEOUT		0x08 /* timed out */
199#define TCO_INT_STS		0x04 /* data out (DO NOT USE) */
200#define TCO_SMI_STS		0x02 /* data in (DO NOT USE) */
201
202/* status bits for TCO2_STS */
203#define TCO_BOOT_STS		0x04 /* failed to come out of reset */
204#define TCO_SECOND_TO_STS	0x02 /* ran down twice */
205
206/* control bits for TCO1_CNT */
207#define TCO_TMR_HALT		0x0800		/* clear to enable WDT */
208#define TCO_NMI2SMI_EN		0x0200		/* convert NMIs to SMIs */
209#define TCO_CNT_PRESERVE	TCO_NMI2SMI_EN	/* preserve these bits */
210#define TCO_NMI_NOW		0x0100		/* trigger an NMI */
211
212/*
213 * Masks for the TCO timer value field in TCO_RLD.
214 * If the datasheets are to be believed, the minimum value actually varies
215 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
216 * I suspect this is a bug in the ICH5 datasheet and that the minimum is
217 * uniformly 2, but I'd rather err on the side of caution.
218 */
219#define TCO_RLD_TMR_MIN		0x0004
220#define TCO_RLD1_TMR_MAX	0x003f
221#define TCO_RLD2_TMR_MAX	0x03ff
222
223/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */
224#define ICHWD_TICK		600000000
225
226#endif
227