ichwd.h revision 218140
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 218140 2011-01-31 18:41:52Z jfv $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t device; 36129124Sdes char *desc; 37171820Sdes unsigned int version; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42171820Sdes device_t ich; 43175012Sdes int ich_version; 44129124Sdes 45129124Sdes int active; 46129124Sdes unsigned int timeout; 47129124Sdes 48129124Sdes int smi_rid; 49129124Sdes struct resource *smi_res; 50129124Sdes bus_space_tag_t smi_bst; 51129124Sdes bus_space_handle_t smi_bsh; 52129124Sdes 53129124Sdes int tco_rid; 54129124Sdes struct resource *tco_res; 55129124Sdes bus_space_tag_t tco_bst; 56129124Sdes bus_space_handle_t tco_bsh; 57129124Sdes 58171820Sdes int gcs_rid; 59171820Sdes struct resource *gcs_res; 60171820Sdes bus_space_tag_t gcs_bst; 61171820Sdes bus_space_handle_t gcs_bsh; 62171820Sdes 63129124Sdes eventhandler_tag ev_tag; 64129124Sdes}; 65129124Sdes 66129124Sdes#define VENDORID_INTEL 0x8086 67211908Sjfv#define DEVICEID_CPT0 0x1c40 68211908Sjfv#define DEVICEID_CPT1 0x1c41 69211908Sjfv#define DEVICEID_CPT2 0x1c42 70211908Sjfv#define DEVICEID_CPT3 0x1c43 71211908Sjfv#define DEVICEID_CPT4 0x1c44 72211908Sjfv#define DEVICEID_CPT5 0x1c45 73211908Sjfv#define DEVICEID_CPT6 0x1c46 74211908Sjfv#define DEVICEID_CPT7 0x1c47 75211908Sjfv#define DEVICEID_CPT8 0x1c48 76211908Sjfv#define DEVICEID_CPT9 0x1c49 77211908Sjfv#define DEVICEID_CPT10 0x1c4a 78211908Sjfv#define DEVICEID_CPT11 0x1c4b 79211908Sjfv#define DEVICEID_CPT12 0x1c4c 80211908Sjfv#define DEVICEID_CPT13 0x1c4d 81211908Sjfv#define DEVICEID_CPT14 0x1c4e 82211908Sjfv#define DEVICEID_CPT15 0x1c4f 83211908Sjfv#define DEVICEID_CPT16 0x1c50 84211908Sjfv#define DEVICEID_CPT17 0x1c51 85211908Sjfv#define DEVICEID_CPT18 0x1c52 86211908Sjfv#define DEVICEID_CPT19 0x1c53 87211908Sjfv#define DEVICEID_CPT20 0x1c54 88211908Sjfv#define DEVICEID_CPT21 0x1c55 89211908Sjfv#define DEVICEID_CPT22 0x1c56 90211908Sjfv#define DEVICEID_CPT23 0x1c57 91211908Sjfv#define DEVICEID_CPT24 0x1c58 92211908Sjfv#define DEVICEID_CPT25 0x1c59 93211908Sjfv#define DEVICEID_CPT26 0x1c5a 94211908Sjfv#define DEVICEID_CPT27 0x1c5b 95211908Sjfv#define DEVICEID_CPT28 0x1c5c 96211908Sjfv#define DEVICEID_CPT29 0x1c5d 97211908Sjfv#define DEVICEID_CPT30 0x1c5e 98211908Sjfv#define DEVICEID_CPT31 0x1c5f 99218140Sjfv#define DEVICEID_DH89XXCC_LPC 0x2310 100129124Sdes#define DEVICEID_82801AA 0x2410 101129124Sdes#define DEVICEID_82801AB 0x2420 102129124Sdes#define DEVICEID_82801BA 0x2440 103129124Sdes#define DEVICEID_82801BAM 0x244c 104129124Sdes#define DEVICEID_82801CA 0x2480 105129124Sdes#define DEVICEID_82801CAM 0x248c 106129124Sdes#define DEVICEID_82801DB 0x24c0 107129124Sdes#define DEVICEID_82801DBM 0x24cc 108129124Sdes#define DEVICEID_82801E 0x2450 109182161Sjhb#define DEVICEID_82801EB 0x24dc 110129124Sdes#define DEVICEID_82801EBR 0x24d0 111155785Sambrisko#define DEVICEID_6300ESB 0x25a1 112155785Sambrisko#define DEVICEID_82801FBR 0x2640 113171820Sdes#define DEVICEID_ICH6M 0x2641 114171820Sdes#define DEVICEID_ICH6W 0x2642 115173661Sjfv#define DEVICEID_63XXESB 0x2670 116171820Sdes#define DEVICEID_ICH7 0x27b8 117182161Sjhb#define DEVICEID_ICH7DH 0x27b0 118171820Sdes#define DEVICEID_ICH7M 0x27b9 119202917Sremko#define DEVICEID_NM10 0x27bc 120171820Sdes#define DEVICEID_ICH7MDH 0x27bd 121171820Sdes#define DEVICEID_ICH8 0x2810 122171820Sdes#define DEVICEID_ICH8DH 0x2812 123171820Sdes#define DEVICEID_ICH8DO 0x2814 124175128Sdes#define DEVICEID_ICH8M 0x2815 125182161Sjhb#define DEVICEID_ICH8ME 0x2811 126175013Sdes#define DEVICEID_ICH9 0x2918 127175013Sdes#define DEVICEID_ICH9DH 0x2912 128175013Sdes#define DEVICEID_ICH9DO 0x2914 129182161Sjhb#define DEVICEID_ICH9M 0x2919 130182161Sjhb#define DEVICEID_ICH9ME 0x2917 131182161Sjhb#define DEVICEID_ICH9R 0x2916 132182161Sjhb#define DEVICEID_ICH10 0x3a18 133182161Sjhb#define DEVICEID_ICH10D 0x3a1a 134182161Sjhb#define DEVICEID_ICH10DO 0x3a14 135182161Sjhb#define DEVICEID_ICH10R 0x3a16 136211908Sjfv#define DEVICEID_PCH 0x3b00 137211908Sjfv#define DEVICEID_PCHM 0x3b01 138211908Sjfv#define DEVICEID_P55 0x3b02 139211908Sjfv#define DEVICEID_PM55 0x3b03 140202812Semaste#define DEVICEID_H55 0x3b06 141211908Sjfv#define DEVICEID_QM57 0x3b07 142211908Sjfv#define DEVICEID_H57 0x3b08 143211908Sjfv#define DEVICEID_HM55 0x3b09 144211908Sjfv#define DEVICEID_Q57 0x3b0a 145211908Sjfv#define DEVICEID_HM57 0x3b0b 146211908Sjfv#define DEVICEID_PCHMSFF 0x3b0d 147211908Sjfv#define DEVICEID_QS57 0x3b0f 148211908Sjfv#define DEVICEID_3400 0x3b12 149211908Sjfv#define DEVICEID_3420 0x3b14 150211908Sjfv#define DEVICEID_3450 0x3b16 151129124Sdes 152171820Sdes/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 153129124Sdes#define ICH_GEN_STA 0xd4 154129124Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 155129124Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 156129124Sdes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 157129124Sdes 158171820Sdes/* ICH Chipset Configuration Registers (ICH6 and newer) */ 159171820Sdes#define ICH_RCBA 0xf0 160171820Sdes#define ICH_GCS_OFFSET 0x3410 161171820Sdes#define ICH_GCS_SIZE 0x4 162171820Sdes#define ICH_GCS_NO_REBOOT 0x20 163171820Sdes 164129124Sdes/* register names and locations (relative to PMBASE) */ 165129124Sdes#define SMI_BASE 0x30 /* base address for SMI registers */ 166129124Sdes#define SMI_LEN 0x08 167129124Sdes#define SMI_EN 0x00 /* SMI Control and Enable Register */ 168129124Sdes#define SMI_STS 0x04 /* SMI Status Register */ 169129124Sdes#define TCO_BASE 0x60 /* base address for TCO registers */ 170171820Sdes#define TCO_LEN 0x20 171129124Sdes#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 172171820Sdes#define TCO_TMR1 0x01 /* TCO Timer Initial Value 173171820Sdes (ICH5 and older, 8 bits) */ 174171820Sdes#define TCO_TMR2 0x12 /* TCO Timer Initial Value 175171820Sdes (ICH6 and newer, 16 bits) */ 176129124Sdes#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 177129124Sdes#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 178129124Sdes#define TCO1_STS 0x04 /* TCO Status 1 */ 179129124Sdes#define TCO2_STS 0x06 /* TCO Status 2 */ 180129124Sdes#define TCO1_CNT 0x08 /* TCO Control 1 */ 181171820Sdes#define TCO2_CNT 0x08 /* TCO Control 2 */ 182129124Sdes 183129124Sdes/* bit definitions for SMI_EN and SMI_STS */ 184129124Sdes#define SMI_TCO_EN 0x2000 185129124Sdes#define SMI_TCO_STS 0x2000 186129124Sdes 187129124Sdes/* timer value mask for TCO_RLD and TCO_TMR */ 188129124Sdes#define TCO_TIMER_MASK 0x1f 189129124Sdes 190129124Sdes/* status bits for TCO1_STS */ 191129124Sdes#define TCO_TIMEOUT 0x08 /* timed out */ 192129124Sdes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 193129124Sdes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 194129124Sdes 195129124Sdes/* status bits for TCO2_STS */ 196129124Sdes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 197129124Sdes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 198129124Sdes 199129124Sdes/* control bits for TCO1_CNT */ 200129124Sdes#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 201129124Sdes#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 202129124Sdes 203216298Sattilio/* 204216298Sattilio * Masks for the TCO timer value field in TCO_RLD. 205216298Sattilio * If the datasheets are to be believed, the minimum value actually varies 206216298Sattilio * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 207216298Sattilio * I suspect this is a bug in the ICH5 datasheet and that the minimum is 208216298Sattilio * uniformly 2, but I'd rather err on the side of caution. 209216298Sattilio */ 210216298Sattilio#define TCO_RLD_TMR_MIN 0x0004 211216298Sattilio#define TCO_RLD1_TMR_MAX 0x003f 212216298Sattilio#define TCO_RLD2_TMR_MAX 0x03ff 213216298Sattilio 214171820Sdes/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 215171820Sdes#define ICHWD_TICK 600000000 216129124Sdes 217129124Sdes#endif 218